1315a1350SMichael S. Tsirkin /*
2315a1350SMichael S. Tsirkin * pcie_host.c
3315a1350SMichael S. Tsirkin * utility functions for pci express host bridge.
4315a1350SMichael S. Tsirkin *
5315a1350SMichael S. Tsirkin * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
6315a1350SMichael S. Tsirkin * VA Linux Systems Japan K.K.
7315a1350SMichael S. Tsirkin *
8315a1350SMichael S. Tsirkin * This program is free software; you can redistribute it and/or modify
9315a1350SMichael S. Tsirkin * it under the terms of the GNU General Public License as published by
10315a1350SMichael S. Tsirkin * the Free Software Foundation; either version 2 of the License, or
11315a1350SMichael S. Tsirkin * (at your option) any later version.
12315a1350SMichael S. Tsirkin
13315a1350SMichael S. Tsirkin * This program is distributed in the hope that it will be useful,
14315a1350SMichael S. Tsirkin * but WITHOUT ANY WARRANTY; without even the implied warranty of
15315a1350SMichael S. Tsirkin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16315a1350SMichael S. Tsirkin * GNU General Public License for more details.
17315a1350SMichael S. Tsirkin
18315a1350SMichael S. Tsirkin * You should have received a copy of the GNU General Public License along
19315a1350SMichael S. Tsirkin * with this program; if not, see <http://www.gnu.org/licenses/>.
20315a1350SMichael S. Tsirkin */
21315a1350SMichael S. Tsirkin
2297d5408fSPeter Maydell #include "qemu/osdep.h"
23*edf5ca5dSMarkus Armbruster #include "hw/pci/pci_device.h"
24c759b24fSMichael S. Tsirkin #include "hw/pci/pcie_host.h"
250b8fa32fSMarkus Armbruster #include "qemu/module.h"
26315a1350SMichael S. Tsirkin
27315a1350SMichael S. Tsirkin /* a helper function to get a PCIDevice for a given mmconfig address */
pcie_dev_find_by_mmcfg_addr(PCIBus * s,uint32_t mmcfg_addr)28315a1350SMichael S. Tsirkin static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s,
29315a1350SMichael S. Tsirkin uint32_t mmcfg_addr)
30315a1350SMichael S. Tsirkin {
31315a1350SMichael S. Tsirkin return pci_find_device(s, PCIE_MMCFG_BUS(mmcfg_addr),
32315a1350SMichael S. Tsirkin PCIE_MMCFG_DEVFN(mmcfg_addr));
33315a1350SMichael S. Tsirkin }
34315a1350SMichael S. Tsirkin
pcie_mmcfg_data_write(void * opaque,hwaddr mmcfg_addr,uint64_t val,unsigned len)35315a1350SMichael S. Tsirkin static void pcie_mmcfg_data_write(void *opaque, hwaddr mmcfg_addr,
36315a1350SMichael S. Tsirkin uint64_t val, unsigned len)
37315a1350SMichael S. Tsirkin {
38315a1350SMichael S. Tsirkin PCIExpressHost *e = opaque;
39315a1350SMichael S. Tsirkin PCIBus *s = e->pci.bus;
40315a1350SMichael S. Tsirkin PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
41315a1350SMichael S. Tsirkin uint32_t addr;
42315a1350SMichael S. Tsirkin uint32_t limit;
43315a1350SMichael S. Tsirkin
44315a1350SMichael S. Tsirkin if (!pci_dev) {
45315a1350SMichael S. Tsirkin return;
46315a1350SMichael S. Tsirkin }
47315a1350SMichael S. Tsirkin addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr);
48315a1350SMichael S. Tsirkin limit = pci_config_size(pci_dev);
49315a1350SMichael S. Tsirkin pci_host_config_write_common(pci_dev, addr, limit, val, len);
50315a1350SMichael S. Tsirkin }
51315a1350SMichael S. Tsirkin
pcie_mmcfg_data_read(void * opaque,hwaddr mmcfg_addr,unsigned len)52315a1350SMichael S. Tsirkin static uint64_t pcie_mmcfg_data_read(void *opaque,
53315a1350SMichael S. Tsirkin hwaddr mmcfg_addr,
54315a1350SMichael S. Tsirkin unsigned len)
55315a1350SMichael S. Tsirkin {
56315a1350SMichael S. Tsirkin PCIExpressHost *e = opaque;
57315a1350SMichael S. Tsirkin PCIBus *s = e->pci.bus;
58315a1350SMichael S. Tsirkin PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
59315a1350SMichael S. Tsirkin uint32_t addr;
60315a1350SMichael S. Tsirkin uint32_t limit;
61315a1350SMichael S. Tsirkin
62315a1350SMichael S. Tsirkin if (!pci_dev) {
63315a1350SMichael S. Tsirkin return ~0x0;
64315a1350SMichael S. Tsirkin }
65315a1350SMichael S. Tsirkin addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr);
66315a1350SMichael S. Tsirkin limit = pci_config_size(pci_dev);
67315a1350SMichael S. Tsirkin return pci_host_config_read_common(pci_dev, addr, limit, len);
68315a1350SMichael S. Tsirkin }
69315a1350SMichael S. Tsirkin
70315a1350SMichael S. Tsirkin static const MemoryRegionOps pcie_mmcfg_ops = {
71315a1350SMichael S. Tsirkin .read = pcie_mmcfg_data_read,
72315a1350SMichael S. Tsirkin .write = pcie_mmcfg_data_write,
73a6c242aaSMatt Redfearn .endianness = DEVICE_LITTLE_ENDIAN,
74315a1350SMichael S. Tsirkin };
75315a1350SMichael S. Tsirkin
pcie_host_init(Object * obj)767c8b7248SAndreas Färber static void pcie_host_init(Object *obj)
77315a1350SMichael S. Tsirkin {
787c8b7248SAndreas Färber PCIExpressHost *e = PCIE_HOST_BRIDGE(obj);
79315a1350SMichael S. Tsirkin
807c8b7248SAndreas Färber e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
813a8f2a9cSPaolo Bonzini memory_region_init_io(&e->mmio, OBJECT(e), &pcie_mmcfg_ops, e, "pcie-mmcfg-mmio",
823a8f2a9cSPaolo Bonzini PCIE_MMCFG_SIZE_MAX);
83315a1350SMichael S. Tsirkin }
84315a1350SMichael S. Tsirkin
pcie_host_mmcfg_unmap(PCIExpressHost * e)85315a1350SMichael S. Tsirkin void pcie_host_mmcfg_unmap(PCIExpressHost *e)
86315a1350SMichael S. Tsirkin {
87315a1350SMichael S. Tsirkin if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) {
88315a1350SMichael S. Tsirkin memory_region_del_subregion(get_system_memory(), &e->mmio);
89315a1350SMichael S. Tsirkin e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
90315a1350SMichael S. Tsirkin }
91315a1350SMichael S. Tsirkin }
92315a1350SMichael S. Tsirkin
pcie_host_mmcfg_init(PCIExpressHost * e,uint32_t size)9327fb9688SAlexander Graf void pcie_host_mmcfg_init(PCIExpressHost *e, uint32_t size)
94315a1350SMichael S. Tsirkin {
95315a1350SMichael S. Tsirkin assert(!(size & (size - 1))); /* power of 2 */
96315a1350SMichael S. Tsirkin assert(size >= PCIE_MMCFG_SIZE_MIN);
97315a1350SMichael S. Tsirkin assert(size <= PCIE_MMCFG_SIZE_MAX);
98315a1350SMichael S. Tsirkin e->size = size;
993a8f2a9cSPaolo Bonzini memory_region_set_size(&e->mmio, e->size);
10027fb9688SAlexander Graf }
10127fb9688SAlexander Graf
pcie_host_mmcfg_map(PCIExpressHost * e,hwaddr addr,uint32_t size)10227fb9688SAlexander Graf void pcie_host_mmcfg_map(PCIExpressHost *e, hwaddr addr,
10327fb9688SAlexander Graf uint32_t size)
10427fb9688SAlexander Graf {
10527fb9688SAlexander Graf pcie_host_mmcfg_init(e, size);
106315a1350SMichael S. Tsirkin e->base_addr = addr;
107315a1350SMichael S. Tsirkin memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio);
108315a1350SMichael S. Tsirkin }
109315a1350SMichael S. Tsirkin
pcie_host_mmcfg_update(PCIExpressHost * e,int enable,hwaddr addr,uint32_t size)110315a1350SMichael S. Tsirkin void pcie_host_mmcfg_update(PCIExpressHost *e,
111315a1350SMichael S. Tsirkin int enable,
112315a1350SMichael S. Tsirkin hwaddr addr,
113315a1350SMichael S. Tsirkin uint32_t size)
114315a1350SMichael S. Tsirkin {
1153a8f2a9cSPaolo Bonzini memory_region_transaction_begin();
116315a1350SMichael S. Tsirkin pcie_host_mmcfg_unmap(e);
117315a1350SMichael S. Tsirkin if (enable) {
118315a1350SMichael S. Tsirkin pcie_host_mmcfg_map(e, addr, size);
119315a1350SMichael S. Tsirkin }
1203a8f2a9cSPaolo Bonzini memory_region_transaction_commit();
121315a1350SMichael S. Tsirkin }
122315a1350SMichael S. Tsirkin
123315a1350SMichael S. Tsirkin static const TypeInfo pcie_host_type_info = {
124315a1350SMichael S. Tsirkin .name = TYPE_PCIE_HOST_BRIDGE,
125315a1350SMichael S. Tsirkin .parent = TYPE_PCI_HOST_BRIDGE,
126315a1350SMichael S. Tsirkin .abstract = true,
127315a1350SMichael S. Tsirkin .instance_size = sizeof(PCIExpressHost),
1287c8b7248SAndreas Färber .instance_init = pcie_host_init,
129315a1350SMichael S. Tsirkin };
130315a1350SMichael S. Tsirkin
pcie_host_register_types(void)131315a1350SMichael S. Tsirkin static void pcie_host_register_types(void)
132315a1350SMichael S. Tsirkin {
133315a1350SMichael S. Tsirkin type_register_static(&pcie_host_type_info);
134315a1350SMichael S. Tsirkin }
135315a1350SMichael S. Tsirkin
136315a1350SMichael S. Tsirkin type_init(pcie_host_register_types)
137