1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to dea 8 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM 22 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 /* 27 * split out from pci.c 28 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 29 * VA Linux Systems Japan K.K. 30 */ 31 32 #include "qemu/osdep.h" 33 #include "qemu/units.h" 34 #include "hw/pci/pci_bridge.h" 35 #include "hw/pci/pci_bus.h" 36 #include "qemu/module.h" 37 #include "qemu/range.h" 38 #include "qapi/error.h" 39 #include "hw/acpi/acpi_aml_interface.h" 40 41 /* PCI bridge subsystem vendor ID helper functions */ 42 #define PCI_SSVID_SIZEOF 8 43 #define PCI_SSVID_SVID 4 44 #define PCI_SSVID_SSID 6 45 46 int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, 47 uint16_t svid, uint16_t ssid, 48 Error **errp) 49 { 50 int pos; 51 52 pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, 53 PCI_SSVID_SIZEOF, errp); 54 if (pos < 0) { 55 return pos; 56 } 57 58 pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid); 59 pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid); 60 return pos; 61 } 62 63 /* Accessor function to get parent bridge device from pci bus. */ 64 PCIDevice *pci_bridge_get_device(PCIBus *bus) 65 { 66 return bus->parent_dev; 67 } 68 69 /* Accessor function to get secondary bus from pci-to-pci bridge device */ 70 PCIBus *pci_bridge_get_sec_bus(PCIBridge *br) 71 { 72 return &br->sec_bus; 73 } 74 75 static uint32_t pci_config_get_io_base(const PCIDevice *d, 76 uint32_t base, uint32_t base_upper16) 77 { 78 uint32_t val; 79 80 val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8; 81 if (d->config[base] & PCI_IO_RANGE_TYPE_32) { 82 val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16; 83 } 84 return val; 85 } 86 87 static pcibus_t pci_config_get_memory_base(const PCIDevice *d, uint32_t base) 88 { 89 return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK) 90 << 16; 91 } 92 93 static pcibus_t pci_config_get_pref_base(const PCIDevice *d, 94 uint32_t base, uint32_t upper) 95 { 96 pcibus_t tmp; 97 pcibus_t val; 98 99 tmp = (pcibus_t)pci_get_word(d->config + base); 100 val = (tmp & PCI_PREF_RANGE_MASK) << 16; 101 if (tmp & PCI_PREF_RANGE_TYPE_64) { 102 val |= (pcibus_t)pci_get_long(d->config + upper) << 32; 103 } 104 return val; 105 } 106 107 /* accessor function to get bridge filtering base address */ 108 pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type) 109 { 110 pcibus_t base; 111 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 112 base = pci_config_get_io_base(bridge, 113 PCI_IO_BASE, PCI_IO_BASE_UPPER16); 114 } else { 115 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) { 116 base = pci_config_get_pref_base( 117 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32); 118 } else { 119 base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE); 120 } 121 } 122 123 return base; 124 } 125 126 /* accessor function to get bridge filtering limit */ 127 pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type) 128 { 129 pcibus_t limit; 130 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 131 limit = pci_config_get_io_base(bridge, 132 PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16); 133 limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */ 134 } else { 135 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) { 136 limit = pci_config_get_pref_base( 137 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32); 138 } else { 139 limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT); 140 } 141 limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */ 142 } 143 return limit; 144 } 145 146 static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias, 147 uint8_t type, const char *name, 148 MemoryRegion *space, 149 MemoryRegion *parent_space, 150 bool enabled) 151 { 152 PCIDevice *bridge_dev = PCI_DEVICE(bridge); 153 pcibus_t base = pci_bridge_get_base(bridge_dev, type); 154 pcibus_t limit = pci_bridge_get_limit(bridge_dev, type); 155 /* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly. 156 * Apparently no way to do this with existing memory APIs. */ 157 pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0; 158 159 memory_region_init_alias(alias, OBJECT(bridge), name, space, base, size); 160 memory_region_add_subregion_overlap(parent_space, base, alias, 1); 161 } 162 163 static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent, 164 MemoryRegion *alias_vga) 165 { 166 PCIDevice *pd = PCI_DEVICE(br); 167 uint16_t brctl = pci_get_word(pd->config + PCI_BRIDGE_CONTROL); 168 169 memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], OBJECT(br), 170 "pci_bridge_vga_io_lo", &br->address_space_io, 171 QEMU_PCI_VGA_IO_LO_BASE, QEMU_PCI_VGA_IO_LO_SIZE); 172 memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_HI], OBJECT(br), 173 "pci_bridge_vga_io_hi", &br->address_space_io, 174 QEMU_PCI_VGA_IO_HI_BASE, QEMU_PCI_VGA_IO_HI_SIZE); 175 memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_MEM], OBJECT(br), 176 "pci_bridge_vga_mem", &br->address_space_mem, 177 QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZE); 178 179 if (brctl & PCI_BRIDGE_CTL_VGA) { 180 pci_register_vga(pd, &alias_vga[QEMU_PCI_VGA_MEM], 181 &alias_vga[QEMU_PCI_VGA_IO_LO], 182 &alias_vga[QEMU_PCI_VGA_IO_HI]); 183 } 184 } 185 186 static PCIBridgeWindows *pci_bridge_region_init(PCIBridge *br) 187 { 188 PCIDevice *pd = PCI_DEVICE(br); 189 PCIBus *parent = pci_get_bus(pd); 190 PCIBridgeWindows *w = g_new(PCIBridgeWindows, 1); 191 uint16_t cmd = pci_get_word(pd->config + PCI_COMMAND); 192 193 pci_bridge_init_alias(br, &w->alias_pref_mem, 194 PCI_BASE_ADDRESS_MEM_PREFETCH, 195 "pci_bridge_pref_mem", 196 &br->address_space_mem, 197 parent->address_space_mem, 198 cmd & PCI_COMMAND_MEMORY); 199 pci_bridge_init_alias(br, &w->alias_mem, 200 PCI_BASE_ADDRESS_SPACE_MEMORY, 201 "pci_bridge_mem", 202 &br->address_space_mem, 203 parent->address_space_mem, 204 cmd & PCI_COMMAND_MEMORY); 205 pci_bridge_init_alias(br, &w->alias_io, 206 PCI_BASE_ADDRESS_SPACE_IO, 207 "pci_bridge_io", 208 &br->address_space_io, 209 parent->address_space_io, 210 cmd & PCI_COMMAND_IO); 211 212 pci_bridge_init_vga_aliases(br, parent, w->alias_vga); 213 214 return w; 215 } 216 217 static void pci_bridge_region_del(PCIBridge *br, PCIBridgeWindows *w) 218 { 219 PCIDevice *pd = PCI_DEVICE(br); 220 PCIBus *parent = pci_get_bus(pd); 221 222 memory_region_del_subregion(parent->address_space_io, &w->alias_io); 223 memory_region_del_subregion(parent->address_space_mem, &w->alias_mem); 224 memory_region_del_subregion(parent->address_space_mem, &w->alias_pref_mem); 225 pci_unregister_vga(pd); 226 } 227 228 static void pci_bridge_region_cleanup(PCIBridge *br, PCIBridgeWindows *w) 229 { 230 object_unparent(OBJECT(&w->alias_io)); 231 object_unparent(OBJECT(&w->alias_mem)); 232 object_unparent(OBJECT(&w->alias_pref_mem)); 233 object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_LO])); 234 object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_HI])); 235 object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_MEM])); 236 g_free(w); 237 } 238 239 void pci_bridge_update_mappings(PCIBridge *br) 240 { 241 PCIBridgeWindows *w = br->windows; 242 243 /* Make updates atomic to: handle the case of one VCPU updating the bridge 244 * while another accesses an unaffected region. */ 245 memory_region_transaction_begin(); 246 pci_bridge_region_del(br, br->windows); 247 pci_bridge_region_cleanup(br, w); 248 br->windows = pci_bridge_region_init(br); 249 memory_region_transaction_commit(); 250 } 251 252 /* default write_config function for PCI-to-PCI bridge */ 253 void pci_bridge_write_config(PCIDevice *d, 254 uint32_t address, uint32_t val, int len) 255 { 256 PCIBridge *s = PCI_BRIDGE(d); 257 uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL); 258 uint16_t newctl; 259 260 pci_default_write_config(d, address, val, len); 261 262 if (ranges_overlap(address, len, PCI_COMMAND, 2) || 263 264 /* io base/limit */ 265 ranges_overlap(address, len, PCI_IO_BASE, 2) || 266 267 /* memory base/limit, prefetchable base/limit and 268 io base/limit upper 16 */ 269 ranges_overlap(address, len, PCI_MEMORY_BASE, 20) || 270 271 /* vga enable */ 272 ranges_overlap(address, len, PCI_BRIDGE_CONTROL, 2)) { 273 pci_bridge_update_mappings(s); 274 } 275 276 newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL); 277 if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) { 278 /* Trigger hot reset on 0->1 transition. */ 279 bus_cold_reset(BUS(&s->sec_bus)); 280 } 281 } 282 283 void pci_bridge_disable_base_limit(PCIDevice *dev) 284 { 285 uint8_t *conf = dev->config; 286 287 pci_byte_test_and_set_mask(conf + PCI_IO_BASE, 288 PCI_IO_RANGE_MASK & 0xff); 289 pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, 290 PCI_IO_RANGE_MASK & 0xff); 291 pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE, 292 PCI_MEMORY_RANGE_MASK & 0xffff); 293 pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT, 294 PCI_MEMORY_RANGE_MASK & 0xffff); 295 pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE, 296 PCI_PREF_RANGE_MASK & 0xffff); 297 pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT, 298 PCI_PREF_RANGE_MASK & 0xffff); 299 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0); 300 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0); 301 } 302 303 /* reset bridge specific configuration registers */ 304 void pci_bridge_reset(DeviceState *qdev) 305 { 306 PCIDevice *dev = PCI_DEVICE(qdev); 307 uint8_t *conf = dev->config; 308 309 conf[PCI_PRIMARY_BUS] = 0; 310 conf[PCI_SECONDARY_BUS] = 0; 311 conf[PCI_SUBORDINATE_BUS] = 0; 312 conf[PCI_SEC_LATENCY_TIMER] = 0; 313 314 /* 315 * the default values for base/limit registers aren't specified 316 * in the PCI-to-PCI-bridge spec. So we don't touch them here. 317 * Each implementation can override it. 318 * typical implementation does 319 * zero base/limit registers or 320 * disable forwarding: pci_bridge_disable_base_limit() 321 * If disable forwarding is wanted, call pci_bridge_disable_base_limit() 322 * after this function. 323 */ 324 pci_byte_test_and_clear_mask(conf + PCI_IO_BASE, 325 PCI_IO_RANGE_MASK & 0xff); 326 pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, 327 PCI_IO_RANGE_MASK & 0xff); 328 pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE, 329 PCI_MEMORY_RANGE_MASK & 0xffff); 330 pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT, 331 PCI_MEMORY_RANGE_MASK & 0xffff); 332 pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE, 333 PCI_PREF_RANGE_MASK & 0xffff); 334 pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT, 335 PCI_PREF_RANGE_MASK & 0xffff); 336 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0); 337 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0); 338 339 pci_set_word(conf + PCI_BRIDGE_CONTROL, 0); 340 } 341 342 /* default qdev initialization function for PCI-to-PCI bridge */ 343 void pci_bridge_initfn(PCIDevice *dev, const char *typename) 344 { 345 PCIBus *parent = pci_get_bus(dev); 346 PCIBridge *br = PCI_BRIDGE(dev); 347 PCIBus *sec_bus = &br->sec_bus; 348 349 pci_word_test_and_set_mask(dev->config + PCI_STATUS, 350 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); 351 352 /* 353 * TODO: We implement VGA Enable in the Bridge Control Register 354 * therefore per the PCI to PCI bridge spec we must also implement 355 * VGA Palette Snooping. When done, set this bit writable: 356 * 357 * pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, 358 * PCI_COMMAND_VGA_PALETTE); 359 */ 360 361 pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI); 362 dev->config[PCI_HEADER_TYPE] = 363 (dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) | 364 PCI_HEADER_TYPE_BRIDGE; 365 pci_set_word(dev->config + PCI_SEC_STATUS, 366 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); 367 368 /* 369 * If we don't specify the name, the bus will be addressed as <id>.0, where 370 * id is the device id. 371 * Since PCI Bridge devices have a single bus each, we don't need the index: 372 * let users address the bus using the device name. 373 */ 374 if (!br->bus_name && dev->qdev.id && *dev->qdev.id) { 375 br->bus_name = dev->qdev.id; 376 } 377 378 qbus_init(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev), 379 br->bus_name); 380 sec_bus->parent_dev = dev; 381 sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn; 382 sec_bus->address_space_mem = &br->address_space_mem; 383 memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci", UINT64_MAX); 384 sec_bus->address_space_io = &br->address_space_io; 385 memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io", 386 4 * GiB); 387 br->windows = pci_bridge_region_init(br); 388 QLIST_INIT(&sec_bus->child); 389 QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling); 390 } 391 392 /* default qdev clean up function for PCI-to-PCI bridge */ 393 void pci_bridge_exitfn(PCIDevice *pci_dev) 394 { 395 PCIBridge *s = PCI_BRIDGE(pci_dev); 396 assert(QLIST_EMPTY(&s->sec_bus.child)); 397 QLIST_REMOVE(&s->sec_bus, sibling); 398 pci_bridge_region_del(s, s->windows); 399 pci_bridge_region_cleanup(s, s->windows); 400 /* object_unparent() is called automatically during device deletion */ 401 } 402 403 /* 404 * before qdev initialization(qdev_init()), this function sets bus_name and 405 * map_irq callback which are necessary for pci_bridge_initfn() to 406 * initialize bus. 407 */ 408 void pci_bridge_map_irq(PCIBridge *br, const char* bus_name, 409 pci_map_irq_fn map_irq) 410 { 411 br->map_irq = map_irq; 412 br->bus_name = bus_name; 413 } 414 415 416 int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, 417 PCIResReserve res_reserve, Error **errp) 418 { 419 if (res_reserve.mem_pref_32 != (uint64_t)-1 && 420 res_reserve.mem_pref_64 != (uint64_t)-1) { 421 error_setg(errp, 422 "PCI resource reserve cap: PREF32 and PREF64 conflict"); 423 return -EINVAL; 424 } 425 426 if (res_reserve.mem_non_pref != (uint64_t)-1 && 427 res_reserve.mem_non_pref >= 4 * GiB) { 428 error_setg(errp, 429 "PCI resource reserve cap: mem-reserve must be less than 4G"); 430 return -EINVAL; 431 } 432 433 if (res_reserve.mem_pref_32 != (uint64_t)-1 && 434 res_reserve.mem_pref_32 >= 4 * GiB) { 435 error_setg(errp, 436 "PCI resource reserve cap: pref32-reserve must be less than 4G"); 437 return -EINVAL; 438 } 439 440 if (res_reserve.bus == (uint32_t)-1 && 441 res_reserve.io == (uint64_t)-1 && 442 res_reserve.mem_non_pref == (uint64_t)-1 && 443 res_reserve.mem_pref_32 == (uint64_t)-1 && 444 res_reserve.mem_pref_64 == (uint64_t)-1) { 445 return 0; 446 } 447 448 size_t cap_len = sizeof(PCIBridgeQemuCap); 449 PCIBridgeQemuCap cap = { 450 .len = cap_len, 451 .type = REDHAT_PCI_CAP_RESOURCE_RESERVE, 452 .bus_res = cpu_to_le32(res_reserve.bus), 453 .io = cpu_to_le64(res_reserve.io), 454 .mem = cpu_to_le32(res_reserve.mem_non_pref), 455 .mem_pref_32 = cpu_to_le32(res_reserve.mem_pref_32), 456 .mem_pref_64 = cpu_to_le64(res_reserve.mem_pref_64) 457 }; 458 459 int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, 460 cap_offset, cap_len, errp); 461 if (offset < 0) { 462 return offset; 463 } 464 465 memcpy(dev->config + offset + PCI_CAP_FLAGS, 466 (char *)&cap + PCI_CAP_FLAGS, 467 cap_len - PCI_CAP_FLAGS); 468 return 0; 469 } 470 471 static const TypeInfo pci_bridge_type_info = { 472 .name = TYPE_PCI_BRIDGE, 473 .parent = TYPE_PCI_DEVICE, 474 .instance_size = sizeof(PCIBridge), 475 .abstract = true, 476 .interfaces = (InterfaceInfo[]) { 477 { TYPE_ACPI_DEV_AML_IF }, 478 { }, 479 }, 480 }; 481 482 static void pci_bridge_register_types(void) 483 { 484 type_register_static(&pci_bridge_type_info); 485 } 486 487 type_init(pci_bridge_register_types) 488