1d0fb9657SStefano Garzarella# See docs/devel/tracing.rst for syntax documentation. 2cd8c2fe7SDaniel P. Berrange 329d08975SNiek Linnenbank# allwinner-sun8i-emac.c 429d08975SNiek Linnenbankallwinner_sun8i_emac_mii_write_reg(uint32_t reg, uint32_t value) "MII write: reg=0x%" PRIx32 " value=0x%" PRIx32 529d08975SNiek Linnenbankallwinner_sun8i_emac_mii_read_reg(uint32_t reg, uint32_t value) "MII read: reg=0x%" PRIx32 " value=0x%" PRIx32 629d08975SNiek Linnenbankallwinner_sun8i_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes) "RX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32 729d08975SNiek Linnenbankallwinner_sun8i_emac_transmit(uint32_t desc, uint32_t paddr, uint32_t bytes) "TX packet: desc=0x%" PRIx32 " paddr=0x%" PRIx32 " bytes=%" PRIu32 829d08975SNiek Linnenbankallwinner_sun8i_emac_reset(void) "HW reset" 929d08975SNiek Linnenbankallwinner_sun8i_emac_set_link(bool active) "Set link: active=%u" 1029d08975SNiek Linnenbankallwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64 1129d08975SNiek Linnenbankallwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64 1229d08975SNiek Linnenbank 13500016e5SMarkus Armbruster# etraxfs_eth.c 144b46fdd0SPhilippe Mathieu-Daudémdio_phy_read(int regnum, uint16_t value) "read phy_reg:%d value:0x%04x" 154b46fdd0SPhilippe Mathieu-Daudémdio_phy_write(int regnum, uint16_t value) "write phy_reg:%d value:0x%04x" 164b46fdd0SPhilippe Mathieu-Daudémdio_bitbang(bool mdc, bool mdio, int state, uint16_t cnt, unsigned int drive) "bitbang mdc=%u mdio=%u state=%d cnt=%u drv=%d" 174b46fdd0SPhilippe Mathieu-Daudé 18500016e5SMarkus Armbruster# lance.c 198908eb1aSVladimir Sementsov-Ogievskiylance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x" 208908eb1aSVladimir Sementsov-Ogievskiylance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x" 21cd8c2fe7SDaniel P. Berrange 22500016e5SMarkus Armbruster# mipsnet.c 23cd8c2fe7SDaniel P. Berrangemipsnet_send(uint32_t size) "sending len=%u" 24cd8c2fe7SDaniel P. Berrangemipsnet_receive(uint32_t size) "receiving len=%u" 25cd8c2fe7SDaniel P. Berrangemipsnet_read(uint64_t addr, uint32_t val) "read addr=0x%" PRIx64 " val=0x%x" 26cd8c2fe7SDaniel P. Berrangemipsnet_write(uint64_t addr, uint64_t val) "write addr=0x%" PRIx64 " val=0x%" PRIx64 278908eb1aSVladimir Sementsov-Ogievskiymipsnet_irq(uint32_t isr, uint32_t intctl) "set irq to %d (0x%02x)" 28cd8c2fe7SDaniel P. Berrange 29500016e5SMarkus Armbruster# ne2000.c 30cd4479a9SPhilippe Mathieu-Daudéne2000_read(uint64_t addr, uint64_t val) "read addr=0x%" PRIx64 " val=0x%" PRIx64 31cd4479a9SPhilippe Mathieu-Daudéne2000_write(uint64_t addr, uint64_t val) "write addr=0x%" PRIx64 " val=0x%" PRIx64 32a816b625SPhilippe Mathieu-Daudéne2000_ioport_read(uint64_t addr, uint64_t val) "io read addr=0x%02" PRIx64 " val=0x%02" PRIx64 33a816b625SPhilippe Mathieu-Daudéne2000_ioport_write(uint64_t addr, uint64_t val) "io write addr=0x%02" PRIx64 " val=0x%02" PRIx64 34cd4479a9SPhilippe Mathieu-Daudé 35500016e5SMarkus Armbruster# opencores_eth.c 368908eb1aSVladimir Sementsov-Ogievskiyopen_eth_mii_write(unsigned idx, uint16_t v) "MII[0x%02x] <- 0x%04x" 378908eb1aSVladimir Sementsov-Ogievskiyopen_eth_mii_read(unsigned idx, uint16_t v) "MII[0x%02x] -> 0x%04x" 388908eb1aSVladimir Sementsov-Ogievskiyopen_eth_update_irq(uint32_t v) "IRQ <- 0x%x" 39cd8c2fe7SDaniel P. Berrangeopen_eth_receive(unsigned len) "RX: len: %u" 40cd8c2fe7SDaniel P. Berrangeopen_eth_receive_mcast(unsigned idx, uint32_t h0, uint32_t h1) "MCAST: idx = %u, hash: %08x:%08x" 41cd8c2fe7SDaniel P. Berrangeopen_eth_receive_reject(void) "RX: rejected" 428908eb1aSVladimir Sementsov-Ogievskiyopen_eth_receive_desc(uint32_t addr, uint32_t len_flags) "RX: 0x%08x, len_flags: 0x%08x" 438908eb1aSVladimir Sementsov-Ogievskiyopen_eth_start_xmit(uint32_t addr, unsigned len, unsigned tx_len) "TX: 0x%08x, len: %u, tx_len: %u" 448908eb1aSVladimir Sementsov-Ogievskiyopen_eth_reg_read(uint32_t addr, uint32_t v) "MAC[0x%02x] -> 0x%08x" 458908eb1aSVladimir Sementsov-Ogievskiyopen_eth_reg_write(uint32_t addr, uint32_t v) "MAC[0x%02x] <- 0x%08x" 468908eb1aSVladimir Sementsov-Ogievskiyopen_eth_desc_read(uint32_t addr, uint32_t v) "DESC[0x%04x] -> 0x%08x" 478908eb1aSVladimir Sementsov-Ogievskiyopen_eth_desc_write(uint32_t addr, uint32_t v) "DESC[0x%04x] <- 0x%08x" 48cd8c2fe7SDaniel P. Berrange 49500016e5SMarkus Armbruster# pcnet.c 50cd8c2fe7SDaniel P. Berrangepcnet_s_reset(void *s) "s=%p" 51cd8c2fe7SDaniel P. Berrangepcnet_user_int(void *s) "s=%p" 52cd8c2fe7SDaniel P. Berrangepcnet_isr_change(void *s, uint32_t isr, uint32_t isr_old) "s=%p INTA=%d<=%d" 53db73ee4bSVladimir Sementsov-Ogievskiypcnet_init(void *s, uint64_t init_addr) "s=%p init_addr=0x%"PRIx64 54cd8c2fe7SDaniel P. Berrangepcnet_rlen_tlen(void *s, uint32_t rlen, uint32_t tlen) "s=%p rlen=%d tlen=%d" 55cd8c2fe7SDaniel P. Berrangepcnet_ss32_rdra_tdra(void *s, uint32_t ss32, uint32_t rdra, uint32_t rcvrl, uint32_t tdra, uint32_t xmtrl) "s=%p ss32=%d rdra=0x%08x[%d] tdra=0x%08x[%d]" 56cd8c2fe7SDaniel P. Berrange 57500016e5SMarkus Armbruster# pcnet-pci.c 58cd8c2fe7SDaniel P. Berrangepcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val) "opaque=%p addr=0x%08x val=0x%02x" 59cd8c2fe7SDaniel P. Berrangepcnet_aprom_readb(void *opaque, uint32_t addr, uint32_t val) "opaque=%p addr=0x%08x val=0x%02x" 60db73ee4bSVladimir Sementsov-Ogievskiypcnet_ioport_read(void *opaque, uint64_t addr, unsigned size) "opaque=%p addr=0x%"PRIx64" size=%d" 61db73ee4bSVladimir Sementsov-Ogievskiypcnet_ioport_write(void *opaque, uint64_t addr, uint64_t data, unsigned size) "opaque=%p addr=0x%"PRIx64" data=0x%"PRIx64" size=%d" 62cd8c2fe7SDaniel P. Berrange 63500016e5SMarkus Armbruster# net_rx_pkt.c 64cd8c2fe7SDaniel P. Berrangenet_rx_pkt_parsed(bool ip4, bool ip6, bool udp, bool tcp, size_t l3o, size_t l4o, size_t l5o) "RX packet parsed: ip4: %d, ip6: %d, udp: %d, tcp: %d, l3 offset: %zu, l4 offset: %zu, l5 offset: %zu" 65cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l4_csum_validate_entry(void) "Starting L4 checksum validation" 66cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l4_csum_validate_not_xxp(void) "Not a TCP/UDP packet" 67cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l4_csum_validate_udp_with_no_checksum(void) "UDP packet without checksum" 68cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l4_csum_validate_ip4_fragment(void) "IP4 fragment" 69cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l4_csum_validate_csum(bool csum_valid) "Checksum valid: %d" 70cd8c2fe7SDaniel P. Berrange 71cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l4_csum_calc_entry(void) "Starting L4 checksum calculation" 72cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l4_csum_calc_ip4_udp(void) "IP4/UDP packet" 73cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l4_csum_calc_ip4_tcp(void) "IP4/TCP packet" 74cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l4_csum_calc_ip6_udp(void) "IP6/UDP packet" 75cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l4_csum_calc_ip6_tcp(void) "IP6/TCP packet" 76cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l4_csum_calc_ph_csum(uint32_t cntr, uint16_t csl) "Pseudo-header: checksum counter %u, length %u" 77cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l4_csum_calc_csum(size_t l4hdr_off, uint16_t csl, uint32_t cntr, uint16_t csum) "L4 Checksum: L4 header offset: %zu, length: %u, counter: 0x%X, final checksum: 0x%X" 78cd8c2fe7SDaniel P. Berrange 79cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l4_csum_fix_entry(void) "Starting L4 checksum correction" 80cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l4_csum_fix_tcp(uint32_t l4_cso) "TCP packet, L4 cso: %u" 81cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l4_csum_fix_udp(uint32_t l4_cso) "UDP packet, L4 cso: %u" 82cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l4_csum_fix_not_xxp(void) "Not an IP4 packet" 83cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l4_csum_fix_ip4_fragment(void) "IP4 fragment" 84cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l4_csum_fix_udp_with_no_checksum(void) "UDP packet without checksum" 85cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l4_csum_fix_csum(uint32_t cso, uint16_t csum) "L4 Checksum: Offset: %u, value 0x%X" 86cd8c2fe7SDaniel P. Berrange 87cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l3_csum_validate_entry(void) "Starting L3 checksum validation" 88cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l3_csum_validate_not_ip4(void) "Not an IP4 packet" 89cd8c2fe7SDaniel P. Berrangenet_rx_pkt_l3_csum_validate_csum(size_t l3hdr_off, uint32_t csl, uint32_t cntr, uint16_t csum, bool csum_valid) "L3 Checksum: L3 header offset: %zu, length: %u, counter: 0x%X, final checksum: 0x%X, valid: %d" 90cd8c2fe7SDaniel P. Berrange 91cd8c2fe7SDaniel P. Berrangenet_rx_pkt_rss_ip4(void) "Calculating IPv4 RSS hash" 92cd8c2fe7SDaniel P. Berrangenet_rx_pkt_rss_ip4_tcp(void) "Calculating IPv4/TCP RSS hash" 9333bbc05eSYuri Benditovichnet_rx_pkt_rss_ip4_udp(void) "Calculating IPv4/UDP RSS hash" 94cd8c2fe7SDaniel P. Berrangenet_rx_pkt_rss_ip6_tcp(void) "Calculating IPv6/TCP RSS hash" 9533bbc05eSYuri Benditovichnet_rx_pkt_rss_ip6_udp(void) "Calculating IPv6/UDP RSS hash" 96cd8c2fe7SDaniel P. Berrangenet_rx_pkt_rss_ip6(void) "Calculating IPv6 RSS hash" 97cd8c2fe7SDaniel P. Berrangenet_rx_pkt_rss_ip6_ex(void) "Calculating IPv6/EX RSS hash" 9833bbc05eSYuri Benditovichnet_rx_pkt_rss_ip6_ex_tcp(void) "Calculating IPv6/EX/TCP RSS hash" 9933bbc05eSYuri Benditovichnet_rx_pkt_rss_ip6_ex_udp(void) "Calculating IPv6/EX/UDP RSS hash" 100cd8c2fe7SDaniel P. Berrangenet_rx_pkt_rss_hash(size_t rss_length, uint32_t rss_hash) "RSS hash for %zu bytes: 0x%X" 101cd8c2fe7SDaniel P. Berrangenet_rx_pkt_rss_add_chunk(void* ptr, size_t size, size_t input_offset) "Add RSS chunk %p, %zu bytes, RSS input offset %zu bytes" 102cd8c2fe7SDaniel P. Berrange 103500016e5SMarkus Armbruster# e1000.c 1041001cf45SJason Wange1000_receiver_overrun(size_t s, uint32_t rdh, uint32_t rdt) "Receiver overrun: dropped packet of %zu bytes, RDH=%u, RDT=%u" 1051001cf45SJason Wang 106500016e5SMarkus Armbruster# e1000x_common.c 107cd8c2fe7SDaniel P. Berrangee1000x_rx_can_recv_disabled(bool link_up, bool rx_enabled, bool pci_master) "link_up: %d, rx_enabled %d, pci_master %d" 108cd8c2fe7SDaniel P. Berrangee1000x_vlan_is_vlan_pkt(bool is_vlan_pkt, uint16_t eth_proto, uint16_t vet) "Is VLAN packet: %d, ETH proto: 0x%X, VET: 0x%X" 109cd8c2fe7SDaniel P. Berrangee1000x_rx_flt_ucast_match(uint32_t idx, uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x" 110cd8c2fe7SDaniel P. Berrangee1000x_rx_flt_ucast_mismatch(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x" 1118908eb1aSVladimir Sementsov-Ogievskiye1000x_rx_flt_inexact_mismatch(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5, uint32_t mo, uint32_t mta, uint32_t mta_val) "inexact mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] 0x%x" 112cd8c2fe7SDaniel P. Berrangee1000x_rx_link_down(uint32_t status_reg) "Received packet dropped because the link is down STATUS = %u" 113cd8c2fe7SDaniel P. Berrangee1000x_rx_disabled(uint32_t rctl_reg) "Received packet dropped because receive is disabled RCTL = %u" 114cd8c2fe7SDaniel P. Berrangee1000x_rx_oversized(size_t size) "Received packet dropped because it was oversized (%zu bytes)" 115cd8c2fe7SDaniel P. Berrangee1000x_mac_indicate(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "Indicating MAC to guest: %02x:%02x:%02x:%02x:%02x:%02x" 116cd8c2fe7SDaniel P. Berrangee1000x_link_negotiation_start(void) "Start link auto negotiation" 117cd8c2fe7SDaniel P. Berrangee1000x_link_negotiation_done(void) "Auto negotiation is completed" 118cd8c2fe7SDaniel P. Berrange 119500016e5SMarkus Armbruster# e1000e_core.c 120cd8c2fe7SDaniel P. Berrangee1000e_core_write(uint64_t index, uint32_t size, uint64_t val) "Write to register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64 121cd8c2fe7SDaniel P. Berrangee1000e_core_read(uint64_t index, uint32_t size, uint64_t val) "Read from register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64 122cd8c2fe7SDaniel P. Berrangee1000e_core_mdic_read(uint8_t page, uint32_t addr, uint32_t data) "MDIC READ: PHY[%u][%u] = 0x%x" 123cd8c2fe7SDaniel P. Berrangee1000e_core_mdic_read_unhandled(uint8_t page, uint32_t addr) "MDIC READ: PHY[%u][%u] UNHANDLED" 124cd8c2fe7SDaniel P. Berrangee1000e_core_mdic_write(uint8_t page, uint32_t addr, uint32_t data) "MDIC WRITE: PHY[%u][%u] = 0x%x" 125cd8c2fe7SDaniel P. Berrangee1000e_core_mdic_write_unhandled(uint8_t page, uint32_t addr) "MDIC WRITE: PHY[%u][%u] UNHANDLED" 126cd8c2fe7SDaniel P. Berrangee1000e_core_ctrl_write(uint64_t index, uint32_t val) "Write CTRL register 0x%"PRIx64", value: 0x%X" 127cd8c2fe7SDaniel P. Berrangee1000e_core_ctrl_sw_reset(void) "Doing SW reset" 128cd8c2fe7SDaniel P. Berrangee1000e_core_ctrl_phy_reset(void) "Doing PHY reset" 129cd8c2fe7SDaniel P. Berrange 130cd8c2fe7SDaniel P. Berrangee1000e_link_autoneg_flowctl(bool enabled) "Auto-negotiated flow control state is %d" 131cd8c2fe7SDaniel P. Berrangee1000e_link_set_params(bool autodetect, uint32_t speed, bool force_spd, bool force_dplx, bool rx_fctl, bool tx_fctl) "Set link params: Autodetect: %d, Speed: %d, Force speed: %d, Force duplex: %d, RX flow control %d, TX flow control %d" 132cd8c2fe7SDaniel P. Berrangee1000e_link_read_params(bool autodetect, uint32_t speed, bool force_spd, bool force_dplx, bool rx_fctl, bool tx_fctl) "Get link params: Autodetect: %d, Speed: %d, Force speed: %d, Force duplex: %d, RX flow control %d, TX flow control %d" 133cd8c2fe7SDaniel P. Berrangee1000e_link_set_ext_params(bool asd_check, bool speed_select_bypass) "Set extended link params: ASD check: %d, Speed select bypass: %d" 134cd8c2fe7SDaniel P. Berrangee1000e_link_status(bool link_up, bool full_dplx, uint32_t speed, uint32_t asdv) "Link up: %d, Duplex: %d, Speed: %d, ASDV: %d" 135cd8c2fe7SDaniel P. Berrangee1000e_link_status_changed(bool status) "New link status: %d" 136cd8c2fe7SDaniel P. Berrange 137cd8c2fe7SDaniel P. Berrangee1000e_wrn_regs_write_ro(uint64_t index, uint32_t size, uint64_t val) "WARNING: Write to RO register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64 138cd8c2fe7SDaniel P. Berrangee1000e_wrn_regs_write_unknown(uint64_t index, uint32_t size, uint64_t val) "WARNING: Write to unknown register 0x%"PRIx64", %d byte(s), value: 0x%"PRIx64 139cd8c2fe7SDaniel P. Berrangee1000e_wrn_regs_read_unknown(uint64_t index, uint32_t size) "WARNING: Read from unknown register 0x%"PRIx64", %d byte(s)" 140cd8c2fe7SDaniel P. Berrangee1000e_wrn_regs_read_trivial(uint32_t index) "WARNING: Reading register at offset: 0x%05x. It is not fully implemented." 141cd8c2fe7SDaniel P. Berrangee1000e_wrn_regs_write_trivial(uint32_t index) "WARNING: Writing to register at offset: 0x%05x. It is not fully implemented." 142cd8c2fe7SDaniel P. Berrangee1000e_wrn_no_ts_support(void) "WARNING: Guest requested TX timestamping which is not supported" 143cd8c2fe7SDaniel P. Berrangee1000e_wrn_no_snap_support(void) "WARNING: Guest requested TX SNAP header update which is not supported" 144cd8c2fe7SDaniel P. Berrangee1000e_wrn_iscsi_filtering_not_supported(void) "WARNING: Guest requested iSCSI filtering which is not supported" 145cd8c2fe7SDaniel P. Berrangee1000e_wrn_nfsw_filtering_not_supported(void) "WARNING: Guest requested NFS write filtering which is not supported" 146cd8c2fe7SDaniel P. Berrangee1000e_wrn_nfsr_filtering_not_supported(void) "WARNING: Guest requested NFS read filtering which is not supported" 147cd8c2fe7SDaniel P. Berrange 148cd8c2fe7SDaniel P. Berrangee1000e_tx_disabled(void) "TX Disabled" 149cd8c2fe7SDaniel P. Berrangee1000e_tx_descr(void *addr, uint32_t lower, uint32_t upper) "%p : %x %x" 150cd8c2fe7SDaniel P. Berrange 151cd8c2fe7SDaniel P. Berrangee1000e_ring_free_space(int ridx, uint32_t rdlen, uint32_t rdh, uint32_t rdt) "ring #%d: LEN: %u, DH: %u, DT: %u" 152cd8c2fe7SDaniel P. Berrange 153cd8c2fe7SDaniel P. Berrangee1000e_rx_can_recv_rings_full(void) "Cannot receive: all rings are full" 154cd8c2fe7SDaniel P. Berrangee1000e_rx_can_recv(void) "Can receive" 155cd8c2fe7SDaniel P. Berrangee1000e_rx_has_buffers(int ridx, uint32_t free_desc, size_t total_size, uint32_t desc_buf_size) "ring #%d: free descr: %u, packet size %zu, descr buffer size %u" 156cd8c2fe7SDaniel P. Berrangee1000e_rx_null_descriptor(void) "Null RX descriptor!!" 157cd8c2fe7SDaniel P. Berrangee1000e_rx_flt_vlan_mismatch(uint16_t vid) "VID mismatch: 0x%X" 158cd8c2fe7SDaniel P. Berrangee1000e_rx_flt_vlan_match(uint16_t vid) "VID match: 0x%X" 159cd8c2fe7SDaniel P. Berrangee1000e_rx_desc_ps_read(uint64_t a0, uint64_t a1, uint64_t a2, uint64_t a3) "buffers: [0x%"PRIx64", 0x%"PRIx64", 0x%"PRIx64", 0x%"PRIx64"]" 160cd8c2fe7SDaniel P. Berrangee1000e_rx_desc_ps_write(uint16_t a0, uint16_t a1, uint16_t a2, uint16_t a3) "bytes written: [%u, %u, %u, %u]" 161cd8c2fe7SDaniel P. Berrangee1000e_rx_desc_buff_sizes(uint32_t b0, uint32_t b1, uint32_t b2, uint32_t b3) "buffer sizes: [%u, %u, %u, %u]" 162cd8c2fe7SDaniel P. Berrangee1000e_rx_desc_len(uint8_t rx_desc_len) "RX descriptor length: %u" 163cd8c2fe7SDaniel P. Berrangee1000e_rx_desc_buff_write(uint8_t idx, uint64_t addr, uint16_t offset, const void* source, uint32_t len) "buffer #%u, addr: 0x%"PRIx64", offset: %u, from: %p, length: %u" 164cd8c2fe7SDaniel P. Berrangee1000e_rx_descr(int ridx, uint64_t base, uint8_t len) "Next RX descriptor: ring #%d, PA: 0x%"PRIx64", length: %u" 165cd8c2fe7SDaniel P. Berrangee1000e_rx_set_rctl(uint32_t rctl) "RCTL = 0x%x" 166cd8c2fe7SDaniel P. Berrangee1000e_rx_receive_iov(int iovcnt) "Received vector of %d fragments" 167cd8c2fe7SDaniel P. Berrangee1000e_rx_flt_dropped(void) "Received packet dropped by RX filter" 168*bf2a7212SAkihiko Odakie1000e_rx_written_to_guest(int queue_idx) "Received packet written to guest (queue %d)" 169*bf2a7212SAkihiko Odakie1000e_rx_not_written_to_guest(int queue_idx) "Received packet NOT written to guest (queue %d)" 170cd8c2fe7SDaniel P. Berrangee1000e_rx_interrupt_set(uint32_t causes) "Receive interrupt set (ICR causes %u)" 171cd8c2fe7SDaniel P. Berrangee1000e_rx_interrupt_delayed(uint32_t causes) "Receive interrupt delayed (ICR causes %u)" 172cd8c2fe7SDaniel P. Berrangee1000e_rx_set_cso(int cso_state) "RX CSO state set to %d" 173cd8c2fe7SDaniel P. Berrangee1000e_rx_set_rdt(int queue_idx, uint32_t val) "Setting RDT[%d] = %u" 174cd8c2fe7SDaniel P. Berrangee1000e_rx_set_rfctl(uint32_t val) "Setting RFCTL = 0x%X" 175cd8c2fe7SDaniel P. Berrangee1000e_rx_start_recv(void) 176cd8c2fe7SDaniel P. Berrange 177cd8c2fe7SDaniel P. Berrangee1000e_rx_rss_started(void) "Starting RSS processing" 178cd8c2fe7SDaniel P. Berrangee1000e_rx_rss_disabled(void) "RSS is disabled" 179cd8c2fe7SDaniel P. Berrangee1000e_rx_rss_type(uint32_t type) "RSS type is %u" 180cd8c2fe7SDaniel P. Berrangee1000e_rx_rss_ip4(bool isfragment, bool istcp, uint32_t mrqc, bool tcpipv4_enabled, bool ipv4_enabled) "RSS IPv4: fragment %d, tcp %d, mrqc 0x%X, tcpipv4 enabled %d, ipv4 enabled %d" 181cd8c2fe7SDaniel P. Berrangee1000e_rx_rss_ip6_rfctl(uint32_t rfctl) "RSS IPv6: rfctl 0x%X" 182cd8c2fe7SDaniel P. Berrangee1000e_rx_rss_ip6(bool ex_dis, bool new_ex_dis, bool istcp, bool has_ext_headers, bool ex_dst_valid, bool ex_src_valid, uint32_t mrqc, bool tcpipv6_enabled, bool ipv6ex_enabled, bool ipv6_enabled) "RSS IPv6: ex_dis: %d, new_ex_dis: %d, tcp %d, has_ext_headers %d, ex_dst_valid %d, ex_src_valid %d, mrqc 0x%X, tcpipv6 enabled %d, ipv6ex enabled %d, ipv6 enabled %d" 183cd8c2fe7SDaniel P. Berrange 184cd8c2fe7SDaniel P. Berrangee1000e_rx_metadata_protocols(bool isip4, bool isip6, bool isudp, bool istcp) "protocols: ip4: %d, ip6: %d, udp: %d, tcp: %d" 185cd8c2fe7SDaniel P. Berrangee1000e_rx_metadata_vlan(uint16_t vlan_tag) "VLAN tag is 0x%X" 186cd8c2fe7SDaniel P. Berrangee1000e_rx_metadata_rss(uint32_t rss, uint32_t mrq) "RSS data: rss: 0x%X, mrq: 0x%X" 187cd8c2fe7SDaniel P. Berrangee1000e_rx_metadata_ip_id(uint16_t ip_id) "the IPv4 ID is 0x%X" 188cd8c2fe7SDaniel P. Berrangee1000e_rx_metadata_ack(void) "the packet is TCP ACK" 189cd8c2fe7SDaniel P. Berrangee1000e_rx_metadata_pkt_type(uint32_t pkt_type) "the packet type is %u" 190cd8c2fe7SDaniel P. Berrangee1000e_rx_metadata_virthdr_no_csum_info(void) "virt-header does not contain checksum info" 191cd8c2fe7SDaniel P. Berrangee1000e_rx_metadata_l3_cso_disabled(void) "IP4 CSO is disabled" 192cd8c2fe7SDaniel P. Berrangee1000e_rx_metadata_l4_cso_disabled(void) "TCP/UDP CSO is disabled" 193cd8c2fe7SDaniel P. Berrangee1000e_rx_metadata_l3_csum_validation_failed(void) "Cannot validate L3 checksum" 194cd8c2fe7SDaniel P. Berrangee1000e_rx_metadata_l4_csum_validation_failed(void) "Cannot validate L4 checksum" 195cd8c2fe7SDaniel P. Berrangee1000e_rx_metadata_status_flags(uint32_t status_flags) "status_flags is 0x%X" 196cd8c2fe7SDaniel P. Berrangee1000e_rx_metadata_ipv6_sum_disabled(void) "IPv6 RX checksummimg disabled by RFCTL" 197cd8c2fe7SDaniel P. Berrangee1000e_rx_metadata_ipv6_filtering_disabled(void) "IPv6 RX filtering disabled by RFCTL" 198cd8c2fe7SDaniel P. Berrange 199cd8c2fe7SDaniel P. Berrangee1000e_vlan_vet(uint16_t vet) "Setting VLAN ethernet type 0x%X" 200cd8c2fe7SDaniel P. Berrange 201cd8c2fe7SDaniel P. Berrangee1000e_irq_msi_notify(uint32_t cause) "MSI notify 0x%x" 202cd8c2fe7SDaniel P. Berrangee1000e_irq_msi_notify_postponed(void) "Sending MSI postponed by ITR" 203cd8c2fe7SDaniel P. Berrangee1000e_irq_legacy_notify_postponed(void) "Raising legacy IRQ postponed by ITR" 204cd8c2fe7SDaniel P. Berrangee1000e_irq_msix_notify_postponed_vec(int idx) "Sending MSI-X postponed by EITR[%d]" 205cd8c2fe7SDaniel P. Berrangee1000e_irq_legacy_notify(bool level) "IRQ line state: %d" 206cd8c2fe7SDaniel P. Berrangee1000e_irq_msix_notify_vec(uint32_t vector) "MSI-X notify vector 0x%x" 207cd8c2fe7SDaniel P. Berrangee1000e_irq_postponed_by_xitr(uint32_t reg) "Interrupt postponed by [E]ITR register 0x%x" 208cd8c2fe7SDaniel P. Berrangee1000e_irq_clear_ims(uint32_t bits, uint32_t old_ims, uint32_t new_ims) "Clearing IMS bits 0x%x: 0x%x --> 0x%x" 209cd8c2fe7SDaniel P. Berrangee1000e_irq_set_ims(uint32_t bits, uint32_t old_ims, uint32_t new_ims) "Setting IMS bits 0x%x: 0x%x --> 0x%x" 210cd8c2fe7SDaniel P. Berrangee1000e_irq_fix_icr_asserted(uint32_t new_val) "ICR_ASSERTED bit fixed: 0x%x" 211cd8c2fe7SDaniel P. Berrangee1000e_irq_add_msi_other(uint32_t new_val) "ICR_OTHER bit added: 0x%x" 212cd8c2fe7SDaniel P. Berrangee1000e_irq_pending_interrupts(uint32_t pending, uint32_t icr, uint32_t ims) "ICR PENDING: 0x%x (ICR: 0x%x, IMS: 0x%x)" 213cd8c2fe7SDaniel P. Berrangee1000e_irq_set_cause_entry(uint32_t val, uint32_t icr) "Going to set IRQ cause 0x%x, ICR: 0x%x" 214cd8c2fe7SDaniel P. Berrangee1000e_irq_set_cause_exit(uint32_t val, uint32_t icr) "Set IRQ cause 0x%x, ICR: 0x%x" 215cd8c2fe7SDaniel P. Berrangee1000e_irq_icr_write(uint32_t bits, uint32_t old_icr, uint32_t new_icr) "Clearing ICR bits 0x%x: 0x%x --> 0x%x" 216cd8c2fe7SDaniel P. Berrangee1000e_irq_write_ics(uint32_t val) "Adding ICR bits 0x%x" 217cd8c2fe7SDaniel P. Berrangee1000e_irq_icr_process_iame(void) "Clearing IMS bits due to IAME" 218cd8c2fe7SDaniel P. Berrangee1000e_irq_read_ics(uint32_t ics) "Current ICS: 0x%x" 219cd8c2fe7SDaniel P. Berrangee1000e_irq_read_ims(uint32_t ims) "Current IMS: 0x%x" 22087037421SNick Hudsone1000e_irq_icr_clear_nonmsix_icr_read(void) "Clearing ICR on read due to non MSI-X int" 221cd8c2fe7SDaniel P. Berrangee1000e_irq_icr_read_entry(uint32_t icr) "Starting ICR read. Current ICR: 0x%x" 222cd8c2fe7SDaniel P. Berrangee1000e_irq_icr_read_exit(uint32_t icr) "Ending ICR read. Current ICR: 0x%x" 223cd8c2fe7SDaniel P. Berrangee1000e_irq_icr_clear_zero_ims(void) "Clearing ICR on read due to zero IMS" 224cd8c2fe7SDaniel P. Berrangee1000e_irq_icr_clear_iame(void) "Clearing ICR on read due to IAME" 2252d803144SDmitry Fleytmane1000e_irq_iam_clear_eiame(uint32_t iam, uint32_t cause) "Clearing IMS due to EIAME, IAM: 0x%X, cause: 0x%X" 226cd8c2fe7SDaniel P. Berrangee1000e_irq_icr_clear_eiac(uint32_t icr, uint32_t eiac) "Clearing ICR bits due to EIAC, ICR: 0x%X, EIAC: 0x%X" 227cd8c2fe7SDaniel P. Berrangee1000e_irq_ims_clear_set_imc(uint32_t val) "Clearing IMS bits due to IMC write 0x%x" 228cd8c2fe7SDaniel P. Berrangee1000e_irq_fire_delayed_interrupts(void) "Firing delayed interrupts" 229cd8c2fe7SDaniel P. Berrangee1000e_irq_rearm_timer(uint32_t reg, int64_t delay_ns) "Mitigation timer armed for register 0x%X, delay %"PRId64" ns" 230cd8c2fe7SDaniel P. Berrangee1000e_irq_throttling_timer(uint32_t reg) "Mitigation timer shot for register 0x%X" 231cd8c2fe7SDaniel P. Berrangee1000e_irq_rdtr_fpd_running(void) "FPD written while RDTR was running" 232cd8c2fe7SDaniel P. Berrangee1000e_irq_rdtr_fpd_not_running(void) "FPD written while RDTR was not running" 233cd8c2fe7SDaniel P. Berrangee1000e_irq_tidv_fpd_running(void) "FPD written while TIDV was running" 234cd8c2fe7SDaniel P. Berrangee1000e_irq_tidv_fpd_not_running(void) "FPD written while TIDV was not running" 235cd8c2fe7SDaniel P. Berrangee1000e_irq_eitr_set(uint32_t eitr_num, uint32_t val) "EITR[%u] = %u" 236cd8c2fe7SDaniel P. Berrangee1000e_irq_itr_set(uint32_t val) "ITR = %u" 237cd8c2fe7SDaniel P. Berrangee1000e_irq_fire_all_timers(uint32_t val) "Firing all delay/throttling timers on all interrupts enable (0x%X written to IMS)" 238cd8c2fe7SDaniel P. Berrangee1000e_irq_adding_delayed_causes(uint32_t val, uint32_t icr) "Merging delayed causes 0x%X to ICR 0x%X" 239cd8c2fe7SDaniel P. Berrangee1000e_irq_msix_pending_clearing(uint32_t cause, uint32_t int_cfg, uint32_t vec) "Clearing MSI-X pending bit for cause 0x%x, IVAR config 0x%x, vector %u" 240cd8c2fe7SDaniel P. Berrange 241cd8c2fe7SDaniel P. Berrangee1000e_wrn_msix_vec_wrong(uint32_t cause, uint32_t cfg) "Invalid configuration for cause 0x%x: 0x%x" 242cd8c2fe7SDaniel P. Berrangee1000e_wrn_msix_invalid(uint32_t cause, uint32_t cfg) "Invalid entry for cause 0x%x: 0x%x" 243cd8c2fe7SDaniel P. Berrange 244cd8c2fe7SDaniel P. Berrangee1000e_mac_set_sw(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "Set SW MAC: %02x:%02x:%02x:%02x:%02x:%02x" 245cd8c2fe7SDaniel P. Berrange 246dec97760SMarkus Armbrustere1000e_vm_state_running(void) "VM state is running" 247dec97760SMarkus Armbrustere1000e_vm_state_stopped(void) "VM state is stopped" 248dec97760SMarkus Armbruster 249500016e5SMarkus Armbruster# e1000e.c 250cd8c2fe7SDaniel P. Berrangee1000e_cb_pci_realize(void) "E1000E PCI realize entry" 251cd8c2fe7SDaniel P. Berrangee1000e_cb_pci_uninit(void) "E1000E PCI unit entry" 2528a35c648SAkihiko Odakie1000e_cb_qdev_reset_hold(void) "E1000E qdev reset hold" 253cd8c2fe7SDaniel P. Berrangee1000e_cb_pre_save(void) "E1000E pre save entry" 254cd8c2fe7SDaniel P. Berrangee1000e_cb_post_load(void) "E1000E post load entry" 255cd8c2fe7SDaniel P. Berrange 256cd8c2fe7SDaniel P. Berrangee1000e_io_write_addr(uint64_t addr) "IOADDR write 0x%"PRIx64 257cd8c2fe7SDaniel P. Berrangee1000e_io_write_data(uint64_t addr, uint64_t val) "IODATA write 0x%"PRIx64", value: 0x%"PRIx64 258cd8c2fe7SDaniel P. Berrangee1000e_io_read_addr(uint64_t addr) "IOADDR read 0x%"PRIx64 259cd8c2fe7SDaniel P. Berrangee1000e_io_read_data(uint64_t addr, uint64_t val) "IODATA read 0x%"PRIx64", value: 0x%"PRIx64 260cd8c2fe7SDaniel P. Berrangee1000e_wrn_io_write_unknown(uint64_t addr) "IO write unknown address 0x%"PRIx64 261cd8c2fe7SDaniel P. Berrangee1000e_wrn_io_read_unknown(uint64_t addr) "IO read unknown address 0x%"PRIx64 262cd8c2fe7SDaniel P. Berrangee1000e_wrn_io_addr_undefined(uint64_t addr) "IO undefined register 0x%"PRIx64 263cd8c2fe7SDaniel P. Berrangee1000e_wrn_io_addr_flash(uint64_t addr) "IO flash access (0x%"PRIx64") not implemented" 264cd8c2fe7SDaniel P. Berrangee1000e_wrn_io_addr_unknown(uint64_t addr) "IO unknown register 0x%"PRIx64 265cd8c2fe7SDaniel P. Berrange 266cd8c2fe7SDaniel P. Berrangee1000e_msi_init_fail(int32_t res) "Failed to initialize MSI, error %d" 267cd8c2fe7SDaniel P. Berrangee1000e_msix_init_fail(int32_t res) "Failed to initialize MSI-X, error %d" 268cd8c2fe7SDaniel P. Berrangee1000e_msix_use_vector_fail(uint32_t vec, int32_t res) "Failed to use MSI-X vector %d, error %d" 269cd8c2fe7SDaniel P. Berrange 270dec97760SMarkus Armbrustere1000e_mac_set_permanent(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "Set permanent MAC: %02x:%02x:%02x:%02x:%02x:%02x" 271cd8c2fe7SDaniel P. Berrangee1000e_cfg_support_virtio(bool support) "Virtio header supported: %d" 272cd8c2fe7SDaniel P. Berrange 273500016e5SMarkus Armbruster# spapr_llan.c 274e8bb33deSLaurent Vivierspapr_vlan_get_rx_bd_from_pool_found(int pool, int32_t count, uint32_t rx_bufs) "pool=%d count=%"PRId32" rxbufs=%"PRIu32 275e8bb33deSLaurent Vivierspapr_vlan_get_rx_bd_from_page(int buf_ptr, uint64_t bd) "use_buf_ptr=%d bd=0x%016"PRIx64 276e8bb33deSLaurent Vivierspapr_vlan_get_rx_bd_from_page_found(uint32_t use_buf_ptr, uint32_t rx_bufs) "ptr=%"PRIu32" rxbufs=%"PRIu32 277e8bb33deSLaurent Vivierspapr_vlan_receive(const char *id, uint32_t rx_bufs) "[%s] rx_bufs=%"PRIu32 278e8bb33deSLaurent Vivierspapr_vlan_receive_dma_completed(void) "DMA write completed" 279e8bb33deSLaurent Vivierspapr_vlan_receive_wrote(uint64_t ptr, uint64_t hi, uint64_t lo) "rxq entry (ptr=0x%"PRIx64"): 0x%016"PRIx64" 0x%016"PRIx64 280e8bb33deSLaurent Vivierspapr_vlan_add_rxbuf_to_pool_create(int pool, uint64_t len) "created RX pool %d for size %"PRIu64 281e8bb33deSLaurent Vivierspapr_vlan_add_rxbuf_to_pool(int pool, uint64_t len, int32_t count) "add buf using pool %d (size %"PRIu64", count=%"PRId32")" 282e8bb33deSLaurent Vivierspapr_vlan_add_rxbuf_to_page(uint32_t ptr, uint32_t rx_bufs, uint64_t bd) "added buf ptr=%"PRIu32" rx_bufs=%"PRIu32" bd=0x%016"PRIx64 283e8bb33deSLaurent Vivierspapr_vlan_h_add_logical_lan_buffer(uint64_t reg, uint64_t buf) "H_ADD_LOGICAL_LAN_BUFFER(0x%"PRIx64", 0x%"PRIx64")" 284e8bb33deSLaurent Vivierspapr_vlan_h_send_logical_lan(uint64_t reg, uint64_t continue_token) "H_SEND_LOGICAL_LAN(0x%"PRIx64", <bufs>, 0x%"PRIx64")" 285e8bb33deSLaurent Vivierspapr_vlan_h_send_logical_lan_rxbufs(uint32_t rx_bufs) "rxbufs = %"PRIu32 286e8bb33deSLaurent Vivierspapr_vlan_h_send_logical_lan_buf_desc(uint64_t buf) " buf desc: 0x%"PRIx64 287e8bb33deSLaurent Vivierspapr_vlan_h_send_logical_lan_total(int nbufs, unsigned total_len) "%d buffers, total length 0x%x" 288f85504b2SBenjamin Herrenschmidt 289500016e5SMarkus Armbruster# sungem.c 290f85504b2SBenjamin Herrenschmidtsungem_tx_checksum(uint16_t start, uint16_t off) "TX checksumming from byte %d, inserting at %d" 291f85504b2SBenjamin Herrenschmidtsungem_tx_checksum_oob(void) "TX checksum out of packet bounds" 292f85504b2SBenjamin Herrenschmidtsungem_tx_unfinished(void) "TX packet started without finishing the previous one" 293f85504b2SBenjamin Herrenschmidtsungem_tx_overflow(void) "TX packet queue overflow" 294f85504b2SBenjamin Herrenschmidtsungem_tx_finished(uint32_t size) "TX completing %"PRIu32 " bytes packet" 295f85504b2SBenjamin Herrenschmidtsungem_tx_kick(void) "TX Kick..." 296f85504b2SBenjamin Herrenschmidtsungem_tx_disabled(void) "TX not enabled" 297f85504b2SBenjamin Herrenschmidtsungem_tx_process(uint32_t comp, uint32_t kick, uint32_t size) "TX processing comp=%"PRIu32", kick=%"PRIu32" out of %"PRIu32 298f85504b2SBenjamin Herrenschmidtsungem_tx_desc(uint32_t comp, uint64_t control, uint64_t buffer) "TX desc %"PRIu32 ": 0x%"PRIx64" 0x%"PRIx64 299f85504b2SBenjamin Herrenschmidtsungem_tx_reset(void) "TX reset" 300f85504b2SBenjamin Herrenschmidtsungem_rx_mac_disabled(void) "Check RX MAC disabled" 301f85504b2SBenjamin Herrenschmidtsungem_rx_txdma_disabled(void) "Check RX TXDMA disabled" 302f85504b2SBenjamin Herrenschmidtsungem_rx_check(bool full, uint32_t kick, uint32_t done) "Check RX %d (kick=%"PRIu32", done=%"PRIu32")" 303f85504b2SBenjamin Herrenschmidtsungem_rx_mac_check(uint32_t mac0, uint32_t mac1, uint32_t mac2) "Word MAC: 0x%"PRIx32" 0x%"PRIx32" 0x%"PRIx32 304f85504b2SBenjamin Herrenschmidtsungem_rx_mac_multicast(void) "Multicast" 305f85504b2SBenjamin Herrenschmidtsungem_rx_mac_compare(uint32_t mac0, uint32_t mac1, uint32_t mac2) "Compare MAC to 0x%"PRIx32" 0x%"PRIx32" 0x%"PRIx32".." 306f85504b2SBenjamin Herrenschmidtsungem_rx_packet(size_t size) "RX got %zu bytes packet" 307f85504b2SBenjamin Herrenschmidtsungem_rx_disabled(void) "RX not enabled" 308f85504b2SBenjamin Herrenschmidtsungem_rx_bad_frame_size(size_t size) "RX bad frame size %zu, dropped" 309f85504b2SBenjamin Herrenschmidtsungem_rx_unmatched(void) "No match, dropped" 310f85504b2SBenjamin Herrenschmidtsungem_rx_process(uint32_t done, uint32_t kick, uint32_t size) "RX processing done=%"PRIu32", kick=%"PRIu32" out of %"PRIu32 311f85504b2SBenjamin Herrenschmidtsungem_rx_ringfull(void) "RX ring full" 312f85504b2SBenjamin Herrenschmidtsungem_rx_desc(uint64_t control, uint64_t buffer) "RX desc: 0x%"PRIx64" 0x%"PRIx64 313f85504b2SBenjamin Herrenschmidtsungem_rx_reset(void) "RX reset" 314f85504b2SBenjamin Herrenschmidtsungem_rx_kick(uint64_t val) "RXDMA_KICK written to %"PRIu64 315f85504b2SBenjamin Herrenschmidtsungem_reset(bool pci_reset) "Full reset (PCI:%d)" 316f85504b2SBenjamin Herrenschmidtsungem_mii_write(uint8_t phy_addr, uint8_t reg_addr, uint16_t val) "MII write addr 0x%x reg 0x%02x val 0x%04x" 317f85504b2SBenjamin Herrenschmidtsungem_mii_read(uint8_t phy_addr, uint8_t reg_addr, uint16_t val) "MII read addr 0x%x reg 0x%02x val 0x%04x" 318f85504b2SBenjamin Herrenschmidtsungem_mii_invalid_sof(uint32_t val) "MII op, invalid SOF field 0x%"PRIx32 319f85504b2SBenjamin Herrenschmidtsungem_mii_invalid_op(uint8_t op) "MII op, invalid op field 0x%x" 320f85504b2SBenjamin Herrenschmidtsungem_mmio_greg_write(uint64_t addr, uint64_t val) "MMIO greg write to 0x%"PRIx64" val=0x%"PRIx64 321f85504b2SBenjamin Herrenschmidtsungem_mmio_greg_read(uint64_t addr, uint64_t val) "MMIO greg read from 0x%"PRIx64" val=0x%"PRIx64 322f85504b2SBenjamin Herrenschmidtsungem_mmio_txdma_write(uint64_t addr, uint64_t val) "MMIO txdma write to 0x%"PRIx64" val=0x%"PRIx64 323f85504b2SBenjamin Herrenschmidtsungem_mmio_txdma_read(uint64_t addr, uint64_t val) "MMIO txdma read from 0x%"PRIx64" val=0x%"PRIx64 324f85504b2SBenjamin Herrenschmidtsungem_mmio_rxdma_write(uint64_t addr, uint64_t val) "MMIO rxdma write to 0x%"PRIx64" val=0x%"PRIx64 325f85504b2SBenjamin Herrenschmidtsungem_mmio_rxdma_read(uint64_t addr, uint64_t val) "MMIO rxdma read from 0x%"PRIx64" val=0x%"PRIx64 326f85504b2SBenjamin Herrenschmidtsungem_mmio_mac_write(uint64_t addr, uint64_t val) "MMIO mac write to 0x%"PRIx64" val=0x%"PRIx64 327f85504b2SBenjamin Herrenschmidtsungem_mmio_mac_read(uint64_t addr, uint64_t val) "MMIO mac read from 0x%"PRIx64" val=0x%"PRIx64 328f85504b2SBenjamin Herrenschmidtsungem_mmio_mif_write(uint64_t addr, uint64_t val) "MMIO mif write to 0x%"PRIx64" val=0x%"PRIx64 329f85504b2SBenjamin Herrenschmidtsungem_mmio_mif_read(uint64_t addr, uint64_t val) "MMIO mif read from 0x%"PRIx64" val=0x%"PRIx64 330f85504b2SBenjamin Herrenschmidtsungem_mmio_pcs_write(uint64_t addr, uint64_t val) "MMIO pcs write to 0x%"PRIx64" val=0x%"PRIx64 331f85504b2SBenjamin Herrenschmidtsungem_mmio_pcs_read(uint64_t addr, uint64_t val) "MMIO pcs read from 0x%"PRIx64" val=0x%"PRIx64 332c110425dSMark Cave-Ayland 333500016e5SMarkus Armbruster# sunhme.c 334c110425dSMark Cave-Aylandsunhme_seb_write(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 335c110425dSMark Cave-Aylandsunhme_seb_read(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 336c110425dSMark Cave-Aylandsunhme_etx_write(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 337c110425dSMark Cave-Aylandsunhme_etx_read(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 338c110425dSMark Cave-Aylandsunhme_erx_write(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 339c110425dSMark Cave-Aylandsunhme_erx_read(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 340c110425dSMark Cave-Aylandsunhme_mac_write(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 341c110425dSMark Cave-Aylandsunhme_mac_read(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 342c110425dSMark Cave-Aylandsunhme_mii_write(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 343c110425dSMark Cave-Aylandsunhme_mii_read(uint8_t addr, uint16_t value) "addr 0x%x value 0x%x" 344c110425dSMark Cave-Aylandsunhme_mif_write(uint8_t addr, uint16_t value) "addr 0x%x value 0x%x" 345c110425dSMark Cave-Aylandsunhme_mif_read(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%"PRIx64 346c110425dSMark Cave-Aylandsunhme_tx_desc(uint64_t buffer, uint32_t status, int cr, int nr) "addr 0x%"PRIx64" status 0x%"PRIx32 " (ring %d/%d)" 347c110425dSMark Cave-Aylandsunhme_tx_xsum_add(int offset, int len) "adding xsum at offset %d, len %d" 348c110425dSMark Cave-Aylandsunhme_tx_xsum_stuff(uint16_t xsum, int offset) "stuffing xsum 0x%x at offset %d" 349c110425dSMark Cave-Aylandsunhme_tx_done(int len) "successfully transmitted frame with len %d" 350c110425dSMark Cave-Aylandsunhme_rx_incoming(size_t len) "received incoming frame with len %zu" 351c110425dSMark Cave-Aylandsunhme_rx_filter_destmac(uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5) "received frame for MAC: %02x:%02x:%02x:%02x:%02x:%02x" 352c110425dSMark Cave-Aylandsunhme_rx_filter_local_match(void) "incoming frame matches local MAC address" 353c110425dSMark Cave-Aylandsunhme_rx_filter_bcast_match(void) "incoming frame matches broadcast MAC address" 354c110425dSMark Cave-Aylandsunhme_rx_filter_hash_nomatch(void) "incoming MAC address not in hash table" 355c110425dSMark Cave-Aylandsunhme_rx_filter_hash_match(void) "incoming MAC address found in hash table" 356c110425dSMark Cave-Aylandsunhme_rx_filter_promisc_match(void) "incoming frame accepted due to promiscuous mode" 357c110425dSMark Cave-Aylandsunhme_rx_filter_reject(void) "rejecting incoming frame" 358c110425dSMark Cave-Aylandsunhme_rx_filter_accept(void) "accepting incoming frame" 359c110425dSMark Cave-Aylandsunhme_rx_desc(uint32_t addr, int offset, uint32_t status, int len, int cr, int nr) "addr 0x%"PRIx32"(+0x%x) status 0x%"PRIx32 " len %d (ring %d/%d)" 360c110425dSMark Cave-Aylandsunhme_rx_xsum_calc(uint16_t xsum) "calculated incoming xsum as 0x%x" 36109340f49SMark Cave-Aylandsunhme_rx_norxd(void) "no free rx descriptors available" 3626bdc3707SMark Cave-Aylandsunhme_update_irq(uint32_t mifmask, uint32_t mif, uint32_t sebmask, uint32_t seb, int level) "mifmask: 0x%x mif: 0x%x sebmask: 0x%x seb: 0x%x level: %d" 3639d8c6a25SDr. David Alan Gilbert 364500016e5SMarkus Armbruster# virtio-net.c 365b2c929f0SDr. David Alan Gilbertvirtio_net_announce_notify(void) "" 3669d8c6a25SDr. David Alan Gilbertvirtio_net_announce_timer(int round) "%d" 3679d8c6a25SDr. David Alan Gilbertvirtio_net_handle_announce(int round) "%d" 3689d8c6a25SDr. David Alan Gilbertvirtio_net_post_load_device(void) 36959079029SYuri Benditovichvirtio_net_rss_disable(void) 37059079029SYuri Benditovichvirtio_net_rss_error(const char *msg, uint32_t value) "%s, value 0x%08x" 37159079029SYuri Benditovichvirtio_net_rss_enable(uint32_t p1, uint16_t p2, uint8_t p3) "hashes 0x%x, table of %d, key of %d" 37234ea023dSSven Schnelle 37334ea023dSSven Schnelle# tulip.c 37434ea023dSSven Schnelletulip_reg_write(uint64_t addr, const char *name, int size, uint64_t val) "addr 0x%02"PRIx64" (%s) size %d value 0x%08"PRIx64 37534ea023dSSven Schnelletulip_reg_read(uint64_t addr, const char *name, int size, uint64_t val) "addr 0x%02"PRIx64" (%s) size %d value 0x%08"PRIx64 37634ea023dSSven Schnelletulip_receive(const uint8_t *buf, size_t len) "buf %p size %zu" 37734ea023dSSven Schnelletulip_descriptor(const char *prefix, uint32_t addr, uint32_t status, uint32_t control, uint32_t len1, uint32_t len2, uint32_t buf1, uint32_t buf2) "%s 0x%08x: status 0x%08x control 0x%03x len1 %4d len2 %4d buf1 0x%08x buf2 0x%08x" 37834ea023dSSven Schnelletulip_rx_state(const char *state) "RX %s" 37934ea023dSSven Schnelletulip_tx_state(const char *state) "TX %s" 38034ea023dSSven Schnelletulip_irq(uint32_t mask, uint32_t en, const char *state) "mask 0x%08x ie 0x%08x %s" 38134ea023dSSven Schnelletulip_mii_write(int phy, int reg, uint16_t data) "phy 0x%x reg 0x%x data 0x%04x" 38234ea023dSSven Schnelletulip_mii_read(int phy, int reg, uint16_t data) "phy 0x%x, reg 0x%x data 0x%04x" 38334ea023dSSven Schnelletulip_reset(void) "" 38434ea023dSSven Schnelletulip_setup_frame(void) "" 38534ea023dSSven Schnelletulip_setup_filter(int n, uint8_t a, uint8_t b, uint8_t c, uint8_t d, uint8_t e, uint8_t f) "%d: %02x:%02x:%02x:%02x:%02x:%02x" 386376b8519SHelge Deller 387376b8519SHelge Deller# lasi_i82596.c 388376b8519SHelge Dellerlasi_82596_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64" val=0x%04x" 389376b8519SHelge Dellerlasi_82596_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64" val=0x%04x" 390376b8519SHelge Deller 391376b8519SHelge Deller# i82596.c 392376b8519SHelge Delleri82596_s_reset(void *s) "%p Reset chip" 393376b8519SHelge Delleri82596_transmit(uint32_t size, uint32_t addr) "size %u from addr 0x%04x" 394376b8519SHelge Delleri82596_receive_analysis(const char *s) "%s" 395376b8519SHelge Delleri82596_receive_packet(size_t sz) "len=%zu" 396376b8519SHelge Delleri82596_new_mac(const char *id_with_mac) "New MAC for: %s" 397376b8519SHelge Delleri82596_set_multicast(uint16_t count) "Added %d multicast entries" 398376b8519SHelge Delleri82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION" 3998095508aSJean-Christophe Dubois 4008095508aSJean-Christophe Dubois# imx_fec.c 401461c51adSJean-Christophe Duboisimx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]" 402f607dce2SGuenter Roeckimx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)" 403461c51adSJean-Christophe Duboisimx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]" 404f607dce2SGuenter Roeckimx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)" 4058095508aSJean-Christophe Duboisimx_phy_update_link(const char *s) "%s" 4068095508aSJean-Christophe Duboisimx_phy_reset(void) "" 4078095508aSJean-Christophe Duboisimx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x" 4088095508aSJean-Christophe Duboisimx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x" 4098095508aSJean-Christophe Duboisimx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit" 4108095508aSJean-Christophe Duboisimx_eth_rx_bd_full(void) "RX buffer is full" 4118095508aSJean-Christophe Duboisimx_eth_read(int reg, const char *reg_name, uint32_t value) "reg[%d:%s] => 0x%08"PRIx32 4128095508aSJean-Christophe Duboisimx_eth_write(int reg, const char *reg_name, uint64_t value) "reg[%d:%s] <= 0x%08"PRIx64 4138095508aSJean-Christophe Duboisimx_fec_receive(size_t size) "len %zu" 4148095508aSJean-Christophe Duboisimx_fec_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d" 4158095508aSJean-Christophe Duboisimx_fec_receive_last(int last) "rx frame flags 0x%04x" 4168095508aSJean-Christophe Duboisimx_enet_receive(size_t size) "len %zu" 4178095508aSJean-Christophe Duboisimx_enet_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d" 4188095508aSJean-Christophe Duboisimx_enet_receive_last(int last) "rx frame flags 0x%04x" 41901c966b5SDoug Evans 42001c966b5SDoug Evans# npcm7xx_emc.c 42101c966b5SDoug Evansnpcm7xx_emc_reset(int emc_num) "Resetting emc%d" 42201c966b5SDoug Evansnpcm7xx_emc_update_tx_irq(int level) "Setting tx irq to %d" 42301c966b5SDoug Evansnpcm7xx_emc_update_rx_irq(int level) "Setting rx irq to %d" 42401c966b5SDoug Evansnpcm7xx_emc_set_mista(uint32_t flags) "ORing 0x%x into MISTA" 42501c966b5SDoug Evansnpcm7xx_emc_cpu_owned_desc(uint32_t addr) "Can't process cpu-owned descriptor @0x%x" 42601c966b5SDoug Evansnpcm7xx_emc_sent_packet(uint32_t len) "Sent %u byte packet" 42701c966b5SDoug Evansnpcm7xx_emc_tx_done(uint32_t ctxdsa) "TX done, CTXDSA=0x%x" 42801c966b5SDoug Evansnpcm7xx_emc_can_receive(int can_receive) "Can receive: %d" 42901c966b5SDoug Evansnpcm7xx_emc_packet_filtered_out(const char* fail_reason) "Packet filtered out: %s" 43001c966b5SDoug Evansnpcm7xx_emc_packet_dropped(uint32_t len) "%u byte packet dropped" 43101c966b5SDoug Evansnpcm7xx_emc_receiving_packet(uint32_t len) "Receiving %u byte packet" 43201c966b5SDoug Evansnpcm7xx_emc_received_packet(uint32_t len) "Received %u byte packet" 43301c966b5SDoug Evansnpcm7xx_emc_rx_done(uint32_t crxdsa) "RX done, CRXDSA=0x%x" 43401c966b5SDoug Evansnpcm7xx_emc_reg_read(int emc_num, uint32_t result, const char *name, int regno) "emc%d: 0x%x = reg[%s/%d]" 43501c966b5SDoug Evansnpcm7xx_emc_reg_write(int emc_num, const char *name, int regno, uint32_t value) "emc%d: reg[%s/%d] = 0x%x" 436c0af04a4SMark Cave-Ayland 437c0af04a4SMark Cave-Ayland# dp8398x.c 438c0af04a4SMark Cave-Aylanddp8393x_raise_irq(int isr) "raise irq, isr is 0x%04x" 439c0af04a4SMark Cave-Aylanddp8393x_lower_irq(void) "lower irq" 440c0af04a4SMark Cave-Aylanddp8393x_load_cam(int idx, int cam0, int cam1, int cam2, int cam3, int cam4, int cam5) "load cam[%d] with 0x%02x0x%02x0x%02x0x%02x0x%02x0x%02x" 441c0af04a4SMark Cave-Aylanddp8393x_load_cam_done(int cen) "load cam done. cam enable mask 0x%04x" 442c0af04a4SMark Cave-Aylanddp8393x_read_rra_regs(int crba0, int crba1, int rbwc0, int rbwc1) "CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x" 443c0af04a4SMark Cave-Aylanddp8393x_transmit_packet(int ttda) "Transmit packet at 0x%"PRIx32 444c0af04a4SMark Cave-Aylanddp8393x_transmit_txlen_error(int len) "tx_len is %d" 445c0af04a4SMark Cave-Aylanddp8393x_read(int reg, const char *name, int val, int size) "reg=0x%x [%s] val=0x%04x size=%d" 446c0af04a4SMark Cave-Aylanddp8393x_write(int reg, const char *name, int val, int size) "reg=0x%x [%s] val=0x%04x size=%d" 447c0af04a4SMark Cave-Aylanddp8393x_write_invalid(int reg) "writing to reg %d invalid" 448c0af04a4SMark Cave-Aylanddp8393x_write_invalid_dcr(const char *name) "writing to %s invalid" 449c0af04a4SMark Cave-Aylanddp8393x_receive_oversize(int size) "oversize packet, pkt_size is %d" 450c0af04a4SMark Cave-Aylanddp8393x_receive_not_netcard(void) "packet not for netcard" 451c0af04a4SMark Cave-Aylanddp8393x_receive_packet(int crba) "Receive packet at 0x%"PRIx32 452c0af04a4SMark Cave-Aylanddp8393x_receive_write_status(int crba) "Write status at 0x%"PRIx32 453