1 /* 2 * CAN device - SJA1000 chip emulation for QEMU 3 * 4 * Copyright (c) 2013-2014 Jin Yang 5 * Copyright (c) 2014-2018 Pavel Pisa 6 * 7 * Initial development supported by Google GSoC 2013 from RTEMS project slot 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 #include "qemu/osdep.h" 28 #include "qemu/log.h" 29 #include "chardev/char.h" 30 #include "hw/hw.h" 31 #include "net/can_emu.h" 32 33 #include "can_sja1000.h" 34 35 #ifndef DEBUG_FILTER 36 #define DEBUG_FILTER 0 37 #endif /*DEBUG_FILTER*/ 38 39 #ifndef DEBUG_CAN 40 #define DEBUG_CAN 0 41 #endif /*DEBUG_CAN*/ 42 43 #define DPRINTF(fmt, ...) \ 44 do { \ 45 if (DEBUG_CAN) { \ 46 qemu_log("[cansja]: " fmt , ## __VA_ARGS__); \ 47 } \ 48 } while (0) 49 50 static void can_sja_software_reset(CanSJA1000State *s) 51 { 52 s->mode &= ~0x31; 53 s->mode |= 0x01; 54 s->status_pel &= ~0x37; 55 s->status_pel |= 0x34; 56 57 s->rxbuf_start = 0x00; 58 s->rxmsg_cnt = 0x00; 59 s->rx_cnt = 0x00; 60 } 61 62 void can_sja_hardware_reset(CanSJA1000State *s) 63 { 64 /* Reset by hardware, p10 */ 65 s->mode = 0x01; 66 s->status_pel = 0x3c; 67 s->interrupt_pel = 0x00; 68 s->clock = 0x00; 69 s->rxbuf_start = 0x00; 70 s->rxmsg_cnt = 0x00; 71 s->rx_cnt = 0x00; 72 73 s->control = 0x01; 74 s->status_bas = 0x0c; 75 s->interrupt_bas = 0x00; 76 77 qemu_irq_lower(s->irq); 78 } 79 80 static 81 void can_sja_single_filter(struct qemu_can_filter *filter, 82 const uint8_t *acr, const uint8_t *amr, int extended) 83 { 84 if (extended) { 85 filter->can_id = (uint32_t)acr[0] << 21; 86 filter->can_id |= (uint32_t)acr[1] << 13; 87 filter->can_id |= (uint32_t)acr[2] << 5; 88 filter->can_id |= (uint32_t)acr[3] >> 3; 89 if (acr[3] & 4) { 90 filter->can_id |= QEMU_CAN_RTR_FLAG; 91 } 92 93 filter->can_mask = (uint32_t)amr[0] << 21; 94 filter->can_mask |= (uint32_t)amr[1] << 13; 95 filter->can_mask |= (uint32_t)amr[2] << 5; 96 filter->can_mask |= (uint32_t)amr[3] >> 3; 97 filter->can_mask = ~filter->can_mask & QEMU_CAN_EFF_MASK; 98 if (!(amr[3] & 4)) { 99 filter->can_mask |= QEMU_CAN_RTR_FLAG; 100 } 101 } else { 102 filter->can_id = (uint32_t)acr[0] << 3; 103 filter->can_id |= (uint32_t)acr[1] >> 5; 104 if (acr[1] & 0x10) { 105 filter->can_id |= QEMU_CAN_RTR_FLAG; 106 } 107 108 filter->can_mask = (uint32_t)amr[0] << 3; 109 filter->can_mask |= (uint32_t)amr[1] << 5; 110 filter->can_mask = ~filter->can_mask & QEMU_CAN_SFF_MASK; 111 if (!(amr[1] & 0x10)) { 112 filter->can_mask |= QEMU_CAN_RTR_FLAG; 113 } 114 } 115 } 116 117 static 118 void can_sja_dual_filter(struct qemu_can_filter *filter, 119 const uint8_t *acr, const uint8_t *amr, int extended) 120 { 121 if (extended) { 122 filter->can_id = (uint32_t)acr[0] << 21; 123 filter->can_id |= (uint32_t)acr[1] << 13; 124 125 filter->can_mask = (uint32_t)amr[0] << 21; 126 filter->can_mask |= (uint32_t)amr[1] << 13; 127 filter->can_mask = ~filter->can_mask & QEMU_CAN_EFF_MASK & ~0x1fff; 128 } else { 129 filter->can_id = (uint32_t)acr[0] << 3; 130 filter->can_id |= (uint32_t)acr[1] >> 5; 131 if (acr[1] & 0x10) { 132 filter->can_id |= QEMU_CAN_RTR_FLAG; 133 } 134 135 filter->can_mask = (uint32_t)amr[0] << 3; 136 filter->can_mask |= (uint32_t)amr[1] >> 5; 137 filter->can_mask = ~filter->can_mask & QEMU_CAN_SFF_MASK; 138 if (!(amr[1] & 0x10)) { 139 filter->can_mask |= QEMU_CAN_RTR_FLAG; 140 } 141 } 142 } 143 144 /* Details in DS-p22, what we need to do here is to test the data. */ 145 static 146 int can_sja_accept_filter(CanSJA1000State *s, 147 const qemu_can_frame *frame) 148 { 149 150 struct qemu_can_filter filter; 151 152 if (s->clock & 0x80) { /* PeliCAN Mode */ 153 if (s->mode & (1 << 3)) { /* Single mode. */ 154 if (frame->can_id & QEMU_CAN_EFF_FLAG) { /* EFF */ 155 can_sja_single_filter(&filter, 156 s->code_mask + 0, s->code_mask + 4, 1); 157 158 if (!can_bus_filter_match(&filter, frame->can_id)) { 159 return 0; 160 } 161 } else { /* SFF */ 162 can_sja_single_filter(&filter, 163 s->code_mask + 0, s->code_mask + 4, 0); 164 165 if (!can_bus_filter_match(&filter, frame->can_id)) { 166 return 0; 167 } 168 169 if (frame->can_id & QEMU_CAN_RTR_FLAG) { /* RTR */ 170 return 1; 171 } 172 173 if (frame->can_dlc == 0) { 174 return 1; 175 } 176 177 if ((frame->data[0] & ~(s->code_mask[6])) != 178 (s->code_mask[2] & ~(s->code_mask[6]))) { 179 return 0; 180 } 181 182 if (frame->can_dlc < 2) { 183 return 1; 184 } 185 186 if ((frame->data[1] & ~(s->code_mask[7])) == 187 (s->code_mask[3] & ~(s->code_mask[7]))) { 188 return 1; 189 } 190 191 return 0; 192 } 193 } else { /* Dual mode */ 194 if (frame->can_id & QEMU_CAN_EFF_FLAG) { /* EFF */ 195 can_sja_dual_filter(&filter, 196 s->code_mask + 0, s->code_mask + 4, 1); 197 198 if (can_bus_filter_match(&filter, frame->can_id)) { 199 return 1; 200 } 201 202 can_sja_dual_filter(&filter, 203 s->code_mask + 2, s->code_mask + 6, 1); 204 205 if (can_bus_filter_match(&filter, frame->can_id)) { 206 return 1; 207 } 208 209 return 0; 210 } else { 211 can_sja_dual_filter(&filter, 212 s->code_mask + 0, s->code_mask + 4, 0); 213 214 if (can_bus_filter_match(&filter, frame->can_id)) { 215 uint8_t expect; 216 uint8_t mask; 217 expect = s->code_mask[1] << 4; 218 expect |= s->code_mask[3] & 0x0f; 219 220 mask = s->code_mask[5] << 4; 221 mask |= s->code_mask[7] & 0x0f; 222 mask = ~mask & 0xff; 223 224 if ((frame->data[0] & mask) == 225 (expect & mask)) { 226 return 1; 227 } 228 } 229 230 can_sja_dual_filter(&filter, 231 s->code_mask + 2, s->code_mask + 6, 0); 232 233 if (can_bus_filter_match(&filter, frame->can_id)) { 234 return 1; 235 } 236 237 return 0; 238 } 239 } 240 } 241 242 return 1; 243 } 244 245 static void can_display_msg(const char *prefix, const qemu_can_frame *msg) 246 { 247 int i; 248 249 qemu_log_lock(); 250 qemu_log("%s%03X [%01d] %s %s", 251 prefix, 252 msg->can_id & QEMU_CAN_EFF_MASK, 253 msg->can_dlc, 254 msg->can_id & QEMU_CAN_EFF_FLAG ? "EFF" : "SFF", 255 msg->can_id & QEMU_CAN_RTR_FLAG ? "RTR" : "DAT"); 256 257 for (i = 0; i < msg->can_dlc; i++) { 258 qemu_log(" %02X", msg->data[i]); 259 } 260 qemu_log("\n"); 261 qemu_log_flush(); 262 qemu_log_unlock(); 263 } 264 265 static void buff2frame_pel(const uint8_t *buff, qemu_can_frame *frame) 266 { 267 uint8_t i; 268 269 frame->can_id = 0; 270 if (buff[0] & 0x40) { /* RTR */ 271 frame->can_id = QEMU_CAN_RTR_FLAG; 272 } 273 frame->can_dlc = buff[0] & 0x0f; 274 275 if (buff[0] & 0x80) { /* Extended */ 276 frame->can_id |= QEMU_CAN_EFF_FLAG; 277 frame->can_id |= buff[1] << 21; /* ID.28~ID.21 */ 278 frame->can_id |= buff[2] << 13; /* ID.20~ID.13 */ 279 frame->can_id |= buff[3] << 5; 280 frame->can_id |= buff[4] >> 3; 281 for (i = 0; i < frame->can_dlc; i++) { 282 frame->data[i] = buff[5 + i]; 283 } 284 for (; i < 8; i++) { 285 frame->data[i] = 0; 286 } 287 } else { 288 frame->can_id |= buff[1] << 3; 289 frame->can_id |= buff[2] >> 5; 290 for (i = 0; i < frame->can_dlc; i++) { 291 frame->data[i] = buff[3 + i]; 292 } 293 for (; i < 8; i++) { 294 frame->data[i] = 0; 295 } 296 } 297 } 298 299 300 static void buff2frame_bas(const uint8_t *buff, qemu_can_frame *frame) 301 { 302 uint8_t i; 303 304 frame->can_id = ((buff[0] << 3) & (0xff << 3)) + ((buff[1] >> 5) & 0x07); 305 if (buff[1] & 0x10) { /* RTR */ 306 frame->can_id = QEMU_CAN_RTR_FLAG; 307 } 308 frame->can_dlc = buff[1] & 0x0f; 309 310 for (i = 0; i < frame->can_dlc; i++) { 311 frame->data[i] = buff[2 + i]; 312 } 313 for (; i < 8; i++) { 314 frame->data[i] = 0; 315 } 316 } 317 318 319 static int frame2buff_pel(const qemu_can_frame *frame, uint8_t *buff) 320 { 321 int i; 322 323 if (frame->can_id & QEMU_CAN_ERR_FLAG) { /* error frame, NOT support now. */ 324 return -1; 325 } 326 327 buff[0] = 0x0f & frame->can_dlc; /* DLC */ 328 if (frame->can_id & QEMU_CAN_RTR_FLAG) { /* RTR */ 329 buff[0] |= (1 << 6); 330 } 331 if (frame->can_id & QEMU_CAN_EFF_FLAG) { /* EFF */ 332 buff[0] |= (1 << 7); 333 buff[1] = extract32(frame->can_id, 21, 8); /* ID.28~ID.21 */ 334 buff[2] = extract32(frame->can_id, 13, 8); /* ID.20~ID.13 */ 335 buff[3] = extract32(frame->can_id, 5, 8); /* ID.12~ID.05 */ 336 buff[4] = extract32(frame->can_id, 0, 5) << 3; /* ID.04~ID.00,xxx */ 337 for (i = 0; i < frame->can_dlc; i++) { 338 buff[5 + i] = frame->data[i]; 339 } 340 return frame->can_dlc + 5; 341 } else { /* SFF */ 342 buff[1] = extract32(frame->can_id, 3, 8); /* ID.10~ID.03 */ 343 buff[2] = extract32(frame->can_id, 0, 3) << 5; /* ID.02~ID.00,xxxxx */ 344 for (i = 0; i < frame->can_dlc; i++) { 345 buff[3 + i] = frame->data[i]; 346 } 347 348 return frame->can_dlc + 3; 349 } 350 351 return -1; 352 } 353 354 static int frame2buff_bas(const qemu_can_frame *frame, uint8_t *buff) 355 { 356 int i; 357 358 /* 359 * EFF, no support for BasicMode 360 * No use for Error frames now, 361 * they could be used in future to update SJA1000 error state 362 */ 363 if ((frame->can_id & QEMU_CAN_EFF_FLAG) || 364 (frame->can_id & QEMU_CAN_ERR_FLAG)) { 365 return -1; 366 } 367 368 buff[0] = extract32(frame->can_id, 3, 8); /* ID.10~ID.03 */ 369 buff[1] = extract32(frame->can_id, 0, 3) << 5; /* ID.02~ID.00,xxxxx */ 370 if (frame->can_id & QEMU_CAN_RTR_FLAG) { /* RTR */ 371 buff[1] |= (1 << 4); 372 } 373 buff[1] |= frame->can_dlc & 0x0f; 374 for (i = 0; i < frame->can_dlc; i++) { 375 buff[2 + i] = frame->data[i]; 376 } 377 378 return frame->can_dlc + 2; 379 } 380 381 void can_sja_mem_write(CanSJA1000State *s, hwaddr addr, uint64_t val, 382 unsigned size) 383 { 384 qemu_can_frame frame; 385 uint32_t tmp; 386 uint8_t tmp8, count; 387 388 389 DPRINTF("write 0x%02llx addr 0x%02x\n", 390 (unsigned long long)val, (unsigned int)addr); 391 392 if (addr > CAN_SJA_MEM_SIZE) { 393 return ; 394 } 395 396 if (s->clock & 0x80) { /* PeliCAN Mode */ 397 switch (addr) { 398 case SJA_MOD: /* Mode register */ 399 s->mode = 0x1f & val; 400 if ((s->mode & 0x01) && ((val & 0x01) == 0)) { 401 /* Go to operation mode from reset mode. */ 402 if (s->mode & (1 << 3)) { /* Single mode. */ 403 /* For EFF */ 404 can_sja_single_filter(&s->filter[0], 405 s->code_mask + 0, s->code_mask + 4, 1); 406 407 /* For SFF */ 408 can_sja_single_filter(&s->filter[1], 409 s->code_mask + 0, s->code_mask + 4, 0); 410 411 can_bus_client_set_filters(&s->bus_client, s->filter, 2); 412 } else { /* Dual mode */ 413 /* For EFF */ 414 can_sja_dual_filter(&s->filter[0], 415 s->code_mask + 0, s->code_mask + 4, 1); 416 417 can_sja_dual_filter(&s->filter[1], 418 s->code_mask + 2, s->code_mask + 6, 1); 419 420 /* For SFF */ 421 can_sja_dual_filter(&s->filter[2], 422 s->code_mask + 0, s->code_mask + 4, 0); 423 424 can_sja_dual_filter(&s->filter[3], 425 s->code_mask + 2, s->code_mask + 6, 0); 426 427 can_bus_client_set_filters(&s->bus_client, s->filter, 4); 428 } 429 430 s->rxmsg_cnt = 0; 431 s->rx_cnt = 0; 432 } 433 break; 434 435 case SJA_CMR: /* Command register. */ 436 if (0x01 & val) { /* Send transmission request. */ 437 buff2frame_pel(s->tx_buff, &frame); 438 if (DEBUG_FILTER) { 439 can_display_msg("[cansja]: Tx request " , &frame); 440 } 441 442 /* 443 * Clear transmission complete status, 444 * and Transmit Buffer Status. 445 * write to the backends. 446 */ 447 s->status_pel &= ~(3 << 2); 448 449 can_bus_client_send(&s->bus_client, &frame, 1); 450 451 /* 452 * Set transmission complete status 453 * and Transmit Buffer Status. 454 */ 455 s->status_pel |= (3 << 2); 456 457 /* Clear transmit status. */ 458 s->status_pel &= ~(1 << 5); 459 s->interrupt_pel |= 0x02; 460 if (s->interrupt_en & 0x02) { 461 qemu_irq_raise(s->irq); 462 } 463 } 464 if (0x04 & val) { /* Release Receive Buffer */ 465 if (s->rxmsg_cnt <= 0) { 466 break; 467 } 468 469 tmp8 = s->rx_buff[s->rxbuf_start]; count = 0; 470 if (tmp8 & (1 << 7)) { /* EFF */ 471 count += 2; 472 } 473 count += 3; 474 if (!(tmp8 & (1 << 6))) { /* DATA */ 475 count += (tmp8 & 0x0f); 476 } 477 478 if (DEBUG_FILTER) { 479 qemu_log("[cansja]: message released from " 480 "Rx FIFO cnt=%d, count=%d\n", s->rx_cnt, count); 481 } 482 483 s->rxbuf_start += count; 484 s->rxbuf_start %= SJA_RCV_BUF_LEN; 485 486 s->rx_cnt -= count; 487 s->rxmsg_cnt--; 488 if (s->rxmsg_cnt == 0) { 489 s->status_pel &= ~(1 << 0); 490 s->interrupt_pel &= ~(1 << 0); 491 } 492 if ((s->interrupt_en & 0x01) && (s->interrupt_pel == 0)) { 493 /* no other interrupts. */ 494 qemu_irq_lower(s->irq); 495 } 496 } 497 if (0x08 & val) { /* Clear data overrun */ 498 s->status_pel &= ~(1 << 1); 499 s->interrupt_pel &= ~(1 << 3); 500 if ((s->interrupt_en & 0x80) && (s->interrupt_pel == 0)) { 501 /* no other interrupts. */ 502 qemu_irq_lower(s->irq); 503 } 504 } 505 break; 506 case SJA_SR: /* Status register */ 507 case SJA_IR: /* Interrupt register */ 508 break; /* Do nothing */ 509 case SJA_IER: /* Interrupt enable register */ 510 s->interrupt_en = val; 511 break; 512 case 16: /* RX frame information addr16-28. */ 513 s->status_pel |= (1 << 5); /* Set transmit status. */ 514 case 17 ... 28: 515 if (s->mode & 0x01) { /* Reset mode */ 516 if (addr < 24) { 517 s->code_mask[addr - 16] = val; 518 } 519 } else { /* Operation mode */ 520 s->tx_buff[addr - 16] = val; /* Store to TX buffer directly. */ 521 } 522 break; 523 case SJA_CDR: 524 s->clock = val; 525 break; 526 } 527 } else { /* Basic Mode */ 528 switch (addr) { 529 case SJA_BCAN_CTR: /* Control register, addr 0 */ 530 if ((s->control & 0x01) && ((val & 0x01) == 0)) { 531 /* Go to operation mode from reset mode. */ 532 s->filter[0].can_id = (s->code << 3) & (0xff << 3); 533 tmp = (~(s->mask << 3)) & (0xff << 3); 534 tmp |= QEMU_CAN_EFF_FLAG; /* Only Basic CAN Frame. */ 535 s->filter[0].can_mask = tmp; 536 can_bus_client_set_filters(&s->bus_client, s->filter, 1); 537 538 s->rxmsg_cnt = 0; 539 s->rx_cnt = 0; 540 } else if (!(s->control & 0x01) && !(val & 0x01)) { 541 can_sja_software_reset(s); 542 } 543 544 s->control = 0x1f & val; 545 break; 546 case SJA_BCAN_CMR: /* Command register, addr 1 */ 547 if (0x01 & val) { /* Send transmission request. */ 548 buff2frame_bas(s->tx_buff, &frame); 549 if (DEBUG_FILTER) { 550 can_display_msg("[cansja]: Tx request " , &frame); 551 } 552 553 /* 554 * Clear transmission complete status, 555 * and Transmit Buffer Status. 556 */ 557 s->status_bas &= ~(3 << 2); 558 559 /* write to the backends. */ 560 can_bus_client_send(&s->bus_client, &frame, 1); 561 562 /* 563 * Set transmission complete status, 564 * and Transmit Buffer Status. 565 */ 566 s->status_bas |= (3 << 2); 567 568 /* Clear transmit status. */ 569 s->status_bas &= ~(1 << 5); 570 s->interrupt_bas |= 0x02; 571 if (s->control & 0x04) { 572 qemu_irq_raise(s->irq); 573 } 574 } 575 if (0x04 & val) { /* Release Receive Buffer */ 576 if (s->rxmsg_cnt <= 0) { 577 break; 578 } 579 580 tmp8 = s->rx_buff[(s->rxbuf_start + 1) % SJA_RCV_BUF_LEN]; 581 count = 2 + (tmp8 & 0x0f); 582 583 if (DEBUG_FILTER) { 584 qemu_log("[cansja]: message released from " 585 "Rx FIFO cnt=%d, count=%d\n", s->rx_cnt, count); 586 } 587 588 s->rxbuf_start += count; 589 s->rxbuf_start %= SJA_RCV_BUF_LEN; 590 s->rx_cnt -= count; 591 s->rxmsg_cnt--; 592 593 if (s->rxmsg_cnt == 0) { 594 s->status_bas &= ~(1 << 0); 595 s->interrupt_bas &= ~(1 << 0); 596 } 597 if ((s->control & 0x02) && (s->interrupt_bas == 0)) { 598 /* no other interrupts. */ 599 qemu_irq_lower(s->irq); 600 } 601 } 602 if (0x08 & val) { /* Clear data overrun */ 603 s->status_bas &= ~(1 << 1); 604 s->interrupt_bas &= ~(1 << 3); 605 if ((s->control & 0x10) && (s->interrupt_bas == 0)) { 606 /* no other interrupts. */ 607 qemu_irq_lower(s->irq); 608 } 609 } 610 break; 611 case 4: 612 s->code = val; 613 break; 614 case 5: 615 s->mask = val; 616 break; 617 case 10: 618 s->status_bas |= (1 << 5); /* Set transmit status. */ 619 case 11 ... 19: 620 if ((s->control & 0x01) == 0) { /* Operation mode */ 621 s->tx_buff[addr - 10] = val; /* Store to TX buffer directly. */ 622 } 623 break; 624 case SJA_CDR: 625 s->clock = val; 626 break; 627 } 628 } 629 } 630 631 uint64_t can_sja_mem_read(CanSJA1000State *s, hwaddr addr, unsigned size) 632 { 633 uint64_t temp = 0; 634 635 DPRINTF("read addr 0x%02x ...\n", (unsigned int)addr); 636 637 if (addr > CAN_SJA_MEM_SIZE) { 638 return 0; 639 } 640 641 if (s->clock & 0x80) { /* PeliCAN Mode */ 642 switch (addr) { 643 case SJA_MOD: /* Mode register, addr 0 */ 644 temp = s->mode; 645 break; 646 case SJA_CMR: /* Command register, addr 1 */ 647 temp = 0x00; /* Command register, cannot be read. */ 648 break; 649 case SJA_SR: /* Status register, addr 2 */ 650 temp = s->status_pel; 651 break; 652 case SJA_IR: /* Interrupt register, addr 3 */ 653 temp = s->interrupt_pel; 654 s->interrupt_pel = 0; 655 if (s->rxmsg_cnt) { 656 s->interrupt_pel |= (1 << 0); /* Receive interrupt. */ 657 break; 658 } 659 qemu_irq_lower(s->irq); 660 break; 661 case SJA_IER: /* Interrupt enable register, addr 4 */ 662 temp = s->interrupt_en; 663 break; 664 case 5: /* Reserved */ 665 case 6: /* Bus timing 0, hardware related, not support now. */ 666 case 7: /* Bus timing 1, hardware related, not support now. */ 667 case 8: /* 668 * Output control register, hardware related, 669 * not supported for now. 670 */ 671 case 9: /* Test. */ 672 case 10 ... 15: /* Reserved */ 673 temp = 0x00; 674 break; 675 676 case 16 ... 28: 677 if (s->mode & 0x01) { /* Reset mode */ 678 if (addr < 24) { 679 temp = s->code_mask[addr - 16]; 680 } else { 681 temp = 0x00; 682 } 683 } else { /* Operation mode */ 684 temp = s->rx_buff[(s->rxbuf_start + addr - 16) % 685 SJA_RCV_BUF_LEN]; 686 } 687 break; 688 case SJA_CDR: 689 temp = s->clock; 690 break; 691 default: 692 temp = 0xff; 693 } 694 } else { /* Basic Mode */ 695 switch (addr) { 696 case SJA_BCAN_CTR: /* Control register, addr 0 */ 697 temp = s->control; 698 break; 699 case SJA_BCAN_SR: /* Status register, addr 2 */ 700 temp = s->status_bas; 701 break; 702 case SJA_BCAN_IR: /* Interrupt register, addr 3 */ 703 temp = s->interrupt_bas; 704 s->interrupt_bas = 0; 705 if (s->rxmsg_cnt) { 706 s->interrupt_bas |= (1 << 0); /* Receive interrupt. */ 707 break; 708 } 709 qemu_irq_lower(s->irq); 710 break; 711 case 4: 712 temp = s->code; 713 break; 714 case 5: 715 temp = s->mask; 716 break; 717 case 20 ... 29: 718 temp = s->rx_buff[(s->rxbuf_start + addr - 20) % SJA_RCV_BUF_LEN]; 719 break; 720 case 31: 721 temp = s->clock; 722 break; 723 default: 724 temp = 0xff; 725 break; 726 } 727 } 728 DPRINTF("read addr 0x%02x, %d bytes, content 0x%02lx\n", 729 (int)addr, size, (long unsigned int)temp); 730 731 return temp; 732 } 733 734 int can_sja_can_receive(CanBusClientState *client) 735 { 736 CanSJA1000State *s = container_of(client, CanSJA1000State, bus_client); 737 738 if (s->clock & 0x80) { /* PeliCAN Mode */ 739 if (s->mode & 0x01) { /* reset mode. */ 740 return 0; 741 } 742 } else { /* BasicCAN mode */ 743 if (s->control & 0x01) { 744 return 0; 745 } 746 } 747 748 return 1; /* always return 1, when operation mode */ 749 } 750 751 ssize_t can_sja_receive(CanBusClientState *client, const qemu_can_frame *frames, 752 size_t frames_cnt) 753 { 754 CanSJA1000State *s = container_of(client, CanSJA1000State, bus_client); 755 static uint8_t rcv[SJA_MSG_MAX_LEN]; 756 int i; 757 int ret = -1; 758 const qemu_can_frame *frame = frames; 759 760 if (frames_cnt <= 0) { 761 return 0; 762 } 763 if (DEBUG_FILTER) { 764 can_display_msg("[cansja]: receive ", frame); 765 } 766 767 if (s->clock & 0x80) { /* PeliCAN Mode */ 768 769 /* the CAN controller is receiving a message */ 770 s->status_pel |= (1 << 4); 771 772 if (can_sja_accept_filter(s, frame) == 0) { 773 s->status_pel &= ~(1 << 4); 774 if (DEBUG_FILTER) { 775 qemu_log("[cansja]: filter rejects message\n"); 776 } 777 return ret; 778 } 779 780 ret = frame2buff_pel(frame, rcv); 781 if (ret < 0) { 782 s->status_pel &= ~(1 << 4); 783 if (DEBUG_FILTER) { 784 qemu_log("[cansja]: message store failed\n"); 785 } 786 return ret; /* maybe not support now. */ 787 } 788 789 if (s->rx_cnt + ret > SJA_RCV_BUF_LEN) { /* Data overrun. */ 790 s->status_pel |= (1 << 1); /* Overrun status */ 791 s->interrupt_pel |= (1 << 3); 792 if (s->interrupt_en & (1 << 3)) { /* Overrun interrupt enable */ 793 qemu_irq_raise(s->irq); 794 } 795 s->status_pel &= ~(1 << 4); 796 if (DEBUG_FILTER) { 797 qemu_log("[cansja]: receive FIFO overrun\n"); 798 } 799 return ret; 800 } 801 s->rx_cnt += ret; 802 s->rxmsg_cnt++; 803 if (DEBUG_FILTER) { 804 qemu_log("[cansja]: message stored in receive FIFO\n"); 805 } 806 807 for (i = 0; i < ret; i++) { 808 s->rx_buff[(s->rx_ptr++) % SJA_RCV_BUF_LEN] = rcv[i]; 809 } 810 s->rx_ptr %= SJA_RCV_BUF_LEN; /* update the pointer. */ 811 812 s->status_pel |= 0x01; /* Set the Receive Buffer Status. DS-p23 */ 813 s->interrupt_pel |= 0x01; 814 s->status_pel &= ~(1 << 4); 815 s->status_pel |= (1 << 0); 816 if (s->interrupt_en & 0x01) { /* Receive Interrupt enable. */ 817 qemu_irq_raise(s->irq); 818 } 819 } else { /* BasicCAN mode */ 820 821 /* the CAN controller is receiving a message */ 822 s->status_bas |= (1 << 4); 823 824 ret = frame2buff_bas(frame, rcv); 825 if (ret < 0) { 826 s->status_bas &= ~(1 << 4); 827 if (DEBUG_FILTER) { 828 qemu_log("[cansja]: message store failed\n"); 829 } 830 return ret; /* maybe not support now. */ 831 } 832 833 if (s->rx_cnt + ret > SJA_RCV_BUF_LEN) { /* Data overrun. */ 834 s->status_bas |= (1 << 1); /* Overrun status */ 835 s->status_bas &= ~(1 << 4); 836 s->interrupt_bas |= (1 << 3); 837 if (s->control & (1 << 4)) { /* Overrun interrupt enable */ 838 qemu_irq_raise(s->irq); 839 } 840 if (DEBUG_FILTER) { 841 qemu_log("[cansja]: receive FIFO overrun\n"); 842 } 843 return ret; 844 } 845 s->rx_cnt += ret; 846 s->rxmsg_cnt++; 847 848 if (DEBUG_FILTER) { 849 qemu_log("[cansja]: message stored\n"); 850 } 851 852 for (i = 0; i < ret; i++) { 853 s->rx_buff[(s->rx_ptr++) % SJA_RCV_BUF_LEN] = rcv[i]; 854 } 855 s->rx_ptr %= SJA_RCV_BUF_LEN; /* update the pointer. */ 856 857 s->status_bas |= 0x01; /* Set the Receive Buffer Status. DS-p15 */ 858 s->status_bas &= ~(1 << 4); 859 s->interrupt_bas |= 0x01; 860 if (s->control & 0x02) { /* Receive Interrupt enable. */ 861 qemu_irq_raise(s->irq); 862 } 863 } 864 return 1; 865 } 866 867 static CanBusClientInfo can_sja_bus_client_info = { 868 .can_receive = can_sja_can_receive, 869 .receive = can_sja_receive, 870 }; 871 872 873 int can_sja_connect_to_bus(CanSJA1000State *s, CanBusState *bus) 874 { 875 s->bus_client.info = &can_sja_bus_client_info; 876 877 if (can_bus_insert_client(bus, &s->bus_client) < 0) { 878 return -1; 879 } 880 881 return 0; 882 } 883 884 void can_sja_disconnect(CanSJA1000State *s) 885 { 886 can_bus_remove_client(&s->bus_client); 887 } 888 889 int can_sja_init(CanSJA1000State *s, qemu_irq irq) 890 { 891 s->irq = irq; 892 893 qemu_irq_lower(s->irq); 894 895 can_sja_hardware_reset(s); 896 897 return 0; 898 } 899 900 const VMStateDescription vmstate_qemu_can_filter = { 901 .name = "qemu_can_filter", 902 .version_id = 1, 903 .minimum_version_id = 1, 904 .minimum_version_id_old = 1, 905 .fields = (VMStateField[]) { 906 VMSTATE_UINT32(can_id, qemu_can_filter), 907 VMSTATE_UINT32(can_mask, qemu_can_filter), 908 VMSTATE_END_OF_LIST() 909 } 910 }; 911 912 /* VMState is needed for live migration of QEMU images */ 913 const VMStateDescription vmstate_can_sja = { 914 .name = "can_sja", 915 .version_id = 1, 916 .minimum_version_id = 1, 917 .minimum_version_id_old = 1, 918 .fields = (VMStateField[]) { 919 VMSTATE_UINT8(mode, CanSJA1000State), 920 921 VMSTATE_UINT8(status_pel, CanSJA1000State), 922 VMSTATE_UINT8(interrupt_pel, CanSJA1000State), 923 VMSTATE_UINT8(interrupt_en, CanSJA1000State), 924 VMSTATE_UINT8(rxmsg_cnt, CanSJA1000State), 925 VMSTATE_UINT8(rxbuf_start, CanSJA1000State), 926 VMSTATE_UINT8(clock, CanSJA1000State), 927 928 VMSTATE_BUFFER(code_mask, CanSJA1000State), 929 VMSTATE_BUFFER(tx_buff, CanSJA1000State), 930 931 VMSTATE_BUFFER(rx_buff, CanSJA1000State), 932 933 VMSTATE_UINT32(rx_ptr, CanSJA1000State), 934 VMSTATE_UINT32(rx_cnt, CanSJA1000State), 935 936 VMSTATE_UINT8(control, CanSJA1000State), 937 938 VMSTATE_UINT8(status_bas, CanSJA1000State), 939 VMSTATE_UINT8(interrupt_bas, CanSJA1000State), 940 VMSTATE_UINT8(code, CanSJA1000State), 941 VMSTATE_UINT8(mask, CanSJA1000State), 942 943 VMSTATE_STRUCT_ARRAY(filter, CanSJA1000State, 4, 0, 944 vmstate_qemu_can_filter, qemu_can_filter), 945 946 947 VMSTATE_END_OF_LIST() 948 } 949 }; 950