xref: /openbmc/qemu/hw/misc/stm32f2xx_syscfg.c (revision 2562755ee78983930d0662fa4d3bc5e2ac166350)
1bbbbd900SAlistair Francis /*
2bbbbd900SAlistair Francis  * STM32F2XX SYSCFG
3bbbbd900SAlistair Francis  *
4bbbbd900SAlistair Francis  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
5bbbbd900SAlistair Francis  *
6bbbbd900SAlistair Francis  * Permission is hereby granted, free of charge, to any person obtaining a copy
7bbbbd900SAlistair Francis  * of this software and associated documentation files (the "Software"), to deal
8bbbbd900SAlistair Francis  * in the Software without restriction, including without limitation the rights
9bbbbd900SAlistair Francis  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10bbbbd900SAlistair Francis  * copies of the Software, and to permit persons to whom the Software is
11bbbbd900SAlistair Francis  * furnished to do so, subject to the following conditions:
12bbbbd900SAlistair Francis  *
13bbbbd900SAlistair Francis  * The above copyright notice and this permission notice shall be included in
14bbbbd900SAlistair Francis  * all copies or substantial portions of the Software.
15bbbbd900SAlistair Francis  *
16bbbbd900SAlistair Francis  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17bbbbd900SAlistair Francis  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18bbbbd900SAlistair Francis  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19bbbbd900SAlistair Francis  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20bbbbd900SAlistair Francis  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21bbbbd900SAlistair Francis  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22bbbbd900SAlistair Francis  * THE SOFTWARE.
23bbbbd900SAlistair Francis  */
24bbbbd900SAlistair Francis 
250d1c9782SPeter Maydell #include "qemu/osdep.h"
26bbbbd900SAlistair Francis #include "hw/misc/stm32f2xx_syscfg.h"
2703dd024fSPaolo Bonzini #include "qemu/log.h"
28bbbbd900SAlistair Francis 
29bbbbd900SAlistair Francis #ifndef STM_SYSCFG_ERR_DEBUG
30bbbbd900SAlistair Francis #define STM_SYSCFG_ERR_DEBUG 0
31bbbbd900SAlistair Francis #endif
32bbbbd900SAlistair Francis 
33bbbbd900SAlistair Francis #define DB_PRINT_L(lvl, fmt, args...) do { \
34bbbbd900SAlistair Francis     if (STM_SYSCFG_ERR_DEBUG >= lvl) { \
35bbbbd900SAlistair Francis         qemu_log("%s: " fmt, __func__, ## args); \
36bbbbd900SAlistair Francis     } \
37*2562755eSEric Blake } while (0)
38bbbbd900SAlistair Francis 
39bbbbd900SAlistair Francis #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
40bbbbd900SAlistair Francis 
41bbbbd900SAlistair Francis static void stm32f2xx_syscfg_reset(DeviceState *dev)
42bbbbd900SAlistair Francis {
43bbbbd900SAlistair Francis     STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(dev);
44bbbbd900SAlistair Francis 
45bbbbd900SAlistair Francis     s->syscfg_memrmp = 0x00000000;
46bbbbd900SAlistair Francis     s->syscfg_pmc = 0x00000000;
47bbbbd900SAlistair Francis     s->syscfg_exticr1 = 0x00000000;
48bbbbd900SAlistair Francis     s->syscfg_exticr2 = 0x00000000;
49bbbbd900SAlistair Francis     s->syscfg_exticr3 = 0x00000000;
50bbbbd900SAlistair Francis     s->syscfg_exticr4 = 0x00000000;
51bbbbd900SAlistair Francis     s->syscfg_cmpcr = 0x00000000;
52bbbbd900SAlistair Francis }
53bbbbd900SAlistair Francis 
54bbbbd900SAlistair Francis static uint64_t stm32f2xx_syscfg_read(void *opaque, hwaddr addr,
55bbbbd900SAlistair Francis                                      unsigned int size)
56bbbbd900SAlistair Francis {
57bbbbd900SAlistair Francis     STM32F2XXSyscfgState *s = opaque;
58bbbbd900SAlistair Francis 
59bbbbd900SAlistair Francis     DB_PRINT("0x%"HWADDR_PRIx"\n", addr);
60bbbbd900SAlistair Francis 
61bbbbd900SAlistair Francis     switch (addr) {
62bbbbd900SAlistair Francis     case SYSCFG_MEMRMP:
63bbbbd900SAlistair Francis         return s->syscfg_memrmp;
64bbbbd900SAlistair Francis     case SYSCFG_PMC:
65bbbbd900SAlistair Francis         return s->syscfg_pmc;
66bbbbd900SAlistair Francis     case SYSCFG_EXTICR1:
67bbbbd900SAlistair Francis         return s->syscfg_exticr1;
68bbbbd900SAlistair Francis     case SYSCFG_EXTICR2:
69bbbbd900SAlistair Francis         return s->syscfg_exticr2;
70bbbbd900SAlistair Francis     case SYSCFG_EXTICR3:
71bbbbd900SAlistair Francis         return s->syscfg_exticr3;
72bbbbd900SAlistair Francis     case SYSCFG_EXTICR4:
73bbbbd900SAlistair Francis         return s->syscfg_exticr4;
74bbbbd900SAlistair Francis     case SYSCFG_CMPCR:
75bbbbd900SAlistair Francis         return s->syscfg_cmpcr;
76bbbbd900SAlistair Francis     default:
77bbbbd900SAlistair Francis         qemu_log_mask(LOG_GUEST_ERROR,
78bbbbd900SAlistair Francis                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
79bbbbd900SAlistair Francis         return 0;
80bbbbd900SAlistair Francis     }
81bbbbd900SAlistair Francis 
82bbbbd900SAlistair Francis     return 0;
83bbbbd900SAlistair Francis }
84bbbbd900SAlistair Francis 
85bbbbd900SAlistair Francis static void stm32f2xx_syscfg_write(void *opaque, hwaddr addr,
86bbbbd900SAlistair Francis                        uint64_t val64, unsigned int size)
87bbbbd900SAlistair Francis {
88bbbbd900SAlistair Francis     STM32F2XXSyscfgState *s = opaque;
89bbbbd900SAlistair Francis     uint32_t value = val64;
90bbbbd900SAlistair Francis 
91bbbbd900SAlistair Francis     DB_PRINT("0x%x, 0x%"HWADDR_PRIx"\n", value, addr);
92bbbbd900SAlistair Francis 
93bbbbd900SAlistair Francis     switch (addr) {
94bbbbd900SAlistair Francis     case SYSCFG_MEMRMP:
95bbbbd900SAlistair Francis         qemu_log_mask(LOG_UNIMP,
96bbbbd900SAlistair Francis                       "%s: Changeing the memory mapping isn't supported " \
97bbbbd900SAlistair Francis                       "in QEMU\n", __func__);
98bbbbd900SAlistair Francis         return;
99bbbbd900SAlistair Francis     case SYSCFG_PMC:
100bbbbd900SAlistair Francis         qemu_log_mask(LOG_UNIMP,
101bbbbd900SAlistair Francis                       "%s: Changeing the memory mapping isn't supported " \
102bbbbd900SAlistair Francis                       "in QEMU\n", __func__);
103bbbbd900SAlistair Francis         return;
104bbbbd900SAlistair Francis     case SYSCFG_EXTICR1:
105bbbbd900SAlistair Francis         s->syscfg_exticr1 = (value & 0xFFFF);
106bbbbd900SAlistair Francis         return;
107bbbbd900SAlistair Francis     case SYSCFG_EXTICR2:
108bbbbd900SAlistair Francis         s->syscfg_exticr2 = (value & 0xFFFF);
109bbbbd900SAlistair Francis         return;
110bbbbd900SAlistair Francis     case SYSCFG_EXTICR3:
111bbbbd900SAlistair Francis         s->syscfg_exticr3 = (value & 0xFFFF);
112bbbbd900SAlistair Francis         return;
113bbbbd900SAlistair Francis     case SYSCFG_EXTICR4:
114bbbbd900SAlistair Francis         s->syscfg_exticr4 = (value & 0xFFFF);
115bbbbd900SAlistair Francis         return;
116bbbbd900SAlistair Francis     case SYSCFG_CMPCR:
117bbbbd900SAlistair Francis         s->syscfg_cmpcr = value;
118bbbbd900SAlistair Francis         return;
119bbbbd900SAlistair Francis     default:
120bbbbd900SAlistair Francis         qemu_log_mask(LOG_GUEST_ERROR,
121bbbbd900SAlistair Francis                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
122bbbbd900SAlistair Francis     }
123bbbbd900SAlistair Francis }
124bbbbd900SAlistair Francis 
125bbbbd900SAlistair Francis static const MemoryRegionOps stm32f2xx_syscfg_ops = {
126bbbbd900SAlistair Francis     .read = stm32f2xx_syscfg_read,
127bbbbd900SAlistair Francis     .write = stm32f2xx_syscfg_write,
128bbbbd900SAlistair Francis     .endianness = DEVICE_NATIVE_ENDIAN,
129bbbbd900SAlistair Francis };
130bbbbd900SAlistair Francis 
131bbbbd900SAlistair Francis static void stm32f2xx_syscfg_init(Object *obj)
132bbbbd900SAlistair Francis {
133bbbbd900SAlistair Francis     STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj);
134bbbbd900SAlistair Francis 
135bbbbd900SAlistair Francis     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
136bbbbd900SAlistair Francis 
137bbbbd900SAlistair Francis     memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s,
138bbbbd900SAlistair Francis                           TYPE_STM32F2XX_SYSCFG, 0x400);
139bbbbd900SAlistair Francis     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
140bbbbd900SAlistair Francis }
141bbbbd900SAlistair Francis 
142bbbbd900SAlistair Francis static void stm32f2xx_syscfg_class_init(ObjectClass *klass, void *data)
143bbbbd900SAlistair Francis {
144bbbbd900SAlistair Francis     DeviceClass *dc = DEVICE_CLASS(klass);
145bbbbd900SAlistair Francis 
146bbbbd900SAlistair Francis     dc->reset = stm32f2xx_syscfg_reset;
147bbbbd900SAlistair Francis }
148bbbbd900SAlistair Francis 
149bbbbd900SAlistair Francis static const TypeInfo stm32f2xx_syscfg_info = {
150bbbbd900SAlistair Francis     .name          = TYPE_STM32F2XX_SYSCFG,
151bbbbd900SAlistair Francis     .parent        = TYPE_SYS_BUS_DEVICE,
152bbbbd900SAlistair Francis     .instance_size = sizeof(STM32F2XXSyscfgState),
153bbbbd900SAlistair Francis     .instance_init = stm32f2xx_syscfg_init,
154bbbbd900SAlistair Francis     .class_init    = stm32f2xx_syscfg_class_init,
155bbbbd900SAlistair Francis };
156bbbbd900SAlistair Francis 
157bbbbd900SAlistair Francis static void stm32f2xx_syscfg_register_types(void)
158bbbbd900SAlistair Francis {
159bbbbd900SAlistair Francis     type_register_static(&stm32f2xx_syscfg_info);
160bbbbd900SAlistair Francis }
161bbbbd900SAlistair Francis 
162bbbbd900SAlistair Francis type_init(stm32f2xx_syscfg_register_types)
163