1 /* 2 * QEMU PowerMac CUDA device support 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu-common.h" 28 #include "hw/ppc/mac.h" 29 #include "hw/qdev-properties.h" 30 #include "migration/vmstate.h" 31 #include "hw/input/adb.h" 32 #include "hw/misc/mos6522.h" 33 #include "hw/misc/macio/cuda.h" 34 #include "qemu/timer.h" 35 #include "sysemu/runstate.h" 36 #include "qapi/error.h" 37 #include "qemu/cutils.h" 38 #include "qemu/log.h" 39 #include "qemu/module.h" 40 #include "trace.h" 41 42 /* Bits in B data register: all active low */ 43 #define TREQ 0x08 /* Transfer request (input) */ 44 #define TACK 0x10 /* Transfer acknowledge (output) */ 45 #define TIP 0x20 /* Transfer in progress (output) */ 46 47 /* commands (1st byte) */ 48 #define ADB_PACKET 0 49 #define CUDA_PACKET 1 50 #define ERROR_PACKET 2 51 #define TIMER_PACKET 3 52 #define POWER_PACKET 4 53 #define MACIIC_PACKET 5 54 #define PMU_PACKET 6 55 56 #define CUDA_TIMER_FREQ (4700000 / 6) 57 58 /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */ 59 #define RTC_OFFSET 2082844800 60 61 static void cuda_receive_packet_from_host(CUDAState *s, 62 const uint8_t *data, int len); 63 64 /* MacOS uses timer 1 for calibration on startup, so we use 65 * the timebase frequency and cuda_get_counter_value() with 66 * cuda_get_load_time() to steer MacOS to calculate calibrate its timers 67 * correctly for both TCG and KVM (see commit b981289c49 "PPC: Cuda: Use cuda 68 * timer to expose tbfreq to guest" for more information) */ 69 70 static uint64_t cuda_get_counter_value(MOS6522State *s, MOS6522Timer *ti) 71 { 72 MOS6522CUDAState *mcs = container_of(s, MOS6522CUDAState, parent_obj); 73 CUDAState *cs = container_of(mcs, CUDAState, mos6522_cuda); 74 75 /* Reverse of the tb calculation algorithm that Mac OS X uses on bootup */ 76 uint64_t tb_diff = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 77 cs->tb_frequency, NANOSECONDS_PER_SECOND) - 78 ti->load_time; 79 80 return (tb_diff * 0xBF401675E5DULL) / (cs->tb_frequency << 24); 81 } 82 83 static uint64_t cuda_get_load_time(MOS6522State *s, MOS6522Timer *ti) 84 { 85 MOS6522CUDAState *mcs = container_of(s, MOS6522CUDAState, parent_obj); 86 CUDAState *cs = container_of(mcs, CUDAState, mos6522_cuda); 87 88 uint64_t load_time = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 89 cs->tb_frequency, NANOSECONDS_PER_SECOND); 90 return load_time; 91 } 92 93 static void cuda_set_sr_int(void *opaque) 94 { 95 CUDAState *s = opaque; 96 MOS6522CUDAState *mcs = &s->mos6522_cuda; 97 MOS6522State *ms = MOS6522(mcs); 98 MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(ms); 99 100 mdc->set_sr_int(ms); 101 } 102 103 static void cuda_delay_set_sr_int(CUDAState *s) 104 { 105 int64_t expire; 106 107 trace_cuda_delay_set_sr_int(); 108 109 expire = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->sr_delay_ns; 110 timer_mod(s->sr_delay_timer, expire); 111 } 112 113 /* NOTE: TIP and TREQ are negated */ 114 static void cuda_update(CUDAState *s) 115 { 116 MOS6522CUDAState *mcs = &s->mos6522_cuda; 117 MOS6522State *ms = MOS6522(mcs); 118 int packet_received, len; 119 120 packet_received = 0; 121 if (!(ms->b & TIP)) { 122 /* transfer requested from host */ 123 124 if (ms->acr & SR_OUT) { 125 /* data output */ 126 if ((ms->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) { 127 if (s->data_out_index < sizeof(s->data_out)) { 128 trace_cuda_data_send(ms->sr); 129 s->data_out[s->data_out_index++] = ms->sr; 130 cuda_delay_set_sr_int(s); 131 } 132 } 133 } else { 134 if (s->data_in_index < s->data_in_size) { 135 /* data input */ 136 if ((ms->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) { 137 ms->sr = s->data_in[s->data_in_index++]; 138 trace_cuda_data_recv(ms->sr); 139 /* indicate end of transfer */ 140 if (s->data_in_index >= s->data_in_size) { 141 ms->b = (ms->b | TREQ); 142 } 143 cuda_delay_set_sr_int(s); 144 } 145 } 146 } 147 } else { 148 /* no transfer requested: handle sync case */ 149 if ((s->last_b & TIP) && (ms->b & TACK) != (s->last_b & TACK)) { 150 /* update TREQ state each time TACK change state */ 151 if (ms->b & TACK) { 152 ms->b = (ms->b | TREQ); 153 } else { 154 ms->b = (ms->b & ~TREQ); 155 } 156 cuda_delay_set_sr_int(s); 157 } else { 158 if (!(s->last_b & TIP)) { 159 /* handle end of host to cuda transfer */ 160 packet_received = (s->data_out_index > 0); 161 /* always an IRQ at the end of transfer */ 162 cuda_delay_set_sr_int(s); 163 } 164 /* signal if there is data to read */ 165 if (s->data_in_index < s->data_in_size) { 166 ms->b = (ms->b & ~TREQ); 167 } 168 } 169 } 170 171 s->last_acr = ms->acr; 172 s->last_b = ms->b; 173 174 /* NOTE: cuda_receive_packet_from_host() can call cuda_update() 175 recursively */ 176 if (packet_received) { 177 len = s->data_out_index; 178 s->data_out_index = 0; 179 cuda_receive_packet_from_host(s, s->data_out, len); 180 } 181 } 182 183 static void cuda_send_packet_to_host(CUDAState *s, 184 const uint8_t *data, int len) 185 { 186 int i; 187 188 trace_cuda_packet_send(len); 189 for (i = 0; i < len; i++) { 190 trace_cuda_packet_send_data(i, data[i]); 191 } 192 193 memcpy(s->data_in, data, len); 194 s->data_in_size = len; 195 s->data_in_index = 0; 196 cuda_update(s); 197 cuda_delay_set_sr_int(s); 198 } 199 200 static void cuda_adb_poll(void *opaque) 201 { 202 CUDAState *s = opaque; 203 uint8_t obuf[ADB_MAX_OUT_LEN + 2]; 204 int olen; 205 206 olen = adb_poll(&s->adb_bus, obuf + 2, s->adb_poll_mask); 207 if (olen > 0) { 208 obuf[0] = ADB_PACKET; 209 obuf[1] = 0x40; /* polled data */ 210 cuda_send_packet_to_host(s, obuf, olen + 2); 211 } 212 timer_mod(s->adb_poll_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 213 (NANOSECONDS_PER_SECOND / (1000 / s->autopoll_rate_ms))); 214 } 215 216 /* description of commands */ 217 typedef struct CudaCommand { 218 uint8_t command; 219 const char *name; 220 bool (*handler)(CUDAState *s, 221 const uint8_t *in_args, int in_len, 222 uint8_t *out_args, int *out_len); 223 } CudaCommand; 224 225 static bool cuda_cmd_autopoll(CUDAState *s, 226 const uint8_t *in_data, int in_len, 227 uint8_t *out_data, int *out_len) 228 { 229 int autopoll; 230 231 if (in_len != 1) { 232 return false; 233 } 234 235 autopoll = (in_data[0] != 0); 236 if (autopoll != s->autopoll) { 237 s->autopoll = autopoll; 238 if (autopoll) { 239 timer_mod(s->adb_poll_timer, 240 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 241 (NANOSECONDS_PER_SECOND / (1000 / s->autopoll_rate_ms))); 242 } else { 243 timer_del(s->adb_poll_timer); 244 } 245 } 246 return true; 247 } 248 249 static bool cuda_cmd_set_autorate(CUDAState *s, 250 const uint8_t *in_data, int in_len, 251 uint8_t *out_data, int *out_len) 252 { 253 if (in_len != 1) { 254 return false; 255 } 256 257 /* we don't want a period of 0 ms */ 258 /* FIXME: check what real hardware does */ 259 if (in_data[0] == 0) { 260 return false; 261 } 262 263 s->autopoll_rate_ms = in_data[0]; 264 if (s->autopoll) { 265 timer_mod(s->adb_poll_timer, 266 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 267 (NANOSECONDS_PER_SECOND / (1000 / s->autopoll_rate_ms))); 268 } 269 return true; 270 } 271 272 static bool cuda_cmd_set_device_list(CUDAState *s, 273 const uint8_t *in_data, int in_len, 274 uint8_t *out_data, int *out_len) 275 { 276 if (in_len != 2) { 277 return false; 278 } 279 280 s->adb_poll_mask = (((uint16_t)in_data[0]) << 8) | in_data[1]; 281 return true; 282 } 283 284 static bool cuda_cmd_powerdown(CUDAState *s, 285 const uint8_t *in_data, int in_len, 286 uint8_t *out_data, int *out_len) 287 { 288 if (in_len != 0) { 289 return false; 290 } 291 292 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 293 return true; 294 } 295 296 static bool cuda_cmd_reset_system(CUDAState *s, 297 const uint8_t *in_data, int in_len, 298 uint8_t *out_data, int *out_len) 299 { 300 if (in_len != 0) { 301 return false; 302 } 303 304 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 305 return true; 306 } 307 308 static bool cuda_cmd_set_file_server_flag(CUDAState *s, 309 const uint8_t *in_data, int in_len, 310 uint8_t *out_data, int *out_len) 311 { 312 if (in_len != 1) { 313 return false; 314 } 315 316 qemu_log_mask(LOG_UNIMP, 317 "CUDA: unimplemented command FILE_SERVER_FLAG %d\n", 318 in_data[0]); 319 return true; 320 } 321 322 static bool cuda_cmd_set_power_message(CUDAState *s, 323 const uint8_t *in_data, int in_len, 324 uint8_t *out_data, int *out_len) 325 { 326 if (in_len != 1) { 327 return false; 328 } 329 330 qemu_log_mask(LOG_UNIMP, 331 "CUDA: unimplemented command SET_POWER_MESSAGE %d\n", 332 in_data[0]); 333 return true; 334 } 335 336 static bool cuda_cmd_get_time(CUDAState *s, 337 const uint8_t *in_data, int in_len, 338 uint8_t *out_data, int *out_len) 339 { 340 uint32_t ti; 341 342 if (in_len != 0) { 343 return false; 344 } 345 346 ti = s->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) 347 / NANOSECONDS_PER_SECOND); 348 out_data[0] = ti >> 24; 349 out_data[1] = ti >> 16; 350 out_data[2] = ti >> 8; 351 out_data[3] = ti; 352 *out_len = 4; 353 return true; 354 } 355 356 static bool cuda_cmd_set_time(CUDAState *s, 357 const uint8_t *in_data, int in_len, 358 uint8_t *out_data, int *out_len) 359 { 360 uint32_t ti; 361 362 if (in_len != 4) { 363 return false; 364 } 365 366 ti = (((uint32_t)in_data[0]) << 24) + (((uint32_t)in_data[1]) << 16) 367 + (((uint32_t)in_data[2]) << 8) + in_data[3]; 368 s->tick_offset = ti - (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) 369 / NANOSECONDS_PER_SECOND); 370 return true; 371 } 372 373 static const CudaCommand handlers[] = { 374 { CUDA_AUTOPOLL, "AUTOPOLL", cuda_cmd_autopoll }, 375 { CUDA_SET_AUTO_RATE, "SET_AUTO_RATE", cuda_cmd_set_autorate }, 376 { CUDA_SET_DEVICE_LIST, "SET_DEVICE_LIST", cuda_cmd_set_device_list }, 377 { CUDA_POWERDOWN, "POWERDOWN", cuda_cmd_powerdown }, 378 { CUDA_RESET_SYSTEM, "RESET_SYSTEM", cuda_cmd_reset_system }, 379 { CUDA_FILE_SERVER_FLAG, "FILE_SERVER_FLAG", 380 cuda_cmd_set_file_server_flag }, 381 { CUDA_SET_POWER_MESSAGES, "SET_POWER_MESSAGES", 382 cuda_cmd_set_power_message }, 383 { CUDA_GET_TIME, "GET_TIME", cuda_cmd_get_time }, 384 { CUDA_SET_TIME, "SET_TIME", cuda_cmd_set_time }, 385 }; 386 387 static void cuda_receive_packet(CUDAState *s, 388 const uint8_t *data, int len) 389 { 390 uint8_t obuf[16] = { CUDA_PACKET, 0, data[0] }; 391 int i, out_len = 0; 392 393 for (i = 0; i < ARRAY_SIZE(handlers); i++) { 394 const CudaCommand *desc = &handlers[i]; 395 if (desc->command == data[0]) { 396 trace_cuda_receive_packet_cmd(desc->name); 397 out_len = 0; 398 if (desc->handler(s, data + 1, len - 1, obuf + 3, &out_len)) { 399 cuda_send_packet_to_host(s, obuf, 3 + out_len); 400 } else { 401 qemu_log_mask(LOG_GUEST_ERROR, 402 "CUDA: %s: wrong parameters %d\n", 403 desc->name, len); 404 obuf[0] = ERROR_PACKET; 405 obuf[1] = 0x5; /* bad parameters */ 406 obuf[2] = CUDA_PACKET; 407 obuf[3] = data[0]; 408 cuda_send_packet_to_host(s, obuf, 4); 409 } 410 return; 411 } 412 } 413 414 qemu_log_mask(LOG_GUEST_ERROR, "CUDA: unknown command 0x%02x\n", data[0]); 415 obuf[0] = ERROR_PACKET; 416 obuf[1] = 0x2; /* unknown command */ 417 obuf[2] = CUDA_PACKET; 418 obuf[3] = data[0]; 419 cuda_send_packet_to_host(s, obuf, 4); 420 } 421 422 static void cuda_receive_packet_from_host(CUDAState *s, 423 const uint8_t *data, int len) 424 { 425 int i; 426 427 trace_cuda_packet_receive(len); 428 for (i = 0; i < len; i++) { 429 trace_cuda_packet_receive_data(i, data[i]); 430 } 431 432 switch(data[0]) { 433 case ADB_PACKET: 434 { 435 uint8_t obuf[ADB_MAX_OUT_LEN + 3]; 436 int olen; 437 olen = adb_request(&s->adb_bus, obuf + 2, data + 1, len - 1); 438 if (olen > 0) { 439 obuf[0] = ADB_PACKET; 440 obuf[1] = 0x00; 441 cuda_send_packet_to_host(s, obuf, olen + 2); 442 } else { 443 /* error */ 444 obuf[0] = ADB_PACKET; 445 obuf[1] = -olen; 446 obuf[2] = data[1]; 447 olen = 0; 448 cuda_send_packet_to_host(s, obuf, olen + 3); 449 } 450 } 451 break; 452 case CUDA_PACKET: 453 cuda_receive_packet(s, data + 1, len - 1); 454 break; 455 } 456 } 457 458 static uint64_t mos6522_cuda_read(void *opaque, hwaddr addr, unsigned size) 459 { 460 CUDAState *s = opaque; 461 MOS6522CUDAState *mcs = &s->mos6522_cuda; 462 MOS6522State *ms = MOS6522(mcs); 463 464 addr = (addr >> 9) & 0xf; 465 return mos6522_read(ms, addr, size); 466 } 467 468 static void mos6522_cuda_write(void *opaque, hwaddr addr, uint64_t val, 469 unsigned size) 470 { 471 CUDAState *s = opaque; 472 MOS6522CUDAState *mcs = &s->mos6522_cuda; 473 MOS6522State *ms = MOS6522(mcs); 474 475 addr = (addr >> 9) & 0xf; 476 mos6522_write(ms, addr, val, size); 477 } 478 479 static const MemoryRegionOps mos6522_cuda_ops = { 480 .read = mos6522_cuda_read, 481 .write = mos6522_cuda_write, 482 .endianness = DEVICE_BIG_ENDIAN, 483 .valid = { 484 .min_access_size = 1, 485 .max_access_size = 1, 486 }, 487 }; 488 489 static const VMStateDescription vmstate_cuda = { 490 .name = "cuda", 491 .version_id = 5, 492 .minimum_version_id = 5, 493 .fields = (VMStateField[]) { 494 VMSTATE_STRUCT(mos6522_cuda.parent_obj, CUDAState, 0, vmstate_mos6522, 495 MOS6522State), 496 VMSTATE_UINT8(last_b, CUDAState), 497 VMSTATE_UINT8(last_acr, CUDAState), 498 VMSTATE_INT32(data_in_size, CUDAState), 499 VMSTATE_INT32(data_in_index, CUDAState), 500 VMSTATE_INT32(data_out_index, CUDAState), 501 VMSTATE_UINT8(autopoll, CUDAState), 502 VMSTATE_UINT8(autopoll_rate_ms, CUDAState), 503 VMSTATE_UINT16(adb_poll_mask, CUDAState), 504 VMSTATE_BUFFER(data_in, CUDAState), 505 VMSTATE_BUFFER(data_out, CUDAState), 506 VMSTATE_UINT32(tick_offset, CUDAState), 507 VMSTATE_TIMER_PTR(adb_poll_timer, CUDAState), 508 VMSTATE_TIMER_PTR(sr_delay_timer, CUDAState), 509 VMSTATE_END_OF_LIST() 510 } 511 }; 512 513 static void cuda_reset(DeviceState *dev) 514 { 515 CUDAState *s = CUDA(dev); 516 517 s->data_in_size = 0; 518 s->data_in_index = 0; 519 s->data_out_index = 0; 520 s->autopoll = 0; 521 } 522 523 static void cuda_realize(DeviceState *dev, Error **errp) 524 { 525 CUDAState *s = CUDA(dev); 526 Error *err = NULL; 527 SysBusDevice *sbd; 528 struct tm tm; 529 530 object_property_set_bool(OBJECT(&s->mos6522_cuda), true, "realized", 531 &err); 532 if (err) { 533 error_propagate(errp, err); 534 return; 535 } 536 537 /* Pass IRQ from 6522 */ 538 sbd = SYS_BUS_DEVICE(s); 539 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->mos6522_cuda)); 540 541 qemu_get_timedate(&tm, 0); 542 s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; 543 544 s->sr_delay_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_set_sr_int, s); 545 s->sr_delay_ns = 20 * SCALE_US; 546 547 s->adb_poll_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_adb_poll, s); 548 s->adb_poll_mask = 0xffff; 549 s->autopoll_rate_ms = 20; 550 } 551 552 static void cuda_init(Object *obj) 553 { 554 CUDAState *s = CUDA(obj); 555 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 556 557 sysbus_init_child_obj(obj, "mos6522-cuda", &s->mos6522_cuda, 558 sizeof(s->mos6522_cuda), TYPE_MOS6522_CUDA); 559 560 memory_region_init_io(&s->mem, obj, &mos6522_cuda_ops, s, "cuda", 0x2000); 561 sysbus_init_mmio(sbd, &s->mem); 562 563 qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS, 564 DEVICE(obj), "adb.0"); 565 } 566 567 static Property cuda_properties[] = { 568 DEFINE_PROP_UINT64("timebase-frequency", CUDAState, tb_frequency, 0), 569 DEFINE_PROP_END_OF_LIST() 570 }; 571 572 static void cuda_class_init(ObjectClass *oc, void *data) 573 { 574 DeviceClass *dc = DEVICE_CLASS(oc); 575 576 dc->realize = cuda_realize; 577 dc->reset = cuda_reset; 578 dc->vmsd = &vmstate_cuda; 579 device_class_set_props(dc, cuda_properties); 580 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 581 } 582 583 static const TypeInfo cuda_type_info = { 584 .name = TYPE_CUDA, 585 .parent = TYPE_SYS_BUS_DEVICE, 586 .instance_size = sizeof(CUDAState), 587 .instance_init = cuda_init, 588 .class_init = cuda_class_init, 589 }; 590 591 static void mos6522_cuda_portB_write(MOS6522State *s) 592 { 593 MOS6522CUDAState *mcs = container_of(s, MOS6522CUDAState, parent_obj); 594 CUDAState *cs = container_of(mcs, CUDAState, mos6522_cuda); 595 596 cuda_update(cs); 597 } 598 599 static void mos6522_cuda_reset(DeviceState *dev) 600 { 601 MOS6522State *ms = MOS6522(dev); 602 MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(ms); 603 604 mdc->parent_reset(dev); 605 606 ms->timers[0].frequency = CUDA_TIMER_FREQ; 607 ms->timers[1].frequency = (SCALE_US * 6000) / 4700; 608 } 609 610 static void mos6522_cuda_class_init(ObjectClass *oc, void *data) 611 { 612 DeviceClass *dc = DEVICE_CLASS(oc); 613 MOS6522DeviceClass *mdc = MOS6522_DEVICE_CLASS(oc); 614 615 dc->reset = mos6522_cuda_reset; 616 mdc->portB_write = mos6522_cuda_portB_write; 617 mdc->get_timer1_counter_value = cuda_get_counter_value; 618 mdc->get_timer2_counter_value = cuda_get_counter_value; 619 mdc->get_timer1_load_time = cuda_get_load_time; 620 mdc->get_timer2_load_time = cuda_get_load_time; 621 } 622 623 static const TypeInfo mos6522_cuda_type_info = { 624 .name = TYPE_MOS6522_CUDA, 625 .parent = TYPE_MOS6522, 626 .instance_size = sizeof(MOS6522CUDAState), 627 .class_init = mos6522_cuda_class_init, 628 }; 629 630 static void cuda_register_types(void) 631 { 632 type_register_static(&mos6522_cuda_type_info); 633 type_register_static(&cuda_type_info); 634 } 635 636 type_init(cuda_register_types) 637