1 /* 2 * GICv2m extension for MSI/MSI-x support with a GICv2-based system 3 * 4 * Copyright (C) 2015 Linaro, All rights reserved. 5 * 6 * Author: Christoffer Dall <christoffer.dall@linaro.org> 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 /* This file implements an emulated GICv2m widget as described in the ARM 23 * Server Base System Architecture (SBSA) specification Version 2.2 24 * (ARM-DEN-0029 v2.2) pages 35-39 without any optional implementation defined 25 * identification registers and with a single non-secure MSI register frame. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qapi/error.h" 30 #include "hw/sysbus.h" 31 #include "hw/pci/msi.h" 32 #include "sysemu/kvm.h" 33 34 #define TYPE_ARM_GICV2M "arm-gicv2m" 35 #define ARM_GICV2M(obj) OBJECT_CHECK(ARMGICv2mState, (obj), TYPE_ARM_GICV2M) 36 37 #define GICV2M_NUM_SPI_MAX 128 38 39 #define V2M_MSI_TYPER 0x008 40 #define V2M_MSI_SETSPI_NS 0x040 41 #define V2M_MSI_IIDR 0xFCC 42 #define V2M_IIDR0 0xFD0 43 #define V2M_IIDR11 0xFFC 44 45 #define PRODUCT_ID_QEMU 0x51 /* ASCII code Q */ 46 47 typedef struct ARMGICv2mState { 48 SysBusDevice parent_obj; 49 50 MemoryRegion iomem; 51 qemu_irq spi[GICV2M_NUM_SPI_MAX]; 52 53 uint32_t base_spi; 54 uint32_t num_spi; 55 } ARMGICv2mState; 56 57 static void gicv2m_set_irq(void *opaque, int irq) 58 { 59 ARMGICv2mState *s = (ARMGICv2mState *)opaque; 60 61 qemu_irq_pulse(s->spi[irq]); 62 } 63 64 static uint64_t gicv2m_read(void *opaque, hwaddr offset, 65 unsigned size) 66 { 67 ARMGICv2mState *s = (ARMGICv2mState *)opaque; 68 uint32_t val; 69 70 if (size != 4) { 71 qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_read: bad size %u\n", size); 72 return 0; 73 } 74 75 switch (offset) { 76 case V2M_MSI_TYPER: 77 val = (s->base_spi + 32) << 16; 78 val |= s->num_spi; 79 return val; 80 case V2M_MSI_IIDR: 81 /* We don't have any valid implementor so we leave that field as zero 82 * and we return 0 in the arch revision as per the spec. 83 */ 84 return (PRODUCT_ID_QEMU << 20); 85 case V2M_IIDR0 ... V2M_IIDR11: 86 /* We do not implement any optional identification registers and the 87 * mandatory MSI_PIDR2 register reads as 0x0, so we capture all 88 * implementation defined registers here. 89 */ 90 return 0; 91 default: 92 qemu_log_mask(LOG_GUEST_ERROR, 93 "gicv2m_read: Bad offset %x\n", (int)offset); 94 return 0; 95 } 96 } 97 98 static void gicv2m_write(void *opaque, hwaddr offset, 99 uint64_t value, unsigned size) 100 { 101 ARMGICv2mState *s = (ARMGICv2mState *)opaque; 102 103 if (size != 2 && size != 4) { 104 qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_write: bad size %u\n", size); 105 return; 106 } 107 108 switch (offset) { 109 case V2M_MSI_SETSPI_NS: { 110 int spi; 111 112 spi = (value & 0x3ff) - (s->base_spi + 32); 113 if (spi >= 0 && spi < s->num_spi) { 114 gicv2m_set_irq(s, spi); 115 } 116 return; 117 } 118 default: 119 qemu_log_mask(LOG_GUEST_ERROR, 120 "gicv2m_write: Bad offset %x\n", (int)offset); 121 } 122 } 123 124 static const MemoryRegionOps gicv2m_ops = { 125 .read = gicv2m_read, 126 .write = gicv2m_write, 127 .endianness = DEVICE_LITTLE_ENDIAN, 128 }; 129 130 static void gicv2m_realize(DeviceState *dev, Error **errp) 131 { 132 ARMGICv2mState *s = ARM_GICV2M(dev); 133 int i; 134 135 if (s->num_spi > GICV2M_NUM_SPI_MAX) { 136 error_setg(errp, 137 "requested %u SPIs exceeds GICv2m frame maximum %d", 138 s->num_spi, GICV2M_NUM_SPI_MAX); 139 return; 140 } 141 142 if (s->base_spi + 32 > 1020 - s->num_spi) { 143 error_setg(errp, 144 "requested base SPI %u+%u exceeds max. number 1020", 145 s->base_spi + 32, s->num_spi); 146 return; 147 } 148 149 for (i = 0; i < s->num_spi; i++) { 150 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->spi[i]); 151 } 152 153 msi_nonbroken = true; 154 kvm_gsi_direct_mapping = true; 155 kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled(); 156 } 157 158 static void gicv2m_init(Object *obj) 159 { 160 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 161 ARMGICv2mState *s = ARM_GICV2M(obj); 162 163 memory_region_init_io(&s->iomem, OBJECT(s), &gicv2m_ops, s, 164 "gicv2m", 0x1000); 165 sysbus_init_mmio(sbd, &s->iomem); 166 } 167 168 static Property gicv2m_properties[] = { 169 DEFINE_PROP_UINT32("base-spi", ARMGICv2mState, base_spi, 0), 170 DEFINE_PROP_UINT32("num-spi", ARMGICv2mState, num_spi, 64), 171 DEFINE_PROP_END_OF_LIST(), 172 }; 173 174 static void gicv2m_class_init(ObjectClass *klass, void *data) 175 { 176 DeviceClass *dc = DEVICE_CLASS(klass); 177 178 dc->props = gicv2m_properties; 179 dc->realize = gicv2m_realize; 180 } 181 182 static const TypeInfo gicv2m_info = { 183 .name = TYPE_ARM_GICV2M, 184 .parent = TYPE_SYS_BUS_DEVICE, 185 .instance_size = sizeof(ARMGICv2mState), 186 .instance_init = gicv2m_init, 187 .class_init = gicv2m_class_init, 188 }; 189 190 static void gicv2m_register_types(void) 191 { 192 type_register_static(&gicv2m_info); 193 } 194 195 type_init(gicv2m_register_types) 196