1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "hw/hw.h" 26 #include "hw/i386/pc.h" 27 #include "hw/char/serial.h" 28 #include "hw/i386/apic.h" 29 #include "hw/i386/topology.h" 30 #include "sysemu/cpus.h" 31 #include "hw/block/fdc.h" 32 #include "hw/ide.h" 33 #include "hw/pci/pci.h" 34 #include "hw/pci/pci_bus.h" 35 #include "hw/nvram/fw_cfg.h" 36 #include "hw/timer/hpet.h" 37 #include "hw/smbios/smbios.h" 38 #include "hw/loader.h" 39 #include "elf.h" 40 #include "multiboot.h" 41 #include "hw/timer/mc146818rtc.h" 42 #include "hw/timer/i8254.h" 43 #include "hw/audio/pcspk.h" 44 #include "hw/pci/msi.h" 45 #include "hw/sysbus.h" 46 #include "sysemu/sysemu.h" 47 #include "sysemu/numa.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/qtest.h" 50 #include "kvm_i386.h" 51 #include "hw/xen/xen.h" 52 #include "sysemu/block-backend.h" 53 #include "hw/block/block.h" 54 #include "ui/qemu-spice.h" 55 #include "exec/memory.h" 56 #include "exec/address-spaces.h" 57 #include "sysemu/arch_init.h" 58 #include "qemu/bitmap.h" 59 #include "qemu/config-file.h" 60 #include "qemu/error-report.h" 61 #include "hw/acpi/acpi.h" 62 #include "hw/acpi/cpu_hotplug.h" 63 #include "hw/boards.h" 64 #include "hw/pci/pci_host.h" 65 #include "acpi-build.h" 66 #include "hw/mem/pc-dimm.h" 67 #include "qapi/visitor.h" 68 #include "qapi-visit.h" 69 #include "qom/cpu.h" 70 #include "hw/nmi.h" 71 72 /* debug PC/ISA interrupts */ 73 //#define DEBUG_IRQ 74 75 #ifdef DEBUG_IRQ 76 #define DPRINTF(fmt, ...) \ 77 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 78 #else 79 #define DPRINTF(fmt, ...) 80 #endif 81 82 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 83 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 84 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 85 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 86 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 87 88 #define E820_NR_ENTRIES 16 89 90 struct e820_entry { 91 uint64_t address; 92 uint64_t length; 93 uint32_t type; 94 } QEMU_PACKED __attribute((__aligned__(4))); 95 96 struct e820_table { 97 uint32_t count; 98 struct e820_entry entry[E820_NR_ENTRIES]; 99 } QEMU_PACKED __attribute((__aligned__(4))); 100 101 static struct e820_table e820_reserve; 102 static struct e820_entry *e820_table; 103 static unsigned e820_entries; 104 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 105 106 void gsi_handler(void *opaque, int n, int level) 107 { 108 GSIState *s = opaque; 109 110 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 111 if (n < ISA_NUM_IRQS) { 112 qemu_set_irq(s->i8259_irq[n], level); 113 } 114 qemu_set_irq(s->ioapic_irq[n], level); 115 } 116 117 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 118 unsigned size) 119 { 120 } 121 122 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 123 { 124 return 0xffffffffffffffffULL; 125 } 126 127 /* MSDOS compatibility mode FPU exception support */ 128 static qemu_irq ferr_irq; 129 130 void pc_register_ferr_irq(qemu_irq irq) 131 { 132 ferr_irq = irq; 133 } 134 135 /* XXX: add IGNNE support */ 136 void cpu_set_ferr(CPUX86State *s) 137 { 138 qemu_irq_raise(ferr_irq); 139 } 140 141 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 142 unsigned size) 143 { 144 qemu_irq_lower(ferr_irq); 145 } 146 147 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 148 { 149 return 0xffffffffffffffffULL; 150 } 151 152 /* TSC handling */ 153 uint64_t cpu_get_tsc(CPUX86State *env) 154 { 155 return cpu_get_ticks(); 156 } 157 158 /* IRQ handling */ 159 int cpu_get_pic_interrupt(CPUX86State *env) 160 { 161 X86CPU *cpu = x86_env_get_cpu(env); 162 int intno; 163 164 intno = apic_get_interrupt(cpu->apic_state); 165 if (intno >= 0) { 166 return intno; 167 } 168 /* read the irq from the PIC */ 169 if (!apic_accept_pic_intr(cpu->apic_state)) { 170 return -1; 171 } 172 173 intno = pic_read_irq(isa_pic); 174 return intno; 175 } 176 177 static void pic_irq_request(void *opaque, int irq, int level) 178 { 179 CPUState *cs = first_cpu; 180 X86CPU *cpu = X86_CPU(cs); 181 182 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 183 if (cpu->apic_state) { 184 CPU_FOREACH(cs) { 185 cpu = X86_CPU(cs); 186 if (apic_accept_pic_intr(cpu->apic_state)) { 187 apic_deliver_pic_intr(cpu->apic_state, level); 188 } 189 } 190 } else { 191 if (level) { 192 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 193 } else { 194 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 195 } 196 } 197 } 198 199 /* PC cmos mappings */ 200 201 #define REG_EQUIPMENT_BYTE 0x14 202 203 int cmos_get_fd_drive_type(FloppyDriveType fd0) 204 { 205 int val; 206 207 switch (fd0) { 208 case FLOPPY_DRIVE_TYPE_144: 209 /* 1.44 Mb 3"5 drive */ 210 val = 4; 211 break; 212 case FLOPPY_DRIVE_TYPE_288: 213 /* 2.88 Mb 3"5 drive */ 214 val = 5; 215 break; 216 case FLOPPY_DRIVE_TYPE_120: 217 /* 1.2 Mb 5"5 drive */ 218 val = 2; 219 break; 220 case FLOPPY_DRIVE_TYPE_NONE: 221 default: 222 val = 0; 223 break; 224 } 225 return val; 226 } 227 228 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 229 int16_t cylinders, int8_t heads, int8_t sectors) 230 { 231 rtc_set_memory(s, type_ofs, 47); 232 rtc_set_memory(s, info_ofs, cylinders); 233 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 234 rtc_set_memory(s, info_ofs + 2, heads); 235 rtc_set_memory(s, info_ofs + 3, 0xff); 236 rtc_set_memory(s, info_ofs + 4, 0xff); 237 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 238 rtc_set_memory(s, info_ofs + 6, cylinders); 239 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 240 rtc_set_memory(s, info_ofs + 8, sectors); 241 } 242 243 /* convert boot_device letter to something recognizable by the bios */ 244 static int boot_device2nibble(char boot_device) 245 { 246 switch(boot_device) { 247 case 'a': 248 case 'b': 249 return 0x01; /* floppy boot */ 250 case 'c': 251 return 0x02; /* hard drive boot */ 252 case 'd': 253 return 0x03; /* CD-ROM boot */ 254 case 'n': 255 return 0x04; /* Network boot */ 256 } 257 return 0; 258 } 259 260 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 261 { 262 #define PC_MAX_BOOT_DEVICES 3 263 int nbds, bds[3] = { 0, }; 264 int i; 265 266 nbds = strlen(boot_device); 267 if (nbds > PC_MAX_BOOT_DEVICES) { 268 error_setg(errp, "Too many boot devices for PC"); 269 return; 270 } 271 for (i = 0; i < nbds; i++) { 272 bds[i] = boot_device2nibble(boot_device[i]); 273 if (bds[i] == 0) { 274 error_setg(errp, "Invalid boot device for PC: '%c'", 275 boot_device[i]); 276 return; 277 } 278 } 279 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 280 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 281 } 282 283 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 284 { 285 set_boot_dev(opaque, boot_device, errp); 286 } 287 288 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 289 { 290 int val, nb, i; 291 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 292 FLOPPY_DRIVE_TYPE_NONE }; 293 294 /* floppy type */ 295 if (floppy) { 296 for (i = 0; i < 2; i++) { 297 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 298 } 299 } 300 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 301 cmos_get_fd_drive_type(fd_type[1]); 302 rtc_set_memory(rtc_state, 0x10, val); 303 304 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 305 nb = 0; 306 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 307 nb++; 308 } 309 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 310 nb++; 311 } 312 switch (nb) { 313 case 0: 314 break; 315 case 1: 316 val |= 0x01; /* 1 drive, ready for boot */ 317 break; 318 case 2: 319 val |= 0x41; /* 2 drives, ready for boot */ 320 break; 321 } 322 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 323 } 324 325 typedef struct pc_cmos_init_late_arg { 326 ISADevice *rtc_state; 327 BusState *idebus[2]; 328 } pc_cmos_init_late_arg; 329 330 typedef struct check_fdc_state { 331 ISADevice *floppy; 332 bool multiple; 333 } CheckFdcState; 334 335 static int check_fdc(Object *obj, void *opaque) 336 { 337 CheckFdcState *state = opaque; 338 Object *fdc; 339 uint32_t iobase; 340 Error *local_err = NULL; 341 342 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 343 if (!fdc) { 344 return 0; 345 } 346 347 iobase = object_property_get_int(obj, "iobase", &local_err); 348 if (local_err || iobase != 0x3f0) { 349 error_free(local_err); 350 return 0; 351 } 352 353 if (state->floppy) { 354 state->multiple = true; 355 } else { 356 state->floppy = ISA_DEVICE(obj); 357 } 358 return 0; 359 } 360 361 static const char * const fdc_container_path[] = { 362 "/unattached", "/peripheral", "/peripheral-anon" 363 }; 364 365 /* 366 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 367 * and ACPI objects. 368 */ 369 ISADevice *pc_find_fdc0(void) 370 { 371 int i; 372 Object *container; 373 CheckFdcState state = { 0 }; 374 375 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 376 container = container_get(qdev_get_machine(), fdc_container_path[i]); 377 object_child_foreach(container, check_fdc, &state); 378 } 379 380 if (state.multiple) { 381 error_report("warning: multiple floppy disk controllers with " 382 "iobase=0x3f0 have been found"); 383 error_printf("the one being picked for CMOS setup might not reflect " 384 "your intent"); 385 } 386 387 return state.floppy; 388 } 389 390 static void pc_cmos_init_late(void *opaque) 391 { 392 pc_cmos_init_late_arg *arg = opaque; 393 ISADevice *s = arg->rtc_state; 394 int16_t cylinders; 395 int8_t heads, sectors; 396 int val; 397 int i, trans; 398 399 val = 0; 400 if (ide_get_geometry(arg->idebus[0], 0, 401 &cylinders, &heads, §ors) >= 0) { 402 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 403 val |= 0xf0; 404 } 405 if (ide_get_geometry(arg->idebus[0], 1, 406 &cylinders, &heads, §ors) >= 0) { 407 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 408 val |= 0x0f; 409 } 410 rtc_set_memory(s, 0x12, val); 411 412 val = 0; 413 for (i = 0; i < 4; i++) { 414 /* NOTE: ide_get_geometry() returns the physical 415 geometry. It is always such that: 1 <= sects <= 63, 1 416 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 417 geometry can be different if a translation is done. */ 418 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 419 &cylinders, &heads, §ors) >= 0) { 420 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 421 assert((trans & ~3) == 0); 422 val |= trans << (i * 2); 423 } 424 } 425 rtc_set_memory(s, 0x39, val); 426 427 pc_cmos_init_floppy(s, pc_find_fdc0()); 428 429 qemu_unregister_reset(pc_cmos_init_late, opaque); 430 } 431 432 void pc_cmos_init(PCMachineState *pcms, 433 BusState *idebus0, BusState *idebus1, 434 ISADevice *s) 435 { 436 int val; 437 static pc_cmos_init_late_arg arg; 438 439 /* various important CMOS locations needed by PC/Bochs bios */ 440 441 /* memory size */ 442 /* base memory (first MiB) */ 443 val = MIN(pcms->below_4g_mem_size / 1024, 640); 444 rtc_set_memory(s, 0x15, val); 445 rtc_set_memory(s, 0x16, val >> 8); 446 /* extended memory (next 64MiB) */ 447 if (pcms->below_4g_mem_size > 1024 * 1024) { 448 val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024; 449 } else { 450 val = 0; 451 } 452 if (val > 65535) 453 val = 65535; 454 rtc_set_memory(s, 0x17, val); 455 rtc_set_memory(s, 0x18, val >> 8); 456 rtc_set_memory(s, 0x30, val); 457 rtc_set_memory(s, 0x31, val >> 8); 458 /* memory between 16MiB and 4GiB */ 459 if (pcms->below_4g_mem_size > 16 * 1024 * 1024) { 460 val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536; 461 } else { 462 val = 0; 463 } 464 if (val > 65535) 465 val = 65535; 466 rtc_set_memory(s, 0x34, val); 467 rtc_set_memory(s, 0x35, val >> 8); 468 /* memory above 4GiB */ 469 val = pcms->above_4g_mem_size / 65536; 470 rtc_set_memory(s, 0x5b, val); 471 rtc_set_memory(s, 0x5c, val >> 8); 472 rtc_set_memory(s, 0x5d, val >> 16); 473 474 /* set the number of CPU */ 475 rtc_set_memory(s, 0x5f, smp_cpus - 1); 476 477 object_property_add_link(OBJECT(pcms), "rtc_state", 478 TYPE_ISA_DEVICE, 479 (Object **)&pcms->rtc, 480 object_property_allow_set_link, 481 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 482 object_property_set_link(OBJECT(pcms), OBJECT(s), 483 "rtc_state", &error_abort); 484 485 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 486 487 val = 0; 488 val |= 0x02; /* FPU is there */ 489 val |= 0x04; /* PS/2 mouse installed */ 490 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 491 492 /* hard drives and FDC */ 493 arg.rtc_state = s; 494 arg.idebus[0] = idebus0; 495 arg.idebus[1] = idebus1; 496 qemu_register_reset(pc_cmos_init_late, &arg); 497 } 498 499 #define TYPE_PORT92 "port92" 500 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 501 502 /* port 92 stuff: could be split off */ 503 typedef struct Port92State { 504 ISADevice parent_obj; 505 506 MemoryRegion io; 507 uint8_t outport; 508 qemu_irq a20_out; 509 } Port92State; 510 511 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 512 unsigned size) 513 { 514 Port92State *s = opaque; 515 int oldval = s->outport; 516 517 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 518 s->outport = val; 519 qemu_set_irq(s->a20_out, (val >> 1) & 1); 520 if ((val & 1) && !(oldval & 1)) { 521 qemu_system_reset_request(); 522 } 523 } 524 525 static uint64_t port92_read(void *opaque, hwaddr addr, 526 unsigned size) 527 { 528 Port92State *s = opaque; 529 uint32_t ret; 530 531 ret = s->outport; 532 DPRINTF("port92: read 0x%02x\n", ret); 533 return ret; 534 } 535 536 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 537 { 538 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, *a20_out); 539 } 540 541 static const VMStateDescription vmstate_port92_isa = { 542 .name = "port92", 543 .version_id = 1, 544 .minimum_version_id = 1, 545 .fields = (VMStateField[]) { 546 VMSTATE_UINT8(outport, Port92State), 547 VMSTATE_END_OF_LIST() 548 } 549 }; 550 551 static void port92_reset(DeviceState *d) 552 { 553 Port92State *s = PORT92(d); 554 555 s->outport &= ~1; 556 } 557 558 static const MemoryRegionOps port92_ops = { 559 .read = port92_read, 560 .write = port92_write, 561 .impl = { 562 .min_access_size = 1, 563 .max_access_size = 1, 564 }, 565 .endianness = DEVICE_LITTLE_ENDIAN, 566 }; 567 568 static void port92_initfn(Object *obj) 569 { 570 Port92State *s = PORT92(obj); 571 572 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 573 574 s->outport = 0; 575 576 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); 577 } 578 579 static void port92_realizefn(DeviceState *dev, Error **errp) 580 { 581 ISADevice *isadev = ISA_DEVICE(dev); 582 Port92State *s = PORT92(dev); 583 584 isa_register_ioport(isadev, &s->io, 0x92); 585 } 586 587 static void port92_class_initfn(ObjectClass *klass, void *data) 588 { 589 DeviceClass *dc = DEVICE_CLASS(klass); 590 591 dc->realize = port92_realizefn; 592 dc->reset = port92_reset; 593 dc->vmsd = &vmstate_port92_isa; 594 /* 595 * Reason: unlike ordinary ISA devices, this one needs additional 596 * wiring: its A20 output line needs to be wired up by 597 * port92_init(). 598 */ 599 dc->cannot_instantiate_with_device_add_yet = true; 600 } 601 602 static const TypeInfo port92_info = { 603 .name = TYPE_PORT92, 604 .parent = TYPE_ISA_DEVICE, 605 .instance_size = sizeof(Port92State), 606 .instance_init = port92_initfn, 607 .class_init = port92_class_initfn, 608 }; 609 610 static void port92_register_types(void) 611 { 612 type_register_static(&port92_info); 613 } 614 615 type_init(port92_register_types) 616 617 static void handle_a20_line_change(void *opaque, int irq, int level) 618 { 619 X86CPU *cpu = opaque; 620 621 /* XXX: send to all CPUs ? */ 622 /* XXX: add logic to handle multiple A20 line sources */ 623 x86_cpu_set_a20(cpu, level); 624 } 625 626 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 627 { 628 int index = le32_to_cpu(e820_reserve.count); 629 struct e820_entry *entry; 630 631 if (type != E820_RAM) { 632 /* old FW_CFG_E820_TABLE entry -- reservations only */ 633 if (index >= E820_NR_ENTRIES) { 634 return -EBUSY; 635 } 636 entry = &e820_reserve.entry[index++]; 637 638 entry->address = cpu_to_le64(address); 639 entry->length = cpu_to_le64(length); 640 entry->type = cpu_to_le32(type); 641 642 e820_reserve.count = cpu_to_le32(index); 643 } 644 645 /* new "etc/e820" file -- include ram too */ 646 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 647 e820_table[e820_entries].address = cpu_to_le64(address); 648 e820_table[e820_entries].length = cpu_to_le64(length); 649 e820_table[e820_entries].type = cpu_to_le32(type); 650 e820_entries++; 651 652 return e820_entries; 653 } 654 655 int e820_get_num_entries(void) 656 { 657 return e820_entries; 658 } 659 660 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 661 { 662 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 663 *address = le64_to_cpu(e820_table[idx].address); 664 *length = le64_to_cpu(e820_table[idx].length); 665 return true; 666 } 667 return false; 668 } 669 670 /* Enables contiguous-apic-ID mode, for compatibility */ 671 static bool compat_apic_id_mode; 672 673 void enable_compat_apic_id_mode(void) 674 { 675 compat_apic_id_mode = true; 676 } 677 678 /* Calculates initial APIC ID for a specific CPU index 679 * 680 * Currently we need to be able to calculate the APIC ID from the CPU index 681 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 682 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 683 * all CPUs up to max_cpus. 684 */ 685 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 686 { 687 uint32_t correct_id; 688 static bool warned; 689 690 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 691 if (compat_apic_id_mode) { 692 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 693 error_report("APIC IDs set in compatibility mode, " 694 "CPU topology won't match the configuration"); 695 warned = true; 696 } 697 return cpu_index; 698 } else { 699 return correct_id; 700 } 701 } 702 703 static void pc_build_smbios(FWCfgState *fw_cfg) 704 { 705 uint8_t *smbios_tables, *smbios_anchor; 706 size_t smbios_tables_len, smbios_anchor_len; 707 struct smbios_phys_mem_area *mem_array; 708 unsigned i, array_count; 709 710 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 711 if (smbios_tables) { 712 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 713 smbios_tables, smbios_tables_len); 714 } 715 716 /* build the array of physical mem area from e820 table */ 717 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); 718 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { 719 uint64_t addr, len; 720 721 if (e820_get_entry(i, E820_RAM, &addr, &len)) { 722 mem_array[array_count].address = addr; 723 mem_array[array_count].length = len; 724 array_count++; 725 } 726 } 727 smbios_get_tables(mem_array, array_count, 728 &smbios_tables, &smbios_tables_len, 729 &smbios_anchor, &smbios_anchor_len); 730 g_free(mem_array); 731 732 if (smbios_anchor) { 733 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 734 smbios_tables, smbios_tables_len); 735 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 736 smbios_anchor, smbios_anchor_len); 737 } 738 } 739 740 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) 741 { 742 FWCfgState *fw_cfg; 743 uint64_t *numa_fw_cfg; 744 int i, j; 745 746 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); 747 748 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 749 * 750 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 751 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 752 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 753 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 754 * may see". 755 * 756 * So, this means we must not use max_cpus, here, but the maximum possible 757 * APIC ID value, plus one. 758 * 759 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 760 * the APIC ID, not the "CPU index" 761 */ 762 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); 763 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 764 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 765 acpi_tables, acpi_tables_len); 766 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 767 768 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 769 &e820_reserve, sizeof(e820_reserve)); 770 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 771 sizeof(struct e820_entry) * e820_entries); 772 773 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 774 /* allocate memory for the NUMA channel: one (64bit) word for the number 775 * of nodes, one word for each VCPU->node and one word for each node to 776 * hold the amount of memory. 777 */ 778 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); 779 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 780 for (i = 0; i < max_cpus; i++) { 781 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 782 assert(apic_id < pcms->apic_id_limit); 783 for (j = 0; j < nb_numa_nodes; j++) { 784 if (test_bit(i, numa_info[j].node_cpu)) { 785 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 786 break; 787 } 788 } 789 } 790 for (i = 0; i < nb_numa_nodes; i++) { 791 numa_fw_cfg[pcms->apic_id_limit + 1 + i] = 792 cpu_to_le64(numa_info[i].node_mem); 793 } 794 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 795 (1 + pcms->apic_id_limit + nb_numa_nodes) * 796 sizeof(*numa_fw_cfg)); 797 798 return fw_cfg; 799 } 800 801 static long get_file_size(FILE *f) 802 { 803 long where, size; 804 805 /* XXX: on Unix systems, using fstat() probably makes more sense */ 806 807 where = ftell(f); 808 fseek(f, 0, SEEK_END); 809 size = ftell(f); 810 fseek(f, where, SEEK_SET); 811 812 return size; 813 } 814 815 static void load_linux(PCMachineState *pcms, 816 FWCfgState *fw_cfg) 817 { 818 uint16_t protocol; 819 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 820 uint32_t initrd_max; 821 uint8_t header[8192], *setup, *kernel, *initrd_data; 822 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 823 FILE *f; 824 char *vmode; 825 MachineState *machine = MACHINE(pcms); 826 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 827 const char *kernel_filename = machine->kernel_filename; 828 const char *initrd_filename = machine->initrd_filename; 829 const char *kernel_cmdline = machine->kernel_cmdline; 830 831 /* Align to 16 bytes as a paranoia measure */ 832 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 833 834 /* load the kernel header */ 835 f = fopen(kernel_filename, "rb"); 836 if (!f || !(kernel_size = get_file_size(f)) || 837 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 838 MIN(ARRAY_SIZE(header), kernel_size)) { 839 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 840 kernel_filename, strerror(errno)); 841 exit(1); 842 } 843 844 /* kernel protocol version */ 845 #if 0 846 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 847 #endif 848 if (ldl_p(header+0x202) == 0x53726448) { 849 protocol = lduw_p(header+0x206); 850 } else { 851 /* This looks like a multiboot kernel. If it is, let's stop 852 treating it like a Linux kernel. */ 853 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 854 kernel_cmdline, kernel_size, header)) { 855 return; 856 } 857 protocol = 0; 858 } 859 860 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 861 /* Low kernel */ 862 real_addr = 0x90000; 863 cmdline_addr = 0x9a000 - cmdline_size; 864 prot_addr = 0x10000; 865 } else if (protocol < 0x202) { 866 /* High but ancient kernel */ 867 real_addr = 0x90000; 868 cmdline_addr = 0x9a000 - cmdline_size; 869 prot_addr = 0x100000; 870 } else { 871 /* High and recent kernel */ 872 real_addr = 0x10000; 873 cmdline_addr = 0x20000; 874 prot_addr = 0x100000; 875 } 876 877 #if 0 878 fprintf(stderr, 879 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 880 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 881 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 882 real_addr, 883 cmdline_addr, 884 prot_addr); 885 #endif 886 887 /* highest address for loading the initrd */ 888 if (protocol >= 0x203) { 889 initrd_max = ldl_p(header+0x22c); 890 } else { 891 initrd_max = 0x37ffffff; 892 } 893 894 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { 895 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 896 } 897 898 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 899 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 900 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 901 902 if (protocol >= 0x202) { 903 stl_p(header+0x228, cmdline_addr); 904 } else { 905 stw_p(header+0x20, 0xA33F); 906 stw_p(header+0x22, cmdline_addr-real_addr); 907 } 908 909 /* handle vga= parameter */ 910 vmode = strstr(kernel_cmdline, "vga="); 911 if (vmode) { 912 unsigned int video_mode; 913 /* skip "vga=" */ 914 vmode += 4; 915 if (!strncmp(vmode, "normal", 6)) { 916 video_mode = 0xffff; 917 } else if (!strncmp(vmode, "ext", 3)) { 918 video_mode = 0xfffe; 919 } else if (!strncmp(vmode, "ask", 3)) { 920 video_mode = 0xfffd; 921 } else { 922 video_mode = strtol(vmode, NULL, 0); 923 } 924 stw_p(header+0x1fa, video_mode); 925 } 926 927 /* loader type */ 928 /* High nybble = B reserved for QEMU; low nybble is revision number. 929 If this code is substantially changed, you may want to consider 930 incrementing the revision. */ 931 if (protocol >= 0x200) { 932 header[0x210] = 0xB0; 933 } 934 /* heap */ 935 if (protocol >= 0x201) { 936 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 937 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 938 } 939 940 /* load initrd */ 941 if (initrd_filename) { 942 if (protocol < 0x200) { 943 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 944 exit(1); 945 } 946 947 initrd_size = get_image_size(initrd_filename); 948 if (initrd_size < 0) { 949 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 950 initrd_filename, strerror(errno)); 951 exit(1); 952 } 953 954 initrd_addr = (initrd_max-initrd_size) & ~4095; 955 956 initrd_data = g_malloc(initrd_size); 957 load_image(initrd_filename, initrd_data); 958 959 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 960 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 961 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 962 963 stl_p(header+0x218, initrd_addr); 964 stl_p(header+0x21c, initrd_size); 965 } 966 967 /* load kernel and setup */ 968 setup_size = header[0x1f1]; 969 if (setup_size == 0) { 970 setup_size = 4; 971 } 972 setup_size = (setup_size+1)*512; 973 if (setup_size > kernel_size) { 974 fprintf(stderr, "qemu: invalid kernel header\n"); 975 exit(1); 976 } 977 kernel_size -= setup_size; 978 979 setup = g_malloc(setup_size); 980 kernel = g_malloc(kernel_size); 981 fseek(f, 0, SEEK_SET); 982 if (fread(setup, 1, setup_size, f) != setup_size) { 983 fprintf(stderr, "fread() failed\n"); 984 exit(1); 985 } 986 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 987 fprintf(stderr, "fread() failed\n"); 988 exit(1); 989 } 990 fclose(f); 991 memcpy(setup, header, MIN(sizeof(header), setup_size)); 992 993 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 994 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 995 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 996 997 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 998 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 999 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1000 1001 option_rom[nb_option_roms].name = "linuxboot.bin"; 1002 option_rom[nb_option_roms].bootindex = 0; 1003 nb_option_roms++; 1004 } 1005 1006 #define NE2000_NB_MAX 6 1007 1008 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1009 0x280, 0x380 }; 1010 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1011 1012 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1013 { 1014 static int nb_ne2k = 0; 1015 1016 if (nb_ne2k == NE2000_NB_MAX) 1017 return; 1018 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1019 ne2000_irq[nb_ne2k], nd); 1020 nb_ne2k++; 1021 } 1022 1023 DeviceState *cpu_get_current_apic(void) 1024 { 1025 if (current_cpu) { 1026 X86CPU *cpu = X86_CPU(current_cpu); 1027 return cpu->apic_state; 1028 } else { 1029 return NULL; 1030 } 1031 } 1032 1033 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1034 { 1035 X86CPU *cpu = opaque; 1036 1037 if (level) { 1038 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1039 } 1040 } 1041 1042 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 1043 Error **errp) 1044 { 1045 X86CPU *cpu = NULL; 1046 Error *local_err = NULL; 1047 1048 cpu = cpu_x86_create(cpu_model, &local_err); 1049 if (local_err != NULL) { 1050 goto out; 1051 } 1052 1053 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 1054 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 1055 1056 out: 1057 if (local_err) { 1058 error_propagate(errp, local_err); 1059 object_unref(OBJECT(cpu)); 1060 cpu = NULL; 1061 } 1062 return cpu; 1063 } 1064 1065 void pc_hot_add_cpu(const int64_t id, Error **errp) 1066 { 1067 X86CPU *cpu; 1068 MachineState *machine = MACHINE(qdev_get_machine()); 1069 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1070 Error *local_err = NULL; 1071 1072 if (id < 0) { 1073 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1074 return; 1075 } 1076 1077 if (cpu_exists(apic_id)) { 1078 error_setg(errp, "Unable to add CPU: %" PRIi64 1079 ", it already exists", id); 1080 return; 1081 } 1082 1083 if (id >= max_cpus) { 1084 error_setg(errp, "Unable to add CPU: %" PRIi64 1085 ", max allowed: %d", id, max_cpus - 1); 1086 return; 1087 } 1088 1089 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1090 error_setg(errp, "Unable to add CPU: %" PRIi64 1091 ", resulting APIC ID (%" PRIi64 ") is too large", 1092 id, apic_id); 1093 return; 1094 } 1095 1096 cpu = pc_new_cpu(machine->cpu_model, apic_id, &local_err); 1097 if (local_err) { 1098 error_propagate(errp, local_err); 1099 return; 1100 } 1101 object_unref(OBJECT(cpu)); 1102 } 1103 1104 void pc_cpus_init(PCMachineState *pcms) 1105 { 1106 int i; 1107 X86CPU *cpu = NULL; 1108 MachineState *machine = MACHINE(pcms); 1109 1110 /* init CPUs */ 1111 if (machine->cpu_model == NULL) { 1112 #ifdef TARGET_X86_64 1113 machine->cpu_model = "qemu64"; 1114 #else 1115 machine->cpu_model = "qemu32"; 1116 #endif 1117 } 1118 1119 /* Calculates the limit to CPU APIC ID values 1120 * 1121 * Limit for the APIC ID value, so that all 1122 * CPU APIC IDs are < pcms->apic_id_limit. 1123 * 1124 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 1125 */ 1126 pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 1127 if (pcms->apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { 1128 error_report("max_cpus is too large. APIC ID of last CPU is %u", 1129 pcms->apic_id_limit - 1); 1130 exit(1); 1131 } 1132 1133 pcms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1134 sizeof(CPUArchId) * max_cpus); 1135 for (i = 0; i < max_cpus; i++) { 1136 pcms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i); 1137 pcms->possible_cpus->len++; 1138 if (i < smp_cpus) { 1139 cpu = pc_new_cpu(machine->cpu_model, x86_cpu_apic_id_from_index(i), 1140 &error_fatal); 1141 pcms->possible_cpus->cpus[i].cpu = CPU(cpu); 1142 object_unref(OBJECT(cpu)); 1143 } 1144 } 1145 1146 /* tell smbios about cpuid version and features */ 1147 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1148 } 1149 1150 static 1151 void pc_machine_done(Notifier *notifier, void *data) 1152 { 1153 PCMachineState *pcms = container_of(notifier, 1154 PCMachineState, machine_done); 1155 PCIBus *bus = pcms->bus; 1156 1157 if (bus) { 1158 int extra_hosts = 0; 1159 1160 QLIST_FOREACH(bus, &bus->child, sibling) { 1161 /* look for expander root buses */ 1162 if (pci_bus_is_root(bus)) { 1163 extra_hosts++; 1164 } 1165 } 1166 if (extra_hosts && pcms->fw_cfg) { 1167 uint64_t *val = g_malloc(sizeof(*val)); 1168 *val = cpu_to_le64(extra_hosts); 1169 fw_cfg_add_file(pcms->fw_cfg, 1170 "etc/extra-pci-roots", val, sizeof(*val)); 1171 } 1172 } 1173 1174 acpi_setup(); 1175 if (pcms->fw_cfg) { 1176 pc_build_smbios(pcms->fw_cfg); 1177 } 1178 } 1179 1180 void pc_guest_info_init(PCMachineState *pcms) 1181 { 1182 int i; 1183 1184 pcms->apic_xrupt_override = kvm_allows_irq0_override(); 1185 pcms->numa_nodes = nb_numa_nodes; 1186 pcms->node_mem = g_malloc0(pcms->numa_nodes * 1187 sizeof *pcms->node_mem); 1188 for (i = 0; i < nb_numa_nodes; i++) { 1189 pcms->node_mem[i] = numa_info[i].node_mem; 1190 } 1191 1192 pcms->machine_done.notify = pc_machine_done; 1193 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1194 } 1195 1196 /* setup pci memory address space mapping into system address space */ 1197 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1198 MemoryRegion *pci_address_space) 1199 { 1200 /* Set to lower priority than RAM */ 1201 memory_region_add_subregion_overlap(system_memory, 0x0, 1202 pci_address_space, -1); 1203 } 1204 1205 void pc_acpi_init(const char *default_dsdt) 1206 { 1207 char *filename; 1208 1209 if (acpi_tables != NULL) { 1210 /* manually set via -acpitable, leave it alone */ 1211 return; 1212 } 1213 1214 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1215 if (filename == NULL) { 1216 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1217 } else { 1218 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, 1219 &error_abort); 1220 Error *err = NULL; 1221 1222 qemu_opt_set(opts, "file", filename, &error_abort); 1223 1224 acpi_table_add_builtin(opts, &err); 1225 if (err) { 1226 error_reportf_err(err, "WARNING: failed to load %s: ", 1227 filename); 1228 } 1229 g_free(filename); 1230 } 1231 } 1232 1233 void xen_load_linux(PCMachineState *pcms) 1234 { 1235 int i; 1236 FWCfgState *fw_cfg; 1237 1238 assert(MACHINE(pcms)->kernel_filename != NULL); 1239 1240 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 1241 rom_set_fw(fw_cfg); 1242 1243 load_linux(pcms, fw_cfg); 1244 for (i = 0; i < nb_option_roms; i++) { 1245 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1246 !strcmp(option_rom[i].name, "multiboot.bin")); 1247 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1248 } 1249 pcms->fw_cfg = fw_cfg; 1250 } 1251 1252 void pc_memory_init(PCMachineState *pcms, 1253 MemoryRegion *system_memory, 1254 MemoryRegion *rom_memory, 1255 MemoryRegion **ram_memory) 1256 { 1257 int linux_boot, i; 1258 MemoryRegion *ram, *option_rom_mr; 1259 MemoryRegion *ram_below_4g, *ram_above_4g; 1260 FWCfgState *fw_cfg; 1261 MachineState *machine = MACHINE(pcms); 1262 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1263 1264 assert(machine->ram_size == pcms->below_4g_mem_size + 1265 pcms->above_4g_mem_size); 1266 1267 linux_boot = (machine->kernel_filename != NULL); 1268 1269 /* Allocate RAM. We allocate it as a single memory region and use 1270 * aliases to address portions of it, mostly for backwards compatibility 1271 * with older qemus that used qemu_ram_alloc(). 1272 */ 1273 ram = g_malloc(sizeof(*ram)); 1274 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1275 machine->ram_size); 1276 *ram_memory = ram; 1277 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1278 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1279 0, pcms->below_4g_mem_size); 1280 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1281 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); 1282 if (pcms->above_4g_mem_size > 0) { 1283 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1284 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1285 pcms->below_4g_mem_size, 1286 pcms->above_4g_mem_size); 1287 memory_region_add_subregion(system_memory, 0x100000000ULL, 1288 ram_above_4g); 1289 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); 1290 } 1291 1292 if (!pcmc->has_reserved_memory && 1293 (machine->ram_slots || 1294 (machine->maxram_size > machine->ram_size))) { 1295 MachineClass *mc = MACHINE_GET_CLASS(machine); 1296 1297 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1298 mc->name); 1299 exit(EXIT_FAILURE); 1300 } 1301 1302 /* initialize hotplug memory address space */ 1303 if (pcmc->has_reserved_memory && 1304 (machine->ram_size < machine->maxram_size)) { 1305 ram_addr_t hotplug_mem_size = 1306 machine->maxram_size - machine->ram_size; 1307 1308 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1309 error_report("unsupported amount of memory slots: %"PRIu64, 1310 machine->ram_slots); 1311 exit(EXIT_FAILURE); 1312 } 1313 1314 if (QEMU_ALIGN_UP(machine->maxram_size, 1315 TARGET_PAGE_SIZE) != machine->maxram_size) { 1316 error_report("maximum memory size must by aligned to multiple of " 1317 "%d bytes", TARGET_PAGE_SIZE); 1318 exit(EXIT_FAILURE); 1319 } 1320 1321 pcms->hotplug_memory.base = 1322 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30); 1323 1324 if (pcmc->enforce_aligned_dimm) { 1325 /* size hotplug region assuming 1G page max alignment per slot */ 1326 hotplug_mem_size += (1ULL << 30) * machine->ram_slots; 1327 } 1328 1329 if ((pcms->hotplug_memory.base + hotplug_mem_size) < 1330 hotplug_mem_size) { 1331 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1332 machine->maxram_size); 1333 exit(EXIT_FAILURE); 1334 } 1335 1336 memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms), 1337 "hotplug-memory", hotplug_mem_size); 1338 memory_region_add_subregion(system_memory, pcms->hotplug_memory.base, 1339 &pcms->hotplug_memory.mr); 1340 } 1341 1342 /* Initialize PC system firmware */ 1343 pc_system_firmware_init(rom_memory, !pcmc->pci_enabled); 1344 1345 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1346 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1347 &error_fatal); 1348 vmstate_register_ram_global(option_rom_mr); 1349 memory_region_add_subregion_overlap(rom_memory, 1350 PC_ROM_MIN_VGA, 1351 option_rom_mr, 1352 1); 1353 1354 fw_cfg = bochs_bios_init(&address_space_memory, pcms); 1355 1356 rom_set_fw(fw_cfg); 1357 1358 if (pcmc->has_reserved_memory && pcms->hotplug_memory.base) { 1359 uint64_t *val = g_malloc(sizeof(*val)); 1360 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1361 uint64_t res_mem_end = pcms->hotplug_memory.base; 1362 1363 if (!pcmc->broken_reserved_end) { 1364 res_mem_end += memory_region_size(&pcms->hotplug_memory.mr); 1365 } 1366 *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30)); 1367 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1368 } 1369 1370 if (linux_boot) { 1371 load_linux(pcms, fw_cfg); 1372 } 1373 1374 for (i = 0; i < nb_option_roms; i++) { 1375 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1376 } 1377 pcms->fw_cfg = fw_cfg; 1378 } 1379 1380 qemu_irq pc_allocate_cpu_irq(void) 1381 { 1382 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1383 } 1384 1385 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1386 { 1387 DeviceState *dev = NULL; 1388 1389 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1390 if (pci_bus) { 1391 PCIDevice *pcidev = pci_vga_init(pci_bus); 1392 dev = pcidev ? &pcidev->qdev : NULL; 1393 } else if (isa_bus) { 1394 ISADevice *isadev = isa_vga_init(isa_bus); 1395 dev = isadev ? DEVICE(isadev) : NULL; 1396 } 1397 rom_reset_order_override(); 1398 return dev; 1399 } 1400 1401 static const MemoryRegionOps ioport80_io_ops = { 1402 .write = ioport80_write, 1403 .read = ioport80_read, 1404 .endianness = DEVICE_NATIVE_ENDIAN, 1405 .impl = { 1406 .min_access_size = 1, 1407 .max_access_size = 1, 1408 }, 1409 }; 1410 1411 static const MemoryRegionOps ioportF0_io_ops = { 1412 .write = ioportF0_write, 1413 .read = ioportF0_read, 1414 .endianness = DEVICE_NATIVE_ENDIAN, 1415 .impl = { 1416 .min_access_size = 1, 1417 .max_access_size = 1, 1418 }, 1419 }; 1420 1421 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1422 ISADevice **rtc_state, 1423 bool create_fdctrl, 1424 bool no_vmport, 1425 uint32_t hpet_irqs) 1426 { 1427 int i; 1428 DriveInfo *fd[MAX_FD]; 1429 DeviceState *hpet = NULL; 1430 int pit_isa_irq = 0; 1431 qemu_irq pit_alt_irq = NULL; 1432 qemu_irq rtc_irq = NULL; 1433 qemu_irq *a20_line; 1434 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1435 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1436 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1437 1438 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1439 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1440 1441 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1442 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1443 1444 /* 1445 * Check if an HPET shall be created. 1446 * 1447 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1448 * when the HPET wants to take over. Thus we have to disable the latter. 1449 */ 1450 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1451 /* In order to set property, here not using sysbus_try_create_simple */ 1452 hpet = qdev_try_create(NULL, TYPE_HPET); 1453 if (hpet) { 1454 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1455 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1456 * IRQ8 and IRQ2. 1457 */ 1458 uint8_t compat = object_property_get_int(OBJECT(hpet), 1459 HPET_INTCAP, NULL); 1460 if (!compat) { 1461 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1462 } 1463 qdev_init_nofail(hpet); 1464 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1465 1466 for (i = 0; i < GSI_NUM_PINS; i++) { 1467 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1468 } 1469 pit_isa_irq = -1; 1470 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1471 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1472 } 1473 } 1474 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1475 1476 qemu_register_boot_set(pc_boot_set, *rtc_state); 1477 1478 if (!xen_enabled()) { 1479 if (kvm_pit_in_kernel()) { 1480 pit = kvm_pit_init(isa_bus, 0x40); 1481 } else { 1482 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1483 } 1484 if (hpet) { 1485 /* connect PIT to output control line of the HPET */ 1486 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1487 } 1488 pcspk_init(isa_bus, pit); 1489 } 1490 1491 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); 1492 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1493 1494 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1495 i8042 = isa_create_simple(isa_bus, "i8042"); 1496 i8042_setup_a20_line(i8042, &a20_line[0]); 1497 if (!no_vmport) { 1498 vmport_init(isa_bus); 1499 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1500 } else { 1501 vmmouse = NULL; 1502 } 1503 if (vmmouse) { 1504 DeviceState *dev = DEVICE(vmmouse); 1505 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1506 qdev_init_nofail(dev); 1507 } 1508 port92 = isa_create_simple(isa_bus, "port92"); 1509 port92_init(port92, &a20_line[1]); 1510 1511 DMA_init(isa_bus, 0); 1512 1513 for(i = 0; i < MAX_FD; i++) { 1514 fd[i] = drive_get(IF_FLOPPY, 0, i); 1515 create_fdctrl |= !!fd[i]; 1516 } 1517 if (create_fdctrl) { 1518 fdctrl_init_isa(isa_bus, fd); 1519 } 1520 } 1521 1522 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1523 { 1524 int i; 1525 1526 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1527 for (i = 0; i < nb_nics; i++) { 1528 NICInfo *nd = &nd_table[i]; 1529 1530 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1531 pc_init_ne2k_isa(isa_bus, nd); 1532 } else { 1533 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1534 } 1535 } 1536 rom_reset_order_override(); 1537 } 1538 1539 void pc_pci_device_init(PCIBus *pci_bus) 1540 { 1541 int max_bus; 1542 int bus; 1543 1544 max_bus = drive_get_max_bus(IF_SCSI); 1545 for (bus = 0; bus <= max_bus; bus++) { 1546 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1547 } 1548 } 1549 1550 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1551 { 1552 DeviceState *dev; 1553 SysBusDevice *d; 1554 unsigned int i; 1555 1556 if (kvm_ioapic_in_kernel()) { 1557 dev = qdev_create(NULL, "kvm-ioapic"); 1558 } else { 1559 dev = qdev_create(NULL, "ioapic"); 1560 } 1561 if (parent_name) { 1562 object_property_add_child(object_resolve_path(parent_name, NULL), 1563 "ioapic", OBJECT(dev), NULL); 1564 } 1565 qdev_init_nofail(dev); 1566 d = SYS_BUS_DEVICE(dev); 1567 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1568 1569 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1570 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1571 } 1572 } 1573 1574 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1575 DeviceState *dev, Error **errp) 1576 { 1577 HotplugHandlerClass *hhc; 1578 Error *local_err = NULL; 1579 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1580 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1581 PCDIMMDevice *dimm = PC_DIMM(dev); 1582 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1583 MemoryRegion *mr = ddc->get_memory_region(dimm); 1584 uint64_t align = TARGET_PAGE_SIZE; 1585 1586 if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) { 1587 align = memory_region_get_alignment(mr); 1588 } 1589 1590 if (!pcms->acpi_dev) { 1591 error_setg(&local_err, 1592 "memory hotplug is not enabled: missing acpi device"); 1593 goto out; 1594 } 1595 1596 pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err); 1597 if (local_err) { 1598 goto out; 1599 } 1600 1601 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1602 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 1603 out: 1604 error_propagate(errp, local_err); 1605 } 1606 1607 static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev, 1608 DeviceState *dev, Error **errp) 1609 { 1610 HotplugHandlerClass *hhc; 1611 Error *local_err = NULL; 1612 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1613 1614 if (!pcms->acpi_dev) { 1615 error_setg(&local_err, 1616 "memory hotplug is not enabled: missing acpi device"); 1617 goto out; 1618 } 1619 1620 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1621 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1622 1623 out: 1624 error_propagate(errp, local_err); 1625 } 1626 1627 static void pc_dimm_unplug(HotplugHandler *hotplug_dev, 1628 DeviceState *dev, Error **errp) 1629 { 1630 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1631 PCDIMMDevice *dimm = PC_DIMM(dev); 1632 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1633 MemoryRegion *mr = ddc->get_memory_region(dimm); 1634 HotplugHandlerClass *hhc; 1635 Error *local_err = NULL; 1636 1637 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1638 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1639 1640 if (local_err) { 1641 goto out; 1642 } 1643 1644 pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr); 1645 object_unparent(OBJECT(dev)); 1646 1647 out: 1648 error_propagate(errp, local_err); 1649 } 1650 1651 static int pc_apic_cmp(const void *a, const void *b) 1652 { 1653 CPUArchId *apic_a = (CPUArchId *)a; 1654 CPUArchId *apic_b = (CPUArchId *)b; 1655 1656 return apic_a->arch_id - apic_b->arch_id; 1657 } 1658 1659 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1660 DeviceState *dev, Error **errp) 1661 { 1662 CPUClass *cc = CPU_GET_CLASS(dev); 1663 CPUArchId apic_id, *found_cpu; 1664 HotplugHandlerClass *hhc; 1665 Error *local_err = NULL; 1666 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1667 1668 if (!dev->hotplugged) { 1669 goto out; 1670 } 1671 1672 if (!pcms->acpi_dev) { 1673 error_setg(&local_err, 1674 "cpu hotplug is not enabled: missing acpi device"); 1675 goto out; 1676 } 1677 1678 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1679 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1680 if (local_err) { 1681 goto out; 1682 } 1683 1684 /* increment the number of CPUs */ 1685 rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); 1686 1687 apic_id.arch_id = cc->get_arch_id(CPU(dev)); 1688 found_cpu = bsearch(&apic_id, pcms->possible_cpus->cpus, 1689 pcms->possible_cpus->len, sizeof(*pcms->possible_cpus->cpus), 1690 pc_apic_cmp); 1691 assert(found_cpu); 1692 found_cpu->cpu = CPU(dev); 1693 out: 1694 error_propagate(errp, local_err); 1695 } 1696 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 1697 DeviceState *dev, Error **errp) 1698 { 1699 HotplugHandlerClass *hhc; 1700 Error *local_err = NULL; 1701 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1702 1703 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1704 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1705 1706 if (local_err) { 1707 goto out; 1708 } 1709 1710 out: 1711 error_propagate(errp, local_err); 1712 1713 } 1714 1715 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, 1716 DeviceState *dev, Error **errp) 1717 { 1718 HotplugHandlerClass *hhc; 1719 Error *local_err = NULL; 1720 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1721 1722 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1723 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1724 1725 if (local_err) { 1726 goto out; 1727 } 1728 1729 /* 1730 * TODO: enable unplug once generic CPU remove bits land 1731 * for now guest will be able to eject CPU ACPI wise but 1732 * it will come back again on machine reset. 1733 */ 1734 /* object_unparent(OBJECT(dev)); */ 1735 1736 out: 1737 error_propagate(errp, local_err); 1738 } 1739 1740 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1741 DeviceState *dev, Error **errp) 1742 { 1743 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1744 pc_dimm_plug(hotplug_dev, dev, errp); 1745 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1746 pc_cpu_plug(hotplug_dev, dev, errp); 1747 } 1748 } 1749 1750 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1751 DeviceState *dev, Error **errp) 1752 { 1753 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1754 pc_dimm_unplug_request(hotplug_dev, dev, errp); 1755 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1756 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1757 } else { 1758 error_setg(errp, "acpi: device unplug request for not supported device" 1759 " type: %s", object_get_typename(OBJECT(dev))); 1760 } 1761 } 1762 1763 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1764 DeviceState *dev, Error **errp) 1765 { 1766 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1767 pc_dimm_unplug(hotplug_dev, dev, errp); 1768 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1769 pc_cpu_unplug_cb(hotplug_dev, dev, errp); 1770 } else { 1771 error_setg(errp, "acpi: device unplug for not supported device" 1772 " type: %s", object_get_typename(OBJECT(dev))); 1773 } 1774 } 1775 1776 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 1777 DeviceState *dev) 1778 { 1779 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1780 1781 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1782 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1783 return HOTPLUG_HANDLER(machine); 1784 } 1785 1786 return pcmc->get_hotplug_handler ? 1787 pcmc->get_hotplug_handler(machine, dev) : NULL; 1788 } 1789 1790 static void 1791 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, 1792 const char *name, void *opaque, 1793 Error **errp) 1794 { 1795 PCMachineState *pcms = PC_MACHINE(obj); 1796 int64_t value = memory_region_size(&pcms->hotplug_memory.mr); 1797 1798 visit_type_int(v, name, &value, errp); 1799 } 1800 1801 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1802 const char *name, void *opaque, 1803 Error **errp) 1804 { 1805 PCMachineState *pcms = PC_MACHINE(obj); 1806 uint64_t value = pcms->max_ram_below_4g; 1807 1808 visit_type_size(v, name, &value, errp); 1809 } 1810 1811 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1812 const char *name, void *opaque, 1813 Error **errp) 1814 { 1815 PCMachineState *pcms = PC_MACHINE(obj); 1816 Error *error = NULL; 1817 uint64_t value; 1818 1819 visit_type_size(v, name, &value, &error); 1820 if (error) { 1821 error_propagate(errp, error); 1822 return; 1823 } 1824 if (value > (1ULL << 32)) { 1825 error_setg(&error, 1826 "Machine option 'max-ram-below-4g=%"PRIu64 1827 "' expects size less than or equal to 4G", value); 1828 error_propagate(errp, error); 1829 return; 1830 } 1831 1832 if (value < (1ULL << 20)) { 1833 error_report("Warning: small max_ram_below_4g(%"PRIu64 1834 ") less than 1M. BIOS may not work..", 1835 value); 1836 } 1837 1838 pcms->max_ram_below_4g = value; 1839 } 1840 1841 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1842 void *opaque, Error **errp) 1843 { 1844 PCMachineState *pcms = PC_MACHINE(obj); 1845 OnOffAuto vmport = pcms->vmport; 1846 1847 visit_type_OnOffAuto(v, name, &vmport, errp); 1848 } 1849 1850 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1851 void *opaque, Error **errp) 1852 { 1853 PCMachineState *pcms = PC_MACHINE(obj); 1854 1855 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1856 } 1857 1858 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 1859 { 1860 bool smm_available = false; 1861 1862 if (pcms->smm == ON_OFF_AUTO_OFF) { 1863 return false; 1864 } 1865 1866 if (tcg_enabled() || qtest_enabled()) { 1867 smm_available = true; 1868 } else if (kvm_enabled()) { 1869 smm_available = kvm_has_smm(); 1870 } 1871 1872 if (smm_available) { 1873 return true; 1874 } 1875 1876 if (pcms->smm == ON_OFF_AUTO_ON) { 1877 error_report("System Management Mode not supported by this hypervisor."); 1878 exit(1); 1879 } 1880 return false; 1881 } 1882 1883 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, 1884 void *opaque, Error **errp) 1885 { 1886 PCMachineState *pcms = PC_MACHINE(obj); 1887 OnOffAuto smm = pcms->smm; 1888 1889 visit_type_OnOffAuto(v, name, &smm, errp); 1890 } 1891 1892 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, 1893 void *opaque, Error **errp) 1894 { 1895 PCMachineState *pcms = PC_MACHINE(obj); 1896 1897 visit_type_OnOffAuto(v, name, &pcms->smm, errp); 1898 } 1899 1900 static bool pc_machine_get_nvdimm(Object *obj, Error **errp) 1901 { 1902 PCMachineState *pcms = PC_MACHINE(obj); 1903 1904 return pcms->acpi_nvdimm_state.is_enabled; 1905 } 1906 1907 static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp) 1908 { 1909 PCMachineState *pcms = PC_MACHINE(obj); 1910 1911 pcms->acpi_nvdimm_state.is_enabled = value; 1912 } 1913 1914 static void pc_machine_initfn(Object *obj) 1915 { 1916 PCMachineState *pcms = PC_MACHINE(obj); 1917 1918 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", 1919 pc_machine_get_hotplug_memory_region_size, 1920 NULL, NULL, NULL, &error_abort); 1921 1922 pcms->max_ram_below_4g = 0xe0000000; /* 3.5G */ 1923 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1924 pc_machine_get_max_ram_below_4g, 1925 pc_machine_set_max_ram_below_4g, 1926 NULL, NULL, &error_abort); 1927 object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G, 1928 "Maximum ram below the 4G boundary (32bit boundary)", 1929 &error_abort); 1930 1931 pcms->smm = ON_OFF_AUTO_AUTO; 1932 object_property_add(obj, PC_MACHINE_SMM, "OnOffAuto", 1933 pc_machine_get_smm, 1934 pc_machine_set_smm, 1935 NULL, NULL, &error_abort); 1936 object_property_set_description(obj, PC_MACHINE_SMM, 1937 "Enable SMM (pc & q35)", 1938 &error_abort); 1939 1940 pcms->vmport = ON_OFF_AUTO_AUTO; 1941 object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto", 1942 pc_machine_get_vmport, 1943 pc_machine_set_vmport, 1944 NULL, NULL, &error_abort); 1945 object_property_set_description(obj, PC_MACHINE_VMPORT, 1946 "Enable vmport (pc & q35)", 1947 &error_abort); 1948 1949 /* nvdimm is disabled on default. */ 1950 pcms->acpi_nvdimm_state.is_enabled = false; 1951 object_property_add_bool(obj, PC_MACHINE_NVDIMM, pc_machine_get_nvdimm, 1952 pc_machine_set_nvdimm, &error_abort); 1953 } 1954 1955 static void pc_machine_reset(void) 1956 { 1957 CPUState *cs; 1958 X86CPU *cpu; 1959 1960 qemu_devices_reset(); 1961 1962 /* Reset APIC after devices have been reset to cancel 1963 * any changes that qemu_devices_reset() might have done. 1964 */ 1965 CPU_FOREACH(cs) { 1966 cpu = X86_CPU(cs); 1967 1968 if (cpu->apic_state) { 1969 device_reset(cpu->apic_state); 1970 } 1971 } 1972 } 1973 1974 static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index) 1975 { 1976 X86CPUTopoInfo topo; 1977 x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index, 1978 &topo); 1979 return topo.pkg_id; 1980 } 1981 1982 static CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *machine) 1983 { 1984 PCMachineState *pcms = PC_MACHINE(machine); 1985 int len = sizeof(CPUArchIdList) + 1986 sizeof(CPUArchId) * (pcms->possible_cpus->len); 1987 CPUArchIdList *list = g_malloc(len); 1988 1989 memcpy(list, pcms->possible_cpus, len); 1990 return list; 1991 } 1992 1993 static void x86_nmi(NMIState *n, int cpu_index, Error **errp) 1994 { 1995 /* cpu index isn't used */ 1996 CPUState *cs; 1997 1998 CPU_FOREACH(cs) { 1999 X86CPU *cpu = X86_CPU(cs); 2000 2001 if (!cpu->apic_state) { 2002 cpu_interrupt(cs, CPU_INTERRUPT_NMI); 2003 } else { 2004 apic_deliver_nmi(cpu->apic_state); 2005 } 2006 } 2007 } 2008 2009 static void pc_machine_class_init(ObjectClass *oc, void *data) 2010 { 2011 MachineClass *mc = MACHINE_CLASS(oc); 2012 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 2013 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2014 NMIClass *nc = NMI_CLASS(oc); 2015 2016 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 2017 pcmc->pci_enabled = true; 2018 pcmc->has_acpi_build = true; 2019 pcmc->rsdp_in_ram = true; 2020 pcmc->smbios_defaults = true; 2021 pcmc->smbios_uuid_encoded = true; 2022 pcmc->gigabyte_align = true; 2023 pcmc->has_reserved_memory = true; 2024 pcmc->kvmclock_enabled = true; 2025 pcmc->enforce_aligned_dimm = true; 2026 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 2027 * to be used at the moment, 32K should be enough for a while. */ 2028 pcmc->acpi_data_size = 0x20000 + 0x8000; 2029 pcmc->save_tsc_khz = true; 2030 mc->get_hotplug_handler = pc_get_hotpug_handler; 2031 mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id; 2032 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; 2033 mc->default_boot_order = "cad"; 2034 mc->hot_add_cpu = pc_hot_add_cpu; 2035 mc->max_cpus = 255; 2036 mc->reset = pc_machine_reset; 2037 hc->plug = pc_machine_device_plug_cb; 2038 hc->unplug_request = pc_machine_device_unplug_request_cb; 2039 hc->unplug = pc_machine_device_unplug_cb; 2040 nc->nmi_monitor_handler = x86_nmi; 2041 } 2042 2043 static const TypeInfo pc_machine_info = { 2044 .name = TYPE_PC_MACHINE, 2045 .parent = TYPE_MACHINE, 2046 .abstract = true, 2047 .instance_size = sizeof(PCMachineState), 2048 .instance_init = pc_machine_initfn, 2049 .class_size = sizeof(PCMachineClass), 2050 .class_init = pc_machine_class_init, 2051 .interfaces = (InterfaceInfo[]) { 2052 { TYPE_HOTPLUG_HANDLER }, 2053 { TYPE_NMI }, 2054 { } 2055 }, 2056 }; 2057 2058 static void pc_machine_register_types(void) 2059 { 2060 type_register_static(&pc_machine_info); 2061 } 2062 2063 type_init(pc_machine_register_types) 2064