1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "hw/hw.h" 26 #include "hw/i386/pc.h" 27 #include "hw/char/serial.h" 28 #include "hw/i386/apic.h" 29 #include "hw/i386/topology.h" 30 #include "sysemu/cpus.h" 31 #include "hw/block/fdc.h" 32 #include "hw/ide.h" 33 #include "hw/pci/pci.h" 34 #include "hw/pci/pci_bus.h" 35 #include "hw/nvram/fw_cfg.h" 36 #include "hw/timer/hpet.h" 37 #include "hw/smbios/smbios.h" 38 #include "hw/loader.h" 39 #include "elf.h" 40 #include "multiboot.h" 41 #include "hw/timer/mc146818rtc.h" 42 #include "hw/timer/i8254.h" 43 #include "hw/audio/pcspk.h" 44 #include "hw/pci/msi.h" 45 #include "hw/sysbus.h" 46 #include "sysemu/sysemu.h" 47 #include "sysemu/numa.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/qtest.h" 50 #include "kvm_i386.h" 51 #include "hw/xen/xen.h" 52 #include "sysemu/block-backend.h" 53 #include "hw/block/block.h" 54 #include "ui/qemu-spice.h" 55 #include "exec/memory.h" 56 #include "exec/address-spaces.h" 57 #include "sysemu/arch_init.h" 58 #include "qemu/bitmap.h" 59 #include "qemu/config-file.h" 60 #include "qemu/error-report.h" 61 #include "hw/acpi/acpi.h" 62 #include "hw/acpi/cpu_hotplug.h" 63 #include "hw/boards.h" 64 #include "hw/pci/pci_host.h" 65 #include "acpi-build.h" 66 #include "hw/mem/pc-dimm.h" 67 #include "qapi/visitor.h" 68 #include "qapi-visit.h" 69 #include "qom/cpu.h" 70 #include "hw/nmi.h" 71 #include "hw/i386/intel_iommu.h" 72 73 /* debug PC/ISA interrupts */ 74 //#define DEBUG_IRQ 75 76 #ifdef DEBUG_IRQ 77 #define DPRINTF(fmt, ...) \ 78 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 79 #else 80 #define DPRINTF(fmt, ...) 81 #endif 82 83 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 84 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 85 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 86 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 87 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 88 89 #define E820_NR_ENTRIES 16 90 91 struct e820_entry { 92 uint64_t address; 93 uint64_t length; 94 uint32_t type; 95 } QEMU_PACKED __attribute((__aligned__(4))); 96 97 struct e820_table { 98 uint32_t count; 99 struct e820_entry entry[E820_NR_ENTRIES]; 100 } QEMU_PACKED __attribute((__aligned__(4))); 101 102 static struct e820_table e820_reserve; 103 static struct e820_entry *e820_table; 104 static unsigned e820_entries; 105 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 106 107 void gsi_handler(void *opaque, int n, int level) 108 { 109 GSIState *s = opaque; 110 111 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 112 if (n < ISA_NUM_IRQS) { 113 qemu_set_irq(s->i8259_irq[n], level); 114 } 115 qemu_set_irq(s->ioapic_irq[n], level); 116 } 117 118 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 119 unsigned size) 120 { 121 } 122 123 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 124 { 125 return 0xffffffffffffffffULL; 126 } 127 128 /* MSDOS compatibility mode FPU exception support */ 129 static qemu_irq ferr_irq; 130 131 void pc_register_ferr_irq(qemu_irq irq) 132 { 133 ferr_irq = irq; 134 } 135 136 /* XXX: add IGNNE support */ 137 void cpu_set_ferr(CPUX86State *s) 138 { 139 qemu_irq_raise(ferr_irq); 140 } 141 142 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 143 unsigned size) 144 { 145 qemu_irq_lower(ferr_irq); 146 } 147 148 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 149 { 150 return 0xffffffffffffffffULL; 151 } 152 153 /* TSC handling */ 154 uint64_t cpu_get_tsc(CPUX86State *env) 155 { 156 return cpu_get_ticks(); 157 } 158 159 /* IRQ handling */ 160 int cpu_get_pic_interrupt(CPUX86State *env) 161 { 162 X86CPU *cpu = x86_env_get_cpu(env); 163 int intno; 164 165 if (!kvm_irqchip_in_kernel()) { 166 intno = apic_get_interrupt(cpu->apic_state); 167 if (intno >= 0) { 168 return intno; 169 } 170 /* read the irq from the PIC */ 171 if (!apic_accept_pic_intr(cpu->apic_state)) { 172 return -1; 173 } 174 } 175 176 intno = pic_read_irq(isa_pic); 177 return intno; 178 } 179 180 static void pic_irq_request(void *opaque, int irq, int level) 181 { 182 CPUState *cs = first_cpu; 183 X86CPU *cpu = X86_CPU(cs); 184 185 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 186 if (cpu->apic_state && !kvm_irqchip_in_kernel()) { 187 CPU_FOREACH(cs) { 188 cpu = X86_CPU(cs); 189 if (apic_accept_pic_intr(cpu->apic_state)) { 190 apic_deliver_pic_intr(cpu->apic_state, level); 191 } 192 } 193 } else { 194 if (level) { 195 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 196 } else { 197 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 198 } 199 } 200 } 201 202 /* PC cmos mappings */ 203 204 #define REG_EQUIPMENT_BYTE 0x14 205 206 int cmos_get_fd_drive_type(FloppyDriveType fd0) 207 { 208 int val; 209 210 switch (fd0) { 211 case FLOPPY_DRIVE_TYPE_144: 212 /* 1.44 Mb 3"5 drive */ 213 val = 4; 214 break; 215 case FLOPPY_DRIVE_TYPE_288: 216 /* 2.88 Mb 3"5 drive */ 217 val = 5; 218 break; 219 case FLOPPY_DRIVE_TYPE_120: 220 /* 1.2 Mb 5"5 drive */ 221 val = 2; 222 break; 223 case FLOPPY_DRIVE_TYPE_NONE: 224 default: 225 val = 0; 226 break; 227 } 228 return val; 229 } 230 231 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 232 int16_t cylinders, int8_t heads, int8_t sectors) 233 { 234 rtc_set_memory(s, type_ofs, 47); 235 rtc_set_memory(s, info_ofs, cylinders); 236 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 237 rtc_set_memory(s, info_ofs + 2, heads); 238 rtc_set_memory(s, info_ofs + 3, 0xff); 239 rtc_set_memory(s, info_ofs + 4, 0xff); 240 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 241 rtc_set_memory(s, info_ofs + 6, cylinders); 242 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 243 rtc_set_memory(s, info_ofs + 8, sectors); 244 } 245 246 /* convert boot_device letter to something recognizable by the bios */ 247 static int boot_device2nibble(char boot_device) 248 { 249 switch(boot_device) { 250 case 'a': 251 case 'b': 252 return 0x01; /* floppy boot */ 253 case 'c': 254 return 0x02; /* hard drive boot */ 255 case 'd': 256 return 0x03; /* CD-ROM boot */ 257 case 'n': 258 return 0x04; /* Network boot */ 259 } 260 return 0; 261 } 262 263 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 264 { 265 #define PC_MAX_BOOT_DEVICES 3 266 int nbds, bds[3] = { 0, }; 267 int i; 268 269 nbds = strlen(boot_device); 270 if (nbds > PC_MAX_BOOT_DEVICES) { 271 error_setg(errp, "Too many boot devices for PC"); 272 return; 273 } 274 for (i = 0; i < nbds; i++) { 275 bds[i] = boot_device2nibble(boot_device[i]); 276 if (bds[i] == 0) { 277 error_setg(errp, "Invalid boot device for PC: '%c'", 278 boot_device[i]); 279 return; 280 } 281 } 282 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 283 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 284 } 285 286 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 287 { 288 set_boot_dev(opaque, boot_device, errp); 289 } 290 291 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 292 { 293 int val, nb, i; 294 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 295 FLOPPY_DRIVE_TYPE_NONE }; 296 297 /* floppy type */ 298 if (floppy) { 299 for (i = 0; i < 2; i++) { 300 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 301 } 302 } 303 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 304 cmos_get_fd_drive_type(fd_type[1]); 305 rtc_set_memory(rtc_state, 0x10, val); 306 307 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 308 nb = 0; 309 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 310 nb++; 311 } 312 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 313 nb++; 314 } 315 switch (nb) { 316 case 0: 317 break; 318 case 1: 319 val |= 0x01; /* 1 drive, ready for boot */ 320 break; 321 case 2: 322 val |= 0x41; /* 2 drives, ready for boot */ 323 break; 324 } 325 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 326 } 327 328 typedef struct pc_cmos_init_late_arg { 329 ISADevice *rtc_state; 330 BusState *idebus[2]; 331 } pc_cmos_init_late_arg; 332 333 typedef struct check_fdc_state { 334 ISADevice *floppy; 335 bool multiple; 336 } CheckFdcState; 337 338 static int check_fdc(Object *obj, void *opaque) 339 { 340 CheckFdcState *state = opaque; 341 Object *fdc; 342 uint32_t iobase; 343 Error *local_err = NULL; 344 345 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 346 if (!fdc) { 347 return 0; 348 } 349 350 iobase = object_property_get_int(obj, "iobase", &local_err); 351 if (local_err || iobase != 0x3f0) { 352 error_free(local_err); 353 return 0; 354 } 355 356 if (state->floppy) { 357 state->multiple = true; 358 } else { 359 state->floppy = ISA_DEVICE(obj); 360 } 361 return 0; 362 } 363 364 static const char * const fdc_container_path[] = { 365 "/unattached", "/peripheral", "/peripheral-anon" 366 }; 367 368 /* 369 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 370 * and ACPI objects. 371 */ 372 ISADevice *pc_find_fdc0(void) 373 { 374 int i; 375 Object *container; 376 CheckFdcState state = { 0 }; 377 378 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 379 container = container_get(qdev_get_machine(), fdc_container_path[i]); 380 object_child_foreach(container, check_fdc, &state); 381 } 382 383 if (state.multiple) { 384 error_report("warning: multiple floppy disk controllers with " 385 "iobase=0x3f0 have been found"); 386 error_printf("the one being picked for CMOS setup might not reflect " 387 "your intent\n"); 388 } 389 390 return state.floppy; 391 } 392 393 static void pc_cmos_init_late(void *opaque) 394 { 395 pc_cmos_init_late_arg *arg = opaque; 396 ISADevice *s = arg->rtc_state; 397 int16_t cylinders; 398 int8_t heads, sectors; 399 int val; 400 int i, trans; 401 402 val = 0; 403 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 404 &cylinders, &heads, §ors) >= 0) { 405 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 406 val |= 0xf0; 407 } 408 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 409 &cylinders, &heads, §ors) >= 0) { 410 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 411 val |= 0x0f; 412 } 413 rtc_set_memory(s, 0x12, val); 414 415 val = 0; 416 for (i = 0; i < 4; i++) { 417 /* NOTE: ide_get_geometry() returns the physical 418 geometry. It is always such that: 1 <= sects <= 63, 1 419 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 420 geometry can be different if a translation is done. */ 421 if (arg->idebus[i / 2] && 422 ide_get_geometry(arg->idebus[i / 2], i % 2, 423 &cylinders, &heads, §ors) >= 0) { 424 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 425 assert((trans & ~3) == 0); 426 val |= trans << (i * 2); 427 } 428 } 429 rtc_set_memory(s, 0x39, val); 430 431 pc_cmos_init_floppy(s, pc_find_fdc0()); 432 433 qemu_unregister_reset(pc_cmos_init_late, opaque); 434 } 435 436 void pc_cmos_init(PCMachineState *pcms, 437 BusState *idebus0, BusState *idebus1, 438 ISADevice *s) 439 { 440 int val; 441 static pc_cmos_init_late_arg arg; 442 443 /* various important CMOS locations needed by PC/Bochs bios */ 444 445 /* memory size */ 446 /* base memory (first MiB) */ 447 val = MIN(pcms->below_4g_mem_size / 1024, 640); 448 rtc_set_memory(s, 0x15, val); 449 rtc_set_memory(s, 0x16, val >> 8); 450 /* extended memory (next 64MiB) */ 451 if (pcms->below_4g_mem_size > 1024 * 1024) { 452 val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024; 453 } else { 454 val = 0; 455 } 456 if (val > 65535) 457 val = 65535; 458 rtc_set_memory(s, 0x17, val); 459 rtc_set_memory(s, 0x18, val >> 8); 460 rtc_set_memory(s, 0x30, val); 461 rtc_set_memory(s, 0x31, val >> 8); 462 /* memory between 16MiB and 4GiB */ 463 if (pcms->below_4g_mem_size > 16 * 1024 * 1024) { 464 val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536; 465 } else { 466 val = 0; 467 } 468 if (val > 65535) 469 val = 65535; 470 rtc_set_memory(s, 0x34, val); 471 rtc_set_memory(s, 0x35, val >> 8); 472 /* memory above 4GiB */ 473 val = pcms->above_4g_mem_size / 65536; 474 rtc_set_memory(s, 0x5b, val); 475 rtc_set_memory(s, 0x5c, val >> 8); 476 rtc_set_memory(s, 0x5d, val >> 16); 477 478 object_property_add_link(OBJECT(pcms), "rtc_state", 479 TYPE_ISA_DEVICE, 480 (Object **)&pcms->rtc, 481 object_property_allow_set_link, 482 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 483 object_property_set_link(OBJECT(pcms), OBJECT(s), 484 "rtc_state", &error_abort); 485 486 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 487 488 val = 0; 489 val |= 0x02; /* FPU is there */ 490 val |= 0x04; /* PS/2 mouse installed */ 491 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 492 493 /* hard drives and FDC */ 494 arg.rtc_state = s; 495 arg.idebus[0] = idebus0; 496 arg.idebus[1] = idebus1; 497 qemu_register_reset(pc_cmos_init_late, &arg); 498 } 499 500 #define TYPE_PORT92 "port92" 501 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 502 503 /* port 92 stuff: could be split off */ 504 typedef struct Port92State { 505 ISADevice parent_obj; 506 507 MemoryRegion io; 508 uint8_t outport; 509 qemu_irq a20_out; 510 } Port92State; 511 512 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 513 unsigned size) 514 { 515 Port92State *s = opaque; 516 int oldval = s->outport; 517 518 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 519 s->outport = val; 520 qemu_set_irq(s->a20_out, (val >> 1) & 1); 521 if ((val & 1) && !(oldval & 1)) { 522 qemu_system_reset_request(); 523 } 524 } 525 526 static uint64_t port92_read(void *opaque, hwaddr addr, 527 unsigned size) 528 { 529 Port92State *s = opaque; 530 uint32_t ret; 531 532 ret = s->outport; 533 DPRINTF("port92: read 0x%02x\n", ret); 534 return ret; 535 } 536 537 static void port92_init(ISADevice *dev, qemu_irq a20_out) 538 { 539 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); 540 } 541 542 static const VMStateDescription vmstate_port92_isa = { 543 .name = "port92", 544 .version_id = 1, 545 .minimum_version_id = 1, 546 .fields = (VMStateField[]) { 547 VMSTATE_UINT8(outport, Port92State), 548 VMSTATE_END_OF_LIST() 549 } 550 }; 551 552 static void port92_reset(DeviceState *d) 553 { 554 Port92State *s = PORT92(d); 555 556 s->outport &= ~1; 557 } 558 559 static const MemoryRegionOps port92_ops = { 560 .read = port92_read, 561 .write = port92_write, 562 .impl = { 563 .min_access_size = 1, 564 .max_access_size = 1, 565 }, 566 .endianness = DEVICE_LITTLE_ENDIAN, 567 }; 568 569 static void port92_initfn(Object *obj) 570 { 571 Port92State *s = PORT92(obj); 572 573 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 574 575 s->outport = 0; 576 577 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); 578 } 579 580 static void port92_realizefn(DeviceState *dev, Error **errp) 581 { 582 ISADevice *isadev = ISA_DEVICE(dev); 583 Port92State *s = PORT92(dev); 584 585 isa_register_ioport(isadev, &s->io, 0x92); 586 } 587 588 static void port92_class_initfn(ObjectClass *klass, void *data) 589 { 590 DeviceClass *dc = DEVICE_CLASS(klass); 591 592 dc->realize = port92_realizefn; 593 dc->reset = port92_reset; 594 dc->vmsd = &vmstate_port92_isa; 595 /* 596 * Reason: unlike ordinary ISA devices, this one needs additional 597 * wiring: its A20 output line needs to be wired up by 598 * port92_init(). 599 */ 600 dc->cannot_instantiate_with_device_add_yet = true; 601 } 602 603 static const TypeInfo port92_info = { 604 .name = TYPE_PORT92, 605 .parent = TYPE_ISA_DEVICE, 606 .instance_size = sizeof(Port92State), 607 .instance_init = port92_initfn, 608 .class_init = port92_class_initfn, 609 }; 610 611 static void port92_register_types(void) 612 { 613 type_register_static(&port92_info); 614 } 615 616 type_init(port92_register_types) 617 618 static void handle_a20_line_change(void *opaque, int irq, int level) 619 { 620 X86CPU *cpu = opaque; 621 622 /* XXX: send to all CPUs ? */ 623 /* XXX: add logic to handle multiple A20 line sources */ 624 x86_cpu_set_a20(cpu, level); 625 } 626 627 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 628 { 629 int index = le32_to_cpu(e820_reserve.count); 630 struct e820_entry *entry; 631 632 if (type != E820_RAM) { 633 /* old FW_CFG_E820_TABLE entry -- reservations only */ 634 if (index >= E820_NR_ENTRIES) { 635 return -EBUSY; 636 } 637 entry = &e820_reserve.entry[index++]; 638 639 entry->address = cpu_to_le64(address); 640 entry->length = cpu_to_le64(length); 641 entry->type = cpu_to_le32(type); 642 643 e820_reserve.count = cpu_to_le32(index); 644 } 645 646 /* new "etc/e820" file -- include ram too */ 647 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 648 e820_table[e820_entries].address = cpu_to_le64(address); 649 e820_table[e820_entries].length = cpu_to_le64(length); 650 e820_table[e820_entries].type = cpu_to_le32(type); 651 e820_entries++; 652 653 return e820_entries; 654 } 655 656 int e820_get_num_entries(void) 657 { 658 return e820_entries; 659 } 660 661 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 662 { 663 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 664 *address = le64_to_cpu(e820_table[idx].address); 665 *length = le64_to_cpu(e820_table[idx].length); 666 return true; 667 } 668 return false; 669 } 670 671 /* Enables contiguous-apic-ID mode, for compatibility */ 672 static bool compat_apic_id_mode; 673 674 void enable_compat_apic_id_mode(void) 675 { 676 compat_apic_id_mode = true; 677 } 678 679 /* Calculates initial APIC ID for a specific CPU index 680 * 681 * Currently we need to be able to calculate the APIC ID from the CPU index 682 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 683 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 684 * all CPUs up to max_cpus. 685 */ 686 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 687 { 688 uint32_t correct_id; 689 static bool warned; 690 691 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 692 if (compat_apic_id_mode) { 693 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 694 error_report("APIC IDs set in compatibility mode, " 695 "CPU topology won't match the configuration"); 696 warned = true; 697 } 698 return cpu_index; 699 } else { 700 return correct_id; 701 } 702 } 703 704 static void pc_build_smbios(PCMachineState *pcms) 705 { 706 uint8_t *smbios_tables, *smbios_anchor; 707 size_t smbios_tables_len, smbios_anchor_len; 708 struct smbios_phys_mem_area *mem_array; 709 unsigned i, array_count; 710 MachineState *ms = MACHINE(pcms); 711 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); 712 713 /* tell smbios about cpuid version and features */ 714 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 715 716 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 717 if (smbios_tables) { 718 fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES, 719 smbios_tables, smbios_tables_len); 720 } 721 722 /* build the array of physical mem area from e820 table */ 723 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); 724 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { 725 uint64_t addr, len; 726 727 if (e820_get_entry(i, E820_RAM, &addr, &len)) { 728 mem_array[array_count].address = addr; 729 mem_array[array_count].length = len; 730 array_count++; 731 } 732 } 733 smbios_get_tables(mem_array, array_count, 734 &smbios_tables, &smbios_tables_len, 735 &smbios_anchor, &smbios_anchor_len); 736 g_free(mem_array); 737 738 if (smbios_anchor) { 739 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables", 740 smbios_tables, smbios_tables_len); 741 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor", 742 smbios_anchor, smbios_anchor_len); 743 } 744 } 745 746 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) 747 { 748 FWCfgState *fw_cfg; 749 uint64_t *numa_fw_cfg; 750 int i, j; 751 752 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); 753 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 754 755 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 756 * 757 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for 758 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table, 759 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface 760 * for CPU hotplug also uses APIC ID and not "CPU index". 761 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", 762 * but the "limit to the APIC ID values SeaBIOS may see". 763 * 764 * So for compatibility reasons with old BIOSes we are stuck with 765 * "etc/max-cpus" actually being apic_id_limit 766 */ 767 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); 768 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 769 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 770 acpi_tables, acpi_tables_len); 771 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 772 773 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 774 &e820_reserve, sizeof(e820_reserve)); 775 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 776 sizeof(struct e820_entry) * e820_entries); 777 778 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 779 /* allocate memory for the NUMA channel: one (64bit) word for the number 780 * of nodes, one word for each VCPU->node and one word for each node to 781 * hold the amount of memory. 782 */ 783 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); 784 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 785 for (i = 0; i < max_cpus; i++) { 786 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 787 assert(apic_id < pcms->apic_id_limit); 788 j = numa_get_node_for_cpu(i); 789 if (j < nb_numa_nodes) { 790 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 791 } 792 } 793 for (i = 0; i < nb_numa_nodes; i++) { 794 numa_fw_cfg[pcms->apic_id_limit + 1 + i] = 795 cpu_to_le64(numa_info[i].node_mem); 796 } 797 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 798 (1 + pcms->apic_id_limit + nb_numa_nodes) * 799 sizeof(*numa_fw_cfg)); 800 801 return fw_cfg; 802 } 803 804 static long get_file_size(FILE *f) 805 { 806 long where, size; 807 808 /* XXX: on Unix systems, using fstat() probably makes more sense */ 809 810 where = ftell(f); 811 fseek(f, 0, SEEK_END); 812 size = ftell(f); 813 fseek(f, where, SEEK_SET); 814 815 return size; 816 } 817 818 /* setup_data types */ 819 #define SETUP_NONE 0 820 #define SETUP_E820_EXT 1 821 #define SETUP_DTB 2 822 #define SETUP_PCI 3 823 #define SETUP_EFI 4 824 825 struct setup_data { 826 uint64_t next; 827 uint32_t type; 828 uint32_t len; 829 uint8_t data[0]; 830 } __attribute__((packed)); 831 832 static void load_linux(PCMachineState *pcms, 833 FWCfgState *fw_cfg) 834 { 835 uint16_t protocol; 836 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 837 int dtb_size, setup_data_offset; 838 uint32_t initrd_max; 839 uint8_t header[8192], *setup, *kernel, *initrd_data; 840 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 841 FILE *f; 842 char *vmode; 843 MachineState *machine = MACHINE(pcms); 844 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 845 struct setup_data *setup_data; 846 const char *kernel_filename = machine->kernel_filename; 847 const char *initrd_filename = machine->initrd_filename; 848 const char *dtb_filename = machine->dtb; 849 const char *kernel_cmdline = machine->kernel_cmdline; 850 851 /* Align to 16 bytes as a paranoia measure */ 852 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 853 854 /* load the kernel header */ 855 f = fopen(kernel_filename, "rb"); 856 if (!f || !(kernel_size = get_file_size(f)) || 857 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 858 MIN(ARRAY_SIZE(header), kernel_size)) { 859 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 860 kernel_filename, strerror(errno)); 861 exit(1); 862 } 863 864 /* kernel protocol version */ 865 #if 0 866 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 867 #endif 868 if (ldl_p(header+0x202) == 0x53726448) { 869 protocol = lduw_p(header+0x206); 870 } else { 871 /* This looks like a multiboot kernel. If it is, let's stop 872 treating it like a Linux kernel. */ 873 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 874 kernel_cmdline, kernel_size, header)) { 875 return; 876 } 877 protocol = 0; 878 } 879 880 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 881 /* Low kernel */ 882 real_addr = 0x90000; 883 cmdline_addr = 0x9a000 - cmdline_size; 884 prot_addr = 0x10000; 885 } else if (protocol < 0x202) { 886 /* High but ancient kernel */ 887 real_addr = 0x90000; 888 cmdline_addr = 0x9a000 - cmdline_size; 889 prot_addr = 0x100000; 890 } else { 891 /* High and recent kernel */ 892 real_addr = 0x10000; 893 cmdline_addr = 0x20000; 894 prot_addr = 0x100000; 895 } 896 897 #if 0 898 fprintf(stderr, 899 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 900 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 901 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 902 real_addr, 903 cmdline_addr, 904 prot_addr); 905 #endif 906 907 /* highest address for loading the initrd */ 908 if (protocol >= 0x203) { 909 initrd_max = ldl_p(header+0x22c); 910 } else { 911 initrd_max = 0x37ffffff; 912 } 913 914 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { 915 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 916 } 917 918 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 919 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 920 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 921 922 if (protocol >= 0x202) { 923 stl_p(header+0x228, cmdline_addr); 924 } else { 925 stw_p(header+0x20, 0xA33F); 926 stw_p(header+0x22, cmdline_addr-real_addr); 927 } 928 929 /* handle vga= parameter */ 930 vmode = strstr(kernel_cmdline, "vga="); 931 if (vmode) { 932 unsigned int video_mode; 933 /* skip "vga=" */ 934 vmode += 4; 935 if (!strncmp(vmode, "normal", 6)) { 936 video_mode = 0xffff; 937 } else if (!strncmp(vmode, "ext", 3)) { 938 video_mode = 0xfffe; 939 } else if (!strncmp(vmode, "ask", 3)) { 940 video_mode = 0xfffd; 941 } else { 942 video_mode = strtol(vmode, NULL, 0); 943 } 944 stw_p(header+0x1fa, video_mode); 945 } 946 947 /* loader type */ 948 /* High nybble = B reserved for QEMU; low nybble is revision number. 949 If this code is substantially changed, you may want to consider 950 incrementing the revision. */ 951 if (protocol >= 0x200) { 952 header[0x210] = 0xB0; 953 } 954 /* heap */ 955 if (protocol >= 0x201) { 956 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 957 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 958 } 959 960 /* load initrd */ 961 if (initrd_filename) { 962 if (protocol < 0x200) { 963 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 964 exit(1); 965 } 966 967 initrd_size = get_image_size(initrd_filename); 968 if (initrd_size < 0) { 969 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 970 initrd_filename, strerror(errno)); 971 exit(1); 972 } 973 974 initrd_addr = (initrd_max-initrd_size) & ~4095; 975 976 initrd_data = g_malloc(initrd_size); 977 load_image(initrd_filename, initrd_data); 978 979 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 980 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 981 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 982 983 stl_p(header+0x218, initrd_addr); 984 stl_p(header+0x21c, initrd_size); 985 } 986 987 /* load kernel and setup */ 988 setup_size = header[0x1f1]; 989 if (setup_size == 0) { 990 setup_size = 4; 991 } 992 setup_size = (setup_size+1)*512; 993 if (setup_size > kernel_size) { 994 fprintf(stderr, "qemu: invalid kernel header\n"); 995 exit(1); 996 } 997 kernel_size -= setup_size; 998 999 setup = g_malloc(setup_size); 1000 kernel = g_malloc(kernel_size); 1001 fseek(f, 0, SEEK_SET); 1002 if (fread(setup, 1, setup_size, f) != setup_size) { 1003 fprintf(stderr, "fread() failed\n"); 1004 exit(1); 1005 } 1006 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1007 fprintf(stderr, "fread() failed\n"); 1008 exit(1); 1009 } 1010 fclose(f); 1011 1012 /* append dtb to kernel */ 1013 if (dtb_filename) { 1014 if (protocol < 0x209) { 1015 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); 1016 exit(1); 1017 } 1018 1019 dtb_size = get_image_size(dtb_filename); 1020 if (dtb_size <= 0) { 1021 fprintf(stderr, "qemu: error reading dtb %s: %s\n", 1022 dtb_filename, strerror(errno)); 1023 exit(1); 1024 } 1025 1026 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); 1027 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; 1028 kernel = g_realloc(kernel, kernel_size); 1029 1030 stq_p(header+0x250, prot_addr + setup_data_offset); 1031 1032 setup_data = (struct setup_data *)(kernel + setup_data_offset); 1033 setup_data->next = 0; 1034 setup_data->type = cpu_to_le32(SETUP_DTB); 1035 setup_data->len = cpu_to_le32(dtb_size); 1036 1037 load_image_size(dtb_filename, setup_data->data, dtb_size); 1038 } 1039 1040 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1041 1042 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1043 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1044 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1045 1046 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1047 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1048 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1049 1050 if (fw_cfg_dma_enabled(fw_cfg)) { 1051 option_rom[nb_option_roms].name = "linuxboot_dma.bin"; 1052 option_rom[nb_option_roms].bootindex = 0; 1053 } else { 1054 option_rom[nb_option_roms].name = "linuxboot.bin"; 1055 option_rom[nb_option_roms].bootindex = 0; 1056 } 1057 nb_option_roms++; 1058 } 1059 1060 #define NE2000_NB_MAX 6 1061 1062 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1063 0x280, 0x380 }; 1064 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1065 1066 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1067 { 1068 static int nb_ne2k = 0; 1069 1070 if (nb_ne2k == NE2000_NB_MAX) 1071 return; 1072 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1073 ne2000_irq[nb_ne2k], nd); 1074 nb_ne2k++; 1075 } 1076 1077 DeviceState *cpu_get_current_apic(void) 1078 { 1079 if (current_cpu) { 1080 X86CPU *cpu = X86_CPU(current_cpu); 1081 return cpu->apic_state; 1082 } else { 1083 return NULL; 1084 } 1085 } 1086 1087 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1088 { 1089 X86CPU *cpu = opaque; 1090 1091 if (level) { 1092 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1093 } 1094 } 1095 1096 static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp) 1097 { 1098 Object *cpu = NULL; 1099 Error *local_err = NULL; 1100 1101 cpu = object_new(typename); 1102 1103 object_property_set_int(cpu, apic_id, "apic-id", &local_err); 1104 object_property_set_bool(cpu, true, "realized", &local_err); 1105 1106 object_unref(cpu); 1107 error_propagate(errp, local_err); 1108 } 1109 1110 void pc_hot_add_cpu(const int64_t id, Error **errp) 1111 { 1112 ObjectClass *oc; 1113 MachineState *ms = MACHINE(qdev_get_machine()); 1114 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1115 Error *local_err = NULL; 1116 1117 if (id < 0) { 1118 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1119 return; 1120 } 1121 1122 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1123 error_setg(errp, "Unable to add CPU: %" PRIi64 1124 ", resulting APIC ID (%" PRIi64 ") is too large", 1125 id, apic_id); 1126 return; 1127 } 1128 1129 assert(ms->possible_cpus->cpus[0].cpu); /* BSP is always present */ 1130 oc = OBJECT_CLASS(CPU_GET_CLASS(ms->possible_cpus->cpus[0].cpu)); 1131 pc_new_cpu(object_class_get_name(oc), apic_id, &local_err); 1132 if (local_err) { 1133 error_propagate(errp, local_err); 1134 return; 1135 } 1136 } 1137 1138 void pc_cpus_init(PCMachineState *pcms) 1139 { 1140 int i; 1141 CPUClass *cc; 1142 ObjectClass *oc; 1143 const char *typename; 1144 gchar **model_pieces; 1145 const CPUArchIdList *possible_cpus; 1146 MachineState *machine = MACHINE(pcms); 1147 MachineClass *mc = MACHINE_GET_CLASS(pcms); 1148 1149 /* init CPUs */ 1150 if (machine->cpu_model == NULL) { 1151 #ifdef TARGET_X86_64 1152 machine->cpu_model = "qemu64"; 1153 #else 1154 machine->cpu_model = "qemu32"; 1155 #endif 1156 } 1157 1158 model_pieces = g_strsplit(machine->cpu_model, ",", 2); 1159 if (!model_pieces[0]) { 1160 error_report("Invalid/empty CPU model name"); 1161 exit(1); 1162 } 1163 1164 oc = cpu_class_by_name(TYPE_X86_CPU, model_pieces[0]); 1165 if (oc == NULL) { 1166 error_report("Unable to find CPU definition: %s", model_pieces[0]); 1167 exit(1); 1168 } 1169 typename = object_class_get_name(oc); 1170 cc = CPU_CLASS(oc); 1171 cc->parse_features(typename, model_pieces[1], &error_fatal); 1172 g_strfreev(model_pieces); 1173 1174 /* Calculates the limit to CPU APIC ID values 1175 * 1176 * Limit for the APIC ID value, so that all 1177 * CPU APIC IDs are < pcms->apic_id_limit. 1178 * 1179 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 1180 */ 1181 pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 1182 possible_cpus = mc->possible_cpu_arch_ids(machine); 1183 for (i = 0; i < smp_cpus; i++) { 1184 pc_new_cpu(typename, possible_cpus->cpus[i].arch_id, &error_fatal); 1185 } 1186 } 1187 1188 static void pc_build_feature_control_file(PCMachineState *pcms) 1189 { 1190 MachineState *ms = MACHINE(pcms); 1191 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); 1192 CPUX86State *env = &cpu->env; 1193 uint32_t unused, ecx, edx; 1194 uint64_t feature_control_bits = 0; 1195 uint64_t *val; 1196 1197 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); 1198 if (ecx & CPUID_EXT_VMX) { 1199 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 1200 } 1201 1202 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == 1203 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && 1204 (env->mcg_cap & MCG_LMCE_P)) { 1205 feature_control_bits |= FEATURE_CONTROL_LMCE; 1206 } 1207 1208 if (!feature_control_bits) { 1209 return; 1210 } 1211 1212 val = g_malloc(sizeof(*val)); 1213 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); 1214 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); 1215 } 1216 1217 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) 1218 { 1219 if (cpus_count > 0xff) { 1220 /* If the number of CPUs can't be represented in 8 bits, the 1221 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just 1222 * to make old BIOSes fail more predictably. 1223 */ 1224 rtc_set_memory(rtc, 0x5f, 0); 1225 } else { 1226 rtc_set_memory(rtc, 0x5f, cpus_count - 1); 1227 } 1228 } 1229 1230 static 1231 void pc_machine_done(Notifier *notifier, void *data) 1232 { 1233 PCMachineState *pcms = container_of(notifier, 1234 PCMachineState, machine_done); 1235 PCIBus *bus = pcms->bus; 1236 1237 /* set the number of CPUs */ 1238 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 1239 1240 if (bus) { 1241 int extra_hosts = 0; 1242 1243 QLIST_FOREACH(bus, &bus->child, sibling) { 1244 /* look for expander root buses */ 1245 if (pci_bus_is_root(bus)) { 1246 extra_hosts++; 1247 } 1248 } 1249 if (extra_hosts && pcms->fw_cfg) { 1250 uint64_t *val = g_malloc(sizeof(*val)); 1251 *val = cpu_to_le64(extra_hosts); 1252 fw_cfg_add_file(pcms->fw_cfg, 1253 "etc/extra-pci-roots", val, sizeof(*val)); 1254 } 1255 } 1256 1257 acpi_setup(); 1258 if (pcms->fw_cfg) { 1259 pc_build_smbios(pcms); 1260 pc_build_feature_control_file(pcms); 1261 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 1262 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1263 } 1264 1265 if (pcms->apic_id_limit > 255) { 1266 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); 1267 1268 if (!iommu || !iommu->x86_iommu.intr_supported || 1269 iommu->intr_eim != ON_OFF_AUTO_ON) { 1270 error_report("current -smp configuration requires " 1271 "Extended Interrupt Mode enabled. " 1272 "You can add an IOMMU using: " 1273 "-device intel-iommu,intremap=on,eim=on"); 1274 exit(EXIT_FAILURE); 1275 } 1276 } 1277 } 1278 1279 void pc_guest_info_init(PCMachineState *pcms) 1280 { 1281 int i; 1282 1283 pcms->apic_xrupt_override = kvm_allows_irq0_override(); 1284 pcms->numa_nodes = nb_numa_nodes; 1285 pcms->node_mem = g_malloc0(pcms->numa_nodes * 1286 sizeof *pcms->node_mem); 1287 for (i = 0; i < nb_numa_nodes; i++) { 1288 pcms->node_mem[i] = numa_info[i].node_mem; 1289 } 1290 1291 pcms->machine_done.notify = pc_machine_done; 1292 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1293 } 1294 1295 /* setup pci memory address space mapping into system address space */ 1296 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1297 MemoryRegion *pci_address_space) 1298 { 1299 /* Set to lower priority than RAM */ 1300 memory_region_add_subregion_overlap(system_memory, 0x0, 1301 pci_address_space, -1); 1302 } 1303 1304 void pc_acpi_init(const char *default_dsdt) 1305 { 1306 char *filename; 1307 1308 if (acpi_tables != NULL) { 1309 /* manually set via -acpitable, leave it alone */ 1310 return; 1311 } 1312 1313 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1314 if (filename == NULL) { 1315 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1316 } else { 1317 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, 1318 &error_abort); 1319 Error *err = NULL; 1320 1321 qemu_opt_set(opts, "file", filename, &error_abort); 1322 1323 acpi_table_add_builtin(opts, &err); 1324 if (err) { 1325 error_reportf_err(err, "WARNING: failed to load %s: ", 1326 filename); 1327 } 1328 g_free(filename); 1329 } 1330 } 1331 1332 void xen_load_linux(PCMachineState *pcms) 1333 { 1334 int i; 1335 FWCfgState *fw_cfg; 1336 1337 assert(MACHINE(pcms)->kernel_filename != NULL); 1338 1339 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 1340 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1341 rom_set_fw(fw_cfg); 1342 1343 load_linux(pcms, fw_cfg); 1344 for (i = 0; i < nb_option_roms; i++) { 1345 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1346 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 1347 !strcmp(option_rom[i].name, "multiboot.bin")); 1348 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1349 } 1350 pcms->fw_cfg = fw_cfg; 1351 } 1352 1353 void pc_memory_init(PCMachineState *pcms, 1354 MemoryRegion *system_memory, 1355 MemoryRegion *rom_memory, 1356 MemoryRegion **ram_memory) 1357 { 1358 int linux_boot, i; 1359 MemoryRegion *ram, *option_rom_mr; 1360 MemoryRegion *ram_below_4g, *ram_above_4g; 1361 FWCfgState *fw_cfg; 1362 MachineState *machine = MACHINE(pcms); 1363 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1364 1365 assert(machine->ram_size == pcms->below_4g_mem_size + 1366 pcms->above_4g_mem_size); 1367 1368 linux_boot = (machine->kernel_filename != NULL); 1369 1370 /* Allocate RAM. We allocate it as a single memory region and use 1371 * aliases to address portions of it, mostly for backwards compatibility 1372 * with older qemus that used qemu_ram_alloc(). 1373 */ 1374 ram = g_malloc(sizeof(*ram)); 1375 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1376 machine->ram_size); 1377 *ram_memory = ram; 1378 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1379 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1380 0, pcms->below_4g_mem_size); 1381 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1382 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); 1383 if (pcms->above_4g_mem_size > 0) { 1384 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1385 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1386 pcms->below_4g_mem_size, 1387 pcms->above_4g_mem_size); 1388 memory_region_add_subregion(system_memory, 0x100000000ULL, 1389 ram_above_4g); 1390 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); 1391 } 1392 1393 if (!pcmc->has_reserved_memory && 1394 (machine->ram_slots || 1395 (machine->maxram_size > machine->ram_size))) { 1396 MachineClass *mc = MACHINE_GET_CLASS(machine); 1397 1398 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1399 mc->name); 1400 exit(EXIT_FAILURE); 1401 } 1402 1403 /* initialize hotplug memory address space */ 1404 if (pcmc->has_reserved_memory && 1405 (machine->ram_size < machine->maxram_size)) { 1406 ram_addr_t hotplug_mem_size = 1407 machine->maxram_size - machine->ram_size; 1408 1409 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1410 error_report("unsupported amount of memory slots: %"PRIu64, 1411 machine->ram_slots); 1412 exit(EXIT_FAILURE); 1413 } 1414 1415 if (QEMU_ALIGN_UP(machine->maxram_size, 1416 TARGET_PAGE_SIZE) != machine->maxram_size) { 1417 error_report("maximum memory size must by aligned to multiple of " 1418 "%d bytes", TARGET_PAGE_SIZE); 1419 exit(EXIT_FAILURE); 1420 } 1421 1422 pcms->hotplug_memory.base = 1423 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30); 1424 1425 if (pcmc->enforce_aligned_dimm) { 1426 /* size hotplug region assuming 1G page max alignment per slot */ 1427 hotplug_mem_size += (1ULL << 30) * machine->ram_slots; 1428 } 1429 1430 if ((pcms->hotplug_memory.base + hotplug_mem_size) < 1431 hotplug_mem_size) { 1432 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1433 machine->maxram_size); 1434 exit(EXIT_FAILURE); 1435 } 1436 1437 memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms), 1438 "hotplug-memory", hotplug_mem_size); 1439 memory_region_add_subregion(system_memory, pcms->hotplug_memory.base, 1440 &pcms->hotplug_memory.mr); 1441 } 1442 1443 /* Initialize PC system firmware */ 1444 pc_system_firmware_init(rom_memory, !pcmc->pci_enabled); 1445 1446 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1447 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1448 &error_fatal); 1449 vmstate_register_ram_global(option_rom_mr); 1450 memory_region_add_subregion_overlap(rom_memory, 1451 PC_ROM_MIN_VGA, 1452 option_rom_mr, 1453 1); 1454 1455 fw_cfg = bochs_bios_init(&address_space_memory, pcms); 1456 1457 rom_set_fw(fw_cfg); 1458 1459 if (pcmc->has_reserved_memory && pcms->hotplug_memory.base) { 1460 uint64_t *val = g_malloc(sizeof(*val)); 1461 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1462 uint64_t res_mem_end = pcms->hotplug_memory.base; 1463 1464 if (!pcmc->broken_reserved_end) { 1465 res_mem_end += memory_region_size(&pcms->hotplug_memory.mr); 1466 } 1467 *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30)); 1468 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1469 } 1470 1471 if (linux_boot) { 1472 load_linux(pcms, fw_cfg); 1473 } 1474 1475 for (i = 0; i < nb_option_roms; i++) { 1476 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1477 } 1478 pcms->fw_cfg = fw_cfg; 1479 1480 /* Init default IOAPIC address space */ 1481 pcms->ioapic_as = &address_space_memory; 1482 } 1483 1484 qemu_irq pc_allocate_cpu_irq(void) 1485 { 1486 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1487 } 1488 1489 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1490 { 1491 DeviceState *dev = NULL; 1492 1493 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1494 if (pci_bus) { 1495 PCIDevice *pcidev = pci_vga_init(pci_bus); 1496 dev = pcidev ? &pcidev->qdev : NULL; 1497 } else if (isa_bus) { 1498 ISADevice *isadev = isa_vga_init(isa_bus); 1499 dev = isadev ? DEVICE(isadev) : NULL; 1500 } 1501 rom_reset_order_override(); 1502 return dev; 1503 } 1504 1505 static const MemoryRegionOps ioport80_io_ops = { 1506 .write = ioport80_write, 1507 .read = ioport80_read, 1508 .endianness = DEVICE_NATIVE_ENDIAN, 1509 .impl = { 1510 .min_access_size = 1, 1511 .max_access_size = 1, 1512 }, 1513 }; 1514 1515 static const MemoryRegionOps ioportF0_io_ops = { 1516 .write = ioportF0_write, 1517 .read = ioportF0_read, 1518 .endianness = DEVICE_NATIVE_ENDIAN, 1519 .impl = { 1520 .min_access_size = 1, 1521 .max_access_size = 1, 1522 }, 1523 }; 1524 1525 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1526 ISADevice **rtc_state, 1527 bool create_fdctrl, 1528 bool no_vmport, 1529 bool has_pit, 1530 uint32_t hpet_irqs) 1531 { 1532 int i; 1533 DriveInfo *fd[MAX_FD]; 1534 DeviceState *hpet = NULL; 1535 int pit_isa_irq = 0; 1536 qemu_irq pit_alt_irq = NULL; 1537 qemu_irq rtc_irq = NULL; 1538 qemu_irq *a20_line; 1539 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1540 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1541 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1542 1543 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1544 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1545 1546 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1547 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1548 1549 /* 1550 * Check if an HPET shall be created. 1551 * 1552 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1553 * when the HPET wants to take over. Thus we have to disable the latter. 1554 */ 1555 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1556 /* In order to set property, here not using sysbus_try_create_simple */ 1557 hpet = qdev_try_create(NULL, TYPE_HPET); 1558 if (hpet) { 1559 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1560 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1561 * IRQ8 and IRQ2. 1562 */ 1563 uint8_t compat = object_property_get_int(OBJECT(hpet), 1564 HPET_INTCAP, NULL); 1565 if (!compat) { 1566 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1567 } 1568 qdev_init_nofail(hpet); 1569 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1570 1571 for (i = 0; i < GSI_NUM_PINS; i++) { 1572 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1573 } 1574 pit_isa_irq = -1; 1575 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1576 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1577 } 1578 } 1579 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1580 1581 qemu_register_boot_set(pc_boot_set, *rtc_state); 1582 1583 if (!xen_enabled() && has_pit) { 1584 if (kvm_pit_in_kernel()) { 1585 pit = kvm_pit_init(isa_bus, 0x40); 1586 } else { 1587 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1588 } 1589 if (hpet) { 1590 /* connect PIT to output control line of the HPET */ 1591 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1592 } 1593 pcspk_init(isa_bus, pit); 1594 } 1595 1596 serial_hds_isa_init(isa_bus, 0, MAX_SERIAL_PORTS); 1597 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1598 1599 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1600 i8042 = isa_create_simple(isa_bus, "i8042"); 1601 i8042_setup_a20_line(i8042, a20_line[0]); 1602 if (!no_vmport) { 1603 vmport_init(isa_bus); 1604 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1605 } else { 1606 vmmouse = NULL; 1607 } 1608 if (vmmouse) { 1609 DeviceState *dev = DEVICE(vmmouse); 1610 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1611 qdev_init_nofail(dev); 1612 } 1613 port92 = isa_create_simple(isa_bus, "port92"); 1614 port92_init(port92, a20_line[1]); 1615 g_free(a20_line); 1616 1617 DMA_init(isa_bus, 0); 1618 1619 for(i = 0; i < MAX_FD; i++) { 1620 fd[i] = drive_get(IF_FLOPPY, 0, i); 1621 create_fdctrl |= !!fd[i]; 1622 } 1623 if (create_fdctrl) { 1624 fdctrl_init_isa(isa_bus, fd); 1625 } 1626 } 1627 1628 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1629 { 1630 int i; 1631 1632 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1633 for (i = 0; i < nb_nics; i++) { 1634 NICInfo *nd = &nd_table[i]; 1635 1636 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1637 pc_init_ne2k_isa(isa_bus, nd); 1638 } else { 1639 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1640 } 1641 } 1642 rom_reset_order_override(); 1643 } 1644 1645 void pc_pci_device_init(PCIBus *pci_bus) 1646 { 1647 int max_bus; 1648 int bus; 1649 1650 /* Note: if=scsi is deprecated with PC machine types */ 1651 max_bus = drive_get_max_bus(IF_SCSI); 1652 for (bus = 0; bus <= max_bus; bus++) { 1653 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1654 /* 1655 * By not creating frontends here, we make 1656 * scsi_legacy_handle_cmdline() create them, and warn that 1657 * this usage is deprecated. 1658 */ 1659 } 1660 } 1661 1662 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1663 { 1664 DeviceState *dev; 1665 SysBusDevice *d; 1666 unsigned int i; 1667 1668 if (kvm_ioapic_in_kernel()) { 1669 dev = qdev_create(NULL, "kvm-ioapic"); 1670 } else { 1671 dev = qdev_create(NULL, "ioapic"); 1672 } 1673 if (parent_name) { 1674 object_property_add_child(object_resolve_path(parent_name, NULL), 1675 "ioapic", OBJECT(dev), NULL); 1676 } 1677 qdev_init_nofail(dev); 1678 d = SYS_BUS_DEVICE(dev); 1679 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1680 1681 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1682 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1683 } 1684 } 1685 1686 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1687 DeviceState *dev, Error **errp) 1688 { 1689 HotplugHandlerClass *hhc; 1690 Error *local_err = NULL; 1691 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1692 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1693 PCDIMMDevice *dimm = PC_DIMM(dev); 1694 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1695 MemoryRegion *mr = ddc->get_memory_region(dimm); 1696 uint64_t align = TARGET_PAGE_SIZE; 1697 1698 if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) { 1699 align = memory_region_get_alignment(mr); 1700 } 1701 1702 if (!pcms->acpi_dev) { 1703 error_setg(&local_err, 1704 "memory hotplug is not enabled: missing acpi device"); 1705 goto out; 1706 } 1707 1708 pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err); 1709 if (local_err) { 1710 goto out; 1711 } 1712 1713 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1714 if (!pcms->acpi_nvdimm_state.is_enabled) { 1715 error_setg(&local_err, 1716 "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1717 goto out; 1718 } 1719 nvdimm_plug(&pcms->acpi_nvdimm_state); 1720 } 1721 1722 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1723 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 1724 out: 1725 error_propagate(errp, local_err); 1726 } 1727 1728 static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev, 1729 DeviceState *dev, Error **errp) 1730 { 1731 HotplugHandlerClass *hhc; 1732 Error *local_err = NULL; 1733 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1734 1735 if (!pcms->acpi_dev) { 1736 error_setg(&local_err, 1737 "memory hotplug is not enabled: missing acpi device"); 1738 goto out; 1739 } 1740 1741 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1742 error_setg(&local_err, 1743 "nvdimm device hot unplug is not supported yet."); 1744 goto out; 1745 } 1746 1747 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1748 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1749 1750 out: 1751 error_propagate(errp, local_err); 1752 } 1753 1754 static void pc_dimm_unplug(HotplugHandler *hotplug_dev, 1755 DeviceState *dev, Error **errp) 1756 { 1757 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1758 PCDIMMDevice *dimm = PC_DIMM(dev); 1759 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1760 MemoryRegion *mr = ddc->get_memory_region(dimm); 1761 HotplugHandlerClass *hhc; 1762 Error *local_err = NULL; 1763 1764 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1765 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1766 1767 if (local_err) { 1768 goto out; 1769 } 1770 1771 pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr); 1772 object_unparent(OBJECT(dev)); 1773 1774 out: 1775 error_propagate(errp, local_err); 1776 } 1777 1778 static int pc_apic_cmp(const void *a, const void *b) 1779 { 1780 CPUArchId *apic_a = (CPUArchId *)a; 1781 CPUArchId *apic_b = (CPUArchId *)b; 1782 1783 return apic_a->arch_id - apic_b->arch_id; 1784 } 1785 1786 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id 1787 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no 1788 * entry corresponding to CPU's apic_id returns NULL. 1789 */ 1790 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 1791 { 1792 CPUArchId apic_id, *found_cpu; 1793 1794 apic_id.arch_id = id; 1795 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, 1796 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), 1797 pc_apic_cmp); 1798 if (found_cpu && idx) { 1799 *idx = found_cpu - ms->possible_cpus->cpus; 1800 } 1801 return found_cpu; 1802 } 1803 1804 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1805 DeviceState *dev, Error **errp) 1806 { 1807 CPUArchId *found_cpu; 1808 HotplugHandlerClass *hhc; 1809 Error *local_err = NULL; 1810 X86CPU *cpu = X86_CPU(dev); 1811 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1812 1813 if (pcms->acpi_dev) { 1814 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1815 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1816 if (local_err) { 1817 goto out; 1818 } 1819 } 1820 1821 /* increment the number of CPUs */ 1822 pcms->boot_cpus++; 1823 if (pcms->rtc) { 1824 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 1825 } 1826 if (pcms->fw_cfg) { 1827 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1828 } 1829 1830 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 1831 found_cpu->cpu = OBJECT(dev); 1832 out: 1833 error_propagate(errp, local_err); 1834 } 1835 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 1836 DeviceState *dev, Error **errp) 1837 { 1838 int idx = -1; 1839 HotplugHandlerClass *hhc; 1840 Error *local_err = NULL; 1841 X86CPU *cpu = X86_CPU(dev); 1842 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1843 1844 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 1845 assert(idx != -1); 1846 if (idx == 0) { 1847 error_setg(&local_err, "Boot CPU is unpluggable"); 1848 goto out; 1849 } 1850 1851 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1852 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1853 1854 if (local_err) { 1855 goto out; 1856 } 1857 1858 out: 1859 error_propagate(errp, local_err); 1860 1861 } 1862 1863 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, 1864 DeviceState *dev, Error **errp) 1865 { 1866 CPUArchId *found_cpu; 1867 HotplugHandlerClass *hhc; 1868 Error *local_err = NULL; 1869 X86CPU *cpu = X86_CPU(dev); 1870 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1871 1872 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1873 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1874 1875 if (local_err) { 1876 goto out; 1877 } 1878 1879 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 1880 found_cpu->cpu = NULL; 1881 object_unparent(OBJECT(dev)); 1882 1883 /* decrement the number of CPUs */ 1884 pcms->boot_cpus--; 1885 /* Update the number of CPUs in CMOS */ 1886 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 1887 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1888 out: 1889 error_propagate(errp, local_err); 1890 } 1891 1892 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, 1893 DeviceState *dev, Error **errp) 1894 { 1895 int idx; 1896 CPUState *cs; 1897 CPUArchId *cpu_slot; 1898 X86CPUTopoInfo topo; 1899 X86CPU *cpu = X86_CPU(dev); 1900 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1901 1902 /* if APIC ID is not set, set it based on socket/core/thread properties */ 1903 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 1904 int max_socket = (max_cpus - 1) / smp_threads / smp_cores; 1905 1906 if (cpu->socket_id < 0) { 1907 error_setg(errp, "CPU socket-id is not set"); 1908 return; 1909 } else if (cpu->socket_id > max_socket) { 1910 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 1911 cpu->socket_id, max_socket); 1912 return; 1913 } 1914 if (cpu->core_id < 0) { 1915 error_setg(errp, "CPU core-id is not set"); 1916 return; 1917 } else if (cpu->core_id > (smp_cores - 1)) { 1918 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 1919 cpu->core_id, smp_cores - 1); 1920 return; 1921 } 1922 if (cpu->thread_id < 0) { 1923 error_setg(errp, "CPU thread-id is not set"); 1924 return; 1925 } else if (cpu->thread_id > (smp_threads - 1)) { 1926 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 1927 cpu->thread_id, smp_threads - 1); 1928 return; 1929 } 1930 1931 topo.pkg_id = cpu->socket_id; 1932 topo.core_id = cpu->core_id; 1933 topo.smt_id = cpu->thread_id; 1934 cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo); 1935 } 1936 1937 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 1938 if (!cpu_slot) { 1939 MachineState *ms = MACHINE(pcms); 1940 1941 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); 1942 error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with" 1943 " APIC ID %" PRIu32 ", valid index range 0:%d", 1944 topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id, 1945 ms->possible_cpus->len - 1); 1946 return; 1947 } 1948 1949 if (cpu_slot->cpu) { 1950 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 1951 idx, cpu->apic_id); 1952 return; 1953 } 1954 1955 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 1956 * so that machine_query_hotpluggable_cpus would show correct values 1957 */ 1958 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 1959 * once -smp refactoring is complete and there will be CPU private 1960 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 1961 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); 1962 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { 1963 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 1964 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); 1965 return; 1966 } 1967 cpu->socket_id = topo.pkg_id; 1968 1969 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { 1970 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 1971 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); 1972 return; 1973 } 1974 cpu->core_id = topo.core_id; 1975 1976 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { 1977 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 1978 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); 1979 return; 1980 } 1981 cpu->thread_id = topo.smt_id; 1982 1983 cs = CPU(cpu); 1984 cs->cpu_index = idx; 1985 } 1986 1987 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1988 DeviceState *dev, Error **errp) 1989 { 1990 if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1991 pc_cpu_pre_plug(hotplug_dev, dev, errp); 1992 } 1993 } 1994 1995 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1996 DeviceState *dev, Error **errp) 1997 { 1998 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1999 pc_dimm_plug(hotplug_dev, dev, errp); 2000 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2001 pc_cpu_plug(hotplug_dev, dev, errp); 2002 } 2003 } 2004 2005 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2006 DeviceState *dev, Error **errp) 2007 { 2008 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2009 pc_dimm_unplug_request(hotplug_dev, dev, errp); 2010 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2011 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); 2012 } else { 2013 error_setg(errp, "acpi: device unplug request for not supported device" 2014 " type: %s", object_get_typename(OBJECT(dev))); 2015 } 2016 } 2017 2018 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2019 DeviceState *dev, Error **errp) 2020 { 2021 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2022 pc_dimm_unplug(hotplug_dev, dev, errp); 2023 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2024 pc_cpu_unplug_cb(hotplug_dev, dev, errp); 2025 } else { 2026 error_setg(errp, "acpi: device unplug for not supported device" 2027 " type: %s", object_get_typename(OBJECT(dev))); 2028 } 2029 } 2030 2031 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 2032 DeviceState *dev) 2033 { 2034 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 2035 2036 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2037 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2038 return HOTPLUG_HANDLER(machine); 2039 } 2040 2041 return pcmc->get_hotplug_handler ? 2042 pcmc->get_hotplug_handler(machine, dev) : NULL; 2043 } 2044 2045 static void 2046 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, 2047 const char *name, void *opaque, 2048 Error **errp) 2049 { 2050 PCMachineState *pcms = PC_MACHINE(obj); 2051 int64_t value = memory_region_size(&pcms->hotplug_memory.mr); 2052 2053 visit_type_int(v, name, &value, errp); 2054 } 2055 2056 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 2057 const char *name, void *opaque, 2058 Error **errp) 2059 { 2060 PCMachineState *pcms = PC_MACHINE(obj); 2061 uint64_t value = pcms->max_ram_below_4g; 2062 2063 visit_type_size(v, name, &value, errp); 2064 } 2065 2066 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 2067 const char *name, void *opaque, 2068 Error **errp) 2069 { 2070 PCMachineState *pcms = PC_MACHINE(obj); 2071 Error *error = NULL; 2072 uint64_t value; 2073 2074 visit_type_size(v, name, &value, &error); 2075 if (error) { 2076 error_propagate(errp, error); 2077 return; 2078 } 2079 if (value > (1ULL << 32)) { 2080 error_setg(&error, 2081 "Machine option 'max-ram-below-4g=%"PRIu64 2082 "' expects size less than or equal to 4G", value); 2083 error_propagate(errp, error); 2084 return; 2085 } 2086 2087 if (value < (1ULL << 20)) { 2088 error_report("Warning: small max_ram_below_4g(%"PRIu64 2089 ") less than 1M. BIOS may not work..", 2090 value); 2091 } 2092 2093 pcms->max_ram_below_4g = value; 2094 } 2095 2096 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 2097 void *opaque, Error **errp) 2098 { 2099 PCMachineState *pcms = PC_MACHINE(obj); 2100 OnOffAuto vmport = pcms->vmport; 2101 2102 visit_type_OnOffAuto(v, name, &vmport, errp); 2103 } 2104 2105 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 2106 void *opaque, Error **errp) 2107 { 2108 PCMachineState *pcms = PC_MACHINE(obj); 2109 2110 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 2111 } 2112 2113 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 2114 { 2115 bool smm_available = false; 2116 2117 if (pcms->smm == ON_OFF_AUTO_OFF) { 2118 return false; 2119 } 2120 2121 if (tcg_enabled() || qtest_enabled()) { 2122 smm_available = true; 2123 } else if (kvm_enabled()) { 2124 smm_available = kvm_has_smm(); 2125 } 2126 2127 if (smm_available) { 2128 return true; 2129 } 2130 2131 if (pcms->smm == ON_OFF_AUTO_ON) { 2132 error_report("System Management Mode not supported by this hypervisor."); 2133 exit(1); 2134 } 2135 return false; 2136 } 2137 2138 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, 2139 void *opaque, Error **errp) 2140 { 2141 PCMachineState *pcms = PC_MACHINE(obj); 2142 OnOffAuto smm = pcms->smm; 2143 2144 visit_type_OnOffAuto(v, name, &smm, errp); 2145 } 2146 2147 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, 2148 void *opaque, Error **errp) 2149 { 2150 PCMachineState *pcms = PC_MACHINE(obj); 2151 2152 visit_type_OnOffAuto(v, name, &pcms->smm, errp); 2153 } 2154 2155 static bool pc_machine_get_nvdimm(Object *obj, Error **errp) 2156 { 2157 PCMachineState *pcms = PC_MACHINE(obj); 2158 2159 return pcms->acpi_nvdimm_state.is_enabled; 2160 } 2161 2162 static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp) 2163 { 2164 PCMachineState *pcms = PC_MACHINE(obj); 2165 2166 pcms->acpi_nvdimm_state.is_enabled = value; 2167 } 2168 2169 static bool pc_machine_get_smbus(Object *obj, Error **errp) 2170 { 2171 PCMachineState *pcms = PC_MACHINE(obj); 2172 2173 return pcms->smbus; 2174 } 2175 2176 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 2177 { 2178 PCMachineState *pcms = PC_MACHINE(obj); 2179 2180 pcms->smbus = value; 2181 } 2182 2183 static bool pc_machine_get_sata(Object *obj, Error **errp) 2184 { 2185 PCMachineState *pcms = PC_MACHINE(obj); 2186 2187 return pcms->sata; 2188 } 2189 2190 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 2191 { 2192 PCMachineState *pcms = PC_MACHINE(obj); 2193 2194 pcms->sata = value; 2195 } 2196 2197 static bool pc_machine_get_pit(Object *obj, Error **errp) 2198 { 2199 PCMachineState *pcms = PC_MACHINE(obj); 2200 2201 return pcms->pit; 2202 } 2203 2204 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 2205 { 2206 PCMachineState *pcms = PC_MACHINE(obj); 2207 2208 pcms->pit = value; 2209 } 2210 2211 static void pc_machine_initfn(Object *obj) 2212 { 2213 PCMachineState *pcms = PC_MACHINE(obj); 2214 2215 pcms->max_ram_below_4g = 0; /* use default */ 2216 pcms->smm = ON_OFF_AUTO_AUTO; 2217 pcms->vmport = ON_OFF_AUTO_AUTO; 2218 /* nvdimm is disabled on default. */ 2219 pcms->acpi_nvdimm_state.is_enabled = false; 2220 /* acpi build is enabled by default if machine supports it */ 2221 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 2222 pcms->smbus = true; 2223 pcms->sata = true; 2224 pcms->pit = true; 2225 } 2226 2227 static void pc_machine_reset(void) 2228 { 2229 CPUState *cs; 2230 X86CPU *cpu; 2231 2232 qemu_devices_reset(); 2233 2234 /* Reset APIC after devices have been reset to cancel 2235 * any changes that qemu_devices_reset() might have done. 2236 */ 2237 CPU_FOREACH(cs) { 2238 cpu = X86_CPU(cs); 2239 2240 if (cpu->apic_state) { 2241 device_reset(cpu->apic_state); 2242 } 2243 } 2244 } 2245 2246 static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index) 2247 { 2248 X86CPUTopoInfo topo; 2249 x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index, 2250 &topo); 2251 return topo.pkg_id; 2252 } 2253 2254 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) 2255 { 2256 int i; 2257 2258 if (ms->possible_cpus) { 2259 /* 2260 * make sure that max_cpus hasn't changed since the first use, i.e. 2261 * -smp hasn't been parsed after it 2262 */ 2263 assert(ms->possible_cpus->len == max_cpus); 2264 return ms->possible_cpus; 2265 } 2266 2267 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2268 sizeof(CPUArchId) * max_cpus); 2269 ms->possible_cpus->len = max_cpus; 2270 for (i = 0; i < ms->possible_cpus->len; i++) { 2271 X86CPUTopoInfo topo; 2272 2273 ms->possible_cpus->cpus[i].vcpus_count = 1; 2274 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i); 2275 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, 2276 smp_cores, smp_threads, &topo); 2277 ms->possible_cpus->cpus[i].props.has_socket_id = true; 2278 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id; 2279 ms->possible_cpus->cpus[i].props.has_core_id = true; 2280 ms->possible_cpus->cpus[i].props.core_id = topo.core_id; 2281 ms->possible_cpus->cpus[i].props.has_thread_id = true; 2282 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id; 2283 } 2284 return ms->possible_cpus; 2285 } 2286 2287 static void x86_nmi(NMIState *n, int cpu_index, Error **errp) 2288 { 2289 /* cpu index isn't used */ 2290 CPUState *cs; 2291 2292 CPU_FOREACH(cs) { 2293 X86CPU *cpu = X86_CPU(cs); 2294 2295 if (!cpu->apic_state) { 2296 cpu_interrupt(cs, CPU_INTERRUPT_NMI); 2297 } else { 2298 apic_deliver_nmi(cpu->apic_state); 2299 } 2300 } 2301 } 2302 2303 static void pc_machine_class_init(ObjectClass *oc, void *data) 2304 { 2305 MachineClass *mc = MACHINE_CLASS(oc); 2306 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 2307 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2308 NMIClass *nc = NMI_CLASS(oc); 2309 2310 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 2311 pcmc->pci_enabled = true; 2312 pcmc->has_acpi_build = true; 2313 pcmc->rsdp_in_ram = true; 2314 pcmc->smbios_defaults = true; 2315 pcmc->smbios_uuid_encoded = true; 2316 pcmc->gigabyte_align = true; 2317 pcmc->has_reserved_memory = true; 2318 pcmc->kvmclock_enabled = true; 2319 pcmc->enforce_aligned_dimm = true; 2320 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 2321 * to be used at the moment, 32K should be enough for a while. */ 2322 pcmc->acpi_data_size = 0x20000 + 0x8000; 2323 pcmc->save_tsc_khz = true; 2324 mc->get_hotplug_handler = pc_get_hotpug_handler; 2325 mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id; 2326 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; 2327 mc->has_hotpluggable_cpus = true; 2328 mc->default_boot_order = "cad"; 2329 mc->hot_add_cpu = pc_hot_add_cpu; 2330 mc->block_default_type = IF_IDE; 2331 mc->max_cpus = 255; 2332 mc->reset = pc_machine_reset; 2333 hc->pre_plug = pc_machine_device_pre_plug_cb; 2334 hc->plug = pc_machine_device_plug_cb; 2335 hc->unplug_request = pc_machine_device_unplug_request_cb; 2336 hc->unplug = pc_machine_device_unplug_cb; 2337 nc->nmi_monitor_handler = x86_nmi; 2338 2339 object_class_property_add(oc, PC_MACHINE_MEMHP_REGION_SIZE, "int", 2340 pc_machine_get_hotplug_memory_region_size, NULL, 2341 NULL, NULL, &error_abort); 2342 2343 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 2344 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 2345 NULL, NULL, &error_abort); 2346 2347 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 2348 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort); 2349 2350 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", 2351 pc_machine_get_smm, pc_machine_set_smm, 2352 NULL, NULL, &error_abort); 2353 object_class_property_set_description(oc, PC_MACHINE_SMM, 2354 "Enable SMM (pc & q35)", &error_abort); 2355 2356 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 2357 pc_machine_get_vmport, pc_machine_set_vmport, 2358 NULL, NULL, &error_abort); 2359 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 2360 "Enable vmport (pc & q35)", &error_abort); 2361 2362 object_class_property_add_bool(oc, PC_MACHINE_NVDIMM, 2363 pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort); 2364 2365 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 2366 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); 2367 2368 object_class_property_add_bool(oc, PC_MACHINE_SATA, 2369 pc_machine_get_sata, pc_machine_set_sata, &error_abort); 2370 2371 object_class_property_add_bool(oc, PC_MACHINE_PIT, 2372 pc_machine_get_pit, pc_machine_set_pit, &error_abort); 2373 } 2374 2375 static const TypeInfo pc_machine_info = { 2376 .name = TYPE_PC_MACHINE, 2377 .parent = TYPE_MACHINE, 2378 .abstract = true, 2379 .instance_size = sizeof(PCMachineState), 2380 .instance_init = pc_machine_initfn, 2381 .class_size = sizeof(PCMachineClass), 2382 .class_init = pc_machine_class_init, 2383 .interfaces = (InterfaceInfo[]) { 2384 { TYPE_HOTPLUG_HANDLER }, 2385 { TYPE_NMI }, 2386 { } 2387 }, 2388 }; 2389 2390 static void pc_machine_register_types(void) 2391 { 2392 type_register_static(&pc_machine_info); 2393 } 2394 2395 type_init(pc_machine_register_types) 2396