1 /* Support for generating ACPI tables and passing them to Guests 2 * 3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 4 * Copyright (C) 2006 Fabrice Bellard 5 * Copyright (C) 2013 Red Hat Inc 6 * 7 * Author: Michael S. Tsirkin <mst@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qapi/error.h" 25 #include "qapi/qmp/qnum.h" 26 #include "acpi-build.h" 27 #include "qemu/bitmap.h" 28 #include "qemu/error-report.h" 29 #include "hw/pci/pci.h" 30 #include "qom/cpu.h" 31 #include "target/i386/cpu.h" 32 #include "hw/misc/pvpanic.h" 33 #include "hw/timer/hpet.h" 34 #include "hw/acpi/acpi-defs.h" 35 #include "hw/acpi/acpi.h" 36 #include "hw/acpi/cpu.h" 37 #include "hw/acpi/piix4.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/acpi/bios-linker-loader.h" 40 #include "hw/loader.h" 41 #include "hw/isa/isa.h" 42 #include "hw/block/fdc.h" 43 #include "hw/acpi/memory_hotplug.h" 44 #include "sysemu/tpm.h" 45 #include "hw/acpi/tpm.h" 46 #include "hw/acpi/vmgenid.h" 47 #include "sysemu/tpm_backend.h" 48 #include "hw/timer/mc146818rtc_regs.h" 49 #include "hw/mem/memory-device.h" 50 #include "sysemu/numa.h" 51 52 /* Supported chipsets: */ 53 #include "hw/acpi/piix4.h" 54 #include "hw/acpi/pcihp.h" 55 #include "hw/i386/ich9.h" 56 #include "hw/pci/pci_bus.h" 57 #include "hw/pci-host/q35.h" 58 #include "hw/i386/x86-iommu.h" 59 60 #include "hw/acpi/aml-build.h" 61 #include "hw/acpi/pci.h" 62 63 #include "qom/qom-qobject.h" 64 #include "hw/i386/amd_iommu.h" 65 #include "hw/i386/intel_iommu.h" 66 67 #include "hw/acpi/ipmi.h" 68 69 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and 70 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows 71 * a little bit, there should be plenty of free space since the DSDT 72 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1. 73 */ 74 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97 75 #define ACPI_BUILD_ALIGN_SIZE 0x1000 76 77 #define ACPI_BUILD_TABLE_SIZE 0x20000 78 79 /* #define DEBUG_ACPI_BUILD */ 80 #ifdef DEBUG_ACPI_BUILD 81 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 82 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 83 #else 84 #define ACPI_BUILD_DPRINTF(fmt, ...) 85 #endif 86 87 /* Default IOAPIC ID */ 88 #define ACPI_BUILD_IOAPIC_ID 0x0 89 90 typedef struct AcpiPmInfo { 91 bool s3_disabled; 92 bool s4_disabled; 93 bool pcihp_bridge_en; 94 uint8_t s4_val; 95 AcpiFadtData fadt; 96 uint16_t cpu_hp_io_base; 97 uint16_t pcihp_io_base; 98 uint16_t pcihp_io_len; 99 } AcpiPmInfo; 100 101 typedef struct AcpiMiscInfo { 102 bool is_piix4; 103 bool has_hpet; 104 TPMVersion tpm_version; 105 const unsigned char *dsdt_code; 106 unsigned dsdt_size; 107 uint16_t pvpanic_port; 108 uint16_t applesmc_io_base; 109 } AcpiMiscInfo; 110 111 typedef struct AcpiBuildPciBusHotplugState { 112 GArray *device_table; 113 GArray *notify_table; 114 struct AcpiBuildPciBusHotplugState *parent; 115 bool pcihp_bridge_en; 116 } AcpiBuildPciBusHotplugState; 117 118 typedef struct FwCfgTPMConfig { 119 uint32_t tpmppi_address; 120 uint8_t tpm_version; 121 uint8_t tpmppi_version; 122 } QEMU_PACKED FwCfgTPMConfig; 123 124 static void init_common_fadt_data(Object *o, AcpiFadtData *data) 125 { 126 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); 127 AmlAddressSpace as = AML_AS_SYSTEM_IO; 128 AcpiFadtData fadt = { 129 .rev = 3, 130 .flags = 131 (1 << ACPI_FADT_F_WBINVD) | 132 (1 << ACPI_FADT_F_PROC_C1) | 133 (1 << ACPI_FADT_F_SLP_BUTTON) | 134 (1 << ACPI_FADT_F_RTC_S4) | 135 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) | 136 /* APIC destination mode ("Flat Logical") has an upper limit of 8 137 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be 138 * used 139 */ 140 ((max_cpus > 8) ? (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0), 141 .int_model = 1 /* Multiple APIC */, 142 .rtc_century = RTC_CENTURY, 143 .plvl2_lat = 0xfff /* C2 state not supported */, 144 .plvl3_lat = 0xfff /* C3 state not supported */, 145 .smi_cmd = ACPI_PORT_SMI_CMD, 146 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), 147 .acpi_enable_cmd = 148 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL), 149 .acpi_disable_cmd = 150 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL), 151 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, 152 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, 153 .address = io + 0x04 }, 154 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 }, 155 .gpe0_blk = { .space_id = as, .bit_width = 156 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8, 157 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL) 158 }, 159 }; 160 *data = fadt; 161 } 162 163 static Object *object_resolve_type_unambiguous(const char *typename) 164 { 165 bool ambig; 166 Object *o = object_resolve_path_type("", typename, &ambig); 167 168 if (ambig || !o) { 169 return NULL; 170 } 171 return o; 172 } 173 174 static void acpi_get_pm_info(AcpiPmInfo *pm) 175 { 176 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 177 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 178 Object *obj = piix ? piix : lpc; 179 QObject *o; 180 pm->cpu_hp_io_base = 0; 181 pm->pcihp_io_base = 0; 182 pm->pcihp_io_len = 0; 183 184 assert(obj); 185 init_common_fadt_data(obj, &pm->fadt); 186 if (piix) { 187 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ 188 pm->fadt.rev = 1; 189 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; 190 pm->pcihp_io_base = 191 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); 192 pm->pcihp_io_len = 193 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); 194 } 195 if (lpc) { 196 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, 197 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; 198 pm->fadt.reset_reg = r; 199 pm->fadt.reset_val = 0xf; 200 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; 201 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; 202 } 203 204 /* The above need not be conditional on machine type because the reset port 205 * happens to be the same on PIIX (pc) and ICH9 (q35). */ 206 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT); 207 208 /* Fill in optional s3/s4 related properties */ 209 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL); 210 if (o) { 211 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o)); 212 } else { 213 pm->s3_disabled = false; 214 } 215 qobject_unref(o); 216 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL); 217 if (o) { 218 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o)); 219 } else { 220 pm->s4_disabled = false; 221 } 222 qobject_unref(o); 223 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL); 224 if (o) { 225 pm->s4_val = qnum_get_uint(qobject_to(QNum, o)); 226 } else { 227 pm->s4_val = false; 228 } 229 qobject_unref(o); 230 231 pm->pcihp_bridge_en = 232 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", 233 NULL); 234 } 235 236 static void acpi_get_misc_info(AcpiMiscInfo *info) 237 { 238 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM); 239 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); 240 assert(!!piix != !!lpc); 241 242 if (piix) { 243 info->is_piix4 = true; 244 } 245 if (lpc) { 246 info->is_piix4 = false; 247 } 248 249 info->has_hpet = hpet_find(); 250 info->tpm_version = tpm_get_version(tpm_find()); 251 info->pvpanic_port = pvpanic_port(); 252 info->applesmc_io_base = applesmc_port(); 253 } 254 255 /* 256 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE. 257 * On i386 arch we only have two pci hosts, so we can look only for them. 258 */ 259 static Object *acpi_get_i386_pci_host(void) 260 { 261 PCIHostState *host; 262 263 host = OBJECT_CHECK(PCIHostState, 264 object_resolve_path("/machine/i440fx", NULL), 265 TYPE_PCI_HOST_BRIDGE); 266 if (!host) { 267 host = OBJECT_CHECK(PCIHostState, 268 object_resolve_path("/machine/q35", NULL), 269 TYPE_PCI_HOST_BRIDGE); 270 } 271 272 return OBJECT(host); 273 } 274 275 static void acpi_get_pci_holes(Range *hole, Range *hole64) 276 { 277 Object *pci_host; 278 279 pci_host = acpi_get_i386_pci_host(); 280 g_assert(pci_host); 281 282 range_set_bounds1(hole, 283 object_property_get_uint(pci_host, 284 PCI_HOST_PROP_PCI_HOLE_START, 285 NULL), 286 object_property_get_uint(pci_host, 287 PCI_HOST_PROP_PCI_HOLE_END, 288 NULL)); 289 range_set_bounds1(hole64, 290 object_property_get_uint(pci_host, 291 PCI_HOST_PROP_PCI_HOLE64_START, 292 NULL), 293 object_property_get_uint(pci_host, 294 PCI_HOST_PROP_PCI_HOLE64_END, 295 NULL)); 296 } 297 298 static void acpi_align_size(GArray *blob, unsigned align) 299 { 300 /* Align size to multiple of given size. This reduces the chance 301 * we need to change size in the future (breaking cross version migration). 302 */ 303 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 304 } 305 306 /* FACS */ 307 static void 308 build_facs(GArray *table_data) 309 { 310 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs); 311 memcpy(&facs->signature, "FACS", 4); 312 facs->length = cpu_to_le32(sizeof(*facs)); 313 } 314 315 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, 316 const CPUArchIdList *apic_ids, GArray *entry) 317 { 318 uint32_t apic_id = apic_ids->cpus[uid].arch_id; 319 320 /* ACPI spec says that LAPIC entry for non present 321 * CPU may be omitted from MADT or it must be marked 322 * as disabled. However omitting non present CPU from 323 * MADT breaks hotplug on linux. So possible CPUs 324 * should be put in MADT but kept disabled. 325 */ 326 if (apic_id < 255) { 327 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic); 328 329 apic->type = ACPI_APIC_PROCESSOR; 330 apic->length = sizeof(*apic); 331 apic->processor_id = uid; 332 apic->local_apic_id = apic_id; 333 if (apic_ids->cpus[uid].cpu != NULL) { 334 apic->flags = cpu_to_le32(1); 335 } else { 336 apic->flags = cpu_to_le32(0); 337 } 338 } else { 339 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic); 340 341 apic->type = ACPI_APIC_LOCAL_X2APIC; 342 apic->length = sizeof(*apic); 343 apic->uid = cpu_to_le32(uid); 344 apic->x2apic_id = cpu_to_le32(apic_id); 345 if (apic_ids->cpus[uid].cpu != NULL) { 346 apic->flags = cpu_to_le32(1); 347 } else { 348 apic->flags = cpu_to_le32(0); 349 } 350 } 351 } 352 353 static void 354 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms) 355 { 356 MachineClass *mc = MACHINE_GET_CLASS(pcms); 357 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms)); 358 int madt_start = table_data->len; 359 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev); 360 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev); 361 bool x2apic_mode = false; 362 363 AcpiMultipleApicTable *madt; 364 AcpiMadtIoApic *io_apic; 365 AcpiMadtIntsrcovr *intsrcovr; 366 int i; 367 368 madt = acpi_data_push(table_data, sizeof *madt); 369 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS); 370 madt->flags = cpu_to_le32(1); 371 372 for (i = 0; i < apic_ids->len; i++) { 373 adevc->madt_cpu(adev, i, apic_ids, table_data); 374 if (apic_ids->cpus[i].arch_id > 254) { 375 x2apic_mode = true; 376 } 377 } 378 379 io_apic = acpi_data_push(table_data, sizeof *io_apic); 380 io_apic->type = ACPI_APIC_IO; 381 io_apic->length = sizeof(*io_apic); 382 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; 383 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); 384 io_apic->interrupt = cpu_to_le32(0); 385 386 if (pcms->apic_xrupt_override) { 387 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 388 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 389 intsrcovr->length = sizeof(*intsrcovr); 390 intsrcovr->source = 0; 391 intsrcovr->gsi = cpu_to_le32(2); 392 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */ 393 } 394 for (i = 1; i < 16; i++) { 395 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 396 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) { 397 /* No need for a INT source override structure. */ 398 continue; 399 } 400 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr); 401 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE; 402 intsrcovr->length = sizeof(*intsrcovr); 403 intsrcovr->source = i; 404 intsrcovr->gsi = cpu_to_le32(i); 405 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */ 406 } 407 408 if (x2apic_mode) { 409 AcpiMadtLocalX2ApicNmi *local_nmi; 410 411 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 412 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI; 413 local_nmi->length = sizeof(*local_nmi); 414 local_nmi->uid = 0xFFFFFFFF; /* all processors */ 415 local_nmi->flags = cpu_to_le16(0); 416 local_nmi->lint = 1; /* ACPI_LINT1 */ 417 } else { 418 AcpiMadtLocalNmi *local_nmi; 419 420 local_nmi = acpi_data_push(table_data, sizeof *local_nmi); 421 local_nmi->type = ACPI_APIC_LOCAL_NMI; 422 local_nmi->length = sizeof(*local_nmi); 423 local_nmi->processor_id = 0xff; /* all processors */ 424 local_nmi->flags = cpu_to_le16(0); 425 local_nmi->lint = 1; /* ACPI_LINT1 */ 426 } 427 428 build_header(linker, table_data, 429 (void *)(table_data->data + madt_start), "APIC", 430 table_data->len - madt_start, 1, NULL, NULL); 431 } 432 433 static void build_append_pcihp_notify_entry(Aml *method, int slot) 434 { 435 Aml *if_ctx; 436 int32_t devfn = PCI_DEVFN(slot, 0); 437 438 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); 439 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); 440 aml_append(method, if_ctx); 441 } 442 443 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, 444 bool pcihp_bridge_en) 445 { 446 Aml *dev, *notify_method = NULL, *method; 447 QObject *bsel; 448 PCIBus *sec; 449 int i; 450 451 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL); 452 if (bsel) { 453 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 454 455 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); 456 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED); 457 } 458 459 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) { 460 DeviceClass *dc; 461 PCIDeviceClass *pc; 462 PCIDevice *pdev = bus->devices[i]; 463 int slot = PCI_SLOT(i); 464 bool hotplug_enabled_dev; 465 bool bridge_in_acpi; 466 467 if (!pdev) { 468 if (bsel) { /* add hotplug slots for non present devices */ 469 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 470 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 471 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 472 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 473 aml_append(method, 474 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 475 ); 476 aml_append(dev, method); 477 aml_append(parent_scope, dev); 478 479 build_append_pcihp_notify_entry(notify_method, slot); 480 } 481 continue; 482 } 483 484 pc = PCI_DEVICE_GET_CLASS(pdev); 485 dc = DEVICE_GET_CLASS(pdev); 486 487 /* When hotplug for bridges is enabled, bridges are 488 * described in ACPI separately (see build_pci_bus_end). 489 * In this case they aren't themselves hot-pluggable. 490 * Hotplugged bridges *are* hot-pluggable. 491 */ 492 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && 493 !DEVICE(pdev)->hotplugged; 494 495 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; 496 497 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { 498 continue; 499 } 500 501 /* start to compose PCI slot descriptor */ 502 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); 503 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); 504 505 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) { 506 /* add VGA specific AML methods */ 507 int s3d; 508 509 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) { 510 s3d = 3; 511 } else { 512 s3d = 0; 513 } 514 515 method = aml_method("_S1D", 0, AML_NOTSERIALIZED); 516 aml_append(method, aml_return(aml_int(0))); 517 aml_append(dev, method); 518 519 method = aml_method("_S2D", 0, AML_NOTSERIALIZED); 520 aml_append(method, aml_return(aml_int(0))); 521 aml_append(dev, method); 522 523 method = aml_method("_S3D", 0, AML_NOTSERIALIZED); 524 aml_append(method, aml_return(aml_int(s3d))); 525 aml_append(dev, method); 526 } else if (hotplug_enabled_dev) { 527 /* add _SUN/_EJ0 to make slot hotpluggable */ 528 aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); 529 530 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED); 531 aml_append(method, 532 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) 533 ); 534 aml_append(dev, method); 535 536 if (bsel) { 537 build_append_pcihp_notify_entry(notify_method, slot); 538 } 539 } else if (bridge_in_acpi) { 540 /* 541 * device is coldplugged bridge, 542 * add child device descriptions into its scope 543 */ 544 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 545 546 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en); 547 } 548 /* slot descriptor has been composed, add it into parent context */ 549 aml_append(parent_scope, dev); 550 } 551 552 if (bsel) { 553 aml_append(parent_scope, notify_method); 554 } 555 556 /* Append PCNT method to notify about events on local and child buses. 557 * Add unconditionally for root since DSDT expects it. 558 */ 559 method = aml_method("PCNT", 0, AML_NOTSERIALIZED); 560 561 /* If bus supports hotplug select it and notify about local events */ 562 if (bsel) { 563 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); 564 565 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); 566 aml_append(method, 567 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */) 568 ); 569 aml_append(method, 570 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */) 571 ); 572 } 573 574 /* Notify about child bus events in any case */ 575 if (pcihp_bridge_en) { 576 QLIST_FOREACH(sec, &bus->child, sibling) { 577 int32_t devfn = sec->parent_dev->devfn; 578 579 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { 580 continue; 581 } 582 583 aml_append(method, aml_name("^S%.02X.PCNT", devfn)); 584 } 585 } 586 aml_append(parent_scope, method); 587 qobject_unref(bsel); 588 } 589 590 /** 591 * build_prt_entry: 592 * @link_name: link name for PCI route entry 593 * 594 * build AML package containing a PCI route entry for @link_name 595 */ 596 static Aml *build_prt_entry(const char *link_name) 597 { 598 Aml *a_zero = aml_int(0); 599 Aml *pkg = aml_package(4); 600 aml_append(pkg, a_zero); 601 aml_append(pkg, a_zero); 602 aml_append(pkg, aml_name("%s", link_name)); 603 aml_append(pkg, a_zero); 604 return pkg; 605 } 606 607 /* 608 * initialize_route - Initialize the interrupt routing rule 609 * through a specific LINK: 610 * if (lnk_idx == idx) 611 * route using link 'link_name' 612 */ 613 static Aml *initialize_route(Aml *route, const char *link_name, 614 Aml *lnk_idx, int idx) 615 { 616 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx))); 617 Aml *pkg = build_prt_entry(link_name); 618 619 aml_append(if_ctx, aml_store(pkg, route)); 620 621 return if_ctx; 622 } 623 624 /* 625 * build_prt - Define interrupt rounting rules 626 * 627 * Returns an array of 128 routes, one for each device, 628 * based on device location. 629 * The main goal is to equaly distribute the interrupts 630 * over the 4 existing ACPI links (works only for i440fx). 631 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". 632 * 633 */ 634 static Aml *build_prt(bool is_pci0_prt) 635 { 636 Aml *method, *while_ctx, *pin, *res; 637 638 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 639 res = aml_local(0); 640 pin = aml_local(1); 641 aml_append(method, aml_store(aml_package(128), res)); 642 aml_append(method, aml_store(aml_int(0), pin)); 643 644 /* while (pin < 128) */ 645 while_ctx = aml_while(aml_lless(pin, aml_int(128))); 646 { 647 Aml *slot = aml_local(2); 648 Aml *lnk_idx = aml_local(3); 649 Aml *route = aml_local(4); 650 651 /* slot = pin >> 2 */ 652 aml_append(while_ctx, 653 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot)); 654 /* lnk_idx = (slot + pin) & 3 */ 655 aml_append(while_ctx, 656 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL), 657 lnk_idx)); 658 659 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */ 660 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0)); 661 if (is_pci0_prt) { 662 Aml *if_device_1, *if_pin_4, *else_pin_4; 663 664 /* device 1 is the power-management device, needs SCI */ 665 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1))); 666 { 667 if_pin_4 = aml_if(aml_equal(pin, aml_int(4))); 668 { 669 aml_append(if_pin_4, 670 aml_store(build_prt_entry("LNKS"), route)); 671 } 672 aml_append(if_device_1, if_pin_4); 673 else_pin_4 = aml_else(); 674 { 675 aml_append(else_pin_4, 676 aml_store(build_prt_entry("LNKA"), route)); 677 } 678 aml_append(if_device_1, else_pin_4); 679 } 680 aml_append(while_ctx, if_device_1); 681 } else { 682 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1)); 683 } 684 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2)); 685 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3)); 686 687 /* route[0] = 0x[slot]FFFF */ 688 aml_append(while_ctx, 689 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF), 690 NULL), 691 aml_index(route, aml_int(0)))); 692 /* route[1] = pin & 3 */ 693 aml_append(while_ctx, 694 aml_store(aml_and(pin, aml_int(3), NULL), 695 aml_index(route, aml_int(1)))); 696 /* res[pin] = route */ 697 aml_append(while_ctx, aml_store(route, aml_index(res, pin))); 698 /* pin++ */ 699 aml_append(while_ctx, aml_increment(pin)); 700 } 701 aml_append(method, while_ctx); 702 /* return res*/ 703 aml_append(method, aml_return(res)); 704 705 return method; 706 } 707 708 typedef struct CrsRangeEntry { 709 uint64_t base; 710 uint64_t limit; 711 } CrsRangeEntry; 712 713 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit) 714 { 715 CrsRangeEntry *entry; 716 717 entry = g_malloc(sizeof(*entry)); 718 entry->base = base; 719 entry->limit = limit; 720 721 g_ptr_array_add(ranges, entry); 722 } 723 724 static void crs_range_free(gpointer data) 725 { 726 CrsRangeEntry *entry = (CrsRangeEntry *)data; 727 g_free(entry); 728 } 729 730 typedef struct CrsRangeSet { 731 GPtrArray *io_ranges; 732 GPtrArray *mem_ranges; 733 GPtrArray *mem_64bit_ranges; 734 } CrsRangeSet; 735 736 static void crs_range_set_init(CrsRangeSet *range_set) 737 { 738 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free); 739 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free); 740 range_set->mem_64bit_ranges = 741 g_ptr_array_new_with_free_func(crs_range_free); 742 } 743 744 static void crs_range_set_free(CrsRangeSet *range_set) 745 { 746 g_ptr_array_free(range_set->io_ranges, true); 747 g_ptr_array_free(range_set->mem_ranges, true); 748 g_ptr_array_free(range_set->mem_64bit_ranges, true); 749 } 750 751 static gint crs_range_compare(gconstpointer a, gconstpointer b) 752 { 753 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a; 754 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b; 755 756 return (int64_t)entry_a->base - (int64_t)entry_b->base; 757 } 758 759 /* 760 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end] 761 * interval, computes the 'free' ranges from the same interval. 762 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function 763 * will return { [base - a1], [a2 - b1], [b2 - limit] }. 764 */ 765 static void crs_replace_with_free_ranges(GPtrArray *ranges, 766 uint64_t start, uint64_t end) 767 { 768 GPtrArray *free_ranges = g_ptr_array_new(); 769 uint64_t free_base = start; 770 int i; 771 772 g_ptr_array_sort(ranges, crs_range_compare); 773 for (i = 0; i < ranges->len; i++) { 774 CrsRangeEntry *used = g_ptr_array_index(ranges, i); 775 776 if (free_base < used->base) { 777 crs_range_insert(free_ranges, free_base, used->base - 1); 778 } 779 780 free_base = used->limit + 1; 781 } 782 783 if (free_base < end) { 784 crs_range_insert(free_ranges, free_base, end); 785 } 786 787 g_ptr_array_set_size(ranges, 0); 788 for (i = 0; i < free_ranges->len; i++) { 789 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); 790 } 791 792 g_ptr_array_free(free_ranges, true); 793 } 794 795 /* 796 * crs_range_merge - merges adjacent ranges in the given array. 797 * Array elements are deleted and replaced with the merged ranges. 798 */ 799 static void crs_range_merge(GPtrArray *range) 800 { 801 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free); 802 CrsRangeEntry *entry; 803 uint64_t range_base, range_limit; 804 int i; 805 806 if (!range->len) { 807 return; 808 } 809 810 g_ptr_array_sort(range, crs_range_compare); 811 812 entry = g_ptr_array_index(range, 0); 813 range_base = entry->base; 814 range_limit = entry->limit; 815 for (i = 1; i < range->len; i++) { 816 entry = g_ptr_array_index(range, i); 817 if (entry->base - 1 == range_limit) { 818 range_limit = entry->limit; 819 } else { 820 crs_range_insert(tmp, range_base, range_limit); 821 range_base = entry->base; 822 range_limit = entry->limit; 823 } 824 } 825 crs_range_insert(tmp, range_base, range_limit); 826 827 g_ptr_array_set_size(range, 0); 828 for (i = 0; i < tmp->len; i++) { 829 entry = g_ptr_array_index(tmp, i); 830 crs_range_insert(range, entry->base, entry->limit); 831 } 832 g_ptr_array_free(tmp, true); 833 } 834 835 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) 836 { 837 Aml *crs = aml_resource_template(); 838 CrsRangeSet temp_range_set; 839 CrsRangeEntry *entry; 840 uint8_t max_bus = pci_bus_num(host->bus); 841 uint8_t type; 842 int devfn; 843 int i; 844 845 crs_range_set_init(&temp_range_set); 846 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { 847 uint64_t range_base, range_limit; 848 PCIDevice *dev = host->bus->devices[devfn]; 849 850 if (!dev) { 851 continue; 852 } 853 854 for (i = 0; i < PCI_NUM_REGIONS; i++) { 855 PCIIORegion *r = &dev->io_regions[i]; 856 857 range_base = r->addr; 858 range_limit = r->addr + r->size - 1; 859 860 /* 861 * Work-around for old bioses 862 * that do not support multiple root buses 863 */ 864 if (!range_base || range_base > range_limit) { 865 continue; 866 } 867 868 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 869 crs_range_insert(temp_range_set.io_ranges, 870 range_base, range_limit); 871 } else { /* "memory" */ 872 crs_range_insert(temp_range_set.mem_ranges, 873 range_base, range_limit); 874 } 875 } 876 877 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 878 if (type == PCI_HEADER_TYPE_BRIDGE) { 879 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS]; 880 if (subordinate > max_bus) { 881 max_bus = subordinate; 882 } 883 884 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 885 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 886 887 /* 888 * Work-around for old bioses 889 * that do not support multiple root buses 890 */ 891 if (range_base && range_base <= range_limit) { 892 crs_range_insert(temp_range_set.io_ranges, 893 range_base, range_limit); 894 } 895 896 range_base = 897 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 898 range_limit = 899 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 900 901 /* 902 * Work-around for old bioses 903 * that do not support multiple root buses 904 */ 905 if (range_base && range_base <= range_limit) { 906 uint64_t length = range_limit - range_base + 1; 907 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 908 crs_range_insert(temp_range_set.mem_ranges, 909 range_base, range_limit); 910 } else { 911 crs_range_insert(temp_range_set.mem_64bit_ranges, 912 range_base, range_limit); 913 } 914 } 915 916 range_base = 917 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 918 range_limit = 919 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 920 921 /* 922 * Work-around for old bioses 923 * that do not support multiple root buses 924 */ 925 if (range_base && range_base <= range_limit) { 926 uint64_t length = range_limit - range_base + 1; 927 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) { 928 crs_range_insert(temp_range_set.mem_ranges, 929 range_base, range_limit); 930 } else { 931 crs_range_insert(temp_range_set.mem_64bit_ranges, 932 range_base, range_limit); 933 } 934 } 935 } 936 } 937 938 crs_range_merge(temp_range_set.io_ranges); 939 for (i = 0; i < temp_range_set.io_ranges->len; i++) { 940 entry = g_ptr_array_index(temp_range_set.io_ranges, i); 941 aml_append(crs, 942 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 943 AML_POS_DECODE, AML_ENTIRE_RANGE, 944 0, entry->base, entry->limit, 0, 945 entry->limit - entry->base + 1)); 946 crs_range_insert(range_set->io_ranges, entry->base, entry->limit); 947 } 948 949 crs_range_merge(temp_range_set.mem_ranges); 950 for (i = 0; i < temp_range_set.mem_ranges->len; i++) { 951 entry = g_ptr_array_index(temp_range_set.mem_ranges, i); 952 aml_append(crs, 953 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, 954 AML_MAX_FIXED, AML_NON_CACHEABLE, 955 AML_READ_WRITE, 956 0, entry->base, entry->limit, 0, 957 entry->limit - entry->base + 1)); 958 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); 959 } 960 961 crs_range_merge(temp_range_set.mem_64bit_ranges); 962 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) { 963 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i); 964 aml_append(crs, 965 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 966 AML_MAX_FIXED, AML_NON_CACHEABLE, 967 AML_READ_WRITE, 968 0, entry->base, entry->limit, 0, 969 entry->limit - entry->base + 1)); 970 crs_range_insert(range_set->mem_64bit_ranges, 971 entry->base, entry->limit); 972 } 973 974 crs_range_set_free(&temp_range_set); 975 976 aml_append(crs, 977 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 978 0, 979 pci_bus_num(host->bus), 980 max_bus, 981 0, 982 max_bus - pci_bus_num(host->bus) + 1)); 983 984 return crs; 985 } 986 987 static void build_hpet_aml(Aml *table) 988 { 989 Aml *crs; 990 Aml *field; 991 Aml *method; 992 Aml *if_ctx; 993 Aml *scope = aml_scope("_SB"); 994 Aml *dev = aml_device("HPET"); 995 Aml *zero = aml_int(0); 996 Aml *id = aml_local(0); 997 Aml *period = aml_local(1); 998 999 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103"))); 1000 aml_append(dev, aml_name_decl("_UID", zero)); 1001 1002 aml_append(dev, 1003 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE), 1004 HPET_LEN)); 1005 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE); 1006 aml_append(field, aml_named_field("VEND", 32)); 1007 aml_append(field, aml_named_field("PRD", 32)); 1008 aml_append(dev, field); 1009 1010 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1011 aml_append(method, aml_store(aml_name("VEND"), id)); 1012 aml_append(method, aml_store(aml_name("PRD"), period)); 1013 aml_append(method, aml_shiftright(id, aml_int(16), id)); 1014 if_ctx = aml_if(aml_lor(aml_equal(id, zero), 1015 aml_equal(id, aml_int(0xffff)))); 1016 { 1017 aml_append(if_ctx, aml_return(zero)); 1018 } 1019 aml_append(method, if_ctx); 1020 1021 if_ctx = aml_if(aml_lor(aml_equal(period, zero), 1022 aml_lgreater(period, aml_int(100000000)))); 1023 { 1024 aml_append(if_ctx, aml_return(zero)); 1025 } 1026 aml_append(method, if_ctx); 1027 1028 aml_append(method, aml_return(aml_int(0x0F))); 1029 aml_append(dev, method); 1030 1031 crs = aml_resource_template(); 1032 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY)); 1033 aml_append(dev, aml_name_decl("_CRS", crs)); 1034 1035 aml_append(scope, dev); 1036 aml_append(table, scope); 1037 } 1038 1039 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type) 1040 { 1041 Aml *dev, *fdi; 1042 uint8_t maxc, maxh, maxs; 1043 1044 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs); 1045 1046 dev = aml_device("FLP%c", 'A' + idx); 1047 1048 aml_append(dev, aml_name_decl("_ADR", aml_int(idx))); 1049 1050 fdi = aml_package(16); 1051 aml_append(fdi, aml_int(idx)); /* Drive Number */ 1052 aml_append(fdi, 1053 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */ 1054 /* 1055 * the values below are the limits of the drive, and are thus independent 1056 * of the inserted media 1057 */ 1058 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */ 1059 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */ 1060 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */ 1061 /* 1062 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of 1063 * the drive type, so shall we 1064 */ 1065 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */ 1066 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */ 1067 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */ 1068 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */ 1069 aml_append(fdi, aml_int(0x12)); /* disk_eot */ 1070 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */ 1071 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */ 1072 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */ 1073 aml_append(fdi, aml_int(0xF6)); /* disk_fill */ 1074 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */ 1075 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */ 1076 1077 aml_append(dev, aml_name_decl("_FDI", fdi)); 1078 return dev; 1079 } 1080 1081 static Aml *build_fdc_device_aml(ISADevice *fdc) 1082 { 1083 int i; 1084 Aml *dev; 1085 Aml *crs; 1086 1087 #define ACPI_FDE_MAX_FD 4 1088 uint32_t fde_buf[5] = { 1089 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */ 1090 cpu_to_le32(2) /* tape presence (2 == never present) */ 1091 }; 1092 1093 dev = aml_device("FDC0"); 1094 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700"))); 1095 1096 crs = aml_resource_template(); 1097 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04)); 1098 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01)); 1099 aml_append(crs, aml_irq_no_flags(6)); 1100 aml_append(crs, 1101 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2)); 1102 aml_append(dev, aml_name_decl("_CRS", crs)); 1103 1104 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) { 1105 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i); 1106 1107 if (type < FLOPPY_DRIVE_TYPE_NONE) { 1108 fde_buf[i] = cpu_to_le32(1); /* drive present */ 1109 aml_append(dev, build_fdinfo_aml(i, type)); 1110 } 1111 } 1112 aml_append(dev, aml_name_decl("_FDE", 1113 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf))); 1114 1115 return dev; 1116 } 1117 1118 static Aml *build_rtc_device_aml(void) 1119 { 1120 Aml *dev; 1121 Aml *crs; 1122 1123 dev = aml_device("RTC"); 1124 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00"))); 1125 crs = aml_resource_template(); 1126 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02)); 1127 aml_append(crs, aml_irq_no_flags(8)); 1128 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06)); 1129 aml_append(dev, aml_name_decl("_CRS", crs)); 1130 1131 return dev; 1132 } 1133 1134 static Aml *build_kbd_device_aml(void) 1135 { 1136 Aml *dev; 1137 Aml *crs; 1138 Aml *method; 1139 1140 dev = aml_device("KBD"); 1141 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303"))); 1142 1143 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1144 aml_append(method, aml_return(aml_int(0x0f))); 1145 aml_append(dev, method); 1146 1147 crs = aml_resource_template(); 1148 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01)); 1149 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01)); 1150 aml_append(crs, aml_irq_no_flags(1)); 1151 aml_append(dev, aml_name_decl("_CRS", crs)); 1152 1153 return dev; 1154 } 1155 1156 static Aml *build_mouse_device_aml(void) 1157 { 1158 Aml *dev; 1159 Aml *crs; 1160 Aml *method; 1161 1162 dev = aml_device("MOU"); 1163 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13"))); 1164 1165 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1166 aml_append(method, aml_return(aml_int(0x0f))); 1167 aml_append(dev, method); 1168 1169 crs = aml_resource_template(); 1170 aml_append(crs, aml_irq_no_flags(12)); 1171 aml_append(dev, aml_name_decl("_CRS", crs)); 1172 1173 return dev; 1174 } 1175 1176 static Aml *build_lpt_device_aml(void) 1177 { 1178 Aml *dev; 1179 Aml *crs; 1180 Aml *method; 1181 Aml *if_ctx; 1182 Aml *else_ctx; 1183 Aml *zero = aml_int(0); 1184 Aml *is_present = aml_local(0); 1185 1186 dev = aml_device("LPT"); 1187 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400"))); 1188 1189 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1190 aml_append(method, aml_store(aml_name("LPEN"), is_present)); 1191 if_ctx = aml_if(aml_equal(is_present, zero)); 1192 { 1193 aml_append(if_ctx, aml_return(aml_int(0x00))); 1194 } 1195 aml_append(method, if_ctx); 1196 else_ctx = aml_else(); 1197 { 1198 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1199 } 1200 aml_append(method, else_ctx); 1201 aml_append(dev, method); 1202 1203 crs = aml_resource_template(); 1204 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08)); 1205 aml_append(crs, aml_irq_no_flags(7)); 1206 aml_append(dev, aml_name_decl("_CRS", crs)); 1207 1208 return dev; 1209 } 1210 1211 static Aml *build_com_device_aml(uint8_t uid) 1212 { 1213 Aml *dev; 1214 Aml *crs; 1215 Aml *method; 1216 Aml *if_ctx; 1217 Aml *else_ctx; 1218 Aml *zero = aml_int(0); 1219 Aml *is_present = aml_local(0); 1220 const char *enabled_field = "CAEN"; 1221 uint8_t irq = 4; 1222 uint16_t io_port = 0x03F8; 1223 1224 assert(uid == 1 || uid == 2); 1225 if (uid == 2) { 1226 enabled_field = "CBEN"; 1227 irq = 3; 1228 io_port = 0x02F8; 1229 } 1230 1231 dev = aml_device("COM%d", uid); 1232 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501"))); 1233 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1234 1235 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1236 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present)); 1237 if_ctx = aml_if(aml_equal(is_present, zero)); 1238 { 1239 aml_append(if_ctx, aml_return(aml_int(0x00))); 1240 } 1241 aml_append(method, if_ctx); 1242 else_ctx = aml_else(); 1243 { 1244 aml_append(else_ctx, aml_return(aml_int(0x0f))); 1245 } 1246 aml_append(method, else_ctx); 1247 aml_append(dev, method); 1248 1249 crs = aml_resource_template(); 1250 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08)); 1251 aml_append(crs, aml_irq_no_flags(irq)); 1252 aml_append(dev, aml_name_decl("_CRS", crs)); 1253 1254 return dev; 1255 } 1256 1257 static void build_isa_devices_aml(Aml *table) 1258 { 1259 ISADevice *fdc = pc_find_fdc0(); 1260 bool ambiguous; 1261 1262 Aml *scope = aml_scope("_SB.PCI0.ISA"); 1263 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous); 1264 1265 aml_append(scope, build_rtc_device_aml()); 1266 aml_append(scope, build_kbd_device_aml()); 1267 aml_append(scope, build_mouse_device_aml()); 1268 if (fdc) { 1269 aml_append(scope, build_fdc_device_aml(fdc)); 1270 } 1271 aml_append(scope, build_lpt_device_aml()); 1272 aml_append(scope, build_com_device_aml(1)); 1273 aml_append(scope, build_com_device_aml(2)); 1274 1275 if (ambiguous) { 1276 error_report("Multiple ISA busses, unable to define IPMI ACPI data"); 1277 } else if (!obj) { 1278 error_report("No ISA bus, unable to define IPMI ACPI data"); 1279 } else { 1280 build_acpi_ipmi_devices(scope, BUS(obj)); 1281 } 1282 1283 aml_append(table, scope); 1284 } 1285 1286 static void build_dbg_aml(Aml *table) 1287 { 1288 Aml *field; 1289 Aml *method; 1290 Aml *while_ctx; 1291 Aml *scope = aml_scope("\\"); 1292 Aml *buf = aml_local(0); 1293 Aml *len = aml_local(1); 1294 Aml *idx = aml_local(2); 1295 1296 aml_append(scope, 1297 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); 1298 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1299 aml_append(field, aml_named_field("DBGB", 8)); 1300 aml_append(scope, field); 1301 1302 method = aml_method("DBUG", 1, AML_NOTSERIALIZED); 1303 1304 aml_append(method, aml_to_hexstring(aml_arg(0), buf)); 1305 aml_append(method, aml_to_buffer(buf, buf)); 1306 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); 1307 aml_append(method, aml_store(aml_int(0), idx)); 1308 1309 while_ctx = aml_while(aml_lless(idx, len)); 1310 aml_append(while_ctx, 1311 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); 1312 aml_append(while_ctx, aml_increment(idx)); 1313 aml_append(method, while_ctx); 1314 1315 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); 1316 aml_append(scope, method); 1317 1318 aml_append(table, scope); 1319 } 1320 1321 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg) 1322 { 1323 Aml *dev; 1324 Aml *crs; 1325 Aml *method; 1326 uint32_t irqs[] = {5, 10, 11}; 1327 1328 dev = aml_device("%s", name); 1329 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1330 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1331 1332 crs = aml_resource_template(); 1333 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1334 AML_SHARED, irqs, ARRAY_SIZE(irqs))); 1335 aml_append(dev, aml_name_decl("_PRS", crs)); 1336 1337 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1338 aml_append(method, aml_return(aml_call1("IQST", reg))); 1339 aml_append(dev, method); 1340 1341 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1342 aml_append(method, aml_or(reg, aml_int(0x80), reg)); 1343 aml_append(dev, method); 1344 1345 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1346 aml_append(method, aml_return(aml_call1("IQCR", reg))); 1347 aml_append(dev, method); 1348 1349 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1350 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI")); 1351 aml_append(method, aml_store(aml_name("PRRI"), reg)); 1352 aml_append(dev, method); 1353 1354 return dev; 1355 } 1356 1357 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi) 1358 { 1359 Aml *dev; 1360 Aml *crs; 1361 Aml *method; 1362 uint32_t irqs; 1363 1364 dev = aml_device("%s", name); 1365 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1366 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 1367 1368 crs = aml_resource_template(); 1369 irqs = gsi; 1370 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 1371 AML_SHARED, &irqs, 1)); 1372 aml_append(dev, aml_name_decl("_PRS", crs)); 1373 1374 aml_append(dev, aml_name_decl("_CRS", crs)); 1375 1376 /* 1377 * _DIS can be no-op because the interrupt cannot be disabled. 1378 */ 1379 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1380 aml_append(dev, method); 1381 1382 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1383 aml_append(dev, method); 1384 1385 return dev; 1386 } 1387 1388 /* _CRS method - get current settings */ 1389 static Aml *build_iqcr_method(bool is_piix4) 1390 { 1391 Aml *if_ctx; 1392 uint32_t irqs; 1393 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED); 1394 Aml *crs = aml_resource_template(); 1395 1396 irqs = 0; 1397 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1398 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1)); 1399 aml_append(method, aml_name_decl("PRR0", crs)); 1400 1401 aml_append(method, 1402 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI")); 1403 1404 if (is_piix4) { 1405 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80))); 1406 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI"))); 1407 aml_append(method, if_ctx); 1408 } else { 1409 aml_append(method, 1410 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL), 1411 aml_name("PRRI"))); 1412 } 1413 1414 aml_append(method, aml_return(aml_name("PRR0"))); 1415 return method; 1416 } 1417 1418 /* _STA method - get status */ 1419 static Aml *build_irq_status_method(void) 1420 { 1421 Aml *if_ctx; 1422 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED); 1423 1424 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL)); 1425 aml_append(if_ctx, aml_return(aml_int(0x09))); 1426 aml_append(method, if_ctx); 1427 aml_append(method, aml_return(aml_int(0x0B))); 1428 return method; 1429 } 1430 1431 static void build_piix4_pci0_int(Aml *table) 1432 { 1433 Aml *dev; 1434 Aml *crs; 1435 Aml *field; 1436 Aml *method; 1437 uint32_t irqs; 1438 Aml *sb_scope = aml_scope("_SB"); 1439 Aml *pci0_scope = aml_scope("PCI0"); 1440 1441 aml_append(pci0_scope, build_prt(true)); 1442 aml_append(sb_scope, pci0_scope); 1443 1444 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1445 aml_append(field, aml_named_field("PRQ0", 8)); 1446 aml_append(field, aml_named_field("PRQ1", 8)); 1447 aml_append(field, aml_named_field("PRQ2", 8)); 1448 aml_append(field, aml_named_field("PRQ3", 8)); 1449 aml_append(sb_scope, field); 1450 1451 aml_append(sb_scope, build_irq_status_method()); 1452 aml_append(sb_scope, build_iqcr_method(true)); 1453 1454 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"))); 1455 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"))); 1456 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"))); 1457 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"))); 1458 1459 dev = aml_device("LNKS"); 1460 { 1461 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F"))); 1462 aml_append(dev, aml_name_decl("_UID", aml_int(4))); 1463 1464 crs = aml_resource_template(); 1465 irqs = 9; 1466 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, 1467 AML_ACTIVE_HIGH, AML_SHARED, 1468 &irqs, 1)); 1469 aml_append(dev, aml_name_decl("_PRS", crs)); 1470 1471 /* The SCI cannot be disabled and is always attached to GSI 9, 1472 * so these are no-ops. We only need this link to override the 1473 * polarity to active high and match the content of the MADT. 1474 */ 1475 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 1476 aml_append(method, aml_return(aml_int(0x0b))); 1477 aml_append(dev, method); 1478 1479 method = aml_method("_DIS", 0, AML_NOTSERIALIZED); 1480 aml_append(dev, method); 1481 1482 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 1483 aml_append(method, aml_return(aml_name("_PRS"))); 1484 aml_append(dev, method); 1485 1486 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 1487 aml_append(dev, method); 1488 } 1489 aml_append(sb_scope, dev); 1490 1491 aml_append(table, sb_scope); 1492 } 1493 1494 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name) 1495 { 1496 int i; 1497 int head; 1498 Aml *pkg; 1499 char base = name[3] < 'E' ? 'A' : 'E'; 1500 char *s = g_strdup(name); 1501 Aml *a_nr = aml_int((nr << 16) | 0xffff); 1502 1503 assert(strlen(s) == 4); 1504 1505 head = name[3] - base; 1506 for (i = 0; i < 4; i++) { 1507 if (head + i > 3) { 1508 head = i * -1; 1509 } 1510 s[3] = base + head + i; 1511 pkg = aml_package(4); 1512 aml_append(pkg, a_nr); 1513 aml_append(pkg, aml_int(i)); 1514 aml_append(pkg, aml_name("%s", s)); 1515 aml_append(pkg, aml_int(0)); 1516 aml_append(ctx, pkg); 1517 } 1518 g_free(s); 1519 } 1520 1521 static Aml *build_q35_routing_table(const char *str) 1522 { 1523 int i; 1524 Aml *pkg; 1525 char *name = g_strdup_printf("%s ", str); 1526 1527 pkg = aml_package(128); 1528 for (i = 0; i < 0x18; i++) { 1529 name[3] = 'E' + (i & 0x3); 1530 append_q35_prt_entry(pkg, i, name); 1531 } 1532 1533 name[3] = 'E'; 1534 append_q35_prt_entry(pkg, 0x18, name); 1535 1536 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */ 1537 for (i = 0x0019; i < 0x1e; i++) { 1538 name[3] = 'A'; 1539 append_q35_prt_entry(pkg, i, name); 1540 } 1541 1542 /* PCIe->PCI bridge. use PIRQ[E-H] */ 1543 name[3] = 'E'; 1544 append_q35_prt_entry(pkg, 0x1e, name); 1545 name[3] = 'A'; 1546 append_q35_prt_entry(pkg, 0x1f, name); 1547 1548 g_free(name); 1549 return pkg; 1550 } 1551 1552 static void build_q35_pci0_int(Aml *table) 1553 { 1554 Aml *field; 1555 Aml *method; 1556 Aml *sb_scope = aml_scope("_SB"); 1557 Aml *pci0_scope = aml_scope("PCI0"); 1558 1559 /* Zero => PIC mode, One => APIC Mode */ 1560 aml_append(table, aml_name_decl("PICF", aml_int(0))); 1561 method = aml_method("_PIC", 1, AML_NOTSERIALIZED); 1562 { 1563 aml_append(method, aml_store(aml_arg(0), aml_name("PICF"))); 1564 } 1565 aml_append(table, method); 1566 1567 aml_append(pci0_scope, 1568 aml_name_decl("PRTP", build_q35_routing_table("LNK"))); 1569 aml_append(pci0_scope, 1570 aml_name_decl("PRTA", build_q35_routing_table("GSI"))); 1571 1572 method = aml_method("_PRT", 0, AML_NOTSERIALIZED); 1573 { 1574 Aml *if_ctx; 1575 Aml *else_ctx; 1576 1577 /* PCI IRQ routing table, example from ACPI 2.0a specification, 1578 section 6.2.8.1 */ 1579 /* Note: we provide the same info as the PCI routing 1580 table of the Bochs BIOS */ 1581 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0))); 1582 aml_append(if_ctx, aml_return(aml_name("PRTP"))); 1583 aml_append(method, if_ctx); 1584 else_ctx = aml_else(); 1585 aml_append(else_ctx, aml_return(aml_name("PRTA"))); 1586 aml_append(method, else_ctx); 1587 } 1588 aml_append(pci0_scope, method); 1589 aml_append(sb_scope, pci0_scope); 1590 1591 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 1592 aml_append(field, aml_named_field("PRQA", 8)); 1593 aml_append(field, aml_named_field("PRQB", 8)); 1594 aml_append(field, aml_named_field("PRQC", 8)); 1595 aml_append(field, aml_named_field("PRQD", 8)); 1596 aml_append(field, aml_reserved_field(0x20)); 1597 aml_append(field, aml_named_field("PRQE", 8)); 1598 aml_append(field, aml_named_field("PRQF", 8)); 1599 aml_append(field, aml_named_field("PRQG", 8)); 1600 aml_append(field, aml_named_field("PRQH", 8)); 1601 aml_append(sb_scope, field); 1602 1603 aml_append(sb_scope, build_irq_status_method()); 1604 aml_append(sb_scope, build_iqcr_method(false)); 1605 1606 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"))); 1607 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"))); 1608 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"))); 1609 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"))); 1610 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"))); 1611 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"))); 1612 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"))); 1613 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"))); 1614 1615 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10)); 1616 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11)); 1617 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12)); 1618 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13)); 1619 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14)); 1620 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15)); 1621 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16)); 1622 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17)); 1623 1624 aml_append(table, sb_scope); 1625 } 1626 1627 static void build_q35_isa_bridge(Aml *table) 1628 { 1629 Aml *dev; 1630 Aml *scope; 1631 Aml *field; 1632 1633 scope = aml_scope("_SB.PCI0"); 1634 dev = aml_device("ISA"); 1635 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); 1636 1637 /* ICH9 PCI to ISA irq remapping */ 1638 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, 1639 aml_int(0x60), 0x0C)); 1640 1641 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG, 1642 aml_int(0x80), 0x02)); 1643 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1644 aml_append(field, aml_named_field("COMA", 3)); 1645 aml_append(field, aml_reserved_field(1)); 1646 aml_append(field, aml_named_field("COMB", 3)); 1647 aml_append(field, aml_reserved_field(1)); 1648 aml_append(field, aml_named_field("LPTD", 2)); 1649 aml_append(dev, field); 1650 1651 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG, 1652 aml_int(0x82), 0x02)); 1653 /* enable bits */ 1654 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1655 aml_append(field, aml_named_field("CAEN", 1)); 1656 aml_append(field, aml_named_field("CBEN", 1)); 1657 aml_append(field, aml_named_field("LPEN", 1)); 1658 aml_append(dev, field); 1659 1660 aml_append(scope, dev); 1661 aml_append(table, scope); 1662 } 1663 1664 static void build_piix4_pm(Aml *table) 1665 { 1666 Aml *dev; 1667 Aml *scope; 1668 1669 scope = aml_scope("_SB.PCI0"); 1670 dev = aml_device("PX13"); 1671 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003))); 1672 1673 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG, 1674 aml_int(0x00), 0xff)); 1675 aml_append(scope, dev); 1676 aml_append(table, scope); 1677 } 1678 1679 static void build_piix4_isa_bridge(Aml *table) 1680 { 1681 Aml *dev; 1682 Aml *scope; 1683 Aml *field; 1684 1685 scope = aml_scope("_SB.PCI0"); 1686 dev = aml_device("ISA"); 1687 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000))); 1688 1689 /* PIIX PCI to ISA irq remapping */ 1690 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG, 1691 aml_int(0x60), 0x04)); 1692 /* enable bits */ 1693 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); 1694 /* Offset(0x5f),, 7, */ 1695 aml_append(field, aml_reserved_field(0x2f8)); 1696 aml_append(field, aml_reserved_field(7)); 1697 aml_append(field, aml_named_field("LPEN", 1)); 1698 /* Offset(0x67),, 3, */ 1699 aml_append(field, aml_reserved_field(0x38)); 1700 aml_append(field, aml_reserved_field(3)); 1701 aml_append(field, aml_named_field("CAEN", 1)); 1702 aml_append(field, aml_reserved_field(3)); 1703 aml_append(field, aml_named_field("CBEN", 1)); 1704 aml_append(dev, field); 1705 1706 aml_append(scope, dev); 1707 aml_append(table, scope); 1708 } 1709 1710 static void build_piix4_pci_hotplug(Aml *table) 1711 { 1712 Aml *scope; 1713 Aml *field; 1714 Aml *method; 1715 1716 scope = aml_scope("_SB.PCI0"); 1717 1718 aml_append(scope, 1719 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); 1720 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1721 aml_append(field, aml_named_field("PCIU", 32)); 1722 aml_append(field, aml_named_field("PCID", 32)); 1723 aml_append(scope, field); 1724 1725 aml_append(scope, 1726 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); 1727 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1728 aml_append(field, aml_named_field("B0EJ", 32)); 1729 aml_append(scope, field); 1730 1731 aml_append(scope, 1732 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04)); 1733 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); 1734 aml_append(field, aml_named_field("BNUM", 32)); 1735 aml_append(scope, field); 1736 1737 aml_append(scope, aml_mutex("BLCK", 0)); 1738 1739 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED); 1740 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); 1741 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); 1742 aml_append(method, 1743 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))); 1744 aml_append(method, aml_release(aml_name("BLCK"))); 1745 aml_append(method, aml_return(aml_int(0))); 1746 aml_append(scope, method); 1747 1748 aml_append(table, scope); 1749 } 1750 1751 static Aml *build_q35_osc_method(void) 1752 { 1753 Aml *if_ctx; 1754 Aml *if_ctx2; 1755 Aml *else_ctx; 1756 Aml *method; 1757 Aml *a_cwd1 = aml_name("CDW1"); 1758 Aml *a_ctrl = aml_local(0); 1759 1760 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 1761 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 1762 1763 if_ctx = aml_if(aml_equal( 1764 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); 1765 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 1766 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 1767 1768 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); 1769 1770 /* 1771 * Always allow native PME, AER (no dependencies) 1772 * Allow SHPC (PCI bridges can have SHPC controller) 1773 */ 1774 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); 1775 1776 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); 1777 /* Unknown revision */ 1778 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); 1779 aml_append(if_ctx, if_ctx2); 1780 1781 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); 1782 /* Capabilities bits were masked */ 1783 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); 1784 aml_append(if_ctx, if_ctx2); 1785 1786 /* Update DWORD3 in the buffer */ 1787 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); 1788 aml_append(method, if_ctx); 1789 1790 else_ctx = aml_else(); 1791 /* Unrecognized UUID */ 1792 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); 1793 aml_append(method, else_ctx); 1794 1795 aml_append(method, aml_return(aml_arg(3))); 1796 return method; 1797 } 1798 1799 static void 1800 build_dsdt(GArray *table_data, BIOSLinker *linker, 1801 AcpiPmInfo *pm, AcpiMiscInfo *misc, 1802 Range *pci_hole, Range *pci_hole64, MachineState *machine) 1803 { 1804 CrsRangeEntry *entry; 1805 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; 1806 CrsRangeSet crs_range_set; 1807 PCMachineState *pcms = PC_MACHINE(machine); 1808 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1809 uint32_t nr_mem = machine->ram_slots; 1810 int root_bus_limit = 0xFF; 1811 PCIBus *bus = NULL; 1812 TPMIf *tpm = tpm_find(); 1813 int i; 1814 1815 dsdt = init_aml_allocator(); 1816 1817 /* Reserve space for header */ 1818 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader)); 1819 1820 build_dbg_aml(dsdt); 1821 if (misc->is_piix4) { 1822 sb_scope = aml_scope("_SB"); 1823 dev = aml_device("PCI0"); 1824 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1825 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1826 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1827 aml_append(sb_scope, dev); 1828 aml_append(dsdt, sb_scope); 1829 1830 build_hpet_aml(dsdt); 1831 build_piix4_pm(dsdt); 1832 build_piix4_isa_bridge(dsdt); 1833 build_isa_devices_aml(dsdt); 1834 build_piix4_pci_hotplug(dsdt); 1835 build_piix4_pci0_int(dsdt); 1836 } else { 1837 sb_scope = aml_scope("_SB"); 1838 dev = aml_device("PCI0"); 1839 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); 1840 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); 1841 aml_append(dev, aml_name_decl("_ADR", aml_int(0))); 1842 aml_append(dev, aml_name_decl("_UID", aml_int(1))); 1843 aml_append(dev, build_q35_osc_method()); 1844 aml_append(sb_scope, dev); 1845 aml_append(dsdt, sb_scope); 1846 1847 build_hpet_aml(dsdt); 1848 build_q35_isa_bridge(dsdt); 1849 build_isa_devices_aml(dsdt); 1850 build_q35_pci0_int(dsdt); 1851 } 1852 1853 if (pcmc->legacy_cpu_hotplug) { 1854 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); 1855 } else { 1856 CPUHotplugFeatures opts = { 1857 .acpi_1_compatible = true, .has_legacy_cphp = true 1858 }; 1859 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, 1860 "\\_SB.PCI0", "\\_GPE._E02"); 1861 } 1862 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", "\\_GPE._E03"); 1863 1864 scope = aml_scope("_GPE"); 1865 { 1866 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); 1867 1868 if (misc->is_piix4) { 1869 method = aml_method("_E01", 0, AML_NOTSERIALIZED); 1870 aml_append(method, 1871 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); 1872 aml_append(method, aml_call0("\\_SB.PCI0.PCNT")); 1873 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK"))); 1874 aml_append(scope, method); 1875 } 1876 1877 if (machine->nvdimms_state->is_enabled) { 1878 method = aml_method("_E04", 0, AML_NOTSERIALIZED); 1879 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"), 1880 aml_int(0x80))); 1881 aml_append(scope, method); 1882 } 1883 } 1884 aml_append(dsdt, scope); 1885 1886 crs_range_set_init(&crs_range_set); 1887 bus = PC_MACHINE(machine)->bus; 1888 if (bus) { 1889 QLIST_FOREACH(bus, &bus->child, sibling) { 1890 uint8_t bus_num = pci_bus_num(bus); 1891 uint8_t numa_node = pci_bus_numa_node(bus); 1892 1893 /* look only for expander root buses */ 1894 if (!pci_bus_is_root(bus)) { 1895 continue; 1896 } 1897 1898 if (bus_num < root_bus_limit) { 1899 root_bus_limit = bus_num - 1; 1900 } 1901 1902 scope = aml_scope("\\_SB"); 1903 dev = aml_device("PC%.02X", bus_num); 1904 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); 1905 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); 1906 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 1907 if (pci_bus_is_express(bus)) { 1908 aml_append(dev, build_q35_osc_method()); 1909 } 1910 1911 if (numa_node != NUMA_NODE_UNASSIGNED) { 1912 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 1913 } 1914 1915 aml_append(dev, build_prt(false)); 1916 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); 1917 aml_append(dev, aml_name_decl("_CRS", crs)); 1918 aml_append(scope, dev); 1919 aml_append(dsdt, scope); 1920 } 1921 } 1922 1923 scope = aml_scope("\\_SB.PCI0"); 1924 /* build PCI0._CRS */ 1925 crs = aml_resource_template(); 1926 aml_append(crs, 1927 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 1928 0x0000, 0x0, root_bus_limit, 1929 0x0000, root_bus_limit + 1)); 1930 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08)); 1931 1932 aml_append(crs, 1933 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1934 AML_POS_DECODE, AML_ENTIRE_RANGE, 1935 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); 1936 1937 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); 1938 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 1939 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 1940 aml_append(crs, 1941 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, 1942 AML_POS_DECODE, AML_ENTIRE_RANGE, 1943 0x0000, entry->base, entry->limit, 1944 0x0000, entry->limit - entry->base + 1)); 1945 } 1946 1947 aml_append(crs, 1948 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1949 AML_CACHEABLE, AML_READ_WRITE, 1950 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); 1951 1952 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 1953 range_lob(pci_hole), 1954 range_upb(pci_hole)); 1955 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 1956 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 1957 aml_append(crs, 1958 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 1959 AML_NON_CACHEABLE, AML_READ_WRITE, 1960 0, entry->base, entry->limit, 1961 0, entry->limit - entry->base + 1)); 1962 } 1963 1964 if (!range_is_empty(pci_hole64)) { 1965 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 1966 range_lob(pci_hole64), 1967 range_upb(pci_hole64)); 1968 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 1969 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 1970 aml_append(crs, 1971 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, 1972 AML_MAX_FIXED, 1973 AML_CACHEABLE, AML_READ_WRITE, 1974 0, entry->base, entry->limit, 1975 0, entry->limit - entry->base + 1)); 1976 } 1977 } 1978 1979 if (TPM_IS_TIS(tpm_find())) { 1980 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 1981 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 1982 } 1983 aml_append(scope, aml_name_decl("_CRS", crs)); 1984 1985 /* reserve GPE0 block resources */ 1986 dev = aml_device("GPE0"); 1987 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 1988 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources"))); 1989 /* device present, functioning, decoding, not shown in UI */ 1990 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 1991 crs = aml_resource_template(); 1992 aml_append(crs, 1993 aml_io( 1994 AML_DECODE16, 1995 pm->fadt.gpe0_blk.address, 1996 pm->fadt.gpe0_blk.address, 1997 1, 1998 pm->fadt.gpe0_blk.bit_width / 8) 1999 ); 2000 aml_append(dev, aml_name_decl("_CRS", crs)); 2001 aml_append(scope, dev); 2002 2003 crs_range_set_free(&crs_range_set); 2004 2005 /* reserve PCIHP resources */ 2006 if (pm->pcihp_io_len) { 2007 dev = aml_device("PHPR"); 2008 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); 2009 aml_append(dev, 2010 aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); 2011 /* device present, functioning, decoding, not shown in UI */ 2012 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2013 crs = aml_resource_template(); 2014 aml_append(crs, 2015 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, 2016 pm->pcihp_io_len) 2017 ); 2018 aml_append(dev, aml_name_decl("_CRS", crs)); 2019 aml_append(scope, dev); 2020 } 2021 aml_append(dsdt, scope); 2022 2023 /* create S3_ / S4_ / S5_ packages if necessary */ 2024 scope = aml_scope("\\"); 2025 if (!pm->s3_disabled) { 2026 pkg = aml_package(4); 2027 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */ 2028 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2029 aml_append(pkg, aml_int(0)); /* reserved */ 2030 aml_append(pkg, aml_int(0)); /* reserved */ 2031 aml_append(scope, aml_name_decl("_S3", pkg)); 2032 } 2033 2034 if (!pm->s4_disabled) { 2035 pkg = aml_package(4); 2036 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */ 2037 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */ 2038 aml_append(pkg, aml_int(pm->s4_val)); 2039 aml_append(pkg, aml_int(0)); /* reserved */ 2040 aml_append(pkg, aml_int(0)); /* reserved */ 2041 aml_append(scope, aml_name_decl("_S4", pkg)); 2042 } 2043 2044 pkg = aml_package(4); 2045 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */ 2046 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */ 2047 aml_append(pkg, aml_int(0)); /* reserved */ 2048 aml_append(pkg, aml_int(0)); /* reserved */ 2049 aml_append(scope, aml_name_decl("_S5", pkg)); 2050 aml_append(dsdt, scope); 2051 2052 /* create fw_cfg node, unconditionally */ 2053 { 2054 /* when using port i/o, the 8-bit data register *always* overlaps 2055 * with half of the 16-bit control register. Hence, the total size 2056 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the 2057 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */ 2058 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg), 2059 "dma_enabled", NULL) ? 2060 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) : 2061 FW_CFG_CTL_SIZE; 2062 2063 scope = aml_scope("\\_SB.PCI0"); 2064 dev = aml_device("FWCF"); 2065 2066 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); 2067 2068 /* device present, functioning, decoding, not shown in UI */ 2069 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2070 2071 crs = aml_resource_template(); 2072 aml_append(crs, 2073 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size) 2074 ); 2075 aml_append(dev, aml_name_decl("_CRS", crs)); 2076 2077 aml_append(scope, dev); 2078 aml_append(dsdt, scope); 2079 } 2080 2081 if (misc->applesmc_io_base) { 2082 scope = aml_scope("\\_SB.PCI0.ISA"); 2083 dev = aml_device("SMC"); 2084 2085 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001"))); 2086 /* device present, functioning, decoding, not shown in UI */ 2087 aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); 2088 2089 crs = aml_resource_template(); 2090 aml_append(crs, 2091 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base, 2092 0x01, APPLESMC_MAX_DATA_LENGTH) 2093 ); 2094 aml_append(crs, aml_irq_no_flags(6)); 2095 aml_append(dev, aml_name_decl("_CRS", crs)); 2096 2097 aml_append(scope, dev); 2098 aml_append(dsdt, scope); 2099 } 2100 2101 if (misc->pvpanic_port) { 2102 scope = aml_scope("\\_SB.PCI0.ISA"); 2103 2104 dev = aml_device("PEVT"); 2105 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001"))); 2106 2107 crs = aml_resource_template(); 2108 aml_append(crs, 2109 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1) 2110 ); 2111 aml_append(dev, aml_name_decl("_CRS", crs)); 2112 2113 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO, 2114 aml_int(misc->pvpanic_port), 1)); 2115 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 2116 aml_append(field, aml_named_field("PEPT", 8)); 2117 aml_append(dev, field); 2118 2119 /* device present, functioning, decoding, shown in UI */ 2120 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2121 2122 method = aml_method("RDPT", 0, AML_NOTSERIALIZED); 2123 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0))); 2124 aml_append(method, aml_return(aml_local(0))); 2125 aml_append(dev, method); 2126 2127 method = aml_method("WRPT", 1, AML_NOTSERIALIZED); 2128 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT"))); 2129 aml_append(dev, method); 2130 2131 aml_append(scope, dev); 2132 aml_append(dsdt, scope); 2133 } 2134 2135 sb_scope = aml_scope("\\_SB"); 2136 { 2137 Object *pci_host; 2138 PCIBus *bus = NULL; 2139 2140 pci_host = acpi_get_i386_pci_host(); 2141 if (pci_host) { 2142 bus = PCI_HOST_BRIDGE(pci_host)->bus; 2143 } 2144 2145 if (bus) { 2146 Aml *scope = aml_scope("PCI0"); 2147 /* Scan all PCI buses. Generate tables to support hotplug. */ 2148 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en); 2149 2150 if (TPM_IS_TIS(tpm)) { 2151 if (misc->tpm_version == TPM_VERSION_2_0) { 2152 dev = aml_device("TPM"); 2153 aml_append(dev, aml_name_decl("_HID", 2154 aml_string("MSFT0101"))); 2155 } else { 2156 dev = aml_device("ISA.TPM"); 2157 aml_append(dev, aml_name_decl("_HID", 2158 aml_eisaid("PNP0C31"))); 2159 } 2160 2161 aml_append(dev, aml_name_decl("_STA", aml_int(0xF))); 2162 crs = aml_resource_template(); 2163 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE, 2164 TPM_TIS_ADDR_SIZE, AML_READ_WRITE)); 2165 /* 2166 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs, 2167 Rewrite to take IRQ from TPM device model and 2168 fix default IRQ value there to use some unused IRQ 2169 */ 2170 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */ 2171 aml_append(dev, aml_name_decl("_CRS", crs)); 2172 2173 tpm_build_ppi_acpi(tpm, dev); 2174 2175 aml_append(scope, dev); 2176 } 2177 2178 aml_append(sb_scope, scope); 2179 } 2180 } 2181 2182 if (TPM_IS_CRB(tpm)) { 2183 dev = aml_device("TPM"); 2184 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 2185 crs = aml_resource_template(); 2186 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE, 2187 TPM_CRB_ADDR_SIZE, AML_READ_WRITE)); 2188 aml_append(dev, aml_name_decl("_CRS", crs)); 2189 2190 method = aml_method("_STA", 0, AML_NOTSERIALIZED); 2191 aml_append(method, aml_return(aml_int(0x0f))); 2192 aml_append(dev, method); 2193 2194 tpm_build_ppi_acpi(tpm, dev); 2195 2196 aml_append(sb_scope, dev); 2197 } 2198 2199 aml_append(dsdt, sb_scope); 2200 2201 /* copy AML table into ACPI tables blob and patch header there */ 2202 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 2203 build_header(linker, table_data, 2204 (void *)(table_data->data + table_data->len - dsdt->buf->len), 2205 "DSDT", dsdt->buf->len, 1, NULL, NULL); 2206 free_aml_allocator(); 2207 } 2208 2209 static void 2210 build_hpet(GArray *table_data, BIOSLinker *linker) 2211 { 2212 Acpi20Hpet *hpet; 2213 2214 hpet = acpi_data_push(table_data, sizeof(*hpet)); 2215 /* Note timer_block_id value must be kept in sync with value advertised by 2216 * emulated hpet 2217 */ 2218 hpet->timer_block_id = cpu_to_le32(0x8086a201); 2219 hpet->addr.address = cpu_to_le64(HPET_BASE); 2220 build_header(linker, table_data, 2221 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL); 2222 } 2223 2224 static void 2225 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) 2226 { 2227 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); 2228 unsigned log_addr_size = sizeof(tcpa->log_area_start_address); 2229 unsigned log_addr_offset = 2230 (char *)&tcpa->log_area_start_address - table_data->data; 2231 2232 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); 2233 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 2234 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length)); 2235 2236 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, 2237 false /* high memory */); 2238 2239 /* log area start address to be filled by Guest linker */ 2240 bios_linker_loader_add_pointer(linker, 2241 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size, 2242 ACPI_BUILD_TPMLOG_FILE, 0); 2243 2244 build_header(linker, table_data, 2245 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL); 2246 } 2247 2248 static void 2249 build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) 2250 { 2251 Acpi20TPM2 *tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr); 2252 unsigned log_addr_size = sizeof(tpm2_ptr->log_area_start_address); 2253 unsigned log_addr_offset = 2254 (char *)&tpm2_ptr->log_area_start_address - table_data->data; 2255 2256 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT); 2257 if (TPM_IS_TIS(tpm_find())) { 2258 tpm2_ptr->control_area_address = cpu_to_le64(0); 2259 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO); 2260 } else if (TPM_IS_CRB(tpm_find())) { 2261 tpm2_ptr->control_area_address = cpu_to_le64(TPM_CRB_ADDR_CTRL); 2262 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_CRB); 2263 } else { 2264 g_warn_if_reached(); 2265 } 2266 2267 tpm2_ptr->log_area_minimum_length = 2268 cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); 2269 2270 /* log area start address to be filled by Guest linker */ 2271 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, 2272 log_addr_offset, log_addr_size, 2273 ACPI_BUILD_TPMLOG_FILE, 0); 2274 build_header(linker, table_data, 2275 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL); 2276 } 2277 2278 #define HOLE_640K_START (640 * KiB) 2279 #define HOLE_640K_END (1 * MiB) 2280 2281 static void 2282 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 2283 { 2284 AcpiSystemResourceAffinityTable *srat; 2285 AcpiSratMemoryAffinity *numamem; 2286 2287 int i; 2288 int srat_start, numa_start, slots; 2289 uint64_t mem_len, mem_base, next_base; 2290 MachineClass *mc = MACHINE_GET_CLASS(machine); 2291 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine); 2292 PCMachineState *pcms = PC_MACHINE(machine); 2293 ram_addr_t hotplugabble_address_space_size = 2294 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE, 2295 NULL); 2296 2297 srat_start = table_data->len; 2298 2299 srat = acpi_data_push(table_data, sizeof *srat); 2300 srat->reserved1 = cpu_to_le32(1); 2301 2302 for (i = 0; i < apic_ids->len; i++) { 2303 int node_id = apic_ids->cpus[i].props.node_id; 2304 uint32_t apic_id = apic_ids->cpus[i].arch_id; 2305 2306 if (apic_id < 255) { 2307 AcpiSratProcessorAffinity *core; 2308 2309 core = acpi_data_push(table_data, sizeof *core); 2310 core->type = ACPI_SRAT_PROCESSOR_APIC; 2311 core->length = sizeof(*core); 2312 core->local_apic_id = apic_id; 2313 core->proximity_lo = node_id; 2314 memset(core->proximity_hi, 0, 3); 2315 core->local_sapic_eid = 0; 2316 core->flags = cpu_to_le32(1); 2317 } else { 2318 AcpiSratProcessorX2ApicAffinity *core; 2319 2320 core = acpi_data_push(table_data, sizeof *core); 2321 core->type = ACPI_SRAT_PROCESSOR_x2APIC; 2322 core->length = sizeof(*core); 2323 core->x2apic_id = cpu_to_le32(apic_id); 2324 core->proximity_domain = cpu_to_le32(node_id); 2325 core->flags = cpu_to_le32(1); 2326 } 2327 } 2328 2329 2330 /* the memory map is a bit tricky, it contains at least one hole 2331 * from 640k-1M and possibly another one from 3.5G-4G. 2332 */ 2333 next_base = 0; 2334 numa_start = table_data->len; 2335 2336 for (i = 1; i < pcms->numa_nodes + 1; ++i) { 2337 mem_base = next_base; 2338 mem_len = pcms->node_mem[i - 1]; 2339 next_base = mem_base + mem_len; 2340 2341 /* Cut out the 640K hole */ 2342 if (mem_base <= HOLE_640K_START && 2343 next_base > HOLE_640K_START) { 2344 mem_len -= next_base - HOLE_640K_START; 2345 if (mem_len > 0) { 2346 numamem = acpi_data_push(table_data, sizeof *numamem); 2347 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2348 MEM_AFFINITY_ENABLED); 2349 } 2350 2351 /* Check for the rare case: 640K < RAM < 1M */ 2352 if (next_base <= HOLE_640K_END) { 2353 next_base = HOLE_640K_END; 2354 continue; 2355 } 2356 mem_base = HOLE_640K_END; 2357 mem_len = next_base - HOLE_640K_END; 2358 } 2359 2360 /* Cut out the ACPI_PCI hole */ 2361 if (mem_base <= pcms->below_4g_mem_size && 2362 next_base > pcms->below_4g_mem_size) { 2363 mem_len -= next_base - pcms->below_4g_mem_size; 2364 if (mem_len > 0) { 2365 numamem = acpi_data_push(table_data, sizeof *numamem); 2366 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2367 MEM_AFFINITY_ENABLED); 2368 } 2369 mem_base = 1ULL << 32; 2370 mem_len = next_base - pcms->below_4g_mem_size; 2371 next_base = mem_base + mem_len; 2372 } 2373 2374 if (mem_len > 0) { 2375 numamem = acpi_data_push(table_data, sizeof *numamem); 2376 build_srat_memory(numamem, mem_base, mem_len, i - 1, 2377 MEM_AFFINITY_ENABLED); 2378 } 2379 } 2380 slots = (table_data->len - numa_start) / sizeof *numamem; 2381 for (; slots < pcms->numa_nodes + 2; slots++) { 2382 numamem = acpi_data_push(table_data, sizeof *numamem); 2383 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS); 2384 } 2385 2386 /* 2387 * Entry is required for Windows to enable memory hotplug in OS 2388 * and for Linux to enable SWIOTLB when booted with less than 2389 * 4G of RAM. Windows works better if the entry sets proximity 2390 * to the highest NUMA node in the machine. 2391 * Memory devices may override proximity set by this entry, 2392 * providing _PXM method if necessary. 2393 */ 2394 if (hotplugabble_address_space_size) { 2395 numamem = acpi_data_push(table_data, sizeof *numamem); 2396 build_srat_memory(numamem, machine->device_memory->base, 2397 hotplugabble_address_space_size, pcms->numa_nodes - 1, 2398 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 2399 } 2400 2401 build_header(linker, table_data, 2402 (void *)(table_data->data + srat_start), 2403 "SRAT", 2404 table_data->len - srat_start, 1, NULL, NULL); 2405 } 2406 2407 /* 2408 * VT-d spec 8.1 DMA Remapping Reporting Structure 2409 * (version Oct. 2014 or later) 2410 */ 2411 static void 2412 build_dmar_q35(GArray *table_data, BIOSLinker *linker) 2413 { 2414 int dmar_start = table_data->len; 2415 2416 AcpiTableDmar *dmar; 2417 AcpiDmarHardwareUnit *drhd; 2418 AcpiDmarRootPortATS *atsr; 2419 uint8_t dmar_flags = 0; 2420 X86IOMMUState *iommu = x86_iommu_get_default(); 2421 AcpiDmarDeviceScope *scope = NULL; 2422 /* Root complex IOAPIC use one path[0] only */ 2423 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]); 2424 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2425 2426 assert(iommu); 2427 if (x86_iommu_ir_supported(iommu)) { 2428 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */ 2429 } 2430 2431 dmar = acpi_data_push(table_data, sizeof(*dmar)); 2432 dmar->host_address_width = intel_iommu->aw_bits - 1; 2433 dmar->flags = dmar_flags; 2434 2435 /* DMAR Remapping Hardware Unit Definition structure */ 2436 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size); 2437 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); 2438 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size); 2439 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; 2440 drhd->pci_segment = cpu_to_le16(0); 2441 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); 2442 2443 /* Scope definition for the root-complex IOAPIC. See VT-d spec 2444 * 8.3.1 (version Oct. 2014 or later). */ 2445 scope = &drhd->scope[0]; 2446 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */ 2447 scope->length = ioapic_scope_size; 2448 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID; 2449 scope->bus = Q35_PSEUDO_BUS_PLATFORM; 2450 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC); 2451 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC); 2452 2453 if (iommu->dt_supported) { 2454 atsr = acpi_data_push(table_data, sizeof(*atsr)); 2455 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR); 2456 atsr->length = cpu_to_le16(sizeof(*atsr)); 2457 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS; 2458 atsr->pci_segment = cpu_to_le16(0); 2459 } 2460 2461 build_header(linker, table_data, (void *)(table_data->data + dmar_start), 2462 "DMAR", table_data->len - dmar_start, 1, NULL, NULL); 2463 } 2464 /* 2465 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2 2466 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf 2467 */ 2468 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 2469 2470 static void 2471 build_amd_iommu(GArray *table_data, BIOSLinker *linker) 2472 { 2473 int ivhd_table_len = 28; 2474 int iommu_start = table_data->len; 2475 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default()); 2476 2477 /* IVRS header */ 2478 acpi_data_push(table_data, sizeof(AcpiTableHeader)); 2479 /* IVinfo - IO virtualization information common to all 2480 * IOMMU units in a system 2481 */ 2482 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4); 2483 /* reserved */ 2484 build_append_int_noprefix(table_data, 0, 8); 2485 2486 /* IVHD definition - type 10h */ 2487 build_append_int_noprefix(table_data, 0x10, 1); 2488 /* virtualization flags */ 2489 build_append_int_noprefix(table_data, 2490 (1UL << 0) | /* HtTunEn */ 2491 (1UL << 4) | /* iotblSup */ 2492 (1UL << 6) | /* PrefSup */ 2493 (1UL << 7), /* PPRSup */ 2494 1); 2495 2496 /* 2497 * When interrupt remapping is supported, we add a special IVHD device 2498 * for type IO-APIC. 2499 */ 2500 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2501 ivhd_table_len += 8; 2502 } 2503 /* IVHD length */ 2504 build_append_int_noprefix(table_data, ivhd_table_len, 2); 2505 /* DeviceID */ 2506 build_append_int_noprefix(table_data, s->devid, 2); 2507 /* Capability offset */ 2508 build_append_int_noprefix(table_data, s->capab_offset, 2); 2509 /* IOMMU base address */ 2510 build_append_int_noprefix(table_data, s->mmio.addr, 8); 2511 /* PCI Segment Group */ 2512 build_append_int_noprefix(table_data, 0, 2); 2513 /* IOMMU info */ 2514 build_append_int_noprefix(table_data, 0, 2); 2515 /* IOMMU Feature Reporting */ 2516 build_append_int_noprefix(table_data, 2517 (48UL << 30) | /* HATS */ 2518 (48UL << 28) | /* GATS */ 2519 (1UL << 2) | /* GTSup */ 2520 (1UL << 6), /* GASup */ 2521 4); 2522 /* 2523 * Type 1 device entry reporting all devices 2524 * These are 4-byte device entries currently reporting the range of 2525 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) 2526 */ 2527 build_append_int_noprefix(table_data, 0x0000001, 4); 2528 2529 /* 2530 * Add a special IVHD device type. 2531 * Refer to spec - Table 95: IVHD device entry type codes 2532 * 2533 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC). 2534 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' 2535 */ 2536 if (x86_iommu_ir_supported(x86_iommu_get_default())) { 2537 build_append_int_noprefix(table_data, 2538 (0x1ull << 56) | /* type IOAPIC */ 2539 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */ 2540 0x48, /* special device */ 2541 8); 2542 } 2543 2544 build_header(linker, table_data, (void *)(table_data->data + iommu_start), 2545 "IVRS", table_data->len - iommu_start, 1, NULL, NULL); 2546 } 2547 2548 typedef 2549 struct AcpiBuildState { 2550 /* Copy of table in RAM (for patching). */ 2551 MemoryRegion *table_mr; 2552 /* Is table patched? */ 2553 uint8_t patched; 2554 void *rsdp; 2555 MemoryRegion *rsdp_mr; 2556 MemoryRegion *linker_mr; 2557 } AcpiBuildState; 2558 2559 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg) 2560 { 2561 Object *pci_host; 2562 QObject *o; 2563 2564 pci_host = acpi_get_i386_pci_host(); 2565 g_assert(pci_host); 2566 2567 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL); 2568 if (!o) { 2569 return false; 2570 } 2571 mcfg->base = qnum_get_uint(qobject_to(QNum, o)); 2572 qobject_unref(o); 2573 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) { 2574 return false; 2575 } 2576 2577 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL); 2578 assert(o); 2579 mcfg->size = qnum_get_uint(qobject_to(QNum, o)); 2580 qobject_unref(o); 2581 return true; 2582 } 2583 2584 static 2585 void acpi_build(AcpiBuildTables *tables, MachineState *machine) 2586 { 2587 PCMachineState *pcms = PC_MACHINE(machine); 2588 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2589 GArray *table_offsets; 2590 unsigned facs, dsdt, rsdt, fadt; 2591 AcpiPmInfo pm; 2592 AcpiMiscInfo misc; 2593 AcpiMcfgInfo mcfg; 2594 Range pci_hole, pci_hole64; 2595 uint8_t *u; 2596 size_t aml_len = 0; 2597 GArray *tables_blob = tables->table_data; 2598 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL }; 2599 Object *vmgenid_dev; 2600 2601 acpi_get_pm_info(&pm); 2602 acpi_get_misc_info(&misc); 2603 acpi_get_pci_holes(&pci_hole, &pci_hole64); 2604 acpi_get_slic_oem(&slic_oem); 2605 2606 table_offsets = g_array_new(false, true /* clear */, 2607 sizeof(uint32_t)); 2608 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 2609 2610 bios_linker_loader_alloc(tables->linker, 2611 ACPI_BUILD_TABLE_FILE, tables_blob, 2612 64 /* Ensure FACS is aligned */, 2613 false /* high memory */); 2614 2615 /* 2616 * FACS is pointed to by FADT. 2617 * We place it first since it's the only table that has alignment 2618 * requirements. 2619 */ 2620 facs = tables_blob->len; 2621 build_facs(tables_blob); 2622 2623 /* DSDT is pointed to by FADT */ 2624 dsdt = tables_blob->len; 2625 build_dsdt(tables_blob, tables->linker, &pm, &misc, 2626 &pci_hole, &pci_hole64, machine); 2627 2628 /* Count the size of the DSDT and SSDT, we will need it for legacy 2629 * sizing of ACPI tables. 2630 */ 2631 aml_len += tables_blob->len - dsdt; 2632 2633 /* ACPI tables pointed to by RSDT */ 2634 fadt = tables_blob->len; 2635 acpi_add_table(table_offsets, tables_blob); 2636 pm.fadt.facs_tbl_offset = &facs; 2637 pm.fadt.dsdt_tbl_offset = &dsdt; 2638 pm.fadt.xdsdt_tbl_offset = &dsdt; 2639 build_fadt(tables_blob, tables->linker, &pm.fadt, 2640 slic_oem.id, slic_oem.table_id); 2641 aml_len += tables_blob->len - fadt; 2642 2643 acpi_add_table(table_offsets, tables_blob); 2644 build_madt(tables_blob, tables->linker, pcms); 2645 2646 vmgenid_dev = find_vmgenid_dev(); 2647 if (vmgenid_dev) { 2648 acpi_add_table(table_offsets, tables_blob); 2649 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob, 2650 tables->vmgenid, tables->linker); 2651 } 2652 2653 if (misc.has_hpet) { 2654 acpi_add_table(table_offsets, tables_blob); 2655 build_hpet(tables_blob, tables->linker); 2656 } 2657 if (misc.tpm_version != TPM_VERSION_UNSPEC) { 2658 acpi_add_table(table_offsets, tables_blob); 2659 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog); 2660 2661 if (misc.tpm_version == TPM_VERSION_2_0) { 2662 acpi_add_table(table_offsets, tables_blob); 2663 build_tpm2(tables_blob, tables->linker, tables->tcpalog); 2664 } 2665 } 2666 if (pcms->numa_nodes) { 2667 acpi_add_table(table_offsets, tables_blob); 2668 build_srat(tables_blob, tables->linker, machine); 2669 if (have_numa_distance) { 2670 acpi_add_table(table_offsets, tables_blob); 2671 build_slit(tables_blob, tables->linker); 2672 } 2673 } 2674 if (acpi_get_mcfg(&mcfg)) { 2675 acpi_add_table(table_offsets, tables_blob); 2676 build_mcfg(tables_blob, tables->linker, &mcfg); 2677 } 2678 if (x86_iommu_get_default()) { 2679 IommuType IOMMUType = x86_iommu_get_type(); 2680 if (IOMMUType == TYPE_AMD) { 2681 acpi_add_table(table_offsets, tables_blob); 2682 build_amd_iommu(tables_blob, tables->linker); 2683 } else if (IOMMUType == TYPE_INTEL) { 2684 acpi_add_table(table_offsets, tables_blob); 2685 build_dmar_q35(tables_blob, tables->linker); 2686 } 2687 } 2688 if (machine->nvdimms_state->is_enabled) { 2689 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, 2690 machine->nvdimms_state, machine->ram_slots); 2691 } 2692 2693 /* Add tables supplied by user (if any) */ 2694 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 2695 unsigned len = acpi_table_len(u); 2696 2697 acpi_add_table(table_offsets, tables_blob); 2698 g_array_append_vals(tables_blob, u, len); 2699 } 2700 2701 /* RSDT is pointed to by RSDP */ 2702 rsdt = tables_blob->len; 2703 build_rsdt(tables_blob, tables->linker, table_offsets, 2704 slic_oem.id, slic_oem.table_id); 2705 2706 /* RSDP is in FSEG memory, so allocate it separately */ 2707 { 2708 AcpiRsdpData rsdp_data = { 2709 .revision = 0, 2710 .oem_id = ACPI_BUILD_APPNAME6, 2711 .xsdt_tbl_offset = NULL, 2712 .rsdt_tbl_offset = &rsdt, 2713 }; 2714 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 2715 if (!pcmc->rsdp_in_ram) { 2716 /* We used to allocate some extra space for RSDP revision 2 but 2717 * only used the RSDP revision 0 space. The extra bytes were 2718 * zeroed out and not used. 2719 * Here we continue wasting those extra 16 bytes to make sure we 2720 * don't break migration for machine types 2.2 and older due to 2721 * RSDP blob size mismatch. 2722 */ 2723 build_append_int_noprefix(tables->rsdp, 0, 16); 2724 } 2725 } 2726 2727 /* We'll expose it all to Guest so we want to reduce 2728 * chance of size changes. 2729 * 2730 * We used to align the tables to 4k, but of course this would 2731 * too simple to be enough. 4k turned out to be too small an 2732 * alignment very soon, and in fact it is almost impossible to 2733 * keep the table size stable for all (max_cpus, max_memory_slots) 2734 * combinations. So the table size is always 64k for pc-i440fx-2.1 2735 * and we give an error if the table grows beyond that limit. 2736 * 2737 * We still have the problem of migrating from "-M pc-i440fx-2.0". For 2738 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables 2739 * than 2.0 and we can always pad the smaller tables with zeros. We can 2740 * then use the exact size of the 2.0 tables. 2741 * 2742 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration. 2743 */ 2744 if (pcmc->legacy_acpi_table_size) { 2745 /* Subtracting aml_len gives the size of fixed tables. Then add the 2746 * size of the PIIX4 DSDT/SSDT in QEMU 2.0. 2747 */ 2748 int legacy_aml_len = 2749 pcmc->legacy_acpi_table_size + 2750 ACPI_BUILD_LEGACY_CPU_AML_SIZE * pcms->apic_id_limit; 2751 int legacy_table_size = 2752 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len, 2753 ACPI_BUILD_ALIGN_SIZE); 2754 if (tables_blob->len > legacy_table_size) { 2755 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */ 2756 warn_report("ACPI table size %u exceeds %d bytes," 2757 " migration may not work", 2758 tables_blob->len, legacy_table_size); 2759 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2760 " or PCI bridges."); 2761 } 2762 g_array_set_size(tables_blob, legacy_table_size); 2763 } else { 2764 /* Make sure we have a buffer in case we need to resize the tables. */ 2765 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 2766 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */ 2767 warn_report("ACPI table size %u exceeds %d bytes," 2768 " migration may not work", 2769 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 2770 error_printf("Try removing CPUs, NUMA nodes, memory slots" 2771 " or PCI bridges."); 2772 } 2773 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 2774 } 2775 2776 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 2777 2778 /* Cleanup memory that's no longer used. */ 2779 g_array_free(table_offsets, true); 2780 } 2781 2782 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 2783 { 2784 uint32_t size = acpi_data_len(data); 2785 2786 /* Make sure RAM size is correct - in case it got changed e.g. by migration */ 2787 memory_region_ram_resize(mr, size, &error_abort); 2788 2789 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 2790 memory_region_set_dirty(mr, 0, size); 2791 } 2792 2793 static void acpi_build_update(void *build_opaque) 2794 { 2795 AcpiBuildState *build_state = build_opaque; 2796 AcpiBuildTables tables; 2797 2798 /* No state to update or already patched? Nothing to do. */ 2799 if (!build_state || build_state->patched) { 2800 return; 2801 } 2802 build_state->patched = 1; 2803 2804 acpi_build_tables_init(&tables); 2805 2806 acpi_build(&tables, MACHINE(qdev_get_machine())); 2807 2808 acpi_ram_update(build_state->table_mr, tables.table_data); 2809 2810 if (build_state->rsdp) { 2811 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp)); 2812 } else { 2813 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 2814 } 2815 2816 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 2817 acpi_build_tables_cleanup(&tables, true); 2818 } 2819 2820 static void acpi_build_reset(void *build_opaque) 2821 { 2822 AcpiBuildState *build_state = build_opaque; 2823 build_state->patched = 0; 2824 } 2825 2826 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state, 2827 GArray *blob, const char *name, 2828 uint64_t max_size) 2829 { 2830 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1, 2831 name, acpi_build_update, build_state, NULL, true); 2832 } 2833 2834 static const VMStateDescription vmstate_acpi_build = { 2835 .name = "acpi_build", 2836 .version_id = 1, 2837 .minimum_version_id = 1, 2838 .fields = (VMStateField[]) { 2839 VMSTATE_UINT8(patched, AcpiBuildState), 2840 VMSTATE_END_OF_LIST() 2841 }, 2842 }; 2843 2844 void acpi_setup(void) 2845 { 2846 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 2847 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2848 AcpiBuildTables tables; 2849 AcpiBuildState *build_state; 2850 Object *vmgenid_dev; 2851 TPMIf *tpm; 2852 static FwCfgTPMConfig tpm_config; 2853 2854 if (!pcms->fw_cfg) { 2855 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 2856 return; 2857 } 2858 2859 if (!pcms->acpi_build_enabled) { 2860 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n"); 2861 return; 2862 } 2863 2864 if (!acpi_enabled) { 2865 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 2866 return; 2867 } 2868 2869 build_state = g_malloc0(sizeof *build_state); 2870 2871 acpi_build_tables_init(&tables); 2872 acpi_build(&tables, MACHINE(pcms)); 2873 2874 /* Now expose it all to Guest */ 2875 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data, 2876 ACPI_BUILD_TABLE_FILE, 2877 ACPI_BUILD_TABLE_MAX_SIZE); 2878 assert(build_state->table_mr != NULL); 2879 2880 build_state->linker_mr = 2881 acpi_add_rom_blob(build_state, tables.linker->cmd_blob, 2882 "etc/table-loader", 0); 2883 2884 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, 2885 tables.tcpalog->data, acpi_data_len(tables.tcpalog)); 2886 2887 tpm = tpm_find(); 2888 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) { 2889 tpm_config = (FwCfgTPMConfig) { 2890 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE), 2891 .tpm_version = tpm_get_version(tpm), 2892 .tpmppi_version = TPM_PPI_VERSION_1_30 2893 }; 2894 fw_cfg_add_file(pcms->fw_cfg, "etc/tpm/config", 2895 &tpm_config, sizeof tpm_config); 2896 } 2897 2898 vmgenid_dev = find_vmgenid_dev(); 2899 if (vmgenid_dev) { 2900 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), pcms->fw_cfg, 2901 tables.vmgenid); 2902 } 2903 2904 if (!pcmc->rsdp_in_ram) { 2905 /* 2906 * Keep for compatibility with old machine types. 2907 * Though RSDP is small, its contents isn't immutable, so 2908 * we'll update it along with the rest of tables on guest access. 2909 */ 2910 uint32_t rsdp_size = acpi_data_len(tables.rsdp); 2911 2912 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size); 2913 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE, 2914 acpi_build_update, NULL, build_state, 2915 build_state->rsdp, rsdp_size, true); 2916 build_state->rsdp_mr = NULL; 2917 } else { 2918 build_state->rsdp = NULL; 2919 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp, 2920 ACPI_BUILD_RSDP_FILE, 0); 2921 } 2922 2923 qemu_register_reset(acpi_build_reset, build_state); 2924 acpi_build_reset(build_state); 2925 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 2926 2927 /* Cleanup tables but don't free the memory: we track it 2928 * in build_state. 2929 */ 2930 acpi_build_tables_cleanup(&tables, false); 2931 } 2932