1 /* 2 * QEMU ATI SVGA emulation 3 * 4 * Copyright (c) 2019 BALATON Zoltan 5 * 6 * This work is licensed under the GNU GPL license version 2 or later. 7 */ 8 9 /* 10 * WARNING: 11 * This is very incomplete and only enough for Linux console and some 12 * unaccelerated X output at the moment. 13 * Currently it's little more than a frame buffer with minimal functions, 14 * other more advanced features of the hardware are yet to be implemented. 15 * We only aim for Rage 128 Pro (and some RV100) and 2D only at first, 16 * No 3D at all yet (maybe after 2D works, but feel free to improve it) 17 */ 18 19 #include "qemu/osdep.h" 20 #include "ati_int.h" 21 #include "ati_regs.h" 22 #include "vga-access.h" 23 #include "hw/qdev-properties.h" 24 #include "vga_regs.h" 25 #include "qemu/log.h" 26 #include "qemu/module.h" 27 #include "qemu/error-report.h" 28 #include "qapi/error.h" 29 #include "ui/console.h" 30 #include "hw/display/i2c-ddc.h" 31 #include "trace.h" 32 33 #define ATI_DEBUG_HW_CURSOR 0 34 35 static const struct { 36 const char *name; 37 uint16_t dev_id; 38 } ati_model_aliases[] = { 39 { "rage128p", PCI_DEVICE_ID_ATI_RAGE128_PF }, 40 { "rv100", PCI_DEVICE_ID_ATI_RADEON_QY }, 41 }; 42 43 enum { VGA_MODE, EXT_MODE }; 44 45 static void ati_vga_switch_mode(ATIVGAState *s) 46 { 47 DPRINTF("%d -> %d\n", 48 s->mode, !!(s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN)); 49 if (s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN) { 50 /* Extended mode enabled */ 51 s->mode = EXT_MODE; 52 if (s->regs.crtc_gen_cntl & CRTC2_EN) { 53 /* CRT controller enabled, use CRTC values */ 54 /* FIXME Should these be the same as VGA CRTC regs? */ 55 uint32_t offs = s->regs.crtc_offset & 0x07ffffff; 56 int stride = (s->regs.crtc_pitch & 0x7ff) * 8; 57 int bpp = 0; 58 int h, v; 59 60 if (s->regs.crtc_h_total_disp == 0) { 61 s->regs.crtc_h_total_disp = ((640 / 8) - 1) << 16; 62 } 63 if (s->regs.crtc_v_total_disp == 0) { 64 s->regs.crtc_v_total_disp = (480 - 1) << 16; 65 } 66 h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8; 67 v = (s->regs.crtc_v_total_disp >> 16) + 1; 68 switch (s->regs.crtc_gen_cntl & CRTC_PIX_WIDTH_MASK) { 69 case CRTC_PIX_WIDTH_4BPP: 70 bpp = 4; 71 break; 72 case CRTC_PIX_WIDTH_8BPP: 73 bpp = 8; 74 break; 75 case CRTC_PIX_WIDTH_15BPP: 76 bpp = 15; 77 break; 78 case CRTC_PIX_WIDTH_16BPP: 79 bpp = 16; 80 break; 81 case CRTC_PIX_WIDTH_24BPP: 82 bpp = 24; 83 break; 84 case CRTC_PIX_WIDTH_32BPP: 85 bpp = 32; 86 break; 87 default: 88 qemu_log_mask(LOG_UNIMP, "Unsupported bpp value\n"); 89 return; 90 } 91 DPRINTF("Switching to %dx%d %d %d @ %x\n", h, v, stride, bpp, offs); 92 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE); 93 vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED); 94 s->vga.big_endian_fb = (s->regs.config_cntl & APER_0_ENDIAN || 95 s->regs.config_cntl & APER_1_ENDIAN ? 96 true : false); 97 /* reset VBE regs then set up mode */ 98 s->vga.vbe_regs[VBE_DISPI_INDEX_XRES] = h; 99 s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] = v; 100 s->vga.vbe_regs[VBE_DISPI_INDEX_BPP] = bpp; 101 /* enable mode via ioport so it updates vga regs */ 102 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE); 103 vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_ENABLED | 104 VBE_DISPI_LFB_ENABLED | VBE_DISPI_NOCLEARMEM | 105 (s->regs.dac_cntl & DAC_8BIT_EN ? VBE_DISPI_8BIT_DAC : 0)); 106 /* now set offset and stride after enable as that resets these */ 107 if (stride) { 108 int bypp = DIV_ROUND_UP(bpp, BITS_PER_BYTE); 109 110 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_VIRT_WIDTH); 111 vbe_ioport_write_data(&s->vga, 0, stride); 112 stride *= bypp; 113 if (offs % stride) { 114 DPRINTF("CRTC offset is not multiple of pitch\n"); 115 vbe_ioport_write_index(&s->vga, 0, 116 VBE_DISPI_INDEX_X_OFFSET); 117 vbe_ioport_write_data(&s->vga, 0, offs % stride / bypp); 118 } 119 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_Y_OFFSET); 120 vbe_ioport_write_data(&s->vga, 0, offs / stride); 121 DPRINTF("VBE offset (%d,%d), vbe_start_addr=%x\n", 122 s->vga.vbe_regs[VBE_DISPI_INDEX_X_OFFSET], 123 s->vga.vbe_regs[VBE_DISPI_INDEX_Y_OFFSET], 124 s->vga.vbe_start_addr); 125 } 126 } 127 } else { 128 /* VGA mode enabled */ 129 s->mode = VGA_MODE; 130 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE); 131 vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED); 132 } 133 } 134 135 /* Used by host side hardware cursor */ 136 static void ati_cursor_define(ATIVGAState *s) 137 { 138 uint8_t data[1024]; 139 uint32_t srcoff; 140 int i, j, idx = 0; 141 142 if ((s->regs.cur_offset & BIT(31)) || s->cursor_guest_mode) { 143 return; /* Do not update cursor if locked or rendered by guest */ 144 } 145 /* FIXME handle cur_hv_offs correctly */ 146 srcoff = s->regs.cur_offset - 147 (s->regs.cur_hv_offs >> 16) - (s->regs.cur_hv_offs & 0xffff) * 16; 148 for (i = 0; i < 64; i++) { 149 for (j = 0; j < 8; j++, idx++) { 150 data[idx] = vga_read_byte(&s->vga, srcoff + i * 16 + j); 151 data[512 + idx] = vga_read_byte(&s->vga, srcoff + i * 16 + j + 8); 152 } 153 } 154 if (!s->cursor) { 155 s->cursor = cursor_alloc(64, 64); 156 } 157 cursor_set_mono(s->cursor, s->regs.cur_color1, s->regs.cur_color0, 158 &data[512], 1, &data[0]); 159 dpy_cursor_define(s->vga.con, s->cursor); 160 } 161 162 /* Alternatively support guest rendered hardware cursor */ 163 static void ati_cursor_invalidate(VGACommonState *vga) 164 { 165 ATIVGAState *s = container_of(vga, ATIVGAState, vga); 166 int size = (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) ? 64 : 0; 167 168 if (s->regs.cur_offset & BIT(31)) { 169 return; /* Do not update cursor if locked */ 170 } 171 if (s->cursor_size != size || 172 vga->hw_cursor_x != s->regs.cur_hv_pos >> 16 || 173 vga->hw_cursor_y != (s->regs.cur_hv_pos & 0xffff) || 174 s->cursor_offset != s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) - 175 (s->regs.cur_hv_offs & 0xffff) * 16) { 176 /* Remove old cursor then update and show new one if needed */ 177 vga_invalidate_scanlines(vga, vga->hw_cursor_y, vga->hw_cursor_y + 63); 178 vga->hw_cursor_x = s->regs.cur_hv_pos >> 16; 179 vga->hw_cursor_y = s->regs.cur_hv_pos & 0xffff; 180 s->cursor_offset = s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) - 181 (s->regs.cur_hv_offs & 0xffff) * 16; 182 s->cursor_size = size; 183 if (size) { 184 vga_invalidate_scanlines(vga, 185 vga->hw_cursor_y, vga->hw_cursor_y + 63); 186 } 187 } 188 } 189 190 static void ati_cursor_draw_line(VGACommonState *vga, uint8_t *d, int scr_y) 191 { 192 ATIVGAState *s = container_of(vga, ATIVGAState, vga); 193 uint32_t srcoff; 194 uint32_t *dp = (uint32_t *)d; 195 int i, j, h; 196 197 if (!(s->regs.crtc_gen_cntl & CRTC2_CUR_EN) || 198 scr_y < vga->hw_cursor_y || scr_y >= vga->hw_cursor_y + 64 || 199 scr_y > s->regs.crtc_v_total_disp >> 16) { 200 return; 201 } 202 /* FIXME handle cur_hv_offs correctly */ 203 srcoff = s->cursor_offset + (scr_y - vga->hw_cursor_y) * 16; 204 dp = &dp[vga->hw_cursor_x]; 205 h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8; 206 for (i = 0; i < 8; i++) { 207 uint32_t color; 208 uint8_t abits = vga_read_byte(vga, srcoff + i); 209 uint8_t xbits = vga_read_byte(vga, srcoff + i + 8); 210 for (j = 0; j < 8; j++, abits <<= 1, xbits <<= 1) { 211 if (abits & BIT(7)) { 212 if (xbits & BIT(7)) { 213 color = dp[i * 8 + j] ^ 0xffffffff; /* complement */ 214 } else { 215 continue; /* transparent, no change */ 216 } 217 } else { 218 color = (xbits & BIT(7) ? s->regs.cur_color1 : 219 s->regs.cur_color0) | 0xff000000; 220 } 221 if (vga->hw_cursor_x + i * 8 + j >= h) { 222 return; /* end of screen, don't span to next line */ 223 } 224 dp[i * 8 + j] = color; 225 } 226 } 227 } 228 229 static uint64_t ati_i2c(bitbang_i2c_interface *i2c, uint64_t data, int base) 230 { 231 bool c = (data & BIT(base + 17) ? !!(data & BIT(base + 1)) : 1); 232 bool d = (data & BIT(base + 16) ? !!(data & BIT(base)) : 1); 233 234 bitbang_i2c_set(i2c, BITBANG_I2C_SCL, c); 235 d = bitbang_i2c_set(i2c, BITBANG_I2C_SDA, d); 236 237 data &= ~0xf00ULL; 238 if (c) { 239 data |= BIT(base + 9); 240 } 241 if (d) { 242 data |= BIT(base + 8); 243 } 244 return data; 245 } 246 247 static void ati_vga_update_irq(ATIVGAState *s) 248 { 249 pci_set_irq(&s->dev, !!(s->regs.gen_int_status & s->regs.gen_int_cntl)); 250 } 251 252 static void ati_vga_vblank_irq(void *opaque) 253 { 254 ATIVGAState *s = opaque; 255 256 timer_mod(&s->vblank_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 257 NANOSECONDS_PER_SECOND / 60); 258 s->regs.gen_int_status |= CRTC_VBLANK_INT; 259 ati_vga_update_irq(s); 260 } 261 262 static inline uint64_t ati_reg_read_offs(uint32_t reg, int offs, 263 unsigned int size) 264 { 265 if (offs == 0 && size == 4) { 266 return reg; 267 } else { 268 return extract32(reg, offs * BITS_PER_BYTE, size * BITS_PER_BYTE); 269 } 270 } 271 272 static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size) 273 { 274 ATIVGAState *s = opaque; 275 uint64_t val = 0; 276 277 switch (addr) { 278 case MM_INDEX: 279 val = s->regs.mm_index; 280 break; 281 case MM_DATA ... MM_DATA + 3: 282 /* indexed access to regs or memory */ 283 if (s->regs.mm_index & BIT(31)) { 284 uint32_t idx = s->regs.mm_index & ~BIT(31); 285 if (idx <= s->vga.vram_size - size) { 286 val = ldn_le_p(s->vga.vram_ptr + idx, size); 287 } 288 } else if (s->regs.mm_index > MM_DATA + 3) { 289 val = ati_mm_read(s, s->regs.mm_index + addr - MM_DATA, size); 290 } else { 291 qemu_log_mask(LOG_GUEST_ERROR, 292 "ati_mm_read: mm_index too small: %u\n", s->regs.mm_index); 293 } 294 break; 295 case BIOS_0_SCRATCH ... BUS_CNTL - 1: 296 { 297 int i = (addr - BIOS_0_SCRATCH) / 4; 298 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) { 299 break; 300 } 301 val = ati_reg_read_offs(s->regs.bios_scratch[i], 302 addr - (BIOS_0_SCRATCH + i * 4), size); 303 break; 304 } 305 case GEN_INT_CNTL: 306 val = s->regs.gen_int_cntl; 307 break; 308 case GEN_INT_STATUS: 309 val = s->regs.gen_int_status; 310 break; 311 case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3: 312 val = ati_reg_read_offs(s->regs.crtc_gen_cntl, 313 addr - CRTC_GEN_CNTL, size); 314 break; 315 case CRTC_EXT_CNTL ... CRTC_EXT_CNTL + 3: 316 val = ati_reg_read_offs(s->regs.crtc_ext_cntl, 317 addr - CRTC_EXT_CNTL, size); 318 break; 319 case DAC_CNTL: 320 val = s->regs.dac_cntl; 321 break; 322 case GPIO_VGA_DDC: 323 val = s->regs.gpio_vga_ddc; 324 break; 325 case GPIO_DVI_DDC: 326 val = s->regs.gpio_dvi_ddc; 327 break; 328 case GPIO_MONID ... GPIO_MONID + 3: 329 val = ati_reg_read_offs(s->regs.gpio_monid, 330 addr - GPIO_MONID, size); 331 break; 332 case PALETTE_INDEX: 333 /* FIXME unaligned access */ 334 val = vga_ioport_read(&s->vga, VGA_PEL_IR) << 16; 335 val |= vga_ioport_read(&s->vga, VGA_PEL_IW) & 0xff; 336 break; 337 case PALETTE_DATA: 338 val = vga_ioport_read(&s->vga, VGA_PEL_D); 339 break; 340 case CNFG_CNTL: 341 val = s->regs.config_cntl; 342 break; 343 case CNFG_MEMSIZE: 344 val = s->vga.vram_size; 345 break; 346 case CONFIG_APER_0_BASE: 347 case CONFIG_APER_1_BASE: 348 val = pci_default_read_config(&s->dev, 349 PCI_BASE_ADDRESS_0, size) & 0xfffffff0; 350 break; 351 case CONFIG_APER_SIZE: 352 val = s->vga.vram_size / 2; 353 break; 354 case CONFIG_REG_1_BASE: 355 val = pci_default_read_config(&s->dev, 356 PCI_BASE_ADDRESS_2, size) & 0xfffffff0; 357 break; 358 case CONFIG_REG_APER_SIZE: 359 val = memory_region_size(&s->mm) / 2; 360 break; 361 case HOST_PATH_CNTL: 362 val = BIT(23); /* Radeon HDP_APER_CNTL */ 363 break; 364 case MC_STATUS: 365 val = 5; 366 break; 367 case MEM_SDRAM_MODE_REG: 368 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { 369 val = BIT(28) | BIT(20); 370 } 371 break; 372 case RBBM_STATUS: 373 case GUI_STAT: 374 val = 64; /* free CMDFIFO entries */ 375 break; 376 case CRTC_H_TOTAL_DISP: 377 val = s->regs.crtc_h_total_disp; 378 break; 379 case CRTC_H_SYNC_STRT_WID: 380 val = s->regs.crtc_h_sync_strt_wid; 381 break; 382 case CRTC_V_TOTAL_DISP: 383 val = s->regs.crtc_v_total_disp; 384 break; 385 case CRTC_V_SYNC_STRT_WID: 386 val = s->regs.crtc_v_sync_strt_wid; 387 break; 388 case CRTC_OFFSET: 389 val = s->regs.crtc_offset; 390 break; 391 case CRTC_OFFSET_CNTL: 392 val = s->regs.crtc_offset_cntl; 393 break; 394 case CRTC_PITCH: 395 val = s->regs.crtc_pitch; 396 break; 397 case 0xf00 ... 0xfff: 398 val = pci_default_read_config(&s->dev, addr - 0xf00, size); 399 break; 400 case CUR_OFFSET ... CUR_OFFSET + 3: 401 val = ati_reg_read_offs(s->regs.cur_offset, addr - CUR_OFFSET, size); 402 break; 403 case CUR_HORZ_VERT_POSN ... CUR_HORZ_VERT_POSN + 3: 404 val = ati_reg_read_offs(s->regs.cur_hv_pos, 405 addr - CUR_HORZ_VERT_POSN, size); 406 if (addr + size > CUR_HORZ_VERT_POSN + 3) { 407 val |= (s->regs.cur_offset & BIT(31)) >> (4 - size); 408 } 409 break; 410 case CUR_HORZ_VERT_OFF ... CUR_HORZ_VERT_OFF + 3: 411 val = ati_reg_read_offs(s->regs.cur_hv_offs, 412 addr - CUR_HORZ_VERT_OFF, size); 413 if (addr + size > CUR_HORZ_VERT_OFF + 3) { 414 val |= (s->regs.cur_offset & BIT(31)) >> (4 - size); 415 } 416 break; 417 case CUR_CLR0 ... CUR_CLR0 + 3: 418 val = ati_reg_read_offs(s->regs.cur_color0, addr - CUR_CLR0, size); 419 break; 420 case CUR_CLR1 ... CUR_CLR1 + 3: 421 val = ati_reg_read_offs(s->regs.cur_color1, addr - CUR_CLR1, size); 422 break; 423 case DST_OFFSET: 424 val = s->regs.dst_offset; 425 break; 426 case DST_PITCH: 427 val = s->regs.dst_pitch; 428 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 429 val &= s->regs.dst_tile << 16; 430 } 431 break; 432 case DST_WIDTH: 433 val = s->regs.dst_width; 434 break; 435 case DST_HEIGHT: 436 val = s->regs.dst_height; 437 break; 438 case SRC_X: 439 val = s->regs.src_x; 440 break; 441 case SRC_Y: 442 val = s->regs.src_y; 443 break; 444 case DST_X: 445 val = s->regs.dst_x; 446 break; 447 case DST_Y: 448 val = s->regs.dst_y; 449 break; 450 case DP_GUI_MASTER_CNTL: 451 val = s->regs.dp_gui_master_cntl; 452 break; 453 case SRC_OFFSET: 454 val = s->regs.src_offset; 455 break; 456 case SRC_PITCH: 457 val = s->regs.src_pitch; 458 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 459 val &= s->regs.src_tile << 16; 460 } 461 break; 462 case DP_BRUSH_BKGD_CLR: 463 val = s->regs.dp_brush_bkgd_clr; 464 break; 465 case DP_BRUSH_FRGD_CLR: 466 val = s->regs.dp_brush_frgd_clr; 467 break; 468 case DP_SRC_FRGD_CLR: 469 val = s->regs.dp_src_frgd_clr; 470 break; 471 case DP_SRC_BKGD_CLR: 472 val = s->regs.dp_src_bkgd_clr; 473 break; 474 case DP_CNTL: 475 val = s->regs.dp_cntl; 476 break; 477 case DP_DATATYPE: 478 val = s->regs.dp_datatype; 479 break; 480 case DP_MIX: 481 val = s->regs.dp_mix; 482 break; 483 case DP_WRITE_MASK: 484 val = s->regs.dp_write_mask; 485 break; 486 case DEFAULT_OFFSET: 487 val = s->regs.default_offset; 488 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { 489 val >>= 10; 490 val |= s->regs.default_pitch << 16; 491 val |= s->regs.default_tile << 30; 492 } 493 break; 494 case DEFAULT_PITCH: 495 val = s->regs.default_pitch; 496 val |= s->regs.default_tile << 16; 497 break; 498 case DEFAULT_SC_BOTTOM_RIGHT: 499 val = s->regs.default_sc_bottom_right; 500 break; 501 default: 502 break; 503 } 504 if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) { 505 trace_ati_mm_read(size, addr, ati_reg_name(addr & ~3ULL), val); 506 } 507 return val; 508 } 509 510 static inline void ati_reg_write_offs(uint32_t *reg, int offs, 511 uint64_t data, unsigned int size) 512 { 513 if (offs == 0 && size == 4) { 514 *reg = data; 515 } else { 516 *reg = deposit32(*reg, offs * BITS_PER_BYTE, size * BITS_PER_BYTE, 517 data); 518 } 519 } 520 521 static void ati_mm_write(void *opaque, hwaddr addr, 522 uint64_t data, unsigned int size) 523 { 524 ATIVGAState *s = opaque; 525 526 if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) { 527 trace_ati_mm_write(size, addr, ati_reg_name(addr & ~3ULL), data); 528 } 529 switch (addr) { 530 case MM_INDEX: 531 s->regs.mm_index = data & ~3; 532 break; 533 case MM_DATA ... MM_DATA + 3: 534 /* indexed access to regs or memory */ 535 if (s->regs.mm_index & BIT(31)) { 536 uint32_t idx = s->regs.mm_index & ~BIT(31); 537 if (idx <= s->vga.vram_size - size) { 538 stn_le_p(s->vga.vram_ptr + idx, size, data); 539 } 540 } else if (s->regs.mm_index > MM_DATA + 3) { 541 ati_mm_write(s, s->regs.mm_index + addr - MM_DATA, data, size); 542 } else { 543 qemu_log_mask(LOG_GUEST_ERROR, 544 "ati_mm_write: mm_index too small: %u\n", s->regs.mm_index); 545 } 546 break; 547 case BIOS_0_SCRATCH ... BUS_CNTL - 1: 548 { 549 int i = (addr - BIOS_0_SCRATCH) / 4; 550 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) { 551 break; 552 } 553 ati_reg_write_offs(&s->regs.bios_scratch[i], 554 addr - (BIOS_0_SCRATCH + i * 4), data, size); 555 break; 556 } 557 case GEN_INT_CNTL: 558 s->regs.gen_int_cntl = data; 559 if (data & CRTC_VBLANK_INT) { 560 ati_vga_vblank_irq(s); 561 } else { 562 timer_del(&s->vblank_timer); 563 ati_vga_update_irq(s); 564 } 565 break; 566 case GEN_INT_STATUS: 567 data &= (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF ? 568 0x000f040fUL : 0xfc080effUL); 569 s->regs.gen_int_status &= ~data; 570 ati_vga_update_irq(s); 571 break; 572 case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3: 573 { 574 uint32_t val = s->regs.crtc_gen_cntl; 575 ati_reg_write_offs(&s->regs.crtc_gen_cntl, 576 addr - CRTC_GEN_CNTL, data, size); 577 if ((val & CRTC2_CUR_EN) != (s->regs.crtc_gen_cntl & CRTC2_CUR_EN)) { 578 if (s->cursor_guest_mode) { 579 s->vga.force_shadow = !!(s->regs.crtc_gen_cntl & CRTC2_CUR_EN); 580 } else { 581 if (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) { 582 ati_cursor_define(s); 583 } 584 dpy_mouse_set(s->vga.con, s->regs.cur_hv_pos >> 16, 585 s->regs.cur_hv_pos & 0xffff, 586 (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) != 0); 587 } 588 } 589 if ((val & (CRTC2_EXT_DISP_EN | CRTC2_EN)) != 590 (s->regs.crtc_gen_cntl & (CRTC2_EXT_DISP_EN | CRTC2_EN))) { 591 ati_vga_switch_mode(s); 592 } 593 break; 594 } 595 case CRTC_EXT_CNTL ... CRTC_EXT_CNTL + 3: 596 { 597 uint32_t val = s->regs.crtc_ext_cntl; 598 ati_reg_write_offs(&s->regs.crtc_ext_cntl, 599 addr - CRTC_EXT_CNTL, data, size); 600 if (s->regs.crtc_ext_cntl & CRT_CRTC_DISPLAY_DIS) { 601 DPRINTF("Display disabled\n"); 602 s->vga.ar_index &= ~BIT(5); 603 } else { 604 DPRINTF("Display enabled\n"); 605 s->vga.ar_index |= BIT(5); 606 ati_vga_switch_mode(s); 607 } 608 if ((val & CRT_CRTC_DISPLAY_DIS) != 609 (s->regs.crtc_ext_cntl & CRT_CRTC_DISPLAY_DIS)) { 610 ati_vga_switch_mode(s); 611 } 612 break; 613 } 614 case DAC_CNTL: 615 s->regs.dac_cntl = data & 0xffffe3ff; 616 s->vga.dac_8bit = !!(data & DAC_8BIT_EN); 617 break; 618 case GPIO_VGA_DDC: 619 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { 620 /* FIXME: Maybe add a property to select VGA or DVI port? */ 621 } 622 break; 623 case GPIO_DVI_DDC: 624 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { 625 s->regs.gpio_dvi_ddc = ati_i2c(&s->bbi2c, data, 0); 626 } 627 break; 628 case GPIO_MONID ... GPIO_MONID + 3: 629 /* FIXME What does Radeon have here? */ 630 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 631 ati_reg_write_offs(&s->regs.gpio_monid, 632 addr - GPIO_MONID, data, size); 633 /* 634 * Rage128p accesses DDC used to get EDID via these bits. 635 * Because some drivers access this via multiple byte writes 636 * we have to be careful when we send bits to avoid spurious 637 * changes in bitbang_i2c state. So only do it when mask is set 638 * and either the enable bits are changed or output bits changed 639 * while enabled. 640 */ 641 if ((s->regs.gpio_monid & BIT(25)) && 642 ((addr <= GPIO_MONID + 2 && addr + size > GPIO_MONID + 2) || 643 (addr == GPIO_MONID && (s->regs.gpio_monid & 0x60000)))) { 644 s->regs.gpio_monid = ati_i2c(&s->bbi2c, s->regs.gpio_monid, 1); 645 } 646 } 647 break; 648 case PALETTE_INDEX ... PALETTE_INDEX + 3: 649 if (size == 4) { 650 vga_ioport_write(&s->vga, VGA_PEL_IR, (data >> 16) & 0xff); 651 vga_ioport_write(&s->vga, VGA_PEL_IW, data & 0xff); 652 } else { 653 if (addr == PALETTE_INDEX) { 654 vga_ioport_write(&s->vga, VGA_PEL_IW, data & 0xff); 655 } else { 656 vga_ioport_write(&s->vga, VGA_PEL_IR, data & 0xff); 657 } 658 } 659 break; 660 case PALETTE_DATA ... PALETTE_DATA + 3: 661 data <<= addr - PALETTE_DATA; 662 data = bswap32(data) >> 8; 663 vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff); 664 data >>= 8; 665 vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff); 666 data >>= 8; 667 vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff); 668 break; 669 case CNFG_CNTL: 670 s->regs.config_cntl = data; 671 break; 672 case CRTC_H_TOTAL_DISP: 673 s->regs.crtc_h_total_disp = data & 0x07ff07ff; 674 break; 675 case CRTC_H_SYNC_STRT_WID: 676 s->regs.crtc_h_sync_strt_wid = data & 0x17bf1fff; 677 break; 678 case CRTC_V_TOTAL_DISP: 679 s->regs.crtc_v_total_disp = data & 0x0fff0fff; 680 break; 681 case CRTC_V_SYNC_STRT_WID: 682 s->regs.crtc_v_sync_strt_wid = data & 0x9f0fff; 683 break; 684 case CRTC_OFFSET: 685 s->regs.crtc_offset = data & 0xc7ffffff; 686 break; 687 case CRTC_OFFSET_CNTL: 688 s->regs.crtc_offset_cntl = data; /* FIXME */ 689 break; 690 case CRTC_PITCH: 691 s->regs.crtc_pitch = data & 0x07ff07ff; 692 break; 693 case 0xf00 ... 0xfff: 694 /* read-only copy of PCI config space so ignore writes */ 695 break; 696 case CUR_OFFSET ... CUR_OFFSET + 3: 697 { 698 uint32_t t = s->regs.cur_offset; 699 700 ati_reg_write_offs(&t, addr - CUR_OFFSET, data, size); 701 t &= 0x87fffff0; 702 if (s->regs.cur_offset != t) { 703 s->regs.cur_offset = t; 704 ati_cursor_define(s); 705 } 706 break; 707 } 708 case CUR_HORZ_VERT_POSN ... CUR_HORZ_VERT_POSN + 3: 709 { 710 uint32_t t = s->regs.cur_hv_pos | (s->regs.cur_offset & BIT(31)); 711 712 ati_reg_write_offs(&t, addr - CUR_HORZ_VERT_POSN, data, size); 713 s->regs.cur_hv_pos = t & 0x3fff0fff; 714 if (t & BIT(31)) { 715 s->regs.cur_offset |= t & BIT(31); 716 } else if (s->regs.cur_offset & BIT(31)) { 717 s->regs.cur_offset &= ~BIT(31); 718 ati_cursor_define(s); 719 } 720 if (!s->cursor_guest_mode && 721 (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) && !(t & BIT(31))) { 722 dpy_mouse_set(s->vga.con, s->regs.cur_hv_pos >> 16, 723 s->regs.cur_hv_pos & 0xffff, 1); 724 } 725 break; 726 } 727 case CUR_HORZ_VERT_OFF: 728 { 729 uint32_t t = s->regs.cur_hv_offs | (s->regs.cur_offset & BIT(31)); 730 731 ati_reg_write_offs(&t, addr - CUR_HORZ_VERT_OFF, data, size); 732 s->regs.cur_hv_offs = t & 0x3f003f; 733 if (t & BIT(31)) { 734 s->regs.cur_offset |= t & BIT(31); 735 } else if (s->regs.cur_offset & BIT(31)) { 736 s->regs.cur_offset &= ~BIT(31); 737 ati_cursor_define(s); 738 } 739 break; 740 } 741 case CUR_CLR0 ... CUR_CLR0 + 3: 742 { 743 uint32_t t = s->regs.cur_color0; 744 745 ati_reg_write_offs(&t, addr - CUR_CLR0, data, size); 746 t &= 0xffffff; 747 if (s->regs.cur_color0 != t) { 748 s->regs.cur_color0 = t; 749 ati_cursor_define(s); 750 } 751 break; 752 } 753 case CUR_CLR1 ... CUR_CLR1 + 3: 754 /* 755 * Update cursor unconditionally here because some clients set up 756 * other registers before actually writing cursor data to memory at 757 * offset so we would miss cursor change unless always updating here 758 */ 759 ati_reg_write_offs(&s->regs.cur_color1, addr - CUR_CLR1, data, size); 760 s->regs.cur_color1 &= 0xffffff; 761 ati_cursor_define(s); 762 break; 763 case DST_OFFSET: 764 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 765 s->regs.dst_offset = data & 0xfffffff0; 766 } else { 767 s->regs.dst_offset = data & 0xfffffc00; 768 } 769 break; 770 case DST_PITCH: 771 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 772 s->regs.dst_pitch = data & 0x3fff; 773 s->regs.dst_tile = (data >> 16) & 1; 774 } else { 775 s->regs.dst_pitch = data & 0x3ff0; 776 } 777 break; 778 case DST_TILE: 779 if (s->dev_id == PCI_DEVICE_ID_ATI_RADEON_QY) { 780 s->regs.dst_tile = data & 3; 781 } 782 break; 783 case DST_WIDTH: 784 s->regs.dst_width = data & 0x3fff; 785 ati_2d_blt(s); 786 break; 787 case DST_HEIGHT: 788 s->regs.dst_height = data & 0x3fff; 789 break; 790 case SRC_X: 791 s->regs.src_x = data & 0x3fff; 792 break; 793 case SRC_Y: 794 s->regs.src_y = data & 0x3fff; 795 break; 796 case DST_X: 797 s->regs.dst_x = data & 0x3fff; 798 break; 799 case DST_Y: 800 s->regs.dst_y = data & 0x3fff; 801 break; 802 case SRC_PITCH_OFFSET: 803 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 804 s->regs.src_offset = (data & 0x1fffff) << 5; 805 s->regs.src_pitch = (data & 0x7fe00000) >> 21; 806 s->regs.src_tile = data >> 31; 807 } else { 808 s->regs.src_offset = (data & 0x3fffff) << 10; 809 s->regs.src_pitch = (data & 0x3fc00000) >> 16; 810 s->regs.src_tile = (data >> 30) & 1; 811 } 812 break; 813 case DST_PITCH_OFFSET: 814 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 815 s->regs.dst_offset = (data & 0x1fffff) << 5; 816 s->regs.dst_pitch = (data & 0x7fe00000) >> 21; 817 s->regs.dst_tile = data >> 31; 818 } else { 819 s->regs.dst_offset = (data & 0x3fffff) << 10; 820 s->regs.dst_pitch = (data & 0x3fc00000) >> 16; 821 s->regs.dst_tile = data >> 30; 822 } 823 break; 824 case SRC_Y_X: 825 s->regs.src_x = data & 0x3fff; 826 s->regs.src_y = (data >> 16) & 0x3fff; 827 break; 828 case DST_Y_X: 829 s->regs.dst_x = data & 0x3fff; 830 s->regs.dst_y = (data >> 16) & 0x3fff; 831 break; 832 case DST_HEIGHT_WIDTH: 833 s->regs.dst_width = data & 0x3fff; 834 s->regs.dst_height = (data >> 16) & 0x3fff; 835 ati_2d_blt(s); 836 break; 837 case DP_GUI_MASTER_CNTL: 838 s->regs.dp_gui_master_cntl = data & 0xf800000f; 839 s->regs.dp_datatype = (data & 0x0f00) >> 8 | (data & 0x30f0) << 4 | 840 (data & 0x4000) << 16; 841 s->regs.dp_mix = (data & GMC_ROP3_MASK) | (data & 0x7000000) >> 16; 842 break; 843 case DST_WIDTH_X: 844 s->regs.dst_x = data & 0x3fff; 845 s->regs.dst_width = (data >> 16) & 0x3fff; 846 ati_2d_blt(s); 847 break; 848 case SRC_X_Y: 849 s->regs.src_y = data & 0x3fff; 850 s->regs.src_x = (data >> 16) & 0x3fff; 851 break; 852 case DST_X_Y: 853 s->regs.dst_y = data & 0x3fff; 854 s->regs.dst_x = (data >> 16) & 0x3fff; 855 break; 856 case DST_WIDTH_HEIGHT: 857 s->regs.dst_height = data & 0x3fff; 858 s->regs.dst_width = (data >> 16) & 0x3fff; 859 ati_2d_blt(s); 860 break; 861 case DST_HEIGHT_Y: 862 s->regs.dst_y = data & 0x3fff; 863 s->regs.dst_height = (data >> 16) & 0x3fff; 864 break; 865 case SRC_OFFSET: 866 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 867 s->regs.src_offset = data & 0xfffffff0; 868 } else { 869 s->regs.src_offset = data & 0xfffffc00; 870 } 871 break; 872 case SRC_PITCH: 873 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 874 s->regs.src_pitch = data & 0x3fff; 875 s->regs.src_tile = (data >> 16) & 1; 876 } else { 877 s->regs.src_pitch = data & 0x3ff0; 878 } 879 break; 880 case DP_BRUSH_BKGD_CLR: 881 s->regs.dp_brush_bkgd_clr = data; 882 break; 883 case DP_BRUSH_FRGD_CLR: 884 s->regs.dp_brush_frgd_clr = data; 885 break; 886 case DP_CNTL: 887 s->regs.dp_cntl = data; 888 break; 889 case DP_DATATYPE: 890 s->regs.dp_datatype = data & 0xe0070f0f; 891 break; 892 case DP_MIX: 893 s->regs.dp_mix = data & 0x00ff0700; 894 break; 895 case DP_WRITE_MASK: 896 s->regs.dp_write_mask = data; 897 break; 898 case DEFAULT_OFFSET: 899 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 900 s->regs.default_offset = data & 0xfffffff0; 901 } else { 902 /* Radeon has DEFAULT_PITCH_OFFSET here like DST_PITCH_OFFSET */ 903 s->regs.default_offset = (data & 0x3fffff) << 10; 904 s->regs.default_pitch = (data & 0x3fc00000) >> 16; 905 s->regs.default_tile = data >> 30; 906 } 907 break; 908 case DEFAULT_PITCH: 909 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 910 s->regs.default_pitch = data & 0x3fff; 911 s->regs.default_tile = (data >> 16) & 1; 912 } 913 break; 914 case DEFAULT_SC_BOTTOM_RIGHT: 915 s->regs.default_sc_bottom_right = data & 0x3fff3fff; 916 break; 917 default: 918 break; 919 } 920 } 921 922 static const MemoryRegionOps ati_mm_ops = { 923 .read = ati_mm_read, 924 .write = ati_mm_write, 925 .endianness = DEVICE_LITTLE_ENDIAN, 926 }; 927 928 static void ati_vga_realize(PCIDevice *dev, Error **errp) 929 { 930 ATIVGAState *s = ATI_VGA(dev); 931 VGACommonState *vga = &s->vga; 932 933 if (s->model) { 934 int i; 935 for (i = 0; i < ARRAY_SIZE(ati_model_aliases); i++) { 936 if (!strcmp(s->model, ati_model_aliases[i].name)) { 937 s->dev_id = ati_model_aliases[i].dev_id; 938 break; 939 } 940 } 941 if (i >= ARRAY_SIZE(ati_model_aliases)) { 942 warn_report("Unknown ATI VGA model name, " 943 "using default rage128p"); 944 } 945 } 946 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF && 947 s->dev_id != PCI_DEVICE_ID_ATI_RADEON_QY) { 948 error_setg(errp, "Unknown ATI VGA device id, " 949 "only 0x5046 and 0x5159 are supported"); 950 return; 951 } 952 pci_set_word(dev->config + PCI_DEVICE_ID, s->dev_id); 953 954 if (s->dev_id == PCI_DEVICE_ID_ATI_RADEON_QY && 955 s->vga.vram_size_mb < 16) { 956 warn_report("Too small video memory for device id"); 957 s->vga.vram_size_mb = 16; 958 } 959 960 /* init vga bits */ 961 if (!vga_common_init(vga, OBJECT(s), errp)) { 962 return; 963 } 964 vga_init(vga, OBJECT(s), pci_address_space(dev), 965 pci_address_space_io(dev), true); 966 vga->con = graphic_console_init(DEVICE(s), 0, s->vga.hw_ops, &s->vga); 967 if (s->cursor_guest_mode) { 968 vga->cursor_invalidate = ati_cursor_invalidate; 969 vga->cursor_draw_line = ati_cursor_draw_line; 970 } 971 972 /* ddc, edid */ 973 I2CBus *i2cbus = i2c_init_bus(DEVICE(s), "ati-vga.ddc"); 974 bitbang_i2c_init(&s->bbi2c, i2cbus); 975 I2CSlave *i2cddc = I2C_SLAVE(qdev_new(TYPE_I2CDDC)); 976 i2c_slave_set_address(i2cddc, 0x50); 977 qdev_realize_and_unref(DEVICE(i2cddc), BUS(i2cbus), &error_abort); 978 979 /* mmio register space */ 980 memory_region_init_io(&s->mm, OBJECT(s), &ati_mm_ops, s, 981 "ati.mmregs", 0x4000); 982 /* io space is alias to beginning of mmregs */ 983 memory_region_init_alias(&s->io, OBJECT(s), "ati.io", &s->mm, 0, 0x100); 984 985 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram); 986 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io); 987 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mm); 988 989 /* most interrupts are not yet emulated but MacOS needs at least VBlank */ 990 dev->config[PCI_INTERRUPT_PIN] = 1; 991 timer_init_ns(&s->vblank_timer, QEMU_CLOCK_VIRTUAL, ati_vga_vblank_irq, s); 992 } 993 994 static void ati_vga_reset(DeviceState *dev) 995 { 996 ATIVGAState *s = ATI_VGA(dev); 997 998 timer_del(&s->vblank_timer); 999 ati_vga_update_irq(s); 1000 1001 /* reset vga */ 1002 vga_common_reset(&s->vga); 1003 s->mode = VGA_MODE; 1004 } 1005 1006 static void ati_vga_exit(PCIDevice *dev) 1007 { 1008 ATIVGAState *s = ATI_VGA(dev); 1009 1010 timer_del(&s->vblank_timer); 1011 graphic_console_close(s->vga.con); 1012 } 1013 1014 static Property ati_vga_properties[] = { 1015 DEFINE_PROP_UINT32("vgamem_mb", ATIVGAState, vga.vram_size_mb, 16), 1016 DEFINE_PROP_STRING("model", ATIVGAState, model), 1017 DEFINE_PROP_UINT16("x-device-id", ATIVGAState, dev_id, 1018 PCI_DEVICE_ID_ATI_RAGE128_PF), 1019 DEFINE_PROP_BOOL("guest_hwcursor", ATIVGAState, cursor_guest_mode, false), 1020 DEFINE_PROP_END_OF_LIST() 1021 }; 1022 1023 static void ati_vga_class_init(ObjectClass *klass, void *data) 1024 { 1025 DeviceClass *dc = DEVICE_CLASS(klass); 1026 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1027 1028 dc->reset = ati_vga_reset; 1029 device_class_set_props(dc, ati_vga_properties); 1030 dc->hotpluggable = false; 1031 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 1032 1033 k->class_id = PCI_CLASS_DISPLAY_VGA; 1034 k->vendor_id = PCI_VENDOR_ID_ATI; 1035 k->device_id = PCI_DEVICE_ID_ATI_RAGE128_PF; 1036 k->romfile = "vgabios-ati.bin"; 1037 k->realize = ati_vga_realize; 1038 k->exit = ati_vga_exit; 1039 } 1040 1041 static const TypeInfo ati_vga_info = { 1042 .name = TYPE_ATI_VGA, 1043 .parent = TYPE_PCI_DEVICE, 1044 .instance_size = sizeof(ATIVGAState), 1045 .class_init = ati_vga_class_init, 1046 .interfaces = (InterfaceInfo[]) { 1047 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1048 { }, 1049 }, 1050 }; 1051 1052 static void ati_vga_register_types(void) 1053 { 1054 type_register_static(&ati_vga_info); 1055 } 1056 1057 type_init(ati_vga_register_types) 1058