1 /* 2 * QEMU ATI SVGA emulation 3 * 4 * Copyright (c) 2019 BALATON Zoltan 5 * 6 * This work is licensed under the GNU GPL license version 2 or later. 7 */ 8 9 /* 10 * WARNING: 11 * This is very incomplete and only enough for Linux console and some 12 * unaccelerated X output at the moment. 13 * Currently it's little more than a frame buffer with minimal functions, 14 * other more advanced features of the hardware are yet to be implemented. 15 * We only aim for Rage 128 Pro (and some RV100) and 2D only at first, 16 * No 3D at all yet (maybe after 2D works, but feel free to improve it) 17 */ 18 19 #include "qemu/osdep.h" 20 #include "ati_int.h" 21 #include "ati_regs.h" 22 #include "vga-access.h" 23 #include "hw/qdev-properties.h" 24 #include "vga_regs.h" 25 #include "qemu/log.h" 26 #include "qemu/module.h" 27 #include "qemu/error-report.h" 28 #include "qapi/error.h" 29 #include "ui/console.h" 30 #include "hw/display/i2c-ddc.h" 31 #include "trace.h" 32 33 #define ATI_DEBUG_HW_CURSOR 0 34 35 static const struct { 36 const char *name; 37 uint16_t dev_id; 38 } ati_model_aliases[] = { 39 { "rage128p", PCI_DEVICE_ID_ATI_RAGE128_PF }, 40 { "rv100", PCI_DEVICE_ID_ATI_RADEON_QY }, 41 }; 42 43 enum { VGA_MODE, EXT_MODE }; 44 45 static void ati_vga_switch_mode(ATIVGAState *s) 46 { 47 DPRINTF("%d -> %d\n", 48 s->mode, !!(s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN)); 49 if (s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN) { 50 /* Extended mode enabled */ 51 s->mode = EXT_MODE; 52 if (s->regs.crtc_gen_cntl & CRTC2_EN) { 53 /* CRT controller enabled, use CRTC values */ 54 /* FIXME Should these be the same as VGA CRTC regs? */ 55 uint32_t offs = s->regs.crtc_offset & 0x07ffffff; 56 int stride = (s->regs.crtc_pitch & 0x7ff) * 8; 57 int bpp = 0; 58 int h, v; 59 60 if (s->regs.crtc_h_total_disp == 0) { 61 s->regs.crtc_h_total_disp = ((640 / 8) - 1) << 16; 62 } 63 if (s->regs.crtc_v_total_disp == 0) { 64 s->regs.crtc_v_total_disp = (480 - 1) << 16; 65 } 66 h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8; 67 v = (s->regs.crtc_v_total_disp >> 16) + 1; 68 switch (s->regs.crtc_gen_cntl & CRTC_PIX_WIDTH_MASK) { 69 case CRTC_PIX_WIDTH_4BPP: 70 bpp = 4; 71 break; 72 case CRTC_PIX_WIDTH_8BPP: 73 bpp = 8; 74 break; 75 case CRTC_PIX_WIDTH_15BPP: 76 bpp = 15; 77 break; 78 case CRTC_PIX_WIDTH_16BPP: 79 bpp = 16; 80 break; 81 case CRTC_PIX_WIDTH_24BPP: 82 bpp = 24; 83 break; 84 case CRTC_PIX_WIDTH_32BPP: 85 bpp = 32; 86 break; 87 default: 88 qemu_log_mask(LOG_UNIMP, "Unsupported bpp value\n"); 89 return; 90 } 91 DPRINTF("Switching to %dx%d %d %d @ %x\n", h, v, stride, bpp, offs); 92 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE); 93 vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED); 94 s->vga.big_endian_fb = (s->regs.config_cntl & APER_0_ENDIAN || 95 s->regs.config_cntl & APER_1_ENDIAN ? 96 true : false); 97 /* reset VBE regs then set up mode */ 98 s->vga.vbe_regs[VBE_DISPI_INDEX_XRES] = h; 99 s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] = v; 100 s->vga.vbe_regs[VBE_DISPI_INDEX_BPP] = bpp; 101 /* enable mode via ioport so it updates vga regs */ 102 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE); 103 vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_ENABLED | 104 VBE_DISPI_LFB_ENABLED | VBE_DISPI_NOCLEARMEM | 105 (s->regs.dac_cntl & DAC_8BIT_EN ? VBE_DISPI_8BIT_DAC : 0)); 106 /* now set offset and stride after enable as that resets these */ 107 if (stride) { 108 int bypp = DIV_ROUND_UP(bpp, BITS_PER_BYTE); 109 110 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_VIRT_WIDTH); 111 vbe_ioport_write_data(&s->vga, 0, stride); 112 stride *= bypp; 113 if (offs % stride) { 114 DPRINTF("CRTC offset is not multiple of pitch\n"); 115 vbe_ioport_write_index(&s->vga, 0, 116 VBE_DISPI_INDEX_X_OFFSET); 117 vbe_ioport_write_data(&s->vga, 0, offs % stride / bypp); 118 } 119 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_Y_OFFSET); 120 vbe_ioport_write_data(&s->vga, 0, offs / stride); 121 DPRINTF("VBE offset (%d,%d), vbe_start_addr=%x\n", 122 s->vga.vbe_regs[VBE_DISPI_INDEX_X_OFFSET], 123 s->vga.vbe_regs[VBE_DISPI_INDEX_Y_OFFSET], 124 s->vga.vbe_start_addr); 125 } 126 } 127 } else { 128 /* VGA mode enabled */ 129 s->mode = VGA_MODE; 130 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE); 131 vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED); 132 } 133 } 134 135 /* Used by host side hardware cursor */ 136 static void ati_cursor_define(ATIVGAState *s) 137 { 138 uint8_t data[1024]; 139 uint32_t srcoff; 140 int i, j, idx = 0; 141 142 if ((s->regs.cur_offset & BIT(31)) || s->cursor_guest_mode) { 143 return; /* Do not update cursor if locked or rendered by guest */ 144 } 145 /* FIXME handle cur_hv_offs correctly */ 146 srcoff = s->regs.cur_offset - 147 (s->regs.cur_hv_offs >> 16) - (s->regs.cur_hv_offs & 0xffff) * 16; 148 for (i = 0; i < 64; i++) { 149 for (j = 0; j < 8; j++, idx++) { 150 data[idx] = vga_read_byte(&s->vga, srcoff + i * 16 + j); 151 data[512 + idx] = vga_read_byte(&s->vga, srcoff + i * 16 + j + 8); 152 } 153 } 154 if (!s->cursor) { 155 s->cursor = cursor_alloc(64, 64); 156 } 157 cursor_set_mono(s->cursor, s->regs.cur_color1, s->regs.cur_color0, 158 &data[512], 1, &data[0]); 159 dpy_cursor_define(s->vga.con, s->cursor); 160 } 161 162 /* Alternatively support guest rendered hardware cursor */ 163 static void ati_cursor_invalidate(VGACommonState *vga) 164 { 165 ATIVGAState *s = container_of(vga, ATIVGAState, vga); 166 int size = (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) ? 64 : 0; 167 168 if (s->regs.cur_offset & BIT(31)) { 169 return; /* Do not update cursor if locked */ 170 } 171 if (s->cursor_size != size || 172 vga->hw_cursor_x != s->regs.cur_hv_pos >> 16 || 173 vga->hw_cursor_y != (s->regs.cur_hv_pos & 0xffff) || 174 s->cursor_offset != s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) - 175 (s->regs.cur_hv_offs & 0xffff) * 16) { 176 /* Remove old cursor then update and show new one if needed */ 177 vga_invalidate_scanlines(vga, vga->hw_cursor_y, vga->hw_cursor_y + 63); 178 vga->hw_cursor_x = s->regs.cur_hv_pos >> 16; 179 vga->hw_cursor_y = s->regs.cur_hv_pos & 0xffff; 180 s->cursor_offset = s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) - 181 (s->regs.cur_hv_offs & 0xffff) * 16; 182 s->cursor_size = size; 183 if (size) { 184 vga_invalidate_scanlines(vga, 185 vga->hw_cursor_y, vga->hw_cursor_y + 63); 186 } 187 } 188 } 189 190 static void ati_cursor_draw_line(VGACommonState *vga, uint8_t *d, int scr_y) 191 { 192 ATIVGAState *s = container_of(vga, ATIVGAState, vga); 193 uint32_t srcoff; 194 uint32_t *dp = (uint32_t *)d; 195 int i, j, h; 196 197 if (!(s->regs.crtc_gen_cntl & CRTC2_CUR_EN) || 198 scr_y < vga->hw_cursor_y || scr_y >= vga->hw_cursor_y + 64 || 199 scr_y > s->regs.crtc_v_total_disp >> 16) { 200 return; 201 } 202 /* FIXME handle cur_hv_offs correctly */ 203 srcoff = s->cursor_offset + (scr_y - vga->hw_cursor_y) * 16; 204 dp = &dp[vga->hw_cursor_x]; 205 h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8; 206 for (i = 0; i < 8; i++) { 207 uint32_t color; 208 uint8_t abits = vga_read_byte(vga, srcoff + i); 209 uint8_t xbits = vga_read_byte(vga, srcoff + i + 8); 210 for (j = 0; j < 8; j++, abits <<= 1, xbits <<= 1) { 211 if (abits & BIT(7)) { 212 if (xbits & BIT(7)) { 213 color = dp[i * 8 + j] ^ 0xffffffff; /* complement */ 214 } else { 215 continue; /* transparent, no change */ 216 } 217 } else { 218 color = (xbits & BIT(7) ? s->regs.cur_color1 : 219 s->regs.cur_color0) | 0xff000000; 220 } 221 if (vga->hw_cursor_x + i * 8 + j >= h) { 222 return; /* end of screen, don't span to next line */ 223 } 224 dp[i * 8 + j] = color; 225 } 226 } 227 } 228 229 static uint64_t ati_i2c(bitbang_i2c_interface *i2c, uint64_t data, int base) 230 { 231 bool c = (data & BIT(base + 17) ? !!(data & BIT(base + 1)) : 1); 232 bool d = (data & BIT(base + 16) ? !!(data & BIT(base)) : 1); 233 234 bitbang_i2c_set(i2c, BITBANG_I2C_SCL, c); 235 d = bitbang_i2c_set(i2c, BITBANG_I2C_SDA, d); 236 237 data &= ~0xf00ULL; 238 if (c) { 239 data |= BIT(base + 9); 240 } 241 if (d) { 242 data |= BIT(base + 8); 243 } 244 return data; 245 } 246 247 static void ati_vga_update_irq(ATIVGAState *s) 248 { 249 pci_set_irq(&s->dev, !!(s->regs.gen_int_status & s->regs.gen_int_cntl)); 250 } 251 252 static void ati_vga_vblank_irq(void *opaque) 253 { 254 ATIVGAState *s = opaque; 255 256 timer_mod(&s->vblank_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 257 NANOSECONDS_PER_SECOND / 60); 258 s->regs.gen_int_status |= CRTC_VBLANK_INT; 259 ati_vga_update_irq(s); 260 } 261 262 static inline uint64_t ati_reg_read_offs(uint32_t reg, int offs, 263 unsigned int size) 264 { 265 if (offs == 0 && size == 4) { 266 return reg; 267 } else { 268 return extract32(reg, offs * BITS_PER_BYTE, size * BITS_PER_BYTE); 269 } 270 } 271 272 static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size) 273 { 274 ATIVGAState *s = opaque; 275 uint64_t val = 0; 276 277 switch (addr) { 278 case MM_INDEX: 279 val = s->regs.mm_index; 280 break; 281 case MM_DATA ... MM_DATA + 3: 282 /* indexed access to regs or memory */ 283 if (s->regs.mm_index & BIT(31)) { 284 uint32_t idx = s->regs.mm_index & ~BIT(31); 285 if (idx <= s->vga.vram_size - size) { 286 val = ldn_le_p(s->vga.vram_ptr + idx, size); 287 } 288 } else if (s->regs.mm_index > MM_DATA + 3) { 289 val = ati_mm_read(s, s->regs.mm_index + addr - MM_DATA, size); 290 } else { 291 qemu_log_mask(LOG_GUEST_ERROR, 292 "ati_mm_read: mm_index too small: %u\n", s->regs.mm_index); 293 } 294 break; 295 case BIOS_0_SCRATCH ... BUS_CNTL - 1: 296 { 297 int i = (addr - BIOS_0_SCRATCH) / 4; 298 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) { 299 break; 300 } 301 val = ati_reg_read_offs(s->regs.bios_scratch[i], 302 addr - (BIOS_0_SCRATCH + i * 4), size); 303 break; 304 } 305 case GEN_INT_CNTL: 306 val = s->regs.gen_int_cntl; 307 break; 308 case GEN_INT_STATUS: 309 val = s->regs.gen_int_status; 310 break; 311 case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3: 312 val = ati_reg_read_offs(s->regs.crtc_gen_cntl, 313 addr - CRTC_GEN_CNTL, size); 314 break; 315 case CRTC_EXT_CNTL ... CRTC_EXT_CNTL + 3: 316 val = ati_reg_read_offs(s->regs.crtc_ext_cntl, 317 addr - CRTC_EXT_CNTL, size); 318 break; 319 case DAC_CNTL: 320 val = s->regs.dac_cntl; 321 break; 322 case GPIO_VGA_DDC ... GPIO_VGA_DDC + 3: 323 val = ati_reg_read_offs(s->regs.gpio_vga_ddc, 324 addr - GPIO_VGA_DDC, size); 325 break; 326 case GPIO_DVI_DDC ... GPIO_DVI_DDC + 3: 327 val = ati_reg_read_offs(s->regs.gpio_dvi_ddc, 328 addr - GPIO_DVI_DDC, size); 329 break; 330 case GPIO_MONID ... GPIO_MONID + 3: 331 val = ati_reg_read_offs(s->regs.gpio_monid, 332 addr - GPIO_MONID, size); 333 break; 334 case PALETTE_INDEX: 335 /* FIXME unaligned access */ 336 val = vga_ioport_read(&s->vga, VGA_PEL_IR) << 16; 337 val |= vga_ioport_read(&s->vga, VGA_PEL_IW) & 0xff; 338 break; 339 case PALETTE_DATA: 340 val = vga_ioport_read(&s->vga, VGA_PEL_D); 341 break; 342 case CNFG_CNTL: 343 val = s->regs.config_cntl; 344 break; 345 case CNFG_MEMSIZE: 346 val = s->vga.vram_size; 347 break; 348 case CONFIG_APER_0_BASE: 349 case CONFIG_APER_1_BASE: 350 val = pci_default_read_config(&s->dev, 351 PCI_BASE_ADDRESS_0, size) & 0xfffffff0; 352 break; 353 case CONFIG_APER_SIZE: 354 val = s->vga.vram_size / 2; 355 break; 356 case CONFIG_REG_1_BASE: 357 val = pci_default_read_config(&s->dev, 358 PCI_BASE_ADDRESS_2, size) & 0xfffffff0; 359 break; 360 case CONFIG_REG_APER_SIZE: 361 val = memory_region_size(&s->mm) / 2; 362 break; 363 case HOST_PATH_CNTL: 364 val = BIT(23); /* Radeon HDP_APER_CNTL */ 365 break; 366 case MC_STATUS: 367 val = 5; 368 break; 369 case MEM_SDRAM_MODE_REG: 370 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { 371 val = BIT(28) | BIT(20); 372 } 373 break; 374 case RBBM_STATUS: 375 case GUI_STAT: 376 val = 64; /* free CMDFIFO entries */ 377 break; 378 case CRTC_H_TOTAL_DISP: 379 val = s->regs.crtc_h_total_disp; 380 break; 381 case CRTC_H_SYNC_STRT_WID: 382 val = s->regs.crtc_h_sync_strt_wid; 383 break; 384 case CRTC_V_TOTAL_DISP: 385 val = s->regs.crtc_v_total_disp; 386 break; 387 case CRTC_V_SYNC_STRT_WID: 388 val = s->regs.crtc_v_sync_strt_wid; 389 break; 390 case CRTC_OFFSET: 391 val = s->regs.crtc_offset; 392 break; 393 case CRTC_OFFSET_CNTL: 394 val = s->regs.crtc_offset_cntl; 395 break; 396 case CRTC_PITCH: 397 val = s->regs.crtc_pitch; 398 break; 399 case 0xf00 ... 0xfff: 400 val = pci_default_read_config(&s->dev, addr - 0xf00, size); 401 break; 402 case CUR_OFFSET ... CUR_OFFSET + 3: 403 val = ati_reg_read_offs(s->regs.cur_offset, addr - CUR_OFFSET, size); 404 break; 405 case CUR_HORZ_VERT_POSN ... CUR_HORZ_VERT_POSN + 3: 406 val = ati_reg_read_offs(s->regs.cur_hv_pos, 407 addr - CUR_HORZ_VERT_POSN, size); 408 if (addr + size > CUR_HORZ_VERT_POSN + 3) { 409 val |= (s->regs.cur_offset & BIT(31)) >> (4 - size); 410 } 411 break; 412 case CUR_HORZ_VERT_OFF ... CUR_HORZ_VERT_OFF + 3: 413 val = ati_reg_read_offs(s->regs.cur_hv_offs, 414 addr - CUR_HORZ_VERT_OFF, size); 415 if (addr + size > CUR_HORZ_VERT_OFF + 3) { 416 val |= (s->regs.cur_offset & BIT(31)) >> (4 - size); 417 } 418 break; 419 case CUR_CLR0 ... CUR_CLR0 + 3: 420 val = ati_reg_read_offs(s->regs.cur_color0, addr - CUR_CLR0, size); 421 break; 422 case CUR_CLR1 ... CUR_CLR1 + 3: 423 val = ati_reg_read_offs(s->regs.cur_color1, addr - CUR_CLR1, size); 424 break; 425 case DST_OFFSET: 426 val = s->regs.dst_offset; 427 break; 428 case DST_PITCH: 429 val = s->regs.dst_pitch; 430 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 431 val &= s->regs.dst_tile << 16; 432 } 433 break; 434 case DST_WIDTH: 435 val = s->regs.dst_width; 436 break; 437 case DST_HEIGHT: 438 val = s->regs.dst_height; 439 break; 440 case SRC_X: 441 val = s->regs.src_x; 442 break; 443 case SRC_Y: 444 val = s->regs.src_y; 445 break; 446 case DST_X: 447 val = s->regs.dst_x; 448 break; 449 case DST_Y: 450 val = s->regs.dst_y; 451 break; 452 case DP_GUI_MASTER_CNTL: 453 val = s->regs.dp_gui_master_cntl; 454 break; 455 case SRC_OFFSET: 456 val = s->regs.src_offset; 457 break; 458 case SRC_PITCH: 459 val = s->regs.src_pitch; 460 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 461 val &= s->regs.src_tile << 16; 462 } 463 break; 464 case DP_BRUSH_BKGD_CLR: 465 val = s->regs.dp_brush_bkgd_clr; 466 break; 467 case DP_BRUSH_FRGD_CLR: 468 val = s->regs.dp_brush_frgd_clr; 469 break; 470 case DP_SRC_FRGD_CLR: 471 val = s->regs.dp_src_frgd_clr; 472 break; 473 case DP_SRC_BKGD_CLR: 474 val = s->regs.dp_src_bkgd_clr; 475 break; 476 case DP_CNTL: 477 val = s->regs.dp_cntl; 478 break; 479 case DP_DATATYPE: 480 val = s->regs.dp_datatype; 481 break; 482 case DP_MIX: 483 val = s->regs.dp_mix; 484 break; 485 case DP_WRITE_MASK: 486 val = s->regs.dp_write_mask; 487 break; 488 case DEFAULT_OFFSET: 489 val = s->regs.default_offset; 490 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { 491 val >>= 10; 492 val |= s->regs.default_pitch << 16; 493 val |= s->regs.default_tile << 30; 494 } 495 break; 496 case DEFAULT_PITCH: 497 val = s->regs.default_pitch; 498 val |= s->regs.default_tile << 16; 499 break; 500 case DEFAULT_SC_BOTTOM_RIGHT: 501 val = s->regs.default_sc_bottom_right; 502 break; 503 default: 504 break; 505 } 506 if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) { 507 trace_ati_mm_read(size, addr, ati_reg_name(addr & ~3ULL), val); 508 } 509 return val; 510 } 511 512 static inline void ati_reg_write_offs(uint32_t *reg, int offs, 513 uint64_t data, unsigned int size) 514 { 515 if (offs == 0 && size == 4) { 516 *reg = data; 517 } else { 518 *reg = deposit32(*reg, offs * BITS_PER_BYTE, size * BITS_PER_BYTE, 519 data); 520 } 521 } 522 523 static void ati_mm_write(void *opaque, hwaddr addr, 524 uint64_t data, unsigned int size) 525 { 526 ATIVGAState *s = opaque; 527 528 if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) { 529 trace_ati_mm_write(size, addr, ati_reg_name(addr & ~3ULL), data); 530 } 531 switch (addr) { 532 case MM_INDEX: 533 s->regs.mm_index = data & ~3; 534 break; 535 case MM_DATA ... MM_DATA + 3: 536 /* indexed access to regs or memory */ 537 if (s->regs.mm_index & BIT(31)) { 538 uint32_t idx = s->regs.mm_index & ~BIT(31); 539 if (idx <= s->vga.vram_size - size) { 540 stn_le_p(s->vga.vram_ptr + idx, size, data); 541 } 542 } else if (s->regs.mm_index > MM_DATA + 3) { 543 ati_mm_write(s, s->regs.mm_index + addr - MM_DATA, data, size); 544 } else { 545 qemu_log_mask(LOG_GUEST_ERROR, 546 "ati_mm_write: mm_index too small: %u\n", s->regs.mm_index); 547 } 548 break; 549 case BIOS_0_SCRATCH ... BUS_CNTL - 1: 550 { 551 int i = (addr - BIOS_0_SCRATCH) / 4; 552 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) { 553 break; 554 } 555 ati_reg_write_offs(&s->regs.bios_scratch[i], 556 addr - (BIOS_0_SCRATCH + i * 4), data, size); 557 break; 558 } 559 case GEN_INT_CNTL: 560 s->regs.gen_int_cntl = data; 561 if (data & CRTC_VBLANK_INT) { 562 ati_vga_vblank_irq(s); 563 } else { 564 timer_del(&s->vblank_timer); 565 ati_vga_update_irq(s); 566 } 567 break; 568 case GEN_INT_STATUS: 569 data &= (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF ? 570 0x000f040fUL : 0xfc080effUL); 571 s->regs.gen_int_status &= ~data; 572 ati_vga_update_irq(s); 573 break; 574 case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3: 575 { 576 uint32_t val = s->regs.crtc_gen_cntl; 577 ati_reg_write_offs(&s->regs.crtc_gen_cntl, 578 addr - CRTC_GEN_CNTL, data, size); 579 if ((val & CRTC2_CUR_EN) != (s->regs.crtc_gen_cntl & CRTC2_CUR_EN)) { 580 if (s->cursor_guest_mode) { 581 s->vga.force_shadow = !!(s->regs.crtc_gen_cntl & CRTC2_CUR_EN); 582 } else { 583 if (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) { 584 ati_cursor_define(s); 585 } 586 dpy_mouse_set(s->vga.con, s->regs.cur_hv_pos >> 16, 587 s->regs.cur_hv_pos & 0xffff, 588 (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) != 0); 589 } 590 } 591 if ((val & (CRTC2_EXT_DISP_EN | CRTC2_EN)) != 592 (s->regs.crtc_gen_cntl & (CRTC2_EXT_DISP_EN | CRTC2_EN))) { 593 ati_vga_switch_mode(s); 594 } 595 break; 596 } 597 case CRTC_EXT_CNTL ... CRTC_EXT_CNTL + 3: 598 { 599 uint32_t val = s->regs.crtc_ext_cntl; 600 ati_reg_write_offs(&s->regs.crtc_ext_cntl, 601 addr - CRTC_EXT_CNTL, data, size); 602 if (s->regs.crtc_ext_cntl & CRT_CRTC_DISPLAY_DIS) { 603 DPRINTF("Display disabled\n"); 604 s->vga.ar_index &= ~BIT(5); 605 } else { 606 DPRINTF("Display enabled\n"); 607 s->vga.ar_index |= BIT(5); 608 ati_vga_switch_mode(s); 609 } 610 if ((val & CRT_CRTC_DISPLAY_DIS) != 611 (s->regs.crtc_ext_cntl & CRT_CRTC_DISPLAY_DIS)) { 612 ati_vga_switch_mode(s); 613 } 614 break; 615 } 616 case DAC_CNTL: 617 s->regs.dac_cntl = data & 0xffffe3ff; 618 s->vga.dac_8bit = !!(data & DAC_8BIT_EN); 619 break; 620 /* 621 * GPIO regs for DDC access. Because some drivers access these via 622 * multiple byte writes we have to be careful when we send bits to 623 * avoid spurious changes in bitbang_i2c state. Only do it when either 624 * the enable bits are changed or output bits changed while enabled. 625 */ 626 case GPIO_VGA_DDC ... GPIO_VGA_DDC + 3: 627 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { 628 /* FIXME: Maybe add a property to select VGA or DVI port? */ 629 } 630 break; 631 case GPIO_DVI_DDC ... GPIO_DVI_DDC + 3: 632 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { 633 ati_reg_write_offs(&s->regs.gpio_dvi_ddc, 634 addr - GPIO_DVI_DDC, data, size); 635 if ((addr <= GPIO_DVI_DDC + 2 && addr + size > GPIO_DVI_DDC + 2) || 636 (addr == GPIO_DVI_DDC && (s->regs.gpio_dvi_ddc & 0x30000))) { 637 s->regs.gpio_dvi_ddc = ati_i2c(&s->bbi2c, 638 s->regs.gpio_dvi_ddc, 0); 639 } 640 } 641 break; 642 case GPIO_MONID ... GPIO_MONID + 3: 643 /* FIXME What does Radeon have here? */ 644 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 645 /* Rage128p accesses DDC via MONID(1-2) with additional mask bit */ 646 ati_reg_write_offs(&s->regs.gpio_monid, 647 addr - GPIO_MONID, data, size); 648 if ((s->regs.gpio_monid & BIT(25)) && 649 ((addr <= GPIO_MONID + 2 && addr + size > GPIO_MONID + 2) || 650 (addr == GPIO_MONID && (s->regs.gpio_monid & 0x60000)))) { 651 s->regs.gpio_monid = ati_i2c(&s->bbi2c, s->regs.gpio_monid, 1); 652 } 653 } 654 break; 655 case PALETTE_INDEX ... PALETTE_INDEX + 3: 656 if (size == 4) { 657 vga_ioport_write(&s->vga, VGA_PEL_IR, (data >> 16) & 0xff); 658 vga_ioport_write(&s->vga, VGA_PEL_IW, data & 0xff); 659 } else { 660 if (addr == PALETTE_INDEX) { 661 vga_ioport_write(&s->vga, VGA_PEL_IW, data & 0xff); 662 } else { 663 vga_ioport_write(&s->vga, VGA_PEL_IR, data & 0xff); 664 } 665 } 666 break; 667 case PALETTE_DATA ... PALETTE_DATA + 3: 668 data <<= addr - PALETTE_DATA; 669 data = bswap32(data) >> 8; 670 vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff); 671 data >>= 8; 672 vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff); 673 data >>= 8; 674 vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff); 675 break; 676 case CNFG_CNTL: 677 s->regs.config_cntl = data; 678 break; 679 case CRTC_H_TOTAL_DISP: 680 s->regs.crtc_h_total_disp = data & 0x07ff07ff; 681 break; 682 case CRTC_H_SYNC_STRT_WID: 683 s->regs.crtc_h_sync_strt_wid = data & 0x17bf1fff; 684 break; 685 case CRTC_V_TOTAL_DISP: 686 s->regs.crtc_v_total_disp = data & 0x0fff0fff; 687 break; 688 case CRTC_V_SYNC_STRT_WID: 689 s->regs.crtc_v_sync_strt_wid = data & 0x9f0fff; 690 break; 691 case CRTC_OFFSET: 692 s->regs.crtc_offset = data & 0xc7ffffff; 693 break; 694 case CRTC_OFFSET_CNTL: 695 s->regs.crtc_offset_cntl = data; /* FIXME */ 696 break; 697 case CRTC_PITCH: 698 s->regs.crtc_pitch = data & 0x07ff07ff; 699 break; 700 case 0xf00 ... 0xfff: 701 /* read-only copy of PCI config space so ignore writes */ 702 break; 703 case CUR_OFFSET ... CUR_OFFSET + 3: 704 { 705 uint32_t t = s->regs.cur_offset; 706 707 ati_reg_write_offs(&t, addr - CUR_OFFSET, data, size); 708 t &= 0x87fffff0; 709 if (s->regs.cur_offset != t) { 710 s->regs.cur_offset = t; 711 ati_cursor_define(s); 712 } 713 break; 714 } 715 case CUR_HORZ_VERT_POSN ... CUR_HORZ_VERT_POSN + 3: 716 { 717 uint32_t t = s->regs.cur_hv_pos | (s->regs.cur_offset & BIT(31)); 718 719 ati_reg_write_offs(&t, addr - CUR_HORZ_VERT_POSN, data, size); 720 s->regs.cur_hv_pos = t & 0x3fff0fff; 721 if (t & BIT(31)) { 722 s->regs.cur_offset |= t & BIT(31); 723 } else if (s->regs.cur_offset & BIT(31)) { 724 s->regs.cur_offset &= ~BIT(31); 725 ati_cursor_define(s); 726 } 727 if (!s->cursor_guest_mode && 728 (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) && !(t & BIT(31))) { 729 dpy_mouse_set(s->vga.con, s->regs.cur_hv_pos >> 16, 730 s->regs.cur_hv_pos & 0xffff, 1); 731 } 732 break; 733 } 734 case CUR_HORZ_VERT_OFF: 735 { 736 uint32_t t = s->regs.cur_hv_offs | (s->regs.cur_offset & BIT(31)); 737 738 ati_reg_write_offs(&t, addr - CUR_HORZ_VERT_OFF, data, size); 739 s->regs.cur_hv_offs = t & 0x3f003f; 740 if (t & BIT(31)) { 741 s->regs.cur_offset |= t & BIT(31); 742 } else if (s->regs.cur_offset & BIT(31)) { 743 s->regs.cur_offset &= ~BIT(31); 744 ati_cursor_define(s); 745 } 746 break; 747 } 748 case CUR_CLR0 ... CUR_CLR0 + 3: 749 { 750 uint32_t t = s->regs.cur_color0; 751 752 ati_reg_write_offs(&t, addr - CUR_CLR0, data, size); 753 t &= 0xffffff; 754 if (s->regs.cur_color0 != t) { 755 s->regs.cur_color0 = t; 756 ati_cursor_define(s); 757 } 758 break; 759 } 760 case CUR_CLR1 ... CUR_CLR1 + 3: 761 /* 762 * Update cursor unconditionally here because some clients set up 763 * other registers before actually writing cursor data to memory at 764 * offset so we would miss cursor change unless always updating here 765 */ 766 ati_reg_write_offs(&s->regs.cur_color1, addr - CUR_CLR1, data, size); 767 s->regs.cur_color1 &= 0xffffff; 768 ati_cursor_define(s); 769 break; 770 case DST_OFFSET: 771 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 772 s->regs.dst_offset = data & 0xfffffff0; 773 } else { 774 s->regs.dst_offset = data & 0xfffffc00; 775 } 776 break; 777 case DST_PITCH: 778 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 779 s->regs.dst_pitch = data & 0x3fff; 780 s->regs.dst_tile = (data >> 16) & 1; 781 } else { 782 s->regs.dst_pitch = data & 0x3ff0; 783 } 784 break; 785 case DST_TILE: 786 if (s->dev_id == PCI_DEVICE_ID_ATI_RADEON_QY) { 787 s->regs.dst_tile = data & 3; 788 } 789 break; 790 case DST_WIDTH: 791 s->regs.dst_width = data & 0x3fff; 792 ati_2d_blt(s); 793 break; 794 case DST_HEIGHT: 795 s->regs.dst_height = data & 0x3fff; 796 break; 797 case SRC_X: 798 s->regs.src_x = data & 0x3fff; 799 break; 800 case SRC_Y: 801 s->regs.src_y = data & 0x3fff; 802 break; 803 case DST_X: 804 s->regs.dst_x = data & 0x3fff; 805 break; 806 case DST_Y: 807 s->regs.dst_y = data & 0x3fff; 808 break; 809 case SRC_PITCH_OFFSET: 810 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 811 s->regs.src_offset = (data & 0x1fffff) << 5; 812 s->regs.src_pitch = (data & 0x7fe00000) >> 21; 813 s->regs.src_tile = data >> 31; 814 } else { 815 s->regs.src_offset = (data & 0x3fffff) << 10; 816 s->regs.src_pitch = (data & 0x3fc00000) >> 16; 817 s->regs.src_tile = (data >> 30) & 1; 818 } 819 break; 820 case DST_PITCH_OFFSET: 821 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 822 s->regs.dst_offset = (data & 0x1fffff) << 5; 823 s->regs.dst_pitch = (data & 0x7fe00000) >> 21; 824 s->regs.dst_tile = data >> 31; 825 } else { 826 s->regs.dst_offset = (data & 0x3fffff) << 10; 827 s->regs.dst_pitch = (data & 0x3fc00000) >> 16; 828 s->regs.dst_tile = data >> 30; 829 } 830 break; 831 case SRC_Y_X: 832 s->regs.src_x = data & 0x3fff; 833 s->regs.src_y = (data >> 16) & 0x3fff; 834 break; 835 case DST_Y_X: 836 s->regs.dst_x = data & 0x3fff; 837 s->regs.dst_y = (data >> 16) & 0x3fff; 838 break; 839 case DST_HEIGHT_WIDTH: 840 s->regs.dst_width = data & 0x3fff; 841 s->regs.dst_height = (data >> 16) & 0x3fff; 842 ati_2d_blt(s); 843 break; 844 case DP_GUI_MASTER_CNTL: 845 s->regs.dp_gui_master_cntl = data & 0xf800000f; 846 s->regs.dp_datatype = (data & 0x0f00) >> 8 | (data & 0x30f0) << 4 | 847 (data & 0x4000) << 16; 848 s->regs.dp_mix = (data & GMC_ROP3_MASK) | (data & 0x7000000) >> 16; 849 break; 850 case DST_WIDTH_X: 851 s->regs.dst_x = data & 0x3fff; 852 s->regs.dst_width = (data >> 16) & 0x3fff; 853 ati_2d_blt(s); 854 break; 855 case SRC_X_Y: 856 s->regs.src_y = data & 0x3fff; 857 s->regs.src_x = (data >> 16) & 0x3fff; 858 break; 859 case DST_X_Y: 860 s->regs.dst_y = data & 0x3fff; 861 s->regs.dst_x = (data >> 16) & 0x3fff; 862 break; 863 case DST_WIDTH_HEIGHT: 864 s->regs.dst_height = data & 0x3fff; 865 s->regs.dst_width = (data >> 16) & 0x3fff; 866 ati_2d_blt(s); 867 break; 868 case DST_HEIGHT_Y: 869 s->regs.dst_y = data & 0x3fff; 870 s->regs.dst_height = (data >> 16) & 0x3fff; 871 break; 872 case SRC_OFFSET: 873 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 874 s->regs.src_offset = data & 0xfffffff0; 875 } else { 876 s->regs.src_offset = data & 0xfffffc00; 877 } 878 break; 879 case SRC_PITCH: 880 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 881 s->regs.src_pitch = data & 0x3fff; 882 s->regs.src_tile = (data >> 16) & 1; 883 } else { 884 s->regs.src_pitch = data & 0x3ff0; 885 } 886 break; 887 case DP_BRUSH_BKGD_CLR: 888 s->regs.dp_brush_bkgd_clr = data; 889 break; 890 case DP_BRUSH_FRGD_CLR: 891 s->regs.dp_brush_frgd_clr = data; 892 break; 893 case DP_CNTL: 894 s->regs.dp_cntl = data; 895 break; 896 case DP_DATATYPE: 897 s->regs.dp_datatype = data & 0xe0070f0f; 898 break; 899 case DP_MIX: 900 s->regs.dp_mix = data & 0x00ff0700; 901 break; 902 case DP_WRITE_MASK: 903 s->regs.dp_write_mask = data; 904 break; 905 case DEFAULT_OFFSET: 906 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 907 s->regs.default_offset = data & 0xfffffff0; 908 } else { 909 /* Radeon has DEFAULT_PITCH_OFFSET here like DST_PITCH_OFFSET */ 910 s->regs.default_offset = (data & 0x3fffff) << 10; 911 s->regs.default_pitch = (data & 0x3fc00000) >> 16; 912 s->regs.default_tile = data >> 30; 913 } 914 break; 915 case DEFAULT_PITCH: 916 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 917 s->regs.default_pitch = data & 0x3fff; 918 s->regs.default_tile = (data >> 16) & 1; 919 } 920 break; 921 case DEFAULT_SC_BOTTOM_RIGHT: 922 s->regs.default_sc_bottom_right = data & 0x3fff3fff; 923 break; 924 default: 925 break; 926 } 927 } 928 929 static const MemoryRegionOps ati_mm_ops = { 930 .read = ati_mm_read, 931 .write = ati_mm_write, 932 .endianness = DEVICE_LITTLE_ENDIAN, 933 }; 934 935 static void ati_vga_realize(PCIDevice *dev, Error **errp) 936 { 937 ATIVGAState *s = ATI_VGA(dev); 938 VGACommonState *vga = &s->vga; 939 940 if (s->model) { 941 int i; 942 for (i = 0; i < ARRAY_SIZE(ati_model_aliases); i++) { 943 if (!strcmp(s->model, ati_model_aliases[i].name)) { 944 s->dev_id = ati_model_aliases[i].dev_id; 945 break; 946 } 947 } 948 if (i >= ARRAY_SIZE(ati_model_aliases)) { 949 warn_report("Unknown ATI VGA model name, " 950 "using default rage128p"); 951 } 952 } 953 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF && 954 s->dev_id != PCI_DEVICE_ID_ATI_RADEON_QY) { 955 error_setg(errp, "Unknown ATI VGA device id, " 956 "only 0x5046 and 0x5159 are supported"); 957 return; 958 } 959 pci_set_word(dev->config + PCI_DEVICE_ID, s->dev_id); 960 961 if (s->dev_id == PCI_DEVICE_ID_ATI_RADEON_QY && 962 s->vga.vram_size_mb < 16) { 963 warn_report("Too small video memory for device id"); 964 s->vga.vram_size_mb = 16; 965 } 966 967 /* init vga bits */ 968 if (!vga_common_init(vga, OBJECT(s), errp)) { 969 return; 970 } 971 vga_init(vga, OBJECT(s), pci_address_space(dev), 972 pci_address_space_io(dev), true); 973 vga->con = graphic_console_init(DEVICE(s), 0, s->vga.hw_ops, &s->vga); 974 if (s->cursor_guest_mode) { 975 vga->cursor_invalidate = ati_cursor_invalidate; 976 vga->cursor_draw_line = ati_cursor_draw_line; 977 } 978 979 /* ddc, edid */ 980 I2CBus *i2cbus = i2c_init_bus(DEVICE(s), "ati-vga.ddc"); 981 bitbang_i2c_init(&s->bbi2c, i2cbus); 982 I2CSlave *i2cddc = I2C_SLAVE(qdev_new(TYPE_I2CDDC)); 983 i2c_slave_set_address(i2cddc, 0x50); 984 qdev_realize_and_unref(DEVICE(i2cddc), BUS(i2cbus), &error_abort); 985 986 /* mmio register space */ 987 memory_region_init_io(&s->mm, OBJECT(s), &ati_mm_ops, s, 988 "ati.mmregs", 0x4000); 989 /* io space is alias to beginning of mmregs */ 990 memory_region_init_alias(&s->io, OBJECT(s), "ati.io", &s->mm, 0, 0x100); 991 992 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram); 993 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io); 994 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mm); 995 996 /* most interrupts are not yet emulated but MacOS needs at least VBlank */ 997 dev->config[PCI_INTERRUPT_PIN] = 1; 998 timer_init_ns(&s->vblank_timer, QEMU_CLOCK_VIRTUAL, ati_vga_vblank_irq, s); 999 } 1000 1001 static void ati_vga_reset(DeviceState *dev) 1002 { 1003 ATIVGAState *s = ATI_VGA(dev); 1004 1005 timer_del(&s->vblank_timer); 1006 ati_vga_update_irq(s); 1007 1008 /* reset vga */ 1009 vga_common_reset(&s->vga); 1010 s->mode = VGA_MODE; 1011 } 1012 1013 static void ati_vga_exit(PCIDevice *dev) 1014 { 1015 ATIVGAState *s = ATI_VGA(dev); 1016 1017 timer_del(&s->vblank_timer); 1018 graphic_console_close(s->vga.con); 1019 } 1020 1021 static Property ati_vga_properties[] = { 1022 DEFINE_PROP_UINT32("vgamem_mb", ATIVGAState, vga.vram_size_mb, 16), 1023 DEFINE_PROP_STRING("model", ATIVGAState, model), 1024 DEFINE_PROP_UINT16("x-device-id", ATIVGAState, dev_id, 1025 PCI_DEVICE_ID_ATI_RAGE128_PF), 1026 DEFINE_PROP_BOOL("guest_hwcursor", ATIVGAState, cursor_guest_mode, false), 1027 DEFINE_PROP_END_OF_LIST() 1028 }; 1029 1030 static void ati_vga_class_init(ObjectClass *klass, void *data) 1031 { 1032 DeviceClass *dc = DEVICE_CLASS(klass); 1033 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1034 1035 dc->reset = ati_vga_reset; 1036 device_class_set_props(dc, ati_vga_properties); 1037 dc->hotpluggable = false; 1038 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 1039 1040 k->class_id = PCI_CLASS_DISPLAY_VGA; 1041 k->vendor_id = PCI_VENDOR_ID_ATI; 1042 k->device_id = PCI_DEVICE_ID_ATI_RAGE128_PF; 1043 k->romfile = "vgabios-ati.bin"; 1044 k->realize = ati_vga_realize; 1045 k->exit = ati_vga_exit; 1046 } 1047 1048 static const TypeInfo ati_vga_info = { 1049 .name = TYPE_ATI_VGA, 1050 .parent = TYPE_PCI_DEVICE, 1051 .instance_size = sizeof(ATIVGAState), 1052 .class_init = ati_vga_class_init, 1053 .interfaces = (InterfaceInfo[]) { 1054 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1055 { }, 1056 }, 1057 }; 1058 1059 static void ati_vga_register_types(void) 1060 { 1061 type_register_static(&ati_vga_info); 1062 } 1063 1064 type_init(ati_vga_register_types) 1065