1 /* 2 * QEMU ATI SVGA emulation 3 * 4 * Copyright (c) 2019 BALATON Zoltan 5 * 6 * This work is licensed under the GNU GPL license version 2 or later. 7 */ 8 9 /* 10 * WARNING: 11 * This is very incomplete and only enough for Linux console and some 12 * unaccelerated X output at the moment. 13 * Currently it's little more than a frame buffer with minimal functions, 14 * other more advanced features of the hardware are yet to be implemented. 15 * We only aim for Rage 128 Pro (and some RV100) and 2D only at first, 16 * No 3D at all yet (maybe after 2D works, but feel free to improve it) 17 */ 18 19 #include "qemu/osdep.h" 20 #include "ati_int.h" 21 #include "ati_regs.h" 22 #include "vga-access.h" 23 #include "hw/qdev-properties.h" 24 #include "vga_regs.h" 25 #include "qemu/log.h" 26 #include "qemu/module.h" 27 #include "qemu/error-report.h" 28 #include "qapi/error.h" 29 #include "ui/console.h" 30 #include "hw/display/i2c-ddc.h" 31 #include "trace.h" 32 33 #define ATI_DEBUG_HW_CURSOR 0 34 35 static const struct { 36 const char *name; 37 uint16_t dev_id; 38 } ati_model_aliases[] = { 39 { "rage128p", PCI_DEVICE_ID_ATI_RAGE128_PF }, 40 { "rv100", PCI_DEVICE_ID_ATI_RADEON_QY }, 41 }; 42 43 enum { VGA_MODE, EXT_MODE }; 44 45 static void ati_vga_switch_mode(ATIVGAState *s) 46 { 47 DPRINTF("%d -> %d\n", 48 s->mode, !!(s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN)); 49 if (s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN) { 50 /* Extended mode enabled */ 51 s->mode = EXT_MODE; 52 if (s->regs.crtc_gen_cntl & CRTC2_EN) { 53 /* CRT controller enabled, use CRTC values */ 54 /* FIXME Should these be the same as VGA CRTC regs? */ 55 uint32_t offs = s->regs.crtc_offset & 0x07ffffff; 56 int stride = (s->regs.crtc_pitch & 0x7ff) * 8; 57 int bpp = 0; 58 int h, v; 59 60 if (s->regs.crtc_h_total_disp == 0) { 61 s->regs.crtc_h_total_disp = ((640 / 8) - 1) << 16; 62 } 63 if (s->regs.crtc_v_total_disp == 0) { 64 s->regs.crtc_v_total_disp = (480 - 1) << 16; 65 } 66 h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8; 67 v = (s->regs.crtc_v_total_disp >> 16) + 1; 68 switch (s->regs.crtc_gen_cntl & CRTC_PIX_WIDTH_MASK) { 69 case CRTC_PIX_WIDTH_4BPP: 70 bpp = 4; 71 break; 72 case CRTC_PIX_WIDTH_8BPP: 73 bpp = 8; 74 break; 75 case CRTC_PIX_WIDTH_15BPP: 76 bpp = 15; 77 break; 78 case CRTC_PIX_WIDTH_16BPP: 79 bpp = 16; 80 break; 81 case CRTC_PIX_WIDTH_24BPP: 82 bpp = 24; 83 break; 84 case CRTC_PIX_WIDTH_32BPP: 85 bpp = 32; 86 break; 87 default: 88 qemu_log_mask(LOG_UNIMP, "Unsupported bpp value\n"); 89 return; 90 } 91 DPRINTF("Switching to %dx%d %d %d @ %x\n", h, v, stride, bpp, offs); 92 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE); 93 vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED); 94 s->vga.big_endian_fb = (s->regs.config_cntl & APER_0_ENDIAN || 95 s->regs.config_cntl & APER_1_ENDIAN ? 96 true : false); 97 /* reset VBE regs then set up mode */ 98 s->vga.vbe_regs[VBE_DISPI_INDEX_XRES] = h; 99 s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] = v; 100 s->vga.vbe_regs[VBE_DISPI_INDEX_BPP] = bpp; 101 /* enable mode via ioport so it updates vga regs */ 102 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE); 103 vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_ENABLED | 104 VBE_DISPI_LFB_ENABLED | VBE_DISPI_NOCLEARMEM | 105 (s->regs.dac_cntl & DAC_8BIT_EN ? VBE_DISPI_8BIT_DAC : 0)); 106 /* now set offset and stride after enable as that resets these */ 107 if (stride) { 108 int bypp = DIV_ROUND_UP(bpp, BITS_PER_BYTE); 109 110 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_VIRT_WIDTH); 111 vbe_ioport_write_data(&s->vga, 0, stride); 112 stride *= bypp; 113 if (offs % stride) { 114 DPRINTF("CRTC offset is not multiple of pitch\n"); 115 vbe_ioport_write_index(&s->vga, 0, 116 VBE_DISPI_INDEX_X_OFFSET); 117 vbe_ioport_write_data(&s->vga, 0, offs % stride / bypp); 118 } 119 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_Y_OFFSET); 120 vbe_ioport_write_data(&s->vga, 0, offs / stride); 121 DPRINTF("VBE offset (%d,%d), vbe_start_addr=%x\n", 122 s->vga.vbe_regs[VBE_DISPI_INDEX_X_OFFSET], 123 s->vga.vbe_regs[VBE_DISPI_INDEX_Y_OFFSET], 124 s->vga.vbe_start_addr); 125 } 126 } 127 } else { 128 /* VGA mode enabled */ 129 s->mode = VGA_MODE; 130 vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE); 131 vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED); 132 } 133 } 134 135 /* Used by host side hardware cursor */ 136 static void ati_cursor_define(ATIVGAState *s) 137 { 138 uint8_t data[1024]; 139 uint32_t srcoff; 140 int i, j, idx = 0; 141 142 if ((s->regs.cur_offset & BIT(31)) || s->cursor_guest_mode) { 143 return; /* Do not update cursor if locked or rendered by guest */ 144 } 145 /* FIXME handle cur_hv_offs correctly */ 146 srcoff = s->regs.cur_offset - 147 (s->regs.cur_hv_offs >> 16) - (s->regs.cur_hv_offs & 0xffff) * 16; 148 for (i = 0; i < 64; i++) { 149 for (j = 0; j < 8; j++, idx++) { 150 data[idx] = vga_read_byte(&s->vga, srcoff + i * 16 + j); 151 data[512 + idx] = vga_read_byte(&s->vga, srcoff + i * 16 + j + 8); 152 } 153 } 154 if (!s->cursor) { 155 s->cursor = cursor_alloc(64, 64); 156 } 157 cursor_set_mono(s->cursor, s->regs.cur_color1, s->regs.cur_color0, 158 &data[512], 1, &data[0]); 159 dpy_cursor_define(s->vga.con, s->cursor); 160 } 161 162 /* Alternatively support guest rendered hardware cursor */ 163 static void ati_cursor_invalidate(VGACommonState *vga) 164 { 165 ATIVGAState *s = container_of(vga, ATIVGAState, vga); 166 int size = (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) ? 64 : 0; 167 168 if (s->regs.cur_offset & BIT(31)) { 169 return; /* Do not update cursor if locked */ 170 } 171 if (s->cursor_size != size || 172 vga->hw_cursor_x != s->regs.cur_hv_pos >> 16 || 173 vga->hw_cursor_y != (s->regs.cur_hv_pos & 0xffff) || 174 s->cursor_offset != s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) - 175 (s->regs.cur_hv_offs & 0xffff) * 16) { 176 /* Remove old cursor then update and show new one if needed */ 177 vga_invalidate_scanlines(vga, vga->hw_cursor_y, vga->hw_cursor_y + 63); 178 vga->hw_cursor_x = s->regs.cur_hv_pos >> 16; 179 vga->hw_cursor_y = s->regs.cur_hv_pos & 0xffff; 180 s->cursor_offset = s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) - 181 (s->regs.cur_hv_offs & 0xffff) * 16; 182 s->cursor_size = size; 183 if (size) { 184 vga_invalidate_scanlines(vga, 185 vga->hw_cursor_y, vga->hw_cursor_y + 63); 186 } 187 } 188 } 189 190 static void ati_cursor_draw_line(VGACommonState *vga, uint8_t *d, int scr_y) 191 { 192 ATIVGAState *s = container_of(vga, ATIVGAState, vga); 193 uint32_t srcoff; 194 uint32_t *dp = (uint32_t *)d; 195 int i, j, h; 196 197 if (!(s->regs.crtc_gen_cntl & CRTC2_CUR_EN) || 198 scr_y < vga->hw_cursor_y || scr_y >= vga->hw_cursor_y + 64 || 199 scr_y > s->regs.crtc_v_total_disp >> 16) { 200 return; 201 } 202 /* FIXME handle cur_hv_offs correctly */ 203 srcoff = s->cursor_offset + (scr_y - vga->hw_cursor_y) * 16; 204 dp = &dp[vga->hw_cursor_x]; 205 h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8; 206 for (i = 0; i < 8; i++) { 207 uint32_t color; 208 uint8_t abits = vga_read_byte(vga, srcoff + i); 209 uint8_t xbits = vga_read_byte(vga, srcoff + i + 8); 210 for (j = 0; j < 8; j++, abits <<= 1, xbits <<= 1) { 211 if (abits & BIT(7)) { 212 if (xbits & BIT(7)) { 213 color = dp[i * 8 + j] ^ 0xffffffff; /* complement */ 214 } else { 215 continue; /* transparent, no change */ 216 } 217 } else { 218 color = (xbits & BIT(7) ? s->regs.cur_color1 : 219 s->regs.cur_color0) | 0xff000000; 220 } 221 if (vga->hw_cursor_x + i * 8 + j >= h) { 222 return; /* end of screen, don't span to next line */ 223 } 224 dp[i * 8 + j] = color; 225 } 226 } 227 } 228 229 static uint64_t ati_i2c(bitbang_i2c_interface *i2c, uint64_t data, int base) 230 { 231 bool c = (data & BIT(base + 17) ? !!(data & BIT(base + 1)) : 1); 232 bool d = (data & BIT(base + 16) ? !!(data & BIT(base)) : 1); 233 234 bitbang_i2c_set(i2c, BITBANG_I2C_SCL, c); 235 d = bitbang_i2c_set(i2c, BITBANG_I2C_SDA, d); 236 237 data &= ~0xf00ULL; 238 if (c) { 239 data |= BIT(base + 9); 240 } 241 if (d) { 242 data |= BIT(base + 8); 243 } 244 return data; 245 } 246 247 static void ati_vga_update_irq(ATIVGAState *s) 248 { 249 pci_set_irq(&s->dev, !!(s->regs.gen_int_status & s->regs.gen_int_cntl)); 250 } 251 252 static void ati_vga_vblank_irq(void *opaque) 253 { 254 ATIVGAState *s = opaque; 255 256 timer_mod(&s->vblank_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 257 NANOSECONDS_PER_SECOND / 60); 258 s->regs.gen_int_status |= CRTC_VBLANK_INT; 259 ati_vga_update_irq(s); 260 } 261 262 static inline uint64_t ati_reg_read_offs(uint32_t reg, int offs, 263 unsigned int size) 264 { 265 if (offs == 0 && size == 4) { 266 return reg; 267 } else { 268 return extract32(reg, offs * BITS_PER_BYTE, size * BITS_PER_BYTE); 269 } 270 } 271 272 static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size) 273 { 274 ATIVGAState *s = opaque; 275 uint64_t val = 0; 276 277 switch (addr) { 278 case MM_INDEX: 279 val = s->regs.mm_index; 280 break; 281 case MM_DATA ... MM_DATA + 3: 282 /* indexed access to regs or memory */ 283 if (s->regs.mm_index & BIT(31)) { 284 uint32_t idx = s->regs.mm_index & ~BIT(31); 285 if (idx <= s->vga.vram_size - size) { 286 val = ldn_le_p(s->vga.vram_ptr + idx, size); 287 } 288 } else if (s->regs.mm_index > MM_DATA + 3) { 289 val = ati_mm_read(s, s->regs.mm_index + addr - MM_DATA, size); 290 } else { 291 qemu_log_mask(LOG_GUEST_ERROR, 292 "ati_mm_read: mm_index too small: %u\n", s->regs.mm_index); 293 } 294 break; 295 case BIOS_0_SCRATCH ... BUS_CNTL - 1: 296 { 297 int i = (addr - BIOS_0_SCRATCH) / 4; 298 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) { 299 break; 300 } 301 val = ati_reg_read_offs(s->regs.bios_scratch[i], 302 addr - (BIOS_0_SCRATCH + i * 4), size); 303 break; 304 } 305 case GEN_INT_CNTL: 306 val = s->regs.gen_int_cntl; 307 break; 308 case GEN_INT_STATUS: 309 val = s->regs.gen_int_status; 310 break; 311 case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3: 312 val = ati_reg_read_offs(s->regs.crtc_gen_cntl, 313 addr - CRTC_GEN_CNTL, size); 314 break; 315 case CRTC_EXT_CNTL ... CRTC_EXT_CNTL + 3: 316 val = ati_reg_read_offs(s->regs.crtc_ext_cntl, 317 addr - CRTC_EXT_CNTL, size); 318 break; 319 case DAC_CNTL: 320 val = s->regs.dac_cntl; 321 break; 322 case GPIO_VGA_DDC: 323 val = s->regs.gpio_vga_ddc; 324 break; 325 case GPIO_DVI_DDC: 326 val = s->regs.gpio_dvi_ddc; 327 break; 328 case GPIO_MONID ... GPIO_MONID + 3: 329 val = ati_reg_read_offs(s->regs.gpio_monid, 330 addr - GPIO_MONID, size); 331 break; 332 case PALETTE_INDEX: 333 /* FIXME unaligned access */ 334 val = vga_ioport_read(&s->vga, VGA_PEL_IR) << 16; 335 val |= vga_ioport_read(&s->vga, VGA_PEL_IW) & 0xff; 336 break; 337 case PALETTE_DATA: 338 val = vga_ioport_read(&s->vga, VGA_PEL_D); 339 break; 340 case CNFG_CNTL: 341 val = s->regs.config_cntl; 342 break; 343 case CNFG_MEMSIZE: 344 val = s->vga.vram_size; 345 break; 346 case CONFIG_APER_0_BASE: 347 case CONFIG_APER_1_BASE: 348 val = pci_default_read_config(&s->dev, 349 PCI_BASE_ADDRESS_0, size) & 0xfffffff0; 350 break; 351 case CONFIG_APER_SIZE: 352 val = s->vga.vram_size; 353 break; 354 case CONFIG_REG_1_BASE: 355 val = pci_default_read_config(&s->dev, 356 PCI_BASE_ADDRESS_2, size) & 0xfffffff0; 357 break; 358 case CONFIG_REG_APER_SIZE: 359 val = memory_region_size(&s->mm); 360 break; 361 case MC_STATUS: 362 val = 5; 363 break; 364 case RBBM_STATUS: 365 case GUI_STAT: 366 val = 64; /* free CMDFIFO entries */ 367 break; 368 case CRTC_H_TOTAL_DISP: 369 val = s->regs.crtc_h_total_disp; 370 break; 371 case CRTC_H_SYNC_STRT_WID: 372 val = s->regs.crtc_h_sync_strt_wid; 373 break; 374 case CRTC_V_TOTAL_DISP: 375 val = s->regs.crtc_v_total_disp; 376 break; 377 case CRTC_V_SYNC_STRT_WID: 378 val = s->regs.crtc_v_sync_strt_wid; 379 break; 380 case CRTC_OFFSET: 381 val = s->regs.crtc_offset; 382 break; 383 case CRTC_OFFSET_CNTL: 384 val = s->regs.crtc_offset_cntl; 385 break; 386 case CRTC_PITCH: 387 val = s->regs.crtc_pitch; 388 break; 389 case 0xf00 ... 0xfff: 390 val = pci_default_read_config(&s->dev, addr - 0xf00, size); 391 break; 392 case CUR_OFFSET ... CUR_OFFSET + 3: 393 val = ati_reg_read_offs(s->regs.cur_offset, addr - CUR_OFFSET, size); 394 break; 395 case CUR_HORZ_VERT_POSN ... CUR_HORZ_VERT_POSN + 3: 396 val = ati_reg_read_offs(s->regs.cur_hv_pos, 397 addr - CUR_HORZ_VERT_POSN, size); 398 if (addr + size > CUR_HORZ_VERT_POSN + 3) { 399 val |= (s->regs.cur_offset & BIT(31)) >> (4 - size); 400 } 401 break; 402 case CUR_HORZ_VERT_OFF ... CUR_HORZ_VERT_OFF + 3: 403 val = ati_reg_read_offs(s->regs.cur_hv_offs, 404 addr - CUR_HORZ_VERT_OFF, size); 405 if (addr + size > CUR_HORZ_VERT_OFF + 3) { 406 val |= (s->regs.cur_offset & BIT(31)) >> (4 - size); 407 } 408 break; 409 case CUR_CLR0 ... CUR_CLR0 + 3: 410 val = ati_reg_read_offs(s->regs.cur_color0, addr - CUR_CLR0, size); 411 break; 412 case CUR_CLR1 ... CUR_CLR1 + 3: 413 val = ati_reg_read_offs(s->regs.cur_color1, addr - CUR_CLR1, size); 414 break; 415 case DST_OFFSET: 416 val = s->regs.dst_offset; 417 break; 418 case DST_PITCH: 419 val = s->regs.dst_pitch; 420 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 421 val &= s->regs.dst_tile << 16; 422 } 423 break; 424 case DST_WIDTH: 425 val = s->regs.dst_width; 426 break; 427 case DST_HEIGHT: 428 val = s->regs.dst_height; 429 break; 430 case SRC_X: 431 val = s->regs.src_x; 432 break; 433 case SRC_Y: 434 val = s->regs.src_y; 435 break; 436 case DST_X: 437 val = s->regs.dst_x; 438 break; 439 case DST_Y: 440 val = s->regs.dst_y; 441 break; 442 case DP_GUI_MASTER_CNTL: 443 val = s->regs.dp_gui_master_cntl; 444 break; 445 case SRC_OFFSET: 446 val = s->regs.src_offset; 447 break; 448 case SRC_PITCH: 449 val = s->regs.src_pitch; 450 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 451 val &= s->regs.src_tile << 16; 452 } 453 break; 454 case DP_BRUSH_BKGD_CLR: 455 val = s->regs.dp_brush_bkgd_clr; 456 break; 457 case DP_BRUSH_FRGD_CLR: 458 val = s->regs.dp_brush_frgd_clr; 459 break; 460 case DP_SRC_FRGD_CLR: 461 val = s->regs.dp_src_frgd_clr; 462 break; 463 case DP_SRC_BKGD_CLR: 464 val = s->regs.dp_src_bkgd_clr; 465 break; 466 case DP_CNTL: 467 val = s->regs.dp_cntl; 468 break; 469 case DP_DATATYPE: 470 val = s->regs.dp_datatype; 471 break; 472 case DP_MIX: 473 val = s->regs.dp_mix; 474 break; 475 case DP_WRITE_MASK: 476 val = s->regs.dp_write_mask; 477 break; 478 case DEFAULT_OFFSET: 479 val = s->regs.default_offset; 480 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { 481 val >>= 10; 482 val |= s->regs.default_pitch << 16; 483 val |= s->regs.default_tile << 30; 484 } 485 break; 486 case DEFAULT_PITCH: 487 val = s->regs.default_pitch; 488 val |= s->regs.default_tile << 16; 489 break; 490 case DEFAULT_SC_BOTTOM_RIGHT: 491 val = s->regs.default_sc_bottom_right; 492 break; 493 default: 494 break; 495 } 496 if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) { 497 trace_ati_mm_read(size, addr, ati_reg_name(addr & ~3ULL), val); 498 } 499 return val; 500 } 501 502 static inline void ati_reg_write_offs(uint32_t *reg, int offs, 503 uint64_t data, unsigned int size) 504 { 505 if (offs == 0 && size == 4) { 506 *reg = data; 507 } else { 508 *reg = deposit32(*reg, offs * BITS_PER_BYTE, size * BITS_PER_BYTE, 509 data); 510 } 511 } 512 513 static void ati_mm_write(void *opaque, hwaddr addr, 514 uint64_t data, unsigned int size) 515 { 516 ATIVGAState *s = opaque; 517 518 if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) { 519 trace_ati_mm_write(size, addr, ati_reg_name(addr & ~3ULL), data); 520 } 521 switch (addr) { 522 case MM_INDEX: 523 s->regs.mm_index = data & ~3; 524 break; 525 case MM_DATA ... MM_DATA + 3: 526 /* indexed access to regs or memory */ 527 if (s->regs.mm_index & BIT(31)) { 528 uint32_t idx = s->regs.mm_index & ~BIT(31); 529 if (idx <= s->vga.vram_size - size) { 530 stn_le_p(s->vga.vram_ptr + idx, size, data); 531 } 532 } else if (s->regs.mm_index > MM_DATA + 3) { 533 ati_mm_write(s, s->regs.mm_index + addr - MM_DATA, data, size); 534 } else { 535 qemu_log_mask(LOG_GUEST_ERROR, 536 "ati_mm_write: mm_index too small: %u\n", s->regs.mm_index); 537 } 538 break; 539 case BIOS_0_SCRATCH ... BUS_CNTL - 1: 540 { 541 int i = (addr - BIOS_0_SCRATCH) / 4; 542 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) { 543 break; 544 } 545 ati_reg_write_offs(&s->regs.bios_scratch[i], 546 addr - (BIOS_0_SCRATCH + i * 4), data, size); 547 break; 548 } 549 case GEN_INT_CNTL: 550 s->regs.gen_int_cntl = data; 551 if (data & CRTC_VBLANK_INT) { 552 ati_vga_vblank_irq(s); 553 } else { 554 timer_del(&s->vblank_timer); 555 ati_vga_update_irq(s); 556 } 557 break; 558 case GEN_INT_STATUS: 559 data &= (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF ? 560 0x000f040fUL : 0xfc080effUL); 561 s->regs.gen_int_status &= ~data; 562 ati_vga_update_irq(s); 563 break; 564 case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3: 565 { 566 uint32_t val = s->regs.crtc_gen_cntl; 567 ati_reg_write_offs(&s->regs.crtc_gen_cntl, 568 addr - CRTC_GEN_CNTL, data, size); 569 if ((val & CRTC2_CUR_EN) != (s->regs.crtc_gen_cntl & CRTC2_CUR_EN)) { 570 if (s->cursor_guest_mode) { 571 s->vga.force_shadow = !!(s->regs.crtc_gen_cntl & CRTC2_CUR_EN); 572 } else { 573 if (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) { 574 ati_cursor_define(s); 575 } 576 dpy_mouse_set(s->vga.con, s->regs.cur_hv_pos >> 16, 577 s->regs.cur_hv_pos & 0xffff, 578 (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) != 0); 579 } 580 } 581 if ((val & (CRTC2_EXT_DISP_EN | CRTC2_EN)) != 582 (s->regs.crtc_gen_cntl & (CRTC2_EXT_DISP_EN | CRTC2_EN))) { 583 ati_vga_switch_mode(s); 584 } 585 break; 586 } 587 case CRTC_EXT_CNTL ... CRTC_EXT_CNTL + 3: 588 { 589 uint32_t val = s->regs.crtc_ext_cntl; 590 ati_reg_write_offs(&s->regs.crtc_ext_cntl, 591 addr - CRTC_EXT_CNTL, data, size); 592 if (s->regs.crtc_ext_cntl & CRT_CRTC_DISPLAY_DIS) { 593 DPRINTF("Display disabled\n"); 594 s->vga.ar_index &= ~BIT(5); 595 } else { 596 DPRINTF("Display enabled\n"); 597 s->vga.ar_index |= BIT(5); 598 ati_vga_switch_mode(s); 599 } 600 if ((val & CRT_CRTC_DISPLAY_DIS) != 601 (s->regs.crtc_ext_cntl & CRT_CRTC_DISPLAY_DIS)) { 602 ati_vga_switch_mode(s); 603 } 604 break; 605 } 606 case DAC_CNTL: 607 s->regs.dac_cntl = data & 0xffffe3ff; 608 s->vga.dac_8bit = !!(data & DAC_8BIT_EN); 609 break; 610 case GPIO_VGA_DDC: 611 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { 612 /* FIXME: Maybe add a property to select VGA or DVI port? */ 613 } 614 break; 615 case GPIO_DVI_DDC: 616 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) { 617 s->regs.gpio_dvi_ddc = ati_i2c(&s->bbi2c, data, 0); 618 } 619 break; 620 case GPIO_MONID ... GPIO_MONID + 3: 621 /* FIXME What does Radeon have here? */ 622 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 623 ati_reg_write_offs(&s->regs.gpio_monid, 624 addr - GPIO_MONID, data, size); 625 /* 626 * Rage128p accesses DDC used to get EDID via these bits. 627 * Because some drivers access this via multiple byte writes 628 * we have to be careful when we send bits to avoid spurious 629 * changes in bitbang_i2c state. So only do it when mask is set 630 * and either the enable bits are changed or output bits changed 631 * while enabled. 632 */ 633 if ((s->regs.gpio_monid & BIT(25)) && 634 ((addr <= GPIO_MONID + 2 && addr + size > GPIO_MONID + 2) || 635 (addr == GPIO_MONID && (s->regs.gpio_monid & 0x60000)))) { 636 s->regs.gpio_monid = ati_i2c(&s->bbi2c, s->regs.gpio_monid, 1); 637 } 638 } 639 break; 640 case PALETTE_INDEX ... PALETTE_INDEX + 3: 641 if (size == 4) { 642 vga_ioport_write(&s->vga, VGA_PEL_IR, (data >> 16) & 0xff); 643 vga_ioport_write(&s->vga, VGA_PEL_IW, data & 0xff); 644 } else { 645 if (addr == PALETTE_INDEX) { 646 vga_ioport_write(&s->vga, VGA_PEL_IW, data & 0xff); 647 } else { 648 vga_ioport_write(&s->vga, VGA_PEL_IR, data & 0xff); 649 } 650 } 651 break; 652 case PALETTE_DATA ... PALETTE_DATA + 3: 653 data <<= addr - PALETTE_DATA; 654 data = bswap32(data) >> 8; 655 vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff); 656 data >>= 8; 657 vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff); 658 data >>= 8; 659 vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff); 660 break; 661 case CNFG_CNTL: 662 s->regs.config_cntl = data; 663 break; 664 case CRTC_H_TOTAL_DISP: 665 s->regs.crtc_h_total_disp = data & 0x07ff07ff; 666 break; 667 case CRTC_H_SYNC_STRT_WID: 668 s->regs.crtc_h_sync_strt_wid = data & 0x17bf1fff; 669 break; 670 case CRTC_V_TOTAL_DISP: 671 s->regs.crtc_v_total_disp = data & 0x0fff0fff; 672 break; 673 case CRTC_V_SYNC_STRT_WID: 674 s->regs.crtc_v_sync_strt_wid = data & 0x9f0fff; 675 break; 676 case CRTC_OFFSET: 677 s->regs.crtc_offset = data & 0xc7ffffff; 678 break; 679 case CRTC_OFFSET_CNTL: 680 s->regs.crtc_offset_cntl = data; /* FIXME */ 681 break; 682 case CRTC_PITCH: 683 s->regs.crtc_pitch = data & 0x07ff07ff; 684 break; 685 case 0xf00 ... 0xfff: 686 /* read-only copy of PCI config space so ignore writes */ 687 break; 688 case CUR_OFFSET ... CUR_OFFSET + 3: 689 { 690 uint32_t t = s->regs.cur_offset; 691 692 ati_reg_write_offs(&t, addr - CUR_OFFSET, data, size); 693 t &= 0x87fffff0; 694 if (s->regs.cur_offset != t) { 695 s->regs.cur_offset = t; 696 ati_cursor_define(s); 697 } 698 break; 699 } 700 case CUR_HORZ_VERT_POSN ... CUR_HORZ_VERT_POSN + 3: 701 { 702 uint32_t t = s->regs.cur_hv_pos | (s->regs.cur_offset & BIT(31)); 703 704 ati_reg_write_offs(&t, addr - CUR_HORZ_VERT_POSN, data, size); 705 s->regs.cur_hv_pos = t & 0x3fff0fff; 706 if (t & BIT(31)) { 707 s->regs.cur_offset |= t & BIT(31); 708 } else if (s->regs.cur_offset & BIT(31)) { 709 s->regs.cur_offset &= ~BIT(31); 710 ati_cursor_define(s); 711 } 712 if (!s->cursor_guest_mode && 713 (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) && !(t & BIT(31))) { 714 dpy_mouse_set(s->vga.con, s->regs.cur_hv_pos >> 16, 715 s->regs.cur_hv_pos & 0xffff, 1); 716 } 717 break; 718 } 719 case CUR_HORZ_VERT_OFF: 720 { 721 uint32_t t = s->regs.cur_hv_offs | (s->regs.cur_offset & BIT(31)); 722 723 ati_reg_write_offs(&t, addr - CUR_HORZ_VERT_OFF, data, size); 724 s->regs.cur_hv_offs = t & 0x3f003f; 725 if (t & BIT(31)) { 726 s->regs.cur_offset |= t & BIT(31); 727 } else if (s->regs.cur_offset & BIT(31)) { 728 s->regs.cur_offset &= ~BIT(31); 729 ati_cursor_define(s); 730 } 731 break; 732 } 733 case CUR_CLR0 ... CUR_CLR0 + 3: 734 { 735 uint32_t t = s->regs.cur_color0; 736 737 ati_reg_write_offs(&t, addr - CUR_CLR0, data, size); 738 t &= 0xffffff; 739 if (s->regs.cur_color0 != t) { 740 s->regs.cur_color0 = t; 741 ati_cursor_define(s); 742 } 743 break; 744 } 745 case CUR_CLR1 ... CUR_CLR1 + 3: 746 /* 747 * Update cursor unconditionally here because some clients set up 748 * other registers before actually writing cursor data to memory at 749 * offset so we would miss cursor change unless always updating here 750 */ 751 ati_reg_write_offs(&s->regs.cur_color1, addr - CUR_CLR1, data, size); 752 s->regs.cur_color1 &= 0xffffff; 753 ati_cursor_define(s); 754 break; 755 case DST_OFFSET: 756 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 757 s->regs.dst_offset = data & 0xfffffff0; 758 } else { 759 s->regs.dst_offset = data & 0xfffffc00; 760 } 761 break; 762 case DST_PITCH: 763 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 764 s->regs.dst_pitch = data & 0x3fff; 765 s->regs.dst_tile = (data >> 16) & 1; 766 } else { 767 s->regs.dst_pitch = data & 0x3ff0; 768 } 769 break; 770 case DST_TILE: 771 if (s->dev_id == PCI_DEVICE_ID_ATI_RADEON_QY) { 772 s->regs.dst_tile = data & 3; 773 } 774 break; 775 case DST_WIDTH: 776 s->regs.dst_width = data & 0x3fff; 777 ati_2d_blt(s); 778 break; 779 case DST_HEIGHT: 780 s->regs.dst_height = data & 0x3fff; 781 break; 782 case SRC_X: 783 s->regs.src_x = data & 0x3fff; 784 break; 785 case SRC_Y: 786 s->regs.src_y = data & 0x3fff; 787 break; 788 case DST_X: 789 s->regs.dst_x = data & 0x3fff; 790 break; 791 case DST_Y: 792 s->regs.dst_y = data & 0x3fff; 793 break; 794 case SRC_PITCH_OFFSET: 795 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 796 s->regs.src_offset = (data & 0x1fffff) << 5; 797 s->regs.src_pitch = (data & 0x7fe00000) >> 21; 798 s->regs.src_tile = data >> 31; 799 } else { 800 s->regs.src_offset = (data & 0x3fffff) << 10; 801 s->regs.src_pitch = (data & 0x3fc00000) >> 16; 802 s->regs.src_tile = (data >> 30) & 1; 803 } 804 break; 805 case DST_PITCH_OFFSET: 806 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 807 s->regs.dst_offset = (data & 0x1fffff) << 5; 808 s->regs.dst_pitch = (data & 0x7fe00000) >> 21; 809 s->regs.dst_tile = data >> 31; 810 } else { 811 s->regs.dst_offset = (data & 0x3fffff) << 10; 812 s->regs.dst_pitch = (data & 0x3fc00000) >> 16; 813 s->regs.dst_tile = data >> 30; 814 } 815 break; 816 case SRC_Y_X: 817 s->regs.src_x = data & 0x3fff; 818 s->regs.src_y = (data >> 16) & 0x3fff; 819 break; 820 case DST_Y_X: 821 s->regs.dst_x = data & 0x3fff; 822 s->regs.dst_y = (data >> 16) & 0x3fff; 823 break; 824 case DST_HEIGHT_WIDTH: 825 s->regs.dst_width = data & 0x3fff; 826 s->regs.dst_height = (data >> 16) & 0x3fff; 827 ati_2d_blt(s); 828 break; 829 case DP_GUI_MASTER_CNTL: 830 s->regs.dp_gui_master_cntl = data & 0xf800000f; 831 s->regs.dp_datatype = (data & 0x0f00) >> 8 | (data & 0x30f0) << 4 | 832 (data & 0x4000) << 16; 833 s->regs.dp_mix = (data & GMC_ROP3_MASK) | (data & 0x7000000) >> 16; 834 break; 835 case DST_WIDTH_X: 836 s->regs.dst_x = data & 0x3fff; 837 s->regs.dst_width = (data >> 16) & 0x3fff; 838 ati_2d_blt(s); 839 break; 840 case SRC_X_Y: 841 s->regs.src_y = data & 0x3fff; 842 s->regs.src_x = (data >> 16) & 0x3fff; 843 break; 844 case DST_X_Y: 845 s->regs.dst_y = data & 0x3fff; 846 s->regs.dst_x = (data >> 16) & 0x3fff; 847 break; 848 case DST_WIDTH_HEIGHT: 849 s->regs.dst_height = data & 0x3fff; 850 s->regs.dst_width = (data >> 16) & 0x3fff; 851 ati_2d_blt(s); 852 break; 853 case DST_HEIGHT_Y: 854 s->regs.dst_y = data & 0x3fff; 855 s->regs.dst_height = (data >> 16) & 0x3fff; 856 break; 857 case SRC_OFFSET: 858 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 859 s->regs.src_offset = data & 0xfffffff0; 860 } else { 861 s->regs.src_offset = data & 0xfffffc00; 862 } 863 break; 864 case SRC_PITCH: 865 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 866 s->regs.src_pitch = data & 0x3fff; 867 s->regs.src_tile = (data >> 16) & 1; 868 } else { 869 s->regs.src_pitch = data & 0x3ff0; 870 } 871 break; 872 case DP_BRUSH_BKGD_CLR: 873 s->regs.dp_brush_bkgd_clr = data; 874 break; 875 case DP_BRUSH_FRGD_CLR: 876 s->regs.dp_brush_frgd_clr = data; 877 break; 878 case DP_CNTL: 879 s->regs.dp_cntl = data; 880 break; 881 case DP_DATATYPE: 882 s->regs.dp_datatype = data & 0xe0070f0f; 883 break; 884 case DP_MIX: 885 s->regs.dp_mix = data & 0x00ff0700; 886 break; 887 case DP_WRITE_MASK: 888 s->regs.dp_write_mask = data; 889 break; 890 case DEFAULT_OFFSET: 891 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 892 s->regs.default_offset = data & 0xfffffff0; 893 } else { 894 /* Radeon has DEFAULT_PITCH_OFFSET here like DST_PITCH_OFFSET */ 895 s->regs.default_offset = (data & 0x3fffff) << 10; 896 s->regs.default_pitch = (data & 0x3fc00000) >> 16; 897 s->regs.default_tile = data >> 30; 898 } 899 break; 900 case DEFAULT_PITCH: 901 if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) { 902 s->regs.default_pitch = data & 0x3fff; 903 s->regs.default_tile = (data >> 16) & 1; 904 } 905 break; 906 case DEFAULT_SC_BOTTOM_RIGHT: 907 s->regs.default_sc_bottom_right = data & 0x3fff3fff; 908 break; 909 default: 910 break; 911 } 912 } 913 914 static const MemoryRegionOps ati_mm_ops = { 915 .read = ati_mm_read, 916 .write = ati_mm_write, 917 .endianness = DEVICE_LITTLE_ENDIAN, 918 }; 919 920 static void ati_vga_realize(PCIDevice *dev, Error **errp) 921 { 922 ATIVGAState *s = ATI_VGA(dev); 923 VGACommonState *vga = &s->vga; 924 925 if (s->model) { 926 int i; 927 for (i = 0; i < ARRAY_SIZE(ati_model_aliases); i++) { 928 if (!strcmp(s->model, ati_model_aliases[i].name)) { 929 s->dev_id = ati_model_aliases[i].dev_id; 930 break; 931 } 932 } 933 if (i >= ARRAY_SIZE(ati_model_aliases)) { 934 warn_report("Unknown ATI VGA model name, " 935 "using default rage128p"); 936 } 937 } 938 if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF && 939 s->dev_id != PCI_DEVICE_ID_ATI_RADEON_QY) { 940 error_setg(errp, "Unknown ATI VGA device id, " 941 "only 0x5046 and 0x5159 are supported"); 942 return; 943 } 944 pci_set_word(dev->config + PCI_DEVICE_ID, s->dev_id); 945 946 if (s->dev_id == PCI_DEVICE_ID_ATI_RADEON_QY && 947 s->vga.vram_size_mb < 16) { 948 warn_report("Too small video memory for device id"); 949 s->vga.vram_size_mb = 16; 950 } 951 952 /* init vga bits */ 953 vga_common_init(vga, OBJECT(s)); 954 vga_init(vga, OBJECT(s), pci_address_space(dev), 955 pci_address_space_io(dev), true); 956 vga->con = graphic_console_init(DEVICE(s), 0, s->vga.hw_ops, &s->vga); 957 if (s->cursor_guest_mode) { 958 vga->cursor_invalidate = ati_cursor_invalidate; 959 vga->cursor_draw_line = ati_cursor_draw_line; 960 } 961 962 /* ddc, edid */ 963 I2CBus *i2cbus = i2c_init_bus(DEVICE(s), "ati-vga.ddc"); 964 bitbang_i2c_init(&s->bbi2c, i2cbus); 965 I2CSlave *i2cddc = I2C_SLAVE(qdev_new(TYPE_I2CDDC)); 966 i2c_set_slave_address(i2cddc, 0x50); 967 qdev_realize_and_unref(DEVICE(i2cddc), BUS(i2cbus), &error_abort); 968 969 /* mmio register space */ 970 memory_region_init_io(&s->mm, OBJECT(s), &ati_mm_ops, s, 971 "ati.mmregs", 0x4000); 972 /* io space is alias to beginning of mmregs */ 973 memory_region_init_alias(&s->io, OBJECT(s), "ati.io", &s->mm, 0, 0x100); 974 975 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram); 976 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io); 977 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mm); 978 979 /* most interrupts are not yet emulated but MacOS needs at least VBlank */ 980 dev->config[PCI_INTERRUPT_PIN] = 1; 981 timer_init_ns(&s->vblank_timer, QEMU_CLOCK_VIRTUAL, ati_vga_vblank_irq, s); 982 } 983 984 static void ati_vga_reset(DeviceState *dev) 985 { 986 ATIVGAState *s = ATI_VGA(dev); 987 988 timer_del(&s->vblank_timer); 989 ati_vga_update_irq(s); 990 991 /* reset vga */ 992 vga_common_reset(&s->vga); 993 s->mode = VGA_MODE; 994 } 995 996 static void ati_vga_exit(PCIDevice *dev) 997 { 998 ATIVGAState *s = ATI_VGA(dev); 999 1000 timer_del(&s->vblank_timer); 1001 graphic_console_close(s->vga.con); 1002 } 1003 1004 static Property ati_vga_properties[] = { 1005 DEFINE_PROP_UINT32("vgamem_mb", ATIVGAState, vga.vram_size_mb, 16), 1006 DEFINE_PROP_STRING("model", ATIVGAState, model), 1007 DEFINE_PROP_UINT16("x-device-id", ATIVGAState, dev_id, 1008 PCI_DEVICE_ID_ATI_RAGE128_PF), 1009 DEFINE_PROP_BOOL("guest_hwcursor", ATIVGAState, cursor_guest_mode, false), 1010 DEFINE_PROP_END_OF_LIST() 1011 }; 1012 1013 static void ati_vga_class_init(ObjectClass *klass, void *data) 1014 { 1015 DeviceClass *dc = DEVICE_CLASS(klass); 1016 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1017 1018 dc->reset = ati_vga_reset; 1019 device_class_set_props(dc, ati_vga_properties); 1020 dc->hotpluggable = false; 1021 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 1022 1023 k->class_id = PCI_CLASS_DISPLAY_VGA; 1024 k->vendor_id = PCI_VENDOR_ID_ATI; 1025 k->device_id = PCI_DEVICE_ID_ATI_RAGE128_PF; 1026 k->romfile = "vgabios-ati.bin"; 1027 k->realize = ati_vga_realize; 1028 k->exit = ati_vga_exit; 1029 } 1030 1031 static const TypeInfo ati_vga_info = { 1032 .name = TYPE_ATI_VGA, 1033 .parent = TYPE_PCI_DEVICE, 1034 .instance_size = sizeof(ATIVGAState), 1035 .class_init = ati_vga_class_init, 1036 .interfaces = (InterfaceInfo[]) { 1037 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1038 { }, 1039 }, 1040 }; 1041 1042 static void ati_vga_register_types(void) 1043 { 1044 type_register_static(&ati_vga_info); 1045 } 1046 1047 type_init(ati_vga_register_types) 1048