xref: /openbmc/qemu/hw/cxl/cxl-host.c (revision a99fbb003b2558cb4ff426d8144eff7cc1e2d7dc) 
1 /*
2  * CXL host parameter parsing routines
3  *
4  * Copyright (c) 2022 Huawei
5  * Modeled loosely on the NUMA options handling in hw/core/numa.c
6  */
7 
8 #include "qemu/osdep.h"
9 #include "qemu/units.h"
10 #include "qemu/bitmap.h"
11 #include "qemu/error-report.h"
12 #include "qapi/error.h"
13 #include "sysemu/qtest.h"
14 #include "hw/boards.h"
15 
16 #include "qapi/qapi-visit-machine.h"
17 #include "hw/cxl/cxl.h"
18 #include "hw/cxl/cxl_host.h"
19 #include "hw/pci/pci_bus.h"
20 #include "hw/pci/pci_bridge.h"
21 #include "hw/pci/pci_host.h"
22 #include "hw/pci/pcie_port.h"
23 #include "hw/pci-bridge/pci_expander_bridge.h"
24 
25 static void cxl_fixed_memory_window_config(CXLState *cxl_state,
26                                            CXLFixedMemoryWindowOptions *object,
27                                            Error **errp)
28 {
29     g_autofree CXLFixedWindow *fw = g_malloc0(sizeof(*fw));
30     strList *target;
31     int i;
32 
33     for (target = object->targets; target; target = target->next) {
34         fw->num_targets++;
35     }
36 
37     fw->enc_int_ways = cxl_interleave_ways_enc(fw->num_targets, errp);
38     if (*errp) {
39         return;
40     }
41 
42     fw->targets = g_malloc0_n(fw->num_targets, sizeof(*fw->targets));
43     for (i = 0, target = object->targets; target; i++, target = target->next) {
44         /* This link cannot be resolved yet, so stash the name for now */
45         fw->targets[i] = g_strdup(target->value);
46     }
47 
48     if (object->size % (256 * MiB)) {
49         error_setg(errp,
50                    "Size of a CXL fixed memory window must my a multiple of 256MiB");
51         return;
52     }
53     fw->size = object->size;
54 
55     if (object->has_interleave_granularity) {
56         fw->enc_int_gran =
57             cxl_interleave_granularity_enc(object->interleave_granularity,
58                                            errp);
59         if (*errp) {
60             return;
61         }
62     } else {
63         /* Default to 256 byte interleave */
64         fw->enc_int_gran = 0;
65     }
66 
67     cxl_state->fixed_windows = g_list_append(cxl_state->fixed_windows,
68                                              g_steal_pointer(&fw));
69 
70     return;
71 }
72 
73 void cxl_fmws_link_targets(CXLState *cxl_state, Error **errp)
74 {
75     if (cxl_state && cxl_state->fixed_windows) {
76         GList *it;
77 
78         for (it = cxl_state->fixed_windows; it; it = it->next) {
79             CXLFixedWindow *fw = it->data;
80             int i;
81 
82             for (i = 0; i < fw->num_targets; i++) {
83                 Object *o;
84                 bool ambig;
85 
86                 o = object_resolve_path_type(fw->targets[i],
87                                              TYPE_PXB_CXL_DEVICE,
88                                              &ambig);
89                 if (!o) {
90                     error_setg(errp, "Could not resolve CXLFM target %s",
91                                fw->targets[i]);
92                     return;
93                 }
94                 fw->target_hbs[i] = PXB_CXL_DEV(o);
95             }
96         }
97     }
98 }
99 
100 /* TODO: support, multiple hdm decoders */
101 static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr,
102                                 uint8_t *target)
103 {
104     uint32_t ctrl;
105     uint32_t ig_enc;
106     uint32_t iw_enc;
107     uint32_t target_reg;
108     uint32_t target_idx;
109 
110     ctrl = cache_mem[R_CXL_HDM_DECODER0_CTRL];
111     if (!FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED)) {
112         return false;
113     }
114 
115     ig_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IG);
116     iw_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IW);
117     target_idx = (addr / cxl_decode_ig(ig_enc)) % (1 << iw_enc);
118 
119     if (target_idx > 4) {
120         target_reg = cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO];
121         target_reg >>= target_idx * 8;
122     } else {
123         target_reg = cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO];
124         target_reg >>= (target_idx - 4) * 8;
125     }
126     *target = target_reg & 0xff;
127 
128     return true;
129 }
130 
131 static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow *fw, hwaddr addr)
132 {
133     CXLComponentState *hb_cstate, *usp_cstate;
134     PCIHostState *hb;
135     CXLUpstreamPort *usp;
136     int rb_index;
137     uint32_t *cache_mem;
138     uint8_t target;
139     bool target_found;
140     PCIDevice *rp, *d;
141 
142     /* Address is relative to memory region. Convert to HPA */
143     addr += fw->base;
144 
145     rb_index = (addr / cxl_decode_ig(fw->enc_int_gran)) % fw->num_targets;
146     hb = PCI_HOST_BRIDGE(fw->target_hbs[rb_index]->cxl.cxl_host_bridge);
147     if (!hb || !hb->bus || !pci_bus_is_cxl(hb->bus)) {
148         return NULL;
149     }
150 
151     hb_cstate = cxl_get_hb_cstate(hb);
152     if (!hb_cstate) {
153         return NULL;
154     }
155 
156     cache_mem = hb_cstate->crb.cache_mem_registers;
157 
158     target_found = cxl_hdm_find_target(cache_mem, addr, &target);
159     if (!target_found) {
160         return NULL;
161     }
162 
163     rp = pcie_find_port_by_pn(hb->bus, target);
164     if (!rp) {
165         return NULL;
166     }
167 
168     d = pci_bridge_get_sec_bus(PCI_BRIDGE(rp))->devices[0];
169     if (!d) {
170         return NULL;
171     }
172 
173     if (object_dynamic_cast(OBJECT(d), TYPE_CXL_TYPE3)) {
174         return d;
175     }
176 
177     /*
178      * Could also be a switch.  Note only one level of switching currently
179      * supported.
180      */
181     if (!object_dynamic_cast(OBJECT(d), TYPE_CXL_USP)) {
182         return NULL;
183     }
184     usp = CXL_USP(d);
185 
186     usp_cstate = cxl_usp_to_cstate(usp);
187     if (!usp_cstate) {
188         return NULL;
189     }
190 
191     cache_mem = usp_cstate->crb.cache_mem_registers;
192 
193     target_found = cxl_hdm_find_target(cache_mem, addr, &target);
194     if (!target_found) {
195         return NULL;
196     }
197 
198     d = pcie_find_port_by_pn(&PCI_BRIDGE(d)->sec_bus, target);
199     if (!d) {
200         return NULL;
201     }
202 
203     d = pci_bridge_get_sec_bus(PCI_BRIDGE(d))->devices[0];
204     if (!d) {
205         return NULL;
206     }
207 
208     if (!object_dynamic_cast(OBJECT(d), TYPE_CXL_TYPE3)) {
209         return NULL;
210     }
211 
212     return d;
213 }
214 
215 static MemTxResult cxl_read_cfmws(void *opaque, hwaddr addr, uint64_t *data,
216                                   unsigned size, MemTxAttrs attrs)
217 {
218     CXLFixedWindow *fw = opaque;
219     PCIDevice *d;
220 
221     d = cxl_cfmws_find_device(fw, addr);
222     if (d == NULL) {
223         *data = 0;
224         /* Reads to invalid address return poison */
225         return MEMTX_ERROR;
226     }
227 
228     return cxl_type3_read(d, addr + fw->base, data, size, attrs);
229 }
230 
231 static MemTxResult cxl_write_cfmws(void *opaque, hwaddr addr,
232                                    uint64_t data, unsigned size,
233                                    MemTxAttrs attrs)
234 {
235     CXLFixedWindow *fw = opaque;
236     PCIDevice *d;
237 
238     d = cxl_cfmws_find_device(fw, addr);
239     if (d == NULL) {
240         /* Writes to invalid address are silent */
241         return MEMTX_OK;
242     }
243 
244     return cxl_type3_write(d, addr + fw->base, data, size, attrs);
245 }
246 
247 const MemoryRegionOps cfmws_ops = {
248     .read_with_attrs = cxl_read_cfmws,
249     .write_with_attrs = cxl_write_cfmws,
250     .endianness = DEVICE_LITTLE_ENDIAN,
251     .valid = {
252         .min_access_size = 1,
253         .max_access_size = 8,
254         .unaligned = true,
255     },
256     .impl = {
257         .min_access_size = 1,
258         .max_access_size = 8,
259         .unaligned = true,
260     },
261 };
262 
263 static void machine_get_cxl(Object *obj, Visitor *v, const char *name,
264                             void *opaque, Error **errp)
265 {
266     CXLState *cxl_state = opaque;
267     bool value = cxl_state->is_enabled;
268 
269     visit_type_bool(v, name, &value, errp);
270 }
271 
272 static void machine_set_cxl(Object *obj, Visitor *v, const char *name,
273                             void *opaque, Error **errp)
274 {
275     CXLState *cxl_state = opaque;
276     bool value;
277 
278     if (!visit_type_bool(v, name, &value, errp)) {
279         return;
280     }
281     cxl_state->is_enabled = value;
282 }
283 
284 static void machine_get_cfmw(Object *obj, Visitor *v, const char *name,
285                              void *opaque, Error **errp)
286 {
287     CXLFixedMemoryWindowOptionsList **list = opaque;
288 
289     visit_type_CXLFixedMemoryWindowOptionsList(v, name, list, errp);
290 }
291 
292 static void machine_set_cfmw(Object *obj, Visitor *v, const char *name,
293                              void *opaque, Error **errp)
294 {
295     CXLState *state = opaque;
296     CXLFixedMemoryWindowOptionsList *cfmw_list = NULL;
297     CXLFixedMemoryWindowOptionsList *it;
298 
299     visit_type_CXLFixedMemoryWindowOptionsList(v, name, &cfmw_list, errp);
300     if (!cfmw_list) {
301         return;
302     }
303 
304     for (it = cfmw_list; it; it = it->next) {
305         cxl_fixed_memory_window_config(state, it->value, errp);
306     }
307     state->cfmw_list = cfmw_list;
308 }
309 
310 void cxl_machine_init(Object *obj, CXLState *state)
311 {
312     object_property_add(obj, "cxl", "bool", machine_get_cxl,
313                         machine_set_cxl, NULL, state);
314     object_property_set_description(obj, "cxl",
315                                     "Set on/off to enable/disable "
316                                     "CXL instantiation");
317 
318     object_property_add(obj, "cxl-fmw", "CXLFixedMemoryWindow",
319                         machine_get_cfmw, machine_set_cfmw,
320                         NULL, state);
321     object_property_set_description(obj, "cxl-fmw",
322                                     "CXL Fixed Memory Windows (array)");
323 }
324 
325 void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp)
326 {
327     /* Walk the pci busses looking for pxb busses to hook up */
328     if (bus) {
329         QLIST_FOREACH(bus, &bus->child, sibling) {
330             if (!pci_bus_is_root(bus)) {
331                 continue;
332             }
333             if (pci_bus_is_cxl(bus)) {
334                 if (!state->is_enabled) {
335                     error_setg(errp, "CXL host bridges present, but cxl=off");
336                     return;
337                 }
338                 pxb_cxl_hook_up_registers(state, bus, errp);
339             }
340         }
341     }
342 }
343