xref: /openbmc/qemu/hw/cxl/cxl-host.c (revision 7bd1900b365b5e7ae498cf9c915867fcaa5296fc) 
1 /*
2  * CXL host parameter parsing routines
3  *
4  * Copyright (c) 2022 Huawei
5  * Modeled loosely on the NUMA options handling in hw/core/numa.c
6  */
7 
8 #include "qemu/osdep.h"
9 #include "qemu/units.h"
10 #include "qemu/bitmap.h"
11 #include "qemu/error-report.h"
12 #include "qapi/error.h"
13 #include "sysemu/qtest.h"
14 #include "hw/boards.h"
15 
16 #include "qapi/qapi-visit-machine.h"
17 #include "hw/cxl/cxl.h"
18 #include "hw/cxl/cxl_host.h"
19 #include "hw/pci/pci_bus.h"
20 #include "hw/pci/pci_bridge.h"
21 #include "hw/pci/pci_host.h"
22 #include "hw/pci/pcie_port.h"
23 #include "hw/pci-bridge/pci_expander_bridge.h"
24 
25 static void cxl_fixed_memory_window_config(CXLState *cxl_state,
26                                            CXLFixedMemoryWindowOptions *object,
27                                            Error **errp)
28 {
29     CXLFixedWindow *fw = g_malloc0(sizeof(*fw));
30     strList *target;
31     int i;
32 
33     for (target = object->targets; target; target = target->next) {
34         fw->num_targets++;
35     }
36 
37     fw->enc_int_ways = cxl_interleave_ways_enc(fw->num_targets, errp);
38     if (*errp) {
39         return;
40     }
41 
42     fw->targets = g_malloc0_n(fw->num_targets, sizeof(*fw->targets));
43     for (i = 0, target = object->targets; target; i++, target = target->next) {
44         /* This link cannot be resolved yet, so stash the name for now */
45         fw->targets[i] = g_strdup(target->value);
46     }
47 
48     if (object->size % (256 * MiB)) {
49         error_setg(errp,
50                    "Size of a CXL fixed memory window must my a multiple of 256MiB");
51         return;
52     }
53     fw->size = object->size;
54 
55     if (object->has_interleave_granularity) {
56         fw->enc_int_gran =
57             cxl_interleave_granularity_enc(object->interleave_granularity,
58                                            errp);
59         if (*errp) {
60             return;
61         }
62     } else {
63         /* Default to 256 byte interleave */
64         fw->enc_int_gran = 0;
65     }
66 
67     cxl_state->fixed_windows = g_list_append(cxl_state->fixed_windows, fw);
68 
69     return;
70 }
71 
72 void cxl_fmws_link_targets(CXLState *cxl_state, Error **errp)
73 {
74     if (cxl_state && cxl_state->fixed_windows) {
75         GList *it;
76 
77         for (it = cxl_state->fixed_windows; it; it = it->next) {
78             CXLFixedWindow *fw = it->data;
79             int i;
80 
81             for (i = 0; i < fw->num_targets; i++) {
82                 Object *o;
83                 bool ambig;
84 
85                 o = object_resolve_path_type(fw->targets[i],
86                                              TYPE_PXB_CXL_DEVICE,
87                                              &ambig);
88                 if (!o) {
89                     error_setg(errp, "Could not resolve CXLFM target %s",
90                                fw->targets[i]);
91                     return;
92                 }
93                 fw->target_hbs[i] = PXB_CXL_DEV(o);
94             }
95         }
96     }
97 }
98 
99 /* TODO: support, multiple hdm decoders */
100 static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr,
101                                 uint8_t *target)
102 {
103     uint32_t ctrl;
104     uint32_t ig_enc;
105     uint32_t iw_enc;
106     uint32_t target_reg;
107     uint32_t target_idx;
108 
109     ctrl = cache_mem[R_CXL_HDM_DECODER0_CTRL];
110     if (!FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED)) {
111         return false;
112     }
113 
114     ig_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IG);
115     iw_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IW);
116     target_idx = (addr / cxl_decode_ig(ig_enc)) % (1 << iw_enc);
117 
118     if (target_idx > 4) {
119         target_reg = cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO];
120         target_reg >>= target_idx * 8;
121     } else {
122         target_reg = cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO];
123         target_reg >>= (target_idx - 4) * 8;
124     }
125     *target = target_reg & 0xff;
126 
127     return true;
128 }
129 
130 static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow *fw, hwaddr addr)
131 {
132     CXLComponentState *hb_cstate;
133     PCIHostState *hb;
134     int rb_index;
135     uint32_t *cache_mem;
136     uint8_t target;
137     bool target_found;
138     PCIDevice *rp, *d;
139 
140     /* Address is relative to memory region. Convert to HPA */
141     addr += fw->base;
142 
143     rb_index = (addr / cxl_decode_ig(fw->enc_int_gran)) % fw->num_targets;
144     hb = PCI_HOST_BRIDGE(fw->target_hbs[rb_index]->cxl.cxl_host_bridge);
145     if (!hb || !hb->bus || !pci_bus_is_cxl(hb->bus)) {
146         return NULL;
147     }
148 
149     hb_cstate = cxl_get_hb_cstate(hb);
150     if (!hb_cstate) {
151         return NULL;
152     }
153 
154     cache_mem = hb_cstate->crb.cache_mem_registers;
155 
156     target_found = cxl_hdm_find_target(cache_mem, addr, &target);
157     if (!target_found) {
158         return NULL;
159     }
160 
161     rp = pcie_find_port_by_pn(hb->bus, target);
162     if (!rp) {
163         return NULL;
164     }
165 
166     d = pci_bridge_get_sec_bus(PCI_BRIDGE(rp))->devices[0];
167 
168     if (!d || !object_dynamic_cast(OBJECT(d), TYPE_CXL_TYPE3)) {
169         return NULL;
170     }
171 
172     return d;
173 }
174 
175 static MemTxResult cxl_read_cfmws(void *opaque, hwaddr addr, uint64_t *data,
176                                   unsigned size, MemTxAttrs attrs)
177 {
178     CXLFixedWindow *fw = opaque;
179     PCIDevice *d;
180 
181     d = cxl_cfmws_find_device(fw, addr);
182     if (d == NULL) {
183         *data = 0;
184         /* Reads to invalid address return poison */
185         return MEMTX_ERROR;
186     }
187 
188     return cxl_type3_read(d, addr + fw->base, data, size, attrs);
189 }
190 
191 static MemTxResult cxl_write_cfmws(void *opaque, hwaddr addr,
192                                    uint64_t data, unsigned size,
193                                    MemTxAttrs attrs)
194 {
195     CXLFixedWindow *fw = opaque;
196     PCIDevice *d;
197 
198     d = cxl_cfmws_find_device(fw, addr);
199     if (d == NULL) {
200         /* Writes to invalid address are silent */
201         return MEMTX_OK;
202     }
203 
204     return cxl_type3_write(d, addr + fw->base, data, size, attrs);
205 }
206 
207 const MemoryRegionOps cfmws_ops = {
208     .read_with_attrs = cxl_read_cfmws,
209     .write_with_attrs = cxl_write_cfmws,
210     .endianness = DEVICE_LITTLE_ENDIAN,
211     .valid = {
212         .min_access_size = 1,
213         .max_access_size = 8,
214         .unaligned = true,
215     },
216     .impl = {
217         .min_access_size = 1,
218         .max_access_size = 8,
219         .unaligned = true,
220     },
221 };
222 
223 static void machine_get_cxl(Object *obj, Visitor *v, const char *name,
224                             void *opaque, Error **errp)
225 {
226     CXLState *cxl_state = opaque;
227     bool value = cxl_state->is_enabled;
228 
229     visit_type_bool(v, name, &value, errp);
230 }
231 
232 static void machine_set_cxl(Object *obj, Visitor *v, const char *name,
233                             void *opaque, Error **errp)
234 {
235     CXLState *cxl_state = opaque;
236     bool value;
237 
238     if (!visit_type_bool(v, name, &value, errp)) {
239         return;
240     }
241     cxl_state->is_enabled = value;
242 }
243 
244 static void machine_get_cfmw(Object *obj, Visitor *v, const char *name,
245                              void *opaque, Error **errp)
246 {
247     CXLFixedMemoryWindowOptionsList **list = opaque;
248 
249     visit_type_CXLFixedMemoryWindowOptionsList(v, name, list, errp);
250 }
251 
252 static void machine_set_cfmw(Object *obj, Visitor *v, const char *name,
253                              void *opaque, Error **errp)
254 {
255     CXLState *state = opaque;
256     CXLFixedMemoryWindowOptionsList *cfmw_list = NULL;
257     CXLFixedMemoryWindowOptionsList *it;
258 
259     visit_type_CXLFixedMemoryWindowOptionsList(v, name, &cfmw_list, errp);
260     if (!cfmw_list) {
261         return;
262     }
263 
264     for (it = cfmw_list; it; it = it->next) {
265         cxl_fixed_memory_window_config(state, it->value, errp);
266     }
267     state->cfmw_list = cfmw_list;
268 }
269 
270 void cxl_machine_init(Object *obj, CXLState *state)
271 {
272     object_property_add(obj, "cxl", "bool", machine_get_cxl,
273                         machine_set_cxl, NULL, state);
274     object_property_set_description(obj, "cxl",
275                                     "Set on/off to enable/disable "
276                                     "CXL instantiation");
277 
278     object_property_add(obj, "cxl-fmw", "CXLFixedMemoryWindow",
279                         machine_get_cfmw, machine_set_cfmw,
280                         NULL, state);
281     object_property_set_description(obj, "cxl-fmw",
282                                     "CXL Fixed Memory Windows (array)");
283 }
284 
285 void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp)
286 {
287     /* Walk the pci busses looking for pxb busses to hook up */
288     if (bus) {
289         QLIST_FOREACH(bus, &bus->child, sibling) {
290             if (!pci_bus_is_root(bus)) {
291                 continue;
292             }
293             if (pci_bus_is_cxl(bus)) {
294                 if (!state->is_enabled) {
295                     error_setg(errp, "CXL host bridges present, but cxl=off");
296                     return;
297                 }
298                 pxb_cxl_hook_up_registers(state, bus, errp);
299             }
300         }
301     }
302 }
303