1 /* 2 * QEMU Machine 3 * 4 * Copyright (C) 2014 Red Hat Inc 5 * 6 * Authors: 7 * Marcel Apfelbaum <marcel.a@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/units.h" 15 #include "qemu/accel.h" 16 #include "sysemu/replay.h" 17 #include "hw/boards.h" 18 #include "hw/loader.h" 19 #include "qemu/error-report.h" 20 #include "qapi/error.h" 21 #include "qapi/qapi-visit-machine.h" 22 #include "qemu/madvise.h" 23 #include "qom/object_interfaces.h" 24 #include "sysemu/cpus.h" 25 #include "sysemu/sysemu.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/xen.h" 29 #include "sysemu/qtest.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/mem/nvdimm.h" 32 #include "migration/global_state.h" 33 #include "exec/confidential-guest-support.h" 34 #include "hw/virtio/virtio-pci.h" 35 #include "hw/virtio/virtio-net.h" 36 #include "hw/virtio/virtio-iommu.h" 37 #include "audio/audio.h" 38 39 GlobalProperty hw_compat_9_1[] = {}; 40 const size_t hw_compat_9_1_len = G_N_ELEMENTS(hw_compat_9_1); 41 42 GlobalProperty hw_compat_9_0[] = { 43 {"arm-cpu", "backcompat-cntfrq", "true" }, 44 { "scsi-hd", "migrate-emulated-scsi-request", "false" }, 45 { "scsi-cd", "migrate-emulated-scsi-request", "false" }, 46 {"vfio-pci", "skip-vsc-check", "false" }, 47 { "virtio-pci", "x-pcie-pm-no-soft-reset", "off" }, 48 {"sd-card", "spec_version", "2" }, 49 }; 50 const size_t hw_compat_9_0_len = G_N_ELEMENTS(hw_compat_9_0); 51 52 GlobalProperty hw_compat_8_2[] = { 53 { "migration", "zero-page-detection", "legacy"}, 54 { TYPE_VIRTIO_IOMMU_PCI, "granule", "4k" }, 55 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "64" }, 56 { "virtio-gpu-device", "x-scanout-vmstate-version", "1" }, 57 }; 58 const size_t hw_compat_8_2_len = G_N_ELEMENTS(hw_compat_8_2); 59 60 GlobalProperty hw_compat_8_1[] = { 61 { TYPE_PCI_BRIDGE, "x-pci-express-writeable-slt-bug", "true" }, 62 { "ramfb", "x-migrate", "off" }, 63 { "vfio-pci-nohotplug", "x-ramfb-migrate", "off" }, 64 { "igb", "x-pcie-flr-init", "off" }, 65 { TYPE_VIRTIO_NET, "host_uso", "off"}, 66 { TYPE_VIRTIO_NET, "guest_uso4", "off"}, 67 { TYPE_VIRTIO_NET, "guest_uso6", "off"}, 68 }; 69 const size_t hw_compat_8_1_len = G_N_ELEMENTS(hw_compat_8_1); 70 71 GlobalProperty hw_compat_8_0[] = { 72 { "migration", "multifd-flush-after-each-section", "on"}, 73 { TYPE_PCI_DEVICE, "x-pcie-ari-nextfn-1", "on" }, 74 }; 75 const size_t hw_compat_8_0_len = G_N_ELEMENTS(hw_compat_8_0); 76 77 GlobalProperty hw_compat_7_2[] = { 78 { "e1000e", "migrate-timadj", "off" }, 79 { "virtio-mem", "x-early-migration", "false" }, 80 { "migration", "x-preempt-pre-7-2", "true" }, 81 { TYPE_PCI_DEVICE, "x-pcie-err-unc-mask", "off" }, 82 }; 83 const size_t hw_compat_7_2_len = G_N_ELEMENTS(hw_compat_7_2); 84 85 GlobalProperty hw_compat_7_1[] = { 86 { "virtio-device", "queue_reset", "false" }, 87 { "virtio-rng-pci", "vectors", "0" }, 88 { "virtio-rng-pci-transitional", "vectors", "0" }, 89 { "virtio-rng-pci-non-transitional", "vectors", "0" }, 90 }; 91 const size_t hw_compat_7_1_len = G_N_ELEMENTS(hw_compat_7_1); 92 93 GlobalProperty hw_compat_7_0[] = { 94 { "arm-gicv3-common", "force-8-bit-prio", "on" }, 95 { "nvme-ns", "eui64-default", "on"}, 96 }; 97 const size_t hw_compat_7_0_len = G_N_ELEMENTS(hw_compat_7_0); 98 99 GlobalProperty hw_compat_6_2[] = { 100 { "PIIX4_PM", "x-not-migrate-acpi-index", "on"}, 101 }; 102 const size_t hw_compat_6_2_len = G_N_ELEMENTS(hw_compat_6_2); 103 104 GlobalProperty hw_compat_6_1[] = { 105 { "vhost-user-vsock-device", "seqpacket", "off" }, 106 { "nvme-ns", "shared", "off" }, 107 }; 108 const size_t hw_compat_6_1_len = G_N_ELEMENTS(hw_compat_6_1); 109 110 GlobalProperty hw_compat_6_0[] = { 111 { "gpex-pcihost", "allow-unmapped-accesses", "false" }, 112 { "i8042", "extended-state", "false"}, 113 { "nvme-ns", "eui64-default", "off"}, 114 { "e1000", "init-vet", "off" }, 115 { "e1000e", "init-vet", "off" }, 116 { "vhost-vsock-device", "seqpacket", "off" }, 117 }; 118 const size_t hw_compat_6_0_len = G_N_ELEMENTS(hw_compat_6_0); 119 120 GlobalProperty hw_compat_5_2[] = { 121 { "ICH9-LPC", "smm-compat", "on"}, 122 { "PIIX4_PM", "smm-compat", "on"}, 123 { "virtio-blk-device", "report-discard-granularity", "off" }, 124 { "virtio-net-pci-base", "vectors", "3"}, 125 { "nvme", "msix-exclusive-bar", "on"}, 126 }; 127 const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2); 128 129 GlobalProperty hw_compat_5_1[] = { 130 { "vhost-scsi", "num_queues", "1"}, 131 { "vhost-user-blk", "num-queues", "1"}, 132 { "vhost-user-scsi", "num_queues", "1"}, 133 { "virtio-blk-device", "num-queues", "1"}, 134 { "virtio-scsi-device", "num_queues", "1"}, 135 { "nvme", "use-intel-id", "on"}, 136 { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */ 137 { "pl011", "migrate-clk", "off" }, 138 { "virtio-pci", "x-ats-page-aligned", "off"}, 139 }; 140 const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1); 141 142 GlobalProperty hw_compat_5_0[] = { 143 { "pci-host-bridge", "x-config-reg-migration-enabled", "off" }, 144 { "virtio-balloon-device", "page-poison", "false" }, 145 { "vmport", "x-read-set-eax", "off" }, 146 { "vmport", "x-signal-unsupported-cmd", "off" }, 147 { "vmport", "x-report-vmx-type", "off" }, 148 { "vmport", "x-cmds-v2", "off" }, 149 { "virtio-device", "x-disable-legacy-check", "true" }, 150 }; 151 const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0); 152 153 GlobalProperty hw_compat_4_2[] = { 154 { "virtio-blk-device", "queue-size", "128"}, 155 { "virtio-scsi-device", "virtqueue_size", "128"}, 156 { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" }, 157 { "virtio-blk-device", "seg-max-adjust", "off"}, 158 { "virtio-scsi-device", "seg_max_adjust", "off"}, 159 { "vhost-blk-device", "seg_max_adjust", "off"}, 160 { "usb-host", "suppress-remote-wake", "off" }, 161 { "usb-redir", "suppress-remote-wake", "off" }, 162 { "qxl", "revision", "4" }, 163 { "qxl-vga", "revision", "4" }, 164 { "fw_cfg", "acpi-mr-restore", "false" }, 165 { "virtio-device", "use-disabled-flag", "false" }, 166 }; 167 const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2); 168 169 GlobalProperty hw_compat_4_1[] = { 170 { "virtio-pci", "x-pcie-flr-init", "off" }, 171 }; 172 const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1); 173 174 GlobalProperty hw_compat_4_0[] = { 175 { "VGA", "edid", "false" }, 176 { "secondary-vga", "edid", "false" }, 177 { "bochs-display", "edid", "false" }, 178 { "virtio-vga", "edid", "false" }, 179 { "virtio-gpu-device", "edid", "false" }, 180 { "virtio-device", "use-started", "false" }, 181 { "virtio-balloon-device", "qemu-4-0-config-size", "true" }, 182 { "pl031", "migrate-tick-offset", "false" }, 183 }; 184 const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0); 185 186 GlobalProperty hw_compat_3_1[] = { 187 { "pcie-root-port", "x-speed", "2_5" }, 188 { "pcie-root-port", "x-width", "1" }, 189 { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" }, 190 { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" }, 191 { "tpm-crb", "ppi", "false" }, 192 { "tpm-tis", "ppi", "false" }, 193 { "usb-kbd", "serial", "42" }, 194 { "usb-mouse", "serial", "42" }, 195 { "usb-tablet", "serial", "42" }, 196 { "virtio-blk-device", "discard", "false" }, 197 { "virtio-blk-device", "write-zeroes", "false" }, 198 { "virtio-balloon-device", "qemu-4-0-config-size", "false" }, 199 { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */ 200 }; 201 const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1); 202 203 GlobalProperty hw_compat_3_0[] = {}; 204 const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0); 205 206 GlobalProperty hw_compat_2_12[] = { 207 { "hda-audio", "use-timer", "false" }, 208 { "cirrus-vga", "global-vmstate", "true" }, 209 { "VGA", "global-vmstate", "true" }, 210 { "vmware-svga", "global-vmstate", "true" }, 211 { "qxl-vga", "global-vmstate", "true" }, 212 }; 213 const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12); 214 215 GlobalProperty hw_compat_2_11[] = { 216 { "hpet", "hpet-offset-saved", "false" }, 217 { "virtio-blk-pci", "vectors", "2" }, 218 { "vhost-user-blk-pci", "vectors", "2" }, 219 { "e1000", "migrate_tso_props", "off" }, 220 }; 221 const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11); 222 223 GlobalProperty hw_compat_2_10[] = { 224 { "virtio-mouse-device", "wheel-axis", "false" }, 225 { "virtio-tablet-device", "wheel-axis", "false" }, 226 }; 227 const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10); 228 229 GlobalProperty hw_compat_2_9[] = { 230 { "pci-bridge", "shpc", "off" }, 231 { "intel-iommu", "pt", "off" }, 232 { "virtio-net-device", "x-mtu-bypass-backend", "off" }, 233 { "pcie-root-port", "x-migrate-msix", "false" }, 234 }; 235 const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9); 236 237 GlobalProperty hw_compat_2_8[] = { 238 { "fw_cfg_mem", "x-file-slots", "0x10" }, 239 { "fw_cfg_io", "x-file-slots", "0x10" }, 240 { "pflash_cfi01", "old-multiple-chip-handling", "on" }, 241 { "pci-bridge", "shpc", "on" }, 242 { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" }, 243 { "virtio-pci", "x-pcie-deverr-init", "off" }, 244 { "virtio-pci", "x-pcie-lnkctl-init", "off" }, 245 { "virtio-pci", "x-pcie-pm-init", "off" }, 246 { "cirrus-vga", "vgamem_mb", "8" }, 247 { "isa-cirrus-vga", "vgamem_mb", "8" }, 248 }; 249 const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8); 250 251 GlobalProperty hw_compat_2_7[] = { 252 { "virtio-pci", "page-per-vq", "on" }, 253 { "virtio-serial-device", "emergency-write", "off" }, 254 { "ioapic", "version", "0x11" }, 255 { "intel-iommu", "x-buggy-eim", "true" }, 256 { "virtio-pci", "x-ignore-backend-features", "on" }, 257 }; 258 const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7); 259 260 GlobalProperty hw_compat_2_6[] = { 261 { "virtio-mmio", "format_transport_address", "off" }, 262 /* Optional because not all virtio-pci devices support legacy mode */ 263 { "virtio-pci", "disable-modern", "on", .optional = true }, 264 { "virtio-pci", "disable-legacy", "off", .optional = true }, 265 }; 266 const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6); 267 268 GlobalProperty hw_compat_2_5[] = { 269 { "isa-fdc", "fallback", "144" }, 270 { "pvscsi", "x-old-pci-configuration", "on" }, 271 { "pvscsi", "x-disable-pcie", "on" }, 272 { "vmxnet3", "x-old-msi-offsets", "on" }, 273 { "vmxnet3", "x-disable-pcie", "on" }, 274 }; 275 const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5); 276 277 GlobalProperty hw_compat_2_4[] = { 278 { "e1000", "extra_mac_registers", "off" }, 279 { "virtio-pci", "x-disable-pcie", "on" }, 280 { "virtio-pci", "migrate-extra", "off" }, 281 { "fw_cfg_mem", "dma_enabled", "off" }, 282 { "fw_cfg_io", "dma_enabled", "off" } 283 }; 284 const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4); 285 286 MachineState *current_machine; 287 288 static char *machine_get_kernel(Object *obj, Error **errp) 289 { 290 MachineState *ms = MACHINE(obj); 291 292 return g_strdup(ms->kernel_filename); 293 } 294 295 static void machine_set_kernel(Object *obj, const char *value, Error **errp) 296 { 297 MachineState *ms = MACHINE(obj); 298 299 g_free(ms->kernel_filename); 300 ms->kernel_filename = g_strdup(value); 301 } 302 303 static char *machine_get_initrd(Object *obj, Error **errp) 304 { 305 MachineState *ms = MACHINE(obj); 306 307 return g_strdup(ms->initrd_filename); 308 } 309 310 static void machine_set_initrd(Object *obj, const char *value, Error **errp) 311 { 312 MachineState *ms = MACHINE(obj); 313 314 g_free(ms->initrd_filename); 315 ms->initrd_filename = g_strdup(value); 316 } 317 318 static char *machine_get_append(Object *obj, Error **errp) 319 { 320 MachineState *ms = MACHINE(obj); 321 322 return g_strdup(ms->kernel_cmdline); 323 } 324 325 static void machine_set_append(Object *obj, const char *value, Error **errp) 326 { 327 MachineState *ms = MACHINE(obj); 328 329 g_free(ms->kernel_cmdline); 330 ms->kernel_cmdline = g_strdup(value); 331 } 332 333 static char *machine_get_dtb(Object *obj, Error **errp) 334 { 335 MachineState *ms = MACHINE(obj); 336 337 return g_strdup(ms->dtb); 338 } 339 340 static void machine_set_dtb(Object *obj, const char *value, Error **errp) 341 { 342 MachineState *ms = MACHINE(obj); 343 344 g_free(ms->dtb); 345 ms->dtb = g_strdup(value); 346 } 347 348 static char *machine_get_dumpdtb(Object *obj, Error **errp) 349 { 350 MachineState *ms = MACHINE(obj); 351 352 return g_strdup(ms->dumpdtb); 353 } 354 355 static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp) 356 { 357 MachineState *ms = MACHINE(obj); 358 359 g_free(ms->dumpdtb); 360 ms->dumpdtb = g_strdup(value); 361 } 362 363 static void machine_get_phandle_start(Object *obj, Visitor *v, 364 const char *name, void *opaque, 365 Error **errp) 366 { 367 MachineState *ms = MACHINE(obj); 368 int64_t value = ms->phandle_start; 369 370 visit_type_int(v, name, &value, errp); 371 } 372 373 static void machine_set_phandle_start(Object *obj, Visitor *v, 374 const char *name, void *opaque, 375 Error **errp) 376 { 377 MachineState *ms = MACHINE(obj); 378 int64_t value; 379 380 if (!visit_type_int(v, name, &value, errp)) { 381 return; 382 } 383 384 ms->phandle_start = value; 385 } 386 387 static char *machine_get_dt_compatible(Object *obj, Error **errp) 388 { 389 MachineState *ms = MACHINE(obj); 390 391 return g_strdup(ms->dt_compatible); 392 } 393 394 static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp) 395 { 396 MachineState *ms = MACHINE(obj); 397 398 g_free(ms->dt_compatible); 399 ms->dt_compatible = g_strdup(value); 400 } 401 402 static bool machine_get_dump_guest_core(Object *obj, Error **errp) 403 { 404 MachineState *ms = MACHINE(obj); 405 406 return ms->dump_guest_core; 407 } 408 409 static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp) 410 { 411 MachineState *ms = MACHINE(obj); 412 413 if (!value && QEMU_MADV_DONTDUMP == QEMU_MADV_INVALID) { 414 error_setg(errp, "Dumping guest memory cannot be disabled on this host"); 415 return; 416 } 417 ms->dump_guest_core = value; 418 } 419 420 static bool machine_get_mem_merge(Object *obj, Error **errp) 421 { 422 MachineState *ms = MACHINE(obj); 423 424 return ms->mem_merge; 425 } 426 427 static void machine_set_mem_merge(Object *obj, bool value, Error **errp) 428 { 429 MachineState *ms = MACHINE(obj); 430 431 if (value && QEMU_MADV_MERGEABLE == QEMU_MADV_INVALID) { 432 error_setg(errp, "Memory merging is not supported on this host"); 433 return; 434 } 435 ms->mem_merge = value; 436 } 437 438 static bool machine_get_usb(Object *obj, Error **errp) 439 { 440 MachineState *ms = MACHINE(obj); 441 442 return ms->usb; 443 } 444 445 static void machine_set_usb(Object *obj, bool value, Error **errp) 446 { 447 MachineState *ms = MACHINE(obj); 448 449 ms->usb = value; 450 ms->usb_disabled = !value; 451 } 452 453 static bool machine_get_graphics(Object *obj, Error **errp) 454 { 455 MachineState *ms = MACHINE(obj); 456 457 return ms->enable_graphics; 458 } 459 460 static void machine_set_graphics(Object *obj, bool value, Error **errp) 461 { 462 MachineState *ms = MACHINE(obj); 463 464 ms->enable_graphics = value; 465 } 466 467 static char *machine_get_firmware(Object *obj, Error **errp) 468 { 469 MachineState *ms = MACHINE(obj); 470 471 return g_strdup(ms->firmware); 472 } 473 474 static void machine_set_firmware(Object *obj, const char *value, Error **errp) 475 { 476 MachineState *ms = MACHINE(obj); 477 478 g_free(ms->firmware); 479 ms->firmware = g_strdup(value); 480 } 481 482 static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp) 483 { 484 MachineState *ms = MACHINE(obj); 485 486 ms->suppress_vmdesc = value; 487 } 488 489 static bool machine_get_suppress_vmdesc(Object *obj, Error **errp) 490 { 491 MachineState *ms = MACHINE(obj); 492 493 return ms->suppress_vmdesc; 494 } 495 496 static char *machine_get_memory_encryption(Object *obj, Error **errp) 497 { 498 MachineState *ms = MACHINE(obj); 499 500 if (ms->cgs) { 501 return g_strdup(object_get_canonical_path_component(OBJECT(ms->cgs))); 502 } 503 504 return NULL; 505 } 506 507 static void machine_set_memory_encryption(Object *obj, const char *value, 508 Error **errp) 509 { 510 Object *cgs = 511 object_resolve_path_component(object_get_objects_root(), value); 512 513 if (!cgs) { 514 error_setg(errp, "No such memory encryption object '%s'", value); 515 return; 516 } 517 518 object_property_set_link(obj, "confidential-guest-support", cgs, errp); 519 } 520 521 static void machine_check_confidential_guest_support(const Object *obj, 522 const char *name, 523 Object *new_target, 524 Error **errp) 525 { 526 /* 527 * So far the only constraint is that the target has the 528 * TYPE_CONFIDENTIAL_GUEST_SUPPORT interface, and that's checked 529 * by the QOM core 530 */ 531 } 532 533 static bool machine_get_nvdimm(Object *obj, Error **errp) 534 { 535 MachineState *ms = MACHINE(obj); 536 537 return ms->nvdimms_state->is_enabled; 538 } 539 540 static void machine_set_nvdimm(Object *obj, bool value, Error **errp) 541 { 542 MachineState *ms = MACHINE(obj); 543 544 ms->nvdimms_state->is_enabled = value; 545 } 546 547 static bool machine_get_hmat(Object *obj, Error **errp) 548 { 549 MachineState *ms = MACHINE(obj); 550 551 return ms->numa_state->hmat_enabled; 552 } 553 554 static void machine_set_hmat(Object *obj, bool value, Error **errp) 555 { 556 MachineState *ms = MACHINE(obj); 557 558 ms->numa_state->hmat_enabled = value; 559 } 560 561 static void machine_get_mem(Object *obj, Visitor *v, const char *name, 562 void *opaque, Error **errp) 563 { 564 MachineState *ms = MACHINE(obj); 565 MemorySizeConfiguration mem = { 566 .has_size = true, 567 .size = ms->ram_size, 568 .has_max_size = !!ms->ram_slots, 569 .max_size = ms->maxram_size, 570 .has_slots = !!ms->ram_slots, 571 .slots = ms->ram_slots, 572 }; 573 MemorySizeConfiguration *p_mem = &mem; 574 575 visit_type_MemorySizeConfiguration(v, name, &p_mem, &error_abort); 576 } 577 578 static void machine_set_mem(Object *obj, Visitor *v, const char *name, 579 void *opaque, Error **errp) 580 { 581 ERRP_GUARD(); 582 MachineState *ms = MACHINE(obj); 583 MachineClass *mc = MACHINE_GET_CLASS(obj); 584 MemorySizeConfiguration *mem; 585 586 if (!visit_type_MemorySizeConfiguration(v, name, &mem, errp)) { 587 return; 588 } 589 590 if (!mem->has_size) { 591 mem->has_size = true; 592 mem->size = mc->default_ram_size; 593 } 594 mem->size = QEMU_ALIGN_UP(mem->size, 8192); 595 if (mc->fixup_ram_size) { 596 mem->size = mc->fixup_ram_size(mem->size); 597 } 598 if ((ram_addr_t)mem->size != mem->size) { 599 error_setg(errp, "ram size too large"); 600 goto out_free; 601 } 602 603 if (mem->has_max_size) { 604 if (mem->max_size < mem->size) { 605 error_setg(errp, "invalid value of maxmem: " 606 "maximum memory size (0x%" PRIx64 ") must be at least " 607 "the initial memory size (0x%" PRIx64 ")", 608 mem->max_size, mem->size); 609 goto out_free; 610 } 611 if (mem->has_slots && mem->slots && mem->max_size == mem->size) { 612 error_setg(errp, "invalid value of maxmem: " 613 "memory slots were specified but maximum memory size " 614 "(0x%" PRIx64 ") is equal to the initial memory size " 615 "(0x%" PRIx64 ")", mem->max_size, mem->size); 616 goto out_free; 617 } 618 ms->maxram_size = mem->max_size; 619 } else { 620 if (mem->has_slots) { 621 error_setg(errp, "slots specified but no max-size"); 622 goto out_free; 623 } 624 ms->maxram_size = mem->size; 625 } 626 ms->ram_size = mem->size; 627 ms->ram_slots = mem->has_slots ? mem->slots : 0; 628 out_free: 629 qapi_free_MemorySizeConfiguration(mem); 630 } 631 632 static char *machine_get_nvdimm_persistence(Object *obj, Error **errp) 633 { 634 MachineState *ms = MACHINE(obj); 635 636 return g_strdup(ms->nvdimms_state->persistence_string); 637 } 638 639 static void machine_set_nvdimm_persistence(Object *obj, const char *value, 640 Error **errp) 641 { 642 MachineState *ms = MACHINE(obj); 643 NVDIMMState *nvdimms_state = ms->nvdimms_state; 644 645 if (strcmp(value, "cpu") == 0) { 646 nvdimms_state->persistence = 3; 647 } else if (strcmp(value, "mem-ctrl") == 0) { 648 nvdimms_state->persistence = 2; 649 } else { 650 error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option", 651 value); 652 return; 653 } 654 655 g_free(nvdimms_state->persistence_string); 656 nvdimms_state->persistence_string = g_strdup(value); 657 } 658 659 void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type) 660 { 661 QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type)); 662 } 663 664 bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev) 665 { 666 Object *obj = OBJECT(dev); 667 668 if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) { 669 return false; 670 } 671 672 return device_type_is_dynamic_sysbus(mc, object_get_typename(obj)); 673 } 674 675 bool device_type_is_dynamic_sysbus(MachineClass *mc, const char *type) 676 { 677 bool allowed = false; 678 strList *wl; 679 ObjectClass *klass = object_class_by_name(type); 680 681 for (wl = mc->allowed_dynamic_sysbus_devices; 682 !allowed && wl; 683 wl = wl->next) { 684 allowed |= !!object_class_dynamic_cast(klass, wl->value); 685 } 686 687 return allowed; 688 } 689 690 static char *machine_get_audiodev(Object *obj, Error **errp) 691 { 692 MachineState *ms = MACHINE(obj); 693 694 return g_strdup(ms->audiodev); 695 } 696 697 static void machine_set_audiodev(Object *obj, const char *value, 698 Error **errp) 699 { 700 MachineState *ms = MACHINE(obj); 701 702 if (!audio_state_by_name(value, errp)) { 703 return; 704 } 705 706 g_free(ms->audiodev); 707 ms->audiodev = g_strdup(value); 708 } 709 710 HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine) 711 { 712 int i; 713 HotpluggableCPUList *head = NULL; 714 MachineClass *mc = MACHINE_GET_CLASS(machine); 715 716 /* force board to initialize possible_cpus if it hasn't been done yet */ 717 mc->possible_cpu_arch_ids(machine); 718 719 for (i = 0; i < machine->possible_cpus->len; i++) { 720 CPUState *cpu; 721 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); 722 723 cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type); 724 cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count; 725 cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props, 726 sizeof(*cpu_item->props)); 727 728 cpu = machine->possible_cpus->cpus[i].cpu; 729 if (cpu) { 730 cpu_item->qom_path = object_get_canonical_path(OBJECT(cpu)); 731 } 732 QAPI_LIST_PREPEND(head, cpu_item); 733 } 734 return head; 735 } 736 737 /** 738 * machine_set_cpu_numa_node: 739 * @machine: machine object to modify 740 * @props: specifies which cpu objects to assign to 741 * numa node specified by @props.node_id 742 * @errp: if an error occurs, a pointer to an area to store the error 743 * 744 * Associate NUMA node specified by @props.node_id with cpu slots that 745 * match socket/core/thread-ids specified by @props. It's recommended to use 746 * query-hotpluggable-cpus.props values to specify affected cpu slots, 747 * which would lead to exact 1:1 mapping of cpu slots to NUMA node. 748 * 749 * However for CLI convenience it's possible to pass in subset of properties, 750 * which would affect all cpu slots that match it. 751 * Ex for pc machine: 752 * -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \ 753 * -numa cpu,node-id=0,socket_id=0 \ 754 * -numa cpu,node-id=1,socket_id=1 755 * will assign all child cores of socket 0 to node 0 and 756 * of socket 1 to node 1. 757 * 758 * On attempt of reassigning (already assigned) cpu slot to another NUMA node, 759 * return error. 760 * Empty subset is disallowed and function will return with error in this case. 761 */ 762 void machine_set_cpu_numa_node(MachineState *machine, 763 const CpuInstanceProperties *props, Error **errp) 764 { 765 MachineClass *mc = MACHINE_GET_CLASS(machine); 766 NodeInfo *numa_info = machine->numa_state->nodes; 767 bool match = false; 768 int i; 769 770 if (!mc->possible_cpu_arch_ids) { 771 error_setg(errp, "mapping of CPUs to NUMA node is not supported"); 772 return; 773 } 774 775 /* disabling node mapping is not supported, forbid it */ 776 assert(props->has_node_id); 777 778 /* force board to initialize possible_cpus if it hasn't been done yet */ 779 mc->possible_cpu_arch_ids(machine); 780 781 for (i = 0; i < machine->possible_cpus->len; i++) { 782 CPUArchId *slot = &machine->possible_cpus->cpus[i]; 783 784 /* reject unsupported by board properties */ 785 if (props->has_thread_id && !slot->props.has_thread_id) { 786 error_setg(errp, "thread-id is not supported"); 787 return; 788 } 789 790 if (props->has_core_id && !slot->props.has_core_id) { 791 error_setg(errp, "core-id is not supported"); 792 return; 793 } 794 795 if (props->has_module_id && !slot->props.has_module_id) { 796 error_setg(errp, "module-id is not supported"); 797 return; 798 } 799 800 if (props->has_cluster_id && !slot->props.has_cluster_id) { 801 error_setg(errp, "cluster-id is not supported"); 802 return; 803 } 804 805 if (props->has_socket_id && !slot->props.has_socket_id) { 806 error_setg(errp, "socket-id is not supported"); 807 return; 808 } 809 810 if (props->has_die_id && !slot->props.has_die_id) { 811 error_setg(errp, "die-id is not supported"); 812 return; 813 } 814 815 /* skip slots with explicit mismatch */ 816 if (props->has_thread_id && props->thread_id != slot->props.thread_id) { 817 continue; 818 } 819 820 if (props->has_core_id && props->core_id != slot->props.core_id) { 821 continue; 822 } 823 824 if (props->has_module_id && 825 props->module_id != slot->props.module_id) { 826 continue; 827 } 828 829 if (props->has_cluster_id && 830 props->cluster_id != slot->props.cluster_id) { 831 continue; 832 } 833 834 if (props->has_die_id && props->die_id != slot->props.die_id) { 835 continue; 836 } 837 838 if (props->has_socket_id && props->socket_id != slot->props.socket_id) { 839 continue; 840 } 841 842 /* reject assignment if slot is already assigned, for compatibility 843 * of legacy cpu_index mapping with SPAPR core based mapping do not 844 * error out if cpu thread and matched core have the same node-id */ 845 if (slot->props.has_node_id && 846 slot->props.node_id != props->node_id) { 847 error_setg(errp, "CPU is already assigned to node-id: %" PRId64, 848 slot->props.node_id); 849 return; 850 } 851 852 /* assign slot to node as it's matched '-numa cpu' key */ 853 match = true; 854 slot->props.node_id = props->node_id; 855 slot->props.has_node_id = props->has_node_id; 856 857 if (machine->numa_state->hmat_enabled) { 858 if ((numa_info[props->node_id].initiator < MAX_NODES) && 859 (props->node_id != numa_info[props->node_id].initiator)) { 860 error_setg(errp, "The initiator of CPU NUMA node %" PRId64 861 " should be itself (got %" PRIu16 ")", 862 props->node_id, numa_info[props->node_id].initiator); 863 return; 864 } 865 numa_info[props->node_id].has_cpu = true; 866 numa_info[props->node_id].initiator = props->node_id; 867 } 868 } 869 870 if (!match) { 871 error_setg(errp, "no match found"); 872 } 873 } 874 875 static void machine_get_smp(Object *obj, Visitor *v, const char *name, 876 void *opaque, Error **errp) 877 { 878 MachineState *ms = MACHINE(obj); 879 SMPConfiguration *config = &(SMPConfiguration){ 880 .has_cpus = true, .cpus = ms->smp.cpus, 881 .has_drawers = true, .drawers = ms->smp.drawers, 882 .has_books = true, .books = ms->smp.books, 883 .has_sockets = true, .sockets = ms->smp.sockets, 884 .has_dies = true, .dies = ms->smp.dies, 885 .has_clusters = true, .clusters = ms->smp.clusters, 886 .has_modules = true, .modules = ms->smp.modules, 887 .has_cores = true, .cores = ms->smp.cores, 888 .has_threads = true, .threads = ms->smp.threads, 889 .has_maxcpus = true, .maxcpus = ms->smp.max_cpus, 890 }; 891 892 if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) { 893 return; 894 } 895 } 896 897 static void machine_set_smp(Object *obj, Visitor *v, const char *name, 898 void *opaque, Error **errp) 899 { 900 MachineState *ms = MACHINE(obj); 901 g_autoptr(SMPConfiguration) config = NULL; 902 903 if (!visit_type_SMPConfiguration(v, name, &config, errp)) { 904 return; 905 } 906 907 machine_parse_smp_config(ms, config, errp); 908 } 909 910 static void machine_get_smp_cache(Object *obj, Visitor *v, const char *name, 911 void *opaque, Error **errp) 912 { 913 MachineState *ms = MACHINE(obj); 914 SmpCache *cache = &ms->smp_cache; 915 SmpCachePropertiesList *head = NULL; 916 SmpCachePropertiesList **tail = &head; 917 918 for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) { 919 SmpCacheProperties *node = g_new(SmpCacheProperties, 1); 920 921 node->cache = cache->props[i].cache; 922 node->topology = cache->props[i].topology; 923 QAPI_LIST_APPEND(tail, node); 924 } 925 926 visit_type_SmpCachePropertiesList(v, name, &head, errp); 927 qapi_free_SmpCachePropertiesList(head); 928 } 929 930 static void machine_set_smp_cache(Object *obj, Visitor *v, const char *name, 931 void *opaque, Error **errp) 932 { 933 MachineState *ms = MACHINE(obj); 934 SmpCachePropertiesList *caches; 935 936 if (!visit_type_SmpCachePropertiesList(v, name, &caches, errp)) { 937 return; 938 } 939 940 machine_parse_smp_cache(ms, caches, errp); 941 qapi_free_SmpCachePropertiesList(caches); 942 } 943 944 static void machine_get_boot(Object *obj, Visitor *v, const char *name, 945 void *opaque, Error **errp) 946 { 947 MachineState *ms = MACHINE(obj); 948 BootConfiguration *config = &ms->boot_config; 949 visit_type_BootConfiguration(v, name, &config, &error_abort); 950 } 951 952 static void machine_free_boot_config(MachineState *ms) 953 { 954 g_free(ms->boot_config.order); 955 g_free(ms->boot_config.once); 956 g_free(ms->boot_config.splash); 957 } 958 959 static void machine_copy_boot_config(MachineState *ms, BootConfiguration *config) 960 { 961 MachineClass *machine_class = MACHINE_GET_CLASS(ms); 962 963 machine_free_boot_config(ms); 964 ms->boot_config = *config; 965 if (!config->order) { 966 ms->boot_config.order = g_strdup(machine_class->default_boot_order); 967 } 968 } 969 970 static void machine_set_boot(Object *obj, Visitor *v, const char *name, 971 void *opaque, Error **errp) 972 { 973 ERRP_GUARD(); 974 MachineState *ms = MACHINE(obj); 975 BootConfiguration *config = NULL; 976 977 if (!visit_type_BootConfiguration(v, name, &config, errp)) { 978 return; 979 } 980 if (config->order) { 981 validate_bootdevices(config->order, errp); 982 if (*errp) { 983 goto out_free; 984 } 985 } 986 if (config->once) { 987 validate_bootdevices(config->once, errp); 988 if (*errp) { 989 goto out_free; 990 } 991 } 992 993 machine_copy_boot_config(ms, config); 994 /* Strings live in ms->boot_config. */ 995 free(config); 996 return; 997 998 out_free: 999 qapi_free_BootConfiguration(config); 1000 } 1001 1002 void machine_add_audiodev_property(MachineClass *mc) 1003 { 1004 ObjectClass *oc = OBJECT_CLASS(mc); 1005 1006 object_class_property_add_str(oc, "audiodev", 1007 machine_get_audiodev, 1008 machine_set_audiodev); 1009 object_class_property_set_description(oc, "audiodev", 1010 "Audiodev to use for default machine devices"); 1011 } 1012 1013 static bool create_default_memdev(MachineState *ms, const char *path, 1014 Error **errp) 1015 { 1016 Object *obj; 1017 MachineClass *mc = MACHINE_GET_CLASS(ms); 1018 bool r = false; 1019 1020 obj = object_new(path ? TYPE_MEMORY_BACKEND_FILE : TYPE_MEMORY_BACKEND_RAM); 1021 if (path) { 1022 if (!object_property_set_str(obj, "mem-path", path, errp)) { 1023 goto out; 1024 } 1025 } 1026 if (!object_property_set_int(obj, "size", ms->ram_size, errp)) { 1027 goto out; 1028 } 1029 object_property_add_child(object_get_objects_root(), mc->default_ram_id, 1030 obj); 1031 /* Ensure backend's memory region name is equal to mc->default_ram_id */ 1032 if (!object_property_set_bool(obj, "x-use-canonical-path-for-ramblock-id", 1033 false, errp)) { 1034 goto out; 1035 } 1036 if (!user_creatable_complete(USER_CREATABLE(obj), errp)) { 1037 goto out; 1038 } 1039 r = object_property_set_link(OBJECT(ms), "memory-backend", obj, errp); 1040 1041 out: 1042 object_unref(obj); 1043 return r; 1044 } 1045 1046 static void machine_class_init(ObjectClass *oc, void *data) 1047 { 1048 MachineClass *mc = MACHINE_CLASS(oc); 1049 1050 /* Default 128 MB as guest ram size */ 1051 mc->default_ram_size = 128 * MiB; 1052 mc->rom_file_has_mr = true; 1053 /* 1054 * SMBIOS 3.1.0 7.18.5 Memory Device — Extended Size 1055 * use max possible value that could be encoded into 1056 * 'Extended Size' field (2047Tb). 1057 */ 1058 mc->smbios_memory_device_size = 2047 * TiB; 1059 1060 /* numa node memory size aligned on 8MB by default. 1061 * On Linux, each node's border has to be 8MB aligned 1062 */ 1063 mc->numa_mem_align_shift = 23; 1064 1065 mc->create_default_memdev = create_default_memdev; 1066 1067 object_class_property_add_str(oc, "kernel", 1068 machine_get_kernel, machine_set_kernel); 1069 object_class_property_set_description(oc, "kernel", 1070 "Linux kernel image file"); 1071 1072 object_class_property_add_str(oc, "initrd", 1073 machine_get_initrd, machine_set_initrd); 1074 object_class_property_set_description(oc, "initrd", 1075 "Linux initial ramdisk file"); 1076 1077 object_class_property_add_str(oc, "append", 1078 machine_get_append, machine_set_append); 1079 object_class_property_set_description(oc, "append", 1080 "Linux kernel command line"); 1081 1082 object_class_property_add_str(oc, "dtb", 1083 machine_get_dtb, machine_set_dtb); 1084 object_class_property_set_description(oc, "dtb", 1085 "Linux kernel device tree file"); 1086 1087 object_class_property_add_str(oc, "dumpdtb", 1088 machine_get_dumpdtb, machine_set_dumpdtb); 1089 object_class_property_set_description(oc, "dumpdtb", 1090 "Dump current dtb to a file and quit"); 1091 1092 object_class_property_add(oc, "boot", "BootConfiguration", 1093 machine_get_boot, machine_set_boot, 1094 NULL, NULL); 1095 object_class_property_set_description(oc, "boot", 1096 "Boot configuration"); 1097 1098 object_class_property_add(oc, "smp", "SMPConfiguration", 1099 machine_get_smp, machine_set_smp, 1100 NULL, NULL); 1101 object_class_property_set_description(oc, "smp", 1102 "CPU topology"); 1103 1104 object_class_property_add(oc, "smp-cache", "SmpCachePropertiesWrapper", 1105 machine_get_smp_cache, machine_set_smp_cache, NULL, NULL); 1106 object_class_property_set_description(oc, "smp-cache", 1107 "Cache properties list for SMP machine"); 1108 1109 object_class_property_add(oc, "phandle-start", "int", 1110 machine_get_phandle_start, machine_set_phandle_start, 1111 NULL, NULL); 1112 object_class_property_set_description(oc, "phandle-start", 1113 "The first phandle ID we may generate dynamically"); 1114 1115 object_class_property_add_str(oc, "dt-compatible", 1116 machine_get_dt_compatible, machine_set_dt_compatible); 1117 object_class_property_set_description(oc, "dt-compatible", 1118 "Overrides the \"compatible\" property of the dt root node"); 1119 1120 object_class_property_add_bool(oc, "dump-guest-core", 1121 machine_get_dump_guest_core, machine_set_dump_guest_core); 1122 object_class_property_set_description(oc, "dump-guest-core", 1123 "Include guest memory in a core dump"); 1124 1125 object_class_property_add_bool(oc, "mem-merge", 1126 machine_get_mem_merge, machine_set_mem_merge); 1127 object_class_property_set_description(oc, "mem-merge", 1128 "Enable/disable memory merge support"); 1129 1130 object_class_property_add_bool(oc, "usb", 1131 machine_get_usb, machine_set_usb); 1132 object_class_property_set_description(oc, "usb", 1133 "Set on/off to enable/disable usb"); 1134 1135 object_class_property_add_bool(oc, "graphics", 1136 machine_get_graphics, machine_set_graphics); 1137 object_class_property_set_description(oc, "graphics", 1138 "Set on/off to enable/disable graphics emulation"); 1139 1140 object_class_property_add_str(oc, "firmware", 1141 machine_get_firmware, machine_set_firmware); 1142 object_class_property_set_description(oc, "firmware", 1143 "Firmware image"); 1144 1145 object_class_property_add_bool(oc, "suppress-vmdesc", 1146 machine_get_suppress_vmdesc, machine_set_suppress_vmdesc); 1147 object_class_property_set_description(oc, "suppress-vmdesc", 1148 "Set on to disable self-describing migration"); 1149 1150 object_class_property_add_link(oc, "confidential-guest-support", 1151 TYPE_CONFIDENTIAL_GUEST_SUPPORT, 1152 offsetof(MachineState, cgs), 1153 machine_check_confidential_guest_support, 1154 OBJ_PROP_LINK_STRONG); 1155 object_class_property_set_description(oc, "confidential-guest-support", 1156 "Set confidential guest scheme to support"); 1157 1158 /* For compatibility */ 1159 object_class_property_add_str(oc, "memory-encryption", 1160 machine_get_memory_encryption, machine_set_memory_encryption); 1161 object_class_property_set_description(oc, "memory-encryption", 1162 "Set memory encryption object to use"); 1163 1164 object_class_property_add_link(oc, "memory-backend", TYPE_MEMORY_BACKEND, 1165 offsetof(MachineState, memdev), object_property_allow_set_link, 1166 OBJ_PROP_LINK_STRONG); 1167 object_class_property_set_description(oc, "memory-backend", 1168 "Set RAM backend" 1169 "Valid value is ID of hostmem based backend"); 1170 1171 object_class_property_add(oc, "memory", "MemorySizeConfiguration", 1172 machine_get_mem, machine_set_mem, 1173 NULL, NULL); 1174 object_class_property_set_description(oc, "memory", 1175 "Memory size configuration"); 1176 } 1177 1178 static void machine_class_base_init(ObjectClass *oc, void *data) 1179 { 1180 MachineClass *mc = MACHINE_CLASS(oc); 1181 mc->max_cpus = mc->max_cpus ?: 1; 1182 mc->min_cpus = mc->min_cpus ?: 1; 1183 mc->default_cpus = mc->default_cpus ?: 1; 1184 1185 if (!object_class_is_abstract(oc)) { 1186 const char *cname = object_class_get_name(oc); 1187 assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX)); 1188 mc->name = g_strndup(cname, 1189 strlen(cname) - strlen(TYPE_MACHINE_SUFFIX)); 1190 mc->compat_props = g_ptr_array_new(); 1191 } 1192 } 1193 1194 static void machine_initfn(Object *obj) 1195 { 1196 MachineState *ms = MACHINE(obj); 1197 MachineClass *mc = MACHINE_GET_CLASS(obj); 1198 1199 container_get(obj, "/peripheral"); 1200 container_get(obj, "/peripheral-anon"); 1201 1202 ms->dump_guest_core = true; 1203 ms->mem_merge = (QEMU_MADV_MERGEABLE != QEMU_MADV_INVALID); 1204 ms->enable_graphics = true; 1205 ms->kernel_cmdline = g_strdup(""); 1206 ms->ram_size = mc->default_ram_size; 1207 ms->maxram_size = mc->default_ram_size; 1208 1209 if (mc->nvdimm_supported) { 1210 ms->nvdimms_state = g_new0(NVDIMMState, 1); 1211 object_property_add_bool(obj, "nvdimm", 1212 machine_get_nvdimm, machine_set_nvdimm); 1213 object_property_set_description(obj, "nvdimm", 1214 "Set on/off to enable/disable " 1215 "NVDIMM instantiation"); 1216 1217 object_property_add_str(obj, "nvdimm-persistence", 1218 machine_get_nvdimm_persistence, 1219 machine_set_nvdimm_persistence); 1220 object_property_set_description(obj, "nvdimm-persistence", 1221 "Set NVDIMM persistence" 1222 "Valid values are cpu, mem-ctrl"); 1223 } 1224 1225 if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) { 1226 ms->numa_state = g_new0(NumaState, 1); 1227 object_property_add_bool(obj, "hmat", 1228 machine_get_hmat, machine_set_hmat); 1229 object_property_set_description(obj, "hmat", 1230 "Set on/off to enable/disable " 1231 "ACPI Heterogeneous Memory Attribute " 1232 "Table (HMAT)"); 1233 } 1234 1235 /* default to mc->default_cpus */ 1236 ms->smp.cpus = mc->default_cpus; 1237 ms->smp.max_cpus = mc->default_cpus; 1238 ms->smp.drawers = 1; 1239 ms->smp.books = 1; 1240 ms->smp.sockets = 1; 1241 ms->smp.dies = 1; 1242 ms->smp.clusters = 1; 1243 ms->smp.modules = 1; 1244 ms->smp.cores = 1; 1245 ms->smp.threads = 1; 1246 1247 for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) { 1248 ms->smp_cache.props[i].cache = (CacheLevelAndType)i; 1249 ms->smp_cache.props[i].topology = CPU_TOPOLOGY_LEVEL_DEFAULT; 1250 } 1251 1252 machine_copy_boot_config(ms, &(BootConfiguration){ 0 }); 1253 } 1254 1255 static void machine_finalize(Object *obj) 1256 { 1257 MachineState *ms = MACHINE(obj); 1258 1259 machine_free_boot_config(ms); 1260 g_free(ms->kernel_filename); 1261 g_free(ms->initrd_filename); 1262 g_free(ms->kernel_cmdline); 1263 g_free(ms->dtb); 1264 g_free(ms->dumpdtb); 1265 g_free(ms->dt_compatible); 1266 g_free(ms->firmware); 1267 g_free(ms->device_memory); 1268 g_free(ms->nvdimms_state); 1269 g_free(ms->numa_state); 1270 g_free(ms->audiodev); 1271 } 1272 1273 bool machine_usb(MachineState *machine) 1274 { 1275 return machine->usb; 1276 } 1277 1278 int machine_phandle_start(MachineState *machine) 1279 { 1280 return machine->phandle_start; 1281 } 1282 1283 bool machine_dump_guest_core(MachineState *machine) 1284 { 1285 return machine->dump_guest_core; 1286 } 1287 1288 bool machine_mem_merge(MachineState *machine) 1289 { 1290 return machine->mem_merge; 1291 } 1292 1293 bool machine_require_guest_memfd(MachineState *machine) 1294 { 1295 return machine->cgs && machine->cgs->require_guest_memfd; 1296 } 1297 1298 static char *cpu_slot_to_string(const CPUArchId *cpu) 1299 { 1300 GString *s = g_string_new(NULL); 1301 if (cpu->props.has_socket_id) { 1302 g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id); 1303 } 1304 if (cpu->props.has_die_id) { 1305 if (s->len) { 1306 g_string_append_printf(s, ", "); 1307 } 1308 g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); 1309 } 1310 if (cpu->props.has_cluster_id) { 1311 if (s->len) { 1312 g_string_append_printf(s, ", "); 1313 } 1314 g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id); 1315 } 1316 if (cpu->props.has_module_id) { 1317 if (s->len) { 1318 g_string_append_printf(s, ", "); 1319 } 1320 g_string_append_printf(s, "module-id: %"PRId64, cpu->props.module_id); 1321 } 1322 if (cpu->props.has_core_id) { 1323 if (s->len) { 1324 g_string_append_printf(s, ", "); 1325 } 1326 g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id); 1327 } 1328 if (cpu->props.has_thread_id) { 1329 if (s->len) { 1330 g_string_append_printf(s, ", "); 1331 } 1332 g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id); 1333 } 1334 return g_string_free(s, false); 1335 } 1336 1337 static void numa_validate_initiator(NumaState *numa_state) 1338 { 1339 int i; 1340 NodeInfo *numa_info = numa_state->nodes; 1341 1342 for (i = 0; i < numa_state->num_nodes; i++) { 1343 if (numa_info[i].initiator == MAX_NODES) { 1344 continue; 1345 } 1346 1347 if (!numa_info[numa_info[i].initiator].present) { 1348 error_report("NUMA node %" PRIu16 " is missing, use " 1349 "'-numa node' option to declare it first", 1350 numa_info[i].initiator); 1351 exit(1); 1352 } 1353 1354 if (!numa_info[numa_info[i].initiator].has_cpu) { 1355 error_report("The initiator of NUMA node %d is invalid", i); 1356 exit(1); 1357 } 1358 } 1359 } 1360 1361 static void machine_numa_finish_cpu_init(MachineState *machine) 1362 { 1363 int i; 1364 bool default_mapping; 1365 GString *s = g_string_new(NULL); 1366 MachineClass *mc = MACHINE_GET_CLASS(machine); 1367 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine); 1368 1369 assert(machine->numa_state->num_nodes); 1370 for (i = 0; i < possible_cpus->len; i++) { 1371 if (possible_cpus->cpus[i].props.has_node_id) { 1372 break; 1373 } 1374 } 1375 default_mapping = (i == possible_cpus->len); 1376 1377 for (i = 0; i < possible_cpus->len; i++) { 1378 const CPUArchId *cpu_slot = &possible_cpus->cpus[i]; 1379 1380 if (!cpu_slot->props.has_node_id) { 1381 /* fetch default mapping from board and enable it */ 1382 CpuInstanceProperties props = cpu_slot->props; 1383 1384 props.node_id = mc->get_default_cpu_node_id(machine, i); 1385 if (!default_mapping) { 1386 /* record slots with not set mapping, 1387 * TODO: make it hard error in future */ 1388 char *cpu_str = cpu_slot_to_string(cpu_slot); 1389 g_string_append_printf(s, "%sCPU %d [%s]", 1390 s->len ? ", " : "", i, cpu_str); 1391 g_free(cpu_str); 1392 1393 /* non mapped cpus used to fallback to node 0 */ 1394 props.node_id = 0; 1395 } 1396 1397 props.has_node_id = true; 1398 machine_set_cpu_numa_node(machine, &props, &error_fatal); 1399 } 1400 } 1401 1402 if (machine->numa_state->hmat_enabled) { 1403 numa_validate_initiator(machine->numa_state); 1404 } 1405 1406 if (s->len && !qtest_enabled()) { 1407 warn_report("CPU(s) not present in any NUMA nodes: %s", 1408 s->str); 1409 warn_report("All CPU(s) up to maxcpus should be described " 1410 "in NUMA config, ability to start up with partial NUMA " 1411 "mappings is obsoleted and will be removed in future"); 1412 } 1413 g_string_free(s, true); 1414 } 1415 1416 static void validate_cpu_cluster_to_numa_boundary(MachineState *ms) 1417 { 1418 MachineClass *mc = MACHINE_GET_CLASS(ms); 1419 NumaState *state = ms->numa_state; 1420 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1421 const CPUArchId *cpus = possible_cpus->cpus; 1422 int i, j; 1423 1424 if (qtest_enabled() || state->num_nodes <= 1 || possible_cpus->len <= 1) { 1425 return; 1426 } 1427 1428 /* 1429 * The Linux scheduling domain can't be parsed when the multiple CPUs 1430 * in one cluster have been associated with different NUMA nodes. However, 1431 * it's fine to associate one NUMA node with CPUs in different clusters. 1432 */ 1433 for (i = 0; i < possible_cpus->len; i++) { 1434 for (j = i + 1; j < possible_cpus->len; j++) { 1435 if (cpus[i].props.has_socket_id && 1436 cpus[i].props.has_cluster_id && 1437 cpus[i].props.has_node_id && 1438 cpus[j].props.has_socket_id && 1439 cpus[j].props.has_cluster_id && 1440 cpus[j].props.has_node_id && 1441 cpus[i].props.socket_id == cpus[j].props.socket_id && 1442 cpus[i].props.cluster_id == cpus[j].props.cluster_id && 1443 cpus[i].props.node_id != cpus[j].props.node_id) { 1444 warn_report("CPU-%d and CPU-%d in socket-%" PRId64 "-cluster-%" PRId64 1445 " have been associated with node-%" PRId64 " and node-%" PRId64 1446 " respectively. It can cause OSes like Linux to" 1447 " misbehave", i, j, cpus[i].props.socket_id, 1448 cpus[i].props.cluster_id, cpus[i].props.node_id, 1449 cpus[j].props.node_id); 1450 } 1451 } 1452 } 1453 } 1454 1455 MemoryRegion *machine_consume_memdev(MachineState *machine, 1456 HostMemoryBackend *backend) 1457 { 1458 MemoryRegion *ret = host_memory_backend_get_memory(backend); 1459 1460 if (host_memory_backend_is_mapped(backend)) { 1461 error_report("memory backend %s can't be used multiple times.", 1462 object_get_canonical_path_component(OBJECT(backend))); 1463 exit(EXIT_FAILURE); 1464 } 1465 host_memory_backend_set_mapped(backend, true); 1466 vmstate_register_ram_global(ret); 1467 return ret; 1468 } 1469 1470 const char *machine_class_default_cpu_type(MachineClass *mc) 1471 { 1472 if (mc->valid_cpu_types && !mc->valid_cpu_types[1]) { 1473 /* Only a single CPU type allowed: use it as default. */ 1474 return mc->valid_cpu_types[0]; 1475 } 1476 return mc->default_cpu_type; 1477 } 1478 1479 static bool is_cpu_type_supported(const MachineState *machine, Error **errp) 1480 { 1481 MachineClass *mc = MACHINE_GET_CLASS(machine); 1482 ObjectClass *oc = object_class_by_name(machine->cpu_type); 1483 CPUClass *cc; 1484 int i; 1485 1486 /* 1487 * Check if the user specified CPU type is supported when the valid 1488 * CPU types have been determined. Note that the user specified CPU 1489 * type is provided through '-cpu' option. 1490 */ 1491 if (mc->valid_cpu_types) { 1492 assert(mc->valid_cpu_types[0] != NULL); 1493 for (i = 0; mc->valid_cpu_types[i]; i++) { 1494 if (object_class_dynamic_cast(oc, mc->valid_cpu_types[i])) { 1495 break; 1496 } 1497 } 1498 1499 /* The user specified CPU type isn't valid */ 1500 if (!mc->valid_cpu_types[i]) { 1501 g_autofree char *requested = cpu_model_from_type(machine->cpu_type); 1502 error_setg(errp, "Invalid CPU model: %s", requested); 1503 if (!mc->valid_cpu_types[1]) { 1504 g_autofree char *model = cpu_model_from_type( 1505 mc->valid_cpu_types[0]); 1506 error_append_hint(errp, "The only valid type is: %s\n", model); 1507 } else { 1508 error_append_hint(errp, "The valid models are: "); 1509 for (i = 0; mc->valid_cpu_types[i]; i++) { 1510 g_autofree char *model = cpu_model_from_type( 1511 mc->valid_cpu_types[i]); 1512 error_append_hint(errp, "%s%s", 1513 model, 1514 mc->valid_cpu_types[i + 1] ? ", " : ""); 1515 } 1516 error_append_hint(errp, "\n"); 1517 } 1518 1519 return false; 1520 } 1521 } 1522 1523 /* Check if CPU type is deprecated and warn if so */ 1524 cc = CPU_CLASS(oc); 1525 assert(cc != NULL); 1526 if (cc->deprecation_note) { 1527 warn_report("CPU model %s is deprecated -- %s", 1528 machine->cpu_type, cc->deprecation_note); 1529 } 1530 1531 return true; 1532 } 1533 1534 void machine_run_board_init(MachineState *machine, const char *mem_path, Error **errp) 1535 { 1536 ERRP_GUARD(); 1537 MachineClass *machine_class = MACHINE_GET_CLASS(machine); 1538 1539 /* This checkpoint is required by replay to separate prior clock 1540 reading from the other reads, because timer polling functions query 1541 clock values from the log. */ 1542 replay_checkpoint(CHECKPOINT_INIT); 1543 1544 if (!xen_enabled()) { 1545 /* On 32-bit hosts, QEMU is limited by virtual address space */ 1546 if (machine->ram_size > (2047 << 20) && HOST_LONG_BITS == 32) { 1547 error_setg(errp, "at most 2047 MB RAM can be simulated"); 1548 return; 1549 } 1550 } 1551 1552 if (machine->memdev) { 1553 ram_addr_t backend_size = object_property_get_uint(OBJECT(machine->memdev), 1554 "size", &error_abort); 1555 if (backend_size != machine->ram_size) { 1556 error_setg(errp, "Machine memory size does not match the size of the memory backend"); 1557 return; 1558 } 1559 } else if (machine_class->default_ram_id && machine->ram_size && 1560 numa_uses_legacy_mem()) { 1561 if (object_property_find(object_get_objects_root(), 1562 machine_class->default_ram_id)) { 1563 error_setg(errp, "object's id '%s' is reserved for the default" 1564 " RAM backend, it can't be used for any other purposes", 1565 machine_class->default_ram_id); 1566 error_append_hint(errp, 1567 "Change the object's 'id' to something else or disable" 1568 " automatic creation of the default RAM backend by setting" 1569 " 'memory-backend=%s' with '-machine'.\n", 1570 machine_class->default_ram_id); 1571 return; 1572 } 1573 1574 if (!machine_class->create_default_memdev(current_machine, mem_path, 1575 errp)) { 1576 return; 1577 } 1578 } 1579 1580 if (machine->numa_state) { 1581 numa_complete_configuration(machine); 1582 if (machine->numa_state->num_nodes) { 1583 machine_numa_finish_cpu_init(machine); 1584 if (machine_class->cpu_cluster_has_numa_boundary) { 1585 validate_cpu_cluster_to_numa_boundary(machine); 1586 } 1587 } 1588 } 1589 1590 if (!machine->ram && machine->memdev) { 1591 machine->ram = machine_consume_memdev(machine, machine->memdev); 1592 } 1593 1594 /* Check if the CPU type is supported */ 1595 if (machine->cpu_type && !is_cpu_type_supported(machine, errp)) { 1596 return; 1597 } 1598 1599 if (machine->cgs) { 1600 /* 1601 * With confidential guests, the host can't see the real 1602 * contents of RAM, so there's no point in it trying to merge 1603 * areas. 1604 */ 1605 machine_set_mem_merge(OBJECT(machine), false, &error_abort); 1606 1607 /* 1608 * Virtio devices can't count on directly accessing guest 1609 * memory, so they need iommu_platform=on to use normal DMA 1610 * mechanisms. That requires also disabling legacy virtio 1611 * support for those virtio pci devices which allow it. 1612 */ 1613 object_register_sugar_prop(TYPE_VIRTIO_PCI, "disable-legacy", 1614 "on", true); 1615 object_register_sugar_prop(TYPE_VIRTIO_DEVICE, "iommu_platform", 1616 "on", false); 1617 } 1618 1619 accel_init_interfaces(ACCEL_GET_CLASS(machine->accelerator)); 1620 machine_class->init(machine); 1621 phase_advance(PHASE_MACHINE_INITIALIZED); 1622 } 1623 1624 static NotifierList machine_init_done_notifiers = 1625 NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers); 1626 1627 void qemu_add_machine_init_done_notifier(Notifier *notify) 1628 { 1629 notifier_list_add(&machine_init_done_notifiers, notify); 1630 if (phase_check(PHASE_MACHINE_READY)) { 1631 notify->notify(notify, NULL); 1632 } 1633 } 1634 1635 void qemu_remove_machine_init_done_notifier(Notifier *notify) 1636 { 1637 notifier_remove(notify); 1638 } 1639 1640 void qdev_machine_creation_done(void) 1641 { 1642 cpu_synchronize_all_post_init(); 1643 1644 if (current_machine->boot_config.once) { 1645 qemu_boot_set(current_machine->boot_config.once, &error_fatal); 1646 qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_config.order)); 1647 } 1648 1649 /* 1650 * ok, initial machine setup is done, starting from now we can 1651 * only create hotpluggable devices 1652 */ 1653 phase_advance(PHASE_MACHINE_READY); 1654 qdev_assert_realized_properly(); 1655 1656 /* TODO: once all bus devices are qdevified, this should be done 1657 * when bus is created by qdev.c */ 1658 /* 1659 * This is where we arrange for the sysbus to be reset when the 1660 * whole simulation is reset. In turn, resetting the sysbus will cause 1661 * all devices hanging off it (and all their child buses, recursively) 1662 * to be reset. Note that this will *not* reset any Device objects 1663 * which are not attached to some part of the qbus tree! 1664 */ 1665 qemu_register_resettable(OBJECT(sysbus_get_default())); 1666 1667 notifier_list_notify(&machine_init_done_notifiers, NULL); 1668 1669 if (rom_check_and_register_reset() != 0) { 1670 exit(1); 1671 } 1672 1673 replay_start(); 1674 1675 /* This checkpoint is required by replay to separate prior clock 1676 reading from the other reads, because timer polling functions query 1677 clock values from the log. */ 1678 replay_checkpoint(CHECKPOINT_RESET); 1679 qemu_system_reset(SHUTDOWN_CAUSE_NONE); 1680 register_global_state(); 1681 } 1682 1683 static const TypeInfo machine_info = { 1684 .name = TYPE_MACHINE, 1685 .parent = TYPE_OBJECT, 1686 .abstract = true, 1687 .class_size = sizeof(MachineClass), 1688 .class_init = machine_class_init, 1689 .class_base_init = machine_class_base_init, 1690 .instance_size = sizeof(MachineState), 1691 .instance_init = machine_initfn, 1692 .instance_finalize = machine_finalize, 1693 }; 1694 1695 static void machine_register_types(void) 1696 { 1697 type_register_static(&machine_info); 1698 } 1699 1700 type_init(machine_register_types) 1701