1 /* 2 * QEMU Floppy disk emulator (Intel 82078) 3 * 4 * Copyright (c) 2003, 2007 Jocelyn Mayer 5 * Copyright (c) 2008 Hervé Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 /* 26 * The controller is used in Sun4m systems in a slightly different 27 * way. There are changes in DOR register and DMA is not available. 28 */ 29 30 #include "hw/hw.h" 31 #include "hw/block/fdc.h" 32 #include "qemu/error-report.h" 33 #include "qemu/timer.h" 34 #include "hw/isa/isa.h" 35 #include "hw/sysbus.h" 36 #include "sysemu/block-backend.h" 37 #include "sysemu/blockdev.h" 38 #include "sysemu/sysemu.h" 39 #include "qemu/log.h" 40 41 /********************************************************/ 42 /* debug Floppy devices */ 43 //#define DEBUG_FLOPPY 44 45 #ifdef DEBUG_FLOPPY 46 #define FLOPPY_DPRINTF(fmt, ...) \ 47 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0) 48 #else 49 #define FLOPPY_DPRINTF(fmt, ...) 50 #endif 51 52 /********************************************************/ 53 /* Floppy drive emulation */ 54 55 typedef enum FDriveRate { 56 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */ 57 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */ 58 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */ 59 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */ 60 } FDriveRate; 61 62 typedef struct FDFormat { 63 FDriveType drive; 64 uint8_t last_sect; 65 uint8_t max_track; 66 uint8_t max_head; 67 FDriveRate rate; 68 } FDFormat; 69 70 static const FDFormat fd_formats[] = { 71 /* First entry is default format */ 72 /* 1.44 MB 3"1/2 floppy disks */ 73 { FDRIVE_DRV_144, 18, 80, 1, FDRIVE_RATE_500K, }, 74 { FDRIVE_DRV_144, 20, 80, 1, FDRIVE_RATE_500K, }, 75 { FDRIVE_DRV_144, 21, 80, 1, FDRIVE_RATE_500K, }, 76 { FDRIVE_DRV_144, 21, 82, 1, FDRIVE_RATE_500K, }, 77 { FDRIVE_DRV_144, 21, 83, 1, FDRIVE_RATE_500K, }, 78 { FDRIVE_DRV_144, 22, 80, 1, FDRIVE_RATE_500K, }, 79 { FDRIVE_DRV_144, 23, 80, 1, FDRIVE_RATE_500K, }, 80 { FDRIVE_DRV_144, 24, 80, 1, FDRIVE_RATE_500K, }, 81 /* 2.88 MB 3"1/2 floppy disks */ 82 { FDRIVE_DRV_288, 36, 80, 1, FDRIVE_RATE_1M, }, 83 { FDRIVE_DRV_288, 39, 80, 1, FDRIVE_RATE_1M, }, 84 { FDRIVE_DRV_288, 40, 80, 1, FDRIVE_RATE_1M, }, 85 { FDRIVE_DRV_288, 44, 80, 1, FDRIVE_RATE_1M, }, 86 { FDRIVE_DRV_288, 48, 80, 1, FDRIVE_RATE_1M, }, 87 /* 720 kB 3"1/2 floppy disks */ 88 { FDRIVE_DRV_144, 9, 80, 1, FDRIVE_RATE_250K, }, 89 { FDRIVE_DRV_144, 10, 80, 1, FDRIVE_RATE_250K, }, 90 { FDRIVE_DRV_144, 10, 82, 1, FDRIVE_RATE_250K, }, 91 { FDRIVE_DRV_144, 10, 83, 1, FDRIVE_RATE_250K, }, 92 { FDRIVE_DRV_144, 13, 80, 1, FDRIVE_RATE_250K, }, 93 { FDRIVE_DRV_144, 14, 80, 1, FDRIVE_RATE_250K, }, 94 /* 1.2 MB 5"1/4 floppy disks */ 95 { FDRIVE_DRV_120, 15, 80, 1, FDRIVE_RATE_500K, }, 96 { FDRIVE_DRV_120, 18, 80, 1, FDRIVE_RATE_500K, }, 97 { FDRIVE_DRV_120, 18, 82, 1, FDRIVE_RATE_500K, }, 98 { FDRIVE_DRV_120, 18, 83, 1, FDRIVE_RATE_500K, }, 99 { FDRIVE_DRV_120, 20, 80, 1, FDRIVE_RATE_500K, }, 100 /* 720 kB 5"1/4 floppy disks */ 101 { FDRIVE_DRV_120, 9, 80, 1, FDRIVE_RATE_250K, }, 102 { FDRIVE_DRV_120, 11, 80, 1, FDRIVE_RATE_250K, }, 103 /* 360 kB 5"1/4 floppy disks */ 104 { FDRIVE_DRV_120, 9, 40, 1, FDRIVE_RATE_300K, }, 105 { FDRIVE_DRV_120, 9, 40, 0, FDRIVE_RATE_300K, }, 106 { FDRIVE_DRV_120, 10, 41, 1, FDRIVE_RATE_300K, }, 107 { FDRIVE_DRV_120, 10, 42, 1, FDRIVE_RATE_300K, }, 108 /* 320 kB 5"1/4 floppy disks */ 109 { FDRIVE_DRV_120, 8, 40, 1, FDRIVE_RATE_250K, }, 110 { FDRIVE_DRV_120, 8, 40, 0, FDRIVE_RATE_250K, }, 111 /* 360 kB must match 5"1/4 better than 3"1/2... */ 112 { FDRIVE_DRV_144, 9, 80, 0, FDRIVE_RATE_250K, }, 113 /* end */ 114 { FDRIVE_DRV_NONE, -1, -1, 0, 0, }, 115 }; 116 117 static void pick_geometry(BlockBackend *blk, int *nb_heads, 118 int *max_track, int *last_sect, 119 FDriveType drive_in, FDriveType *drive, 120 FDriveRate *rate) 121 { 122 const FDFormat *parse; 123 uint64_t nb_sectors, size; 124 int i, first_match, match; 125 126 blk_get_geometry(blk, &nb_sectors); 127 match = -1; 128 first_match = -1; 129 for (i = 0; ; i++) { 130 parse = &fd_formats[i]; 131 if (parse->drive == FDRIVE_DRV_NONE) { 132 break; 133 } 134 if (drive_in == parse->drive || 135 drive_in == FDRIVE_DRV_NONE) { 136 size = (parse->max_head + 1) * parse->max_track * 137 parse->last_sect; 138 if (nb_sectors == size) { 139 match = i; 140 break; 141 } 142 if (first_match == -1) { 143 first_match = i; 144 } 145 } 146 } 147 if (match == -1) { 148 if (first_match == -1) { 149 match = 1; 150 } else { 151 match = first_match; 152 } 153 parse = &fd_formats[match]; 154 } 155 *nb_heads = parse->max_head + 1; 156 *max_track = parse->max_track; 157 *last_sect = parse->last_sect; 158 *drive = parse->drive; 159 *rate = parse->rate; 160 } 161 162 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv) 163 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive)) 164 165 /* Will always be a fixed parameter for us */ 166 #define FD_SECTOR_LEN 512 167 #define FD_SECTOR_SC 2 /* Sector size code */ 168 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */ 169 170 typedef struct FDCtrl FDCtrl; 171 172 /* Floppy disk drive emulation */ 173 typedef enum FDiskFlags { 174 FDISK_DBL_SIDES = 0x01, 175 } FDiskFlags; 176 177 typedef struct FDrive { 178 FDCtrl *fdctrl; 179 BlockBackend *blk; 180 /* Drive status */ 181 FDriveType drive; 182 uint8_t perpendicular; /* 2.88 MB access mode */ 183 /* Position */ 184 uint8_t head; 185 uint8_t track; 186 uint8_t sect; 187 /* Media */ 188 FDiskFlags flags; 189 uint8_t last_sect; /* Nb sector per track */ 190 uint8_t max_track; /* Nb of tracks */ 191 uint16_t bps; /* Bytes per sector */ 192 uint8_t ro; /* Is read-only */ 193 uint8_t media_changed; /* Is media changed */ 194 uint8_t media_rate; /* Data rate of medium */ 195 } FDrive; 196 197 static void fd_init(FDrive *drv) 198 { 199 /* Drive */ 200 drv->drive = FDRIVE_DRV_NONE; 201 drv->perpendicular = 0; 202 /* Disk */ 203 drv->last_sect = 0; 204 drv->max_track = 0; 205 } 206 207 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1) 208 209 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect, 210 uint8_t last_sect, uint8_t num_sides) 211 { 212 return (((track * num_sides) + head) * last_sect) + sect - 1; 213 } 214 215 /* Returns current position, in sectors, for given drive */ 216 static int fd_sector(FDrive *drv) 217 { 218 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect, 219 NUM_SIDES(drv)); 220 } 221 222 /* Seek to a new position: 223 * returns 0 if already on right track 224 * returns 1 if track changed 225 * returns 2 if track is invalid 226 * returns 3 if sector is invalid 227 * returns 4 if seek is disabled 228 */ 229 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect, 230 int enable_seek) 231 { 232 uint32_t sector; 233 int ret; 234 235 if (track > drv->max_track || 236 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) { 237 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", 238 head, track, sect, 1, 239 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, 240 drv->max_track, drv->last_sect); 241 return 2; 242 } 243 if (sect > drv->last_sect) { 244 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", 245 head, track, sect, 1, 246 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, 247 drv->max_track, drv->last_sect); 248 return 3; 249 } 250 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv)); 251 ret = 0; 252 if (sector != fd_sector(drv)) { 253 #if 0 254 if (!enable_seek) { 255 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x" 256 " (max=%d %02x %02x)\n", 257 head, track, sect, 1, drv->max_track, 258 drv->last_sect); 259 return 4; 260 } 261 #endif 262 drv->head = head; 263 if (drv->track != track) { 264 if (drv->blk != NULL && blk_is_inserted(drv->blk)) { 265 drv->media_changed = 0; 266 } 267 ret = 1; 268 } 269 drv->track = track; 270 drv->sect = sect; 271 } 272 273 if (drv->blk == NULL || !blk_is_inserted(drv->blk)) { 274 ret = 2; 275 } 276 277 return ret; 278 } 279 280 /* Set drive back to track 0 */ 281 static void fd_recalibrate(FDrive *drv) 282 { 283 FLOPPY_DPRINTF("recalibrate\n"); 284 fd_seek(drv, 0, 0, 1, 1); 285 } 286 287 /* Revalidate a disk drive after a disk change */ 288 static void fd_revalidate(FDrive *drv) 289 { 290 int nb_heads, max_track, last_sect, ro; 291 FDriveType drive; 292 FDriveRate rate; 293 294 FLOPPY_DPRINTF("revalidate\n"); 295 if (drv->blk != NULL) { 296 ro = blk_is_read_only(drv->blk); 297 pick_geometry(drv->blk, &nb_heads, &max_track, 298 &last_sect, drv->drive, &drive, &rate); 299 if (!blk_is_inserted(drv->blk)) { 300 FLOPPY_DPRINTF("No disk in drive\n"); 301 } else { 302 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads, 303 max_track, last_sect, ro ? "ro" : "rw"); 304 } 305 if (nb_heads == 1) { 306 drv->flags &= ~FDISK_DBL_SIDES; 307 } else { 308 drv->flags |= FDISK_DBL_SIDES; 309 } 310 drv->max_track = max_track; 311 drv->last_sect = last_sect; 312 drv->ro = ro; 313 drv->drive = drive; 314 drv->media_rate = rate; 315 } else { 316 FLOPPY_DPRINTF("No drive connected\n"); 317 drv->last_sect = 0; 318 drv->max_track = 0; 319 drv->flags &= ~FDISK_DBL_SIDES; 320 } 321 } 322 323 /********************************************************/ 324 /* Intel 82078 floppy disk controller emulation */ 325 326 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq); 327 static void fdctrl_reset_fifo(FDCtrl *fdctrl); 328 static int fdctrl_transfer_handler (void *opaque, int nchan, 329 int dma_pos, int dma_len); 330 static void fdctrl_raise_irq(FDCtrl *fdctrl); 331 static FDrive *get_cur_drv(FDCtrl *fdctrl); 332 333 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl); 334 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl); 335 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl); 336 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value); 337 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl); 338 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value); 339 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl); 340 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value); 341 static uint32_t fdctrl_read_data(FDCtrl *fdctrl); 342 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value); 343 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl); 344 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value); 345 346 enum { 347 FD_DIR_WRITE = 0, 348 FD_DIR_READ = 1, 349 FD_DIR_SCANE = 2, 350 FD_DIR_SCANL = 3, 351 FD_DIR_SCANH = 4, 352 FD_DIR_VERIFY = 5, 353 }; 354 355 enum { 356 FD_STATE_MULTI = 0x01, /* multi track flag */ 357 FD_STATE_FORMAT = 0x02, /* format flag */ 358 }; 359 360 enum { 361 FD_REG_SRA = 0x00, 362 FD_REG_SRB = 0x01, 363 FD_REG_DOR = 0x02, 364 FD_REG_TDR = 0x03, 365 FD_REG_MSR = 0x04, 366 FD_REG_DSR = 0x04, 367 FD_REG_FIFO = 0x05, 368 FD_REG_DIR = 0x07, 369 FD_REG_CCR = 0x07, 370 }; 371 372 enum { 373 FD_CMD_READ_TRACK = 0x02, 374 FD_CMD_SPECIFY = 0x03, 375 FD_CMD_SENSE_DRIVE_STATUS = 0x04, 376 FD_CMD_WRITE = 0x05, 377 FD_CMD_READ = 0x06, 378 FD_CMD_RECALIBRATE = 0x07, 379 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08, 380 FD_CMD_WRITE_DELETED = 0x09, 381 FD_CMD_READ_ID = 0x0a, 382 FD_CMD_READ_DELETED = 0x0c, 383 FD_CMD_FORMAT_TRACK = 0x0d, 384 FD_CMD_DUMPREG = 0x0e, 385 FD_CMD_SEEK = 0x0f, 386 FD_CMD_VERSION = 0x10, 387 FD_CMD_SCAN_EQUAL = 0x11, 388 FD_CMD_PERPENDICULAR_MODE = 0x12, 389 FD_CMD_CONFIGURE = 0x13, 390 FD_CMD_LOCK = 0x14, 391 FD_CMD_VERIFY = 0x16, 392 FD_CMD_POWERDOWN_MODE = 0x17, 393 FD_CMD_PART_ID = 0x18, 394 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19, 395 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d, 396 FD_CMD_SAVE = 0x2e, 397 FD_CMD_OPTION = 0x33, 398 FD_CMD_RESTORE = 0x4e, 399 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e, 400 FD_CMD_RELATIVE_SEEK_OUT = 0x8f, 401 FD_CMD_FORMAT_AND_WRITE = 0xcd, 402 FD_CMD_RELATIVE_SEEK_IN = 0xcf, 403 }; 404 405 enum { 406 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */ 407 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */ 408 FD_CONFIG_POLL = 0x10, /* Poll enabled */ 409 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */ 410 FD_CONFIG_EIS = 0x40, /* No implied seeks */ 411 }; 412 413 enum { 414 FD_SR0_DS0 = 0x01, 415 FD_SR0_DS1 = 0x02, 416 FD_SR0_HEAD = 0x04, 417 FD_SR0_EQPMT = 0x10, 418 FD_SR0_SEEK = 0x20, 419 FD_SR0_ABNTERM = 0x40, 420 FD_SR0_INVCMD = 0x80, 421 FD_SR0_RDYCHG = 0xc0, 422 }; 423 424 enum { 425 FD_SR1_MA = 0x01, /* Missing address mark */ 426 FD_SR1_NW = 0x02, /* Not writable */ 427 FD_SR1_EC = 0x80, /* End of cylinder */ 428 }; 429 430 enum { 431 FD_SR2_SNS = 0x04, /* Scan not satisfied */ 432 FD_SR2_SEH = 0x08, /* Scan equal hit */ 433 }; 434 435 enum { 436 FD_SRA_DIR = 0x01, 437 FD_SRA_nWP = 0x02, 438 FD_SRA_nINDX = 0x04, 439 FD_SRA_HDSEL = 0x08, 440 FD_SRA_nTRK0 = 0x10, 441 FD_SRA_STEP = 0x20, 442 FD_SRA_nDRV2 = 0x40, 443 FD_SRA_INTPEND = 0x80, 444 }; 445 446 enum { 447 FD_SRB_MTR0 = 0x01, 448 FD_SRB_MTR1 = 0x02, 449 FD_SRB_WGATE = 0x04, 450 FD_SRB_RDATA = 0x08, 451 FD_SRB_WDATA = 0x10, 452 FD_SRB_DR0 = 0x20, 453 }; 454 455 enum { 456 #if MAX_FD == 4 457 FD_DOR_SELMASK = 0x03, 458 #else 459 FD_DOR_SELMASK = 0x01, 460 #endif 461 FD_DOR_nRESET = 0x04, 462 FD_DOR_DMAEN = 0x08, 463 FD_DOR_MOTEN0 = 0x10, 464 FD_DOR_MOTEN1 = 0x20, 465 FD_DOR_MOTEN2 = 0x40, 466 FD_DOR_MOTEN3 = 0x80, 467 }; 468 469 enum { 470 #if MAX_FD == 4 471 FD_TDR_BOOTSEL = 0x0c, 472 #else 473 FD_TDR_BOOTSEL = 0x04, 474 #endif 475 }; 476 477 enum { 478 FD_DSR_DRATEMASK= 0x03, 479 FD_DSR_PWRDOWN = 0x40, 480 FD_DSR_SWRESET = 0x80, 481 }; 482 483 enum { 484 FD_MSR_DRV0BUSY = 0x01, 485 FD_MSR_DRV1BUSY = 0x02, 486 FD_MSR_DRV2BUSY = 0x04, 487 FD_MSR_DRV3BUSY = 0x08, 488 FD_MSR_CMDBUSY = 0x10, 489 FD_MSR_NONDMA = 0x20, 490 FD_MSR_DIO = 0x40, 491 FD_MSR_RQM = 0x80, 492 }; 493 494 enum { 495 FD_DIR_DSKCHG = 0x80, 496 }; 497 498 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI) 499 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT) 500 501 struct FDCtrl { 502 MemoryRegion iomem; 503 qemu_irq irq; 504 /* Controller state */ 505 QEMUTimer *result_timer; 506 int dma_chann; 507 /* Controller's identification */ 508 uint8_t version; 509 /* HW */ 510 uint8_t sra; 511 uint8_t srb; 512 uint8_t dor; 513 uint8_t dor_vmstate; /* only used as temp during vmstate */ 514 uint8_t tdr; 515 uint8_t dsr; 516 uint8_t msr; 517 uint8_t cur_drv; 518 uint8_t status0; 519 uint8_t status1; 520 uint8_t status2; 521 /* Command FIFO */ 522 uint8_t *fifo; 523 int32_t fifo_size; 524 uint32_t data_pos; 525 uint32_t data_len; 526 uint8_t data_state; 527 uint8_t data_dir; 528 uint8_t eot; /* last wanted sector */ 529 /* States kept only to be returned back */ 530 /* precompensation */ 531 uint8_t precomp_trk; 532 uint8_t config; 533 uint8_t lock; 534 /* Power down config (also with status regB access mode */ 535 uint8_t pwrd; 536 /* Floppy drives */ 537 uint8_t num_floppies; 538 FDrive drives[MAX_FD]; 539 int reset_sensei; 540 uint32_t check_media_rate; 541 /* Timers state */ 542 uint8_t timer0; 543 uint8_t timer1; 544 }; 545 546 #define TYPE_SYSBUS_FDC "base-sysbus-fdc" 547 #define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC) 548 549 typedef struct FDCtrlSysBus { 550 /*< private >*/ 551 SysBusDevice parent_obj; 552 /*< public >*/ 553 554 struct FDCtrl state; 555 } FDCtrlSysBus; 556 557 #define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC) 558 559 typedef struct FDCtrlISABus { 560 ISADevice parent_obj; 561 562 uint32_t iobase; 563 uint32_t irq; 564 uint32_t dma; 565 struct FDCtrl state; 566 int32_t bootindexA; 567 int32_t bootindexB; 568 } FDCtrlISABus; 569 570 static uint32_t fdctrl_read (void *opaque, uint32_t reg) 571 { 572 FDCtrl *fdctrl = opaque; 573 uint32_t retval; 574 575 reg &= 7; 576 switch (reg) { 577 case FD_REG_SRA: 578 retval = fdctrl_read_statusA(fdctrl); 579 break; 580 case FD_REG_SRB: 581 retval = fdctrl_read_statusB(fdctrl); 582 break; 583 case FD_REG_DOR: 584 retval = fdctrl_read_dor(fdctrl); 585 break; 586 case FD_REG_TDR: 587 retval = fdctrl_read_tape(fdctrl); 588 break; 589 case FD_REG_MSR: 590 retval = fdctrl_read_main_status(fdctrl); 591 break; 592 case FD_REG_FIFO: 593 retval = fdctrl_read_data(fdctrl); 594 break; 595 case FD_REG_DIR: 596 retval = fdctrl_read_dir(fdctrl); 597 break; 598 default: 599 retval = (uint32_t)(-1); 600 break; 601 } 602 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval); 603 604 return retval; 605 } 606 607 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value) 608 { 609 FDCtrl *fdctrl = opaque; 610 611 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value); 612 613 reg &= 7; 614 switch (reg) { 615 case FD_REG_DOR: 616 fdctrl_write_dor(fdctrl, value); 617 break; 618 case FD_REG_TDR: 619 fdctrl_write_tape(fdctrl, value); 620 break; 621 case FD_REG_DSR: 622 fdctrl_write_rate(fdctrl, value); 623 break; 624 case FD_REG_FIFO: 625 fdctrl_write_data(fdctrl, value); 626 break; 627 case FD_REG_CCR: 628 fdctrl_write_ccr(fdctrl, value); 629 break; 630 default: 631 break; 632 } 633 } 634 635 static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg, 636 unsigned ize) 637 { 638 return fdctrl_read(opaque, (uint32_t)reg); 639 } 640 641 static void fdctrl_write_mem (void *opaque, hwaddr reg, 642 uint64_t value, unsigned size) 643 { 644 fdctrl_write(opaque, (uint32_t)reg, value); 645 } 646 647 static const MemoryRegionOps fdctrl_mem_ops = { 648 .read = fdctrl_read_mem, 649 .write = fdctrl_write_mem, 650 .endianness = DEVICE_NATIVE_ENDIAN, 651 }; 652 653 static const MemoryRegionOps fdctrl_mem_strict_ops = { 654 .read = fdctrl_read_mem, 655 .write = fdctrl_write_mem, 656 .endianness = DEVICE_NATIVE_ENDIAN, 657 .valid = { 658 .min_access_size = 1, 659 .max_access_size = 1, 660 }, 661 }; 662 663 static bool fdrive_media_changed_needed(void *opaque) 664 { 665 FDrive *drive = opaque; 666 667 return (drive->blk != NULL && drive->media_changed != 1); 668 } 669 670 static const VMStateDescription vmstate_fdrive_media_changed = { 671 .name = "fdrive/media_changed", 672 .version_id = 1, 673 .minimum_version_id = 1, 674 .fields = (VMStateField[]) { 675 VMSTATE_UINT8(media_changed, FDrive), 676 VMSTATE_END_OF_LIST() 677 } 678 }; 679 680 static bool fdrive_media_rate_needed(void *opaque) 681 { 682 FDrive *drive = opaque; 683 684 return drive->fdctrl->check_media_rate; 685 } 686 687 static const VMStateDescription vmstate_fdrive_media_rate = { 688 .name = "fdrive/media_rate", 689 .version_id = 1, 690 .minimum_version_id = 1, 691 .fields = (VMStateField[]) { 692 VMSTATE_UINT8(media_rate, FDrive), 693 VMSTATE_END_OF_LIST() 694 } 695 }; 696 697 static bool fdrive_perpendicular_needed(void *opaque) 698 { 699 FDrive *drive = opaque; 700 701 return drive->perpendicular != 0; 702 } 703 704 static const VMStateDescription vmstate_fdrive_perpendicular = { 705 .name = "fdrive/perpendicular", 706 .version_id = 1, 707 .minimum_version_id = 1, 708 .fields = (VMStateField[]) { 709 VMSTATE_UINT8(perpendicular, FDrive), 710 VMSTATE_END_OF_LIST() 711 } 712 }; 713 714 static int fdrive_post_load(void *opaque, int version_id) 715 { 716 fd_revalidate(opaque); 717 return 0; 718 } 719 720 static const VMStateDescription vmstate_fdrive = { 721 .name = "fdrive", 722 .version_id = 1, 723 .minimum_version_id = 1, 724 .post_load = fdrive_post_load, 725 .fields = (VMStateField[]) { 726 VMSTATE_UINT8(head, FDrive), 727 VMSTATE_UINT8(track, FDrive), 728 VMSTATE_UINT8(sect, FDrive), 729 VMSTATE_END_OF_LIST() 730 }, 731 .subsections = (VMStateSubsection[]) { 732 { 733 .vmsd = &vmstate_fdrive_media_changed, 734 .needed = &fdrive_media_changed_needed, 735 } , { 736 .vmsd = &vmstate_fdrive_media_rate, 737 .needed = &fdrive_media_rate_needed, 738 } , { 739 .vmsd = &vmstate_fdrive_perpendicular, 740 .needed = &fdrive_perpendicular_needed, 741 } , { 742 /* empty */ 743 } 744 } 745 }; 746 747 static void fdc_pre_save(void *opaque) 748 { 749 FDCtrl *s = opaque; 750 751 s->dor_vmstate = s->dor | GET_CUR_DRV(s); 752 } 753 754 static int fdc_post_load(void *opaque, int version_id) 755 { 756 FDCtrl *s = opaque; 757 758 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK); 759 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK; 760 return 0; 761 } 762 763 static bool fdc_reset_sensei_needed(void *opaque) 764 { 765 FDCtrl *s = opaque; 766 767 return s->reset_sensei != 0; 768 } 769 770 static const VMStateDescription vmstate_fdc_reset_sensei = { 771 .name = "fdc/reset_sensei", 772 .version_id = 1, 773 .minimum_version_id = 1, 774 .fields = (VMStateField[]) { 775 VMSTATE_INT32(reset_sensei, FDCtrl), 776 VMSTATE_END_OF_LIST() 777 } 778 }; 779 780 static bool fdc_result_timer_needed(void *opaque) 781 { 782 FDCtrl *s = opaque; 783 784 return timer_pending(s->result_timer); 785 } 786 787 static const VMStateDescription vmstate_fdc_result_timer = { 788 .name = "fdc/result_timer", 789 .version_id = 1, 790 .minimum_version_id = 1, 791 .fields = (VMStateField[]) { 792 VMSTATE_TIMER_PTR(result_timer, FDCtrl), 793 VMSTATE_END_OF_LIST() 794 } 795 }; 796 797 static const VMStateDescription vmstate_fdc = { 798 .name = "fdc", 799 .version_id = 2, 800 .minimum_version_id = 2, 801 .pre_save = fdc_pre_save, 802 .post_load = fdc_post_load, 803 .fields = (VMStateField[]) { 804 /* Controller State */ 805 VMSTATE_UINT8(sra, FDCtrl), 806 VMSTATE_UINT8(srb, FDCtrl), 807 VMSTATE_UINT8(dor_vmstate, FDCtrl), 808 VMSTATE_UINT8(tdr, FDCtrl), 809 VMSTATE_UINT8(dsr, FDCtrl), 810 VMSTATE_UINT8(msr, FDCtrl), 811 VMSTATE_UINT8(status0, FDCtrl), 812 VMSTATE_UINT8(status1, FDCtrl), 813 VMSTATE_UINT8(status2, FDCtrl), 814 /* Command FIFO */ 815 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8, 816 uint8_t), 817 VMSTATE_UINT32(data_pos, FDCtrl), 818 VMSTATE_UINT32(data_len, FDCtrl), 819 VMSTATE_UINT8(data_state, FDCtrl), 820 VMSTATE_UINT8(data_dir, FDCtrl), 821 VMSTATE_UINT8(eot, FDCtrl), 822 /* States kept only to be returned back */ 823 VMSTATE_UINT8(timer0, FDCtrl), 824 VMSTATE_UINT8(timer1, FDCtrl), 825 VMSTATE_UINT8(precomp_trk, FDCtrl), 826 VMSTATE_UINT8(config, FDCtrl), 827 VMSTATE_UINT8(lock, FDCtrl), 828 VMSTATE_UINT8(pwrd, FDCtrl), 829 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl), 830 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1, 831 vmstate_fdrive, FDrive), 832 VMSTATE_END_OF_LIST() 833 }, 834 .subsections = (VMStateSubsection[]) { 835 { 836 .vmsd = &vmstate_fdc_reset_sensei, 837 .needed = fdc_reset_sensei_needed, 838 } , { 839 .vmsd = &vmstate_fdc_result_timer, 840 .needed = fdc_result_timer_needed, 841 } , { 842 /* empty */ 843 } 844 } 845 }; 846 847 static void fdctrl_external_reset_sysbus(DeviceState *d) 848 { 849 FDCtrlSysBus *sys = SYSBUS_FDC(d); 850 FDCtrl *s = &sys->state; 851 852 fdctrl_reset(s, 0); 853 } 854 855 static void fdctrl_external_reset_isa(DeviceState *d) 856 { 857 FDCtrlISABus *isa = ISA_FDC(d); 858 FDCtrl *s = &isa->state; 859 860 fdctrl_reset(s, 0); 861 } 862 863 static void fdctrl_handle_tc(void *opaque, int irq, int level) 864 { 865 //FDCtrl *s = opaque; 866 867 if (level) { 868 // XXX 869 FLOPPY_DPRINTF("TC pulsed\n"); 870 } 871 } 872 873 /* Change IRQ state */ 874 static void fdctrl_reset_irq(FDCtrl *fdctrl) 875 { 876 fdctrl->status0 = 0; 877 if (!(fdctrl->sra & FD_SRA_INTPEND)) 878 return; 879 FLOPPY_DPRINTF("Reset interrupt\n"); 880 qemu_set_irq(fdctrl->irq, 0); 881 fdctrl->sra &= ~FD_SRA_INTPEND; 882 } 883 884 static void fdctrl_raise_irq(FDCtrl *fdctrl) 885 { 886 if (!(fdctrl->sra & FD_SRA_INTPEND)) { 887 qemu_set_irq(fdctrl->irq, 1); 888 fdctrl->sra |= FD_SRA_INTPEND; 889 } 890 891 fdctrl->reset_sensei = 0; 892 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0); 893 } 894 895 /* Reset controller */ 896 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq) 897 { 898 int i; 899 900 FLOPPY_DPRINTF("reset controller\n"); 901 fdctrl_reset_irq(fdctrl); 902 /* Initialise controller */ 903 fdctrl->sra = 0; 904 fdctrl->srb = 0xc0; 905 if (!fdctrl->drives[1].blk) { 906 fdctrl->sra |= FD_SRA_nDRV2; 907 } 908 fdctrl->cur_drv = 0; 909 fdctrl->dor = FD_DOR_nRESET; 910 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0; 911 fdctrl->msr = FD_MSR_RQM; 912 fdctrl->reset_sensei = 0; 913 timer_del(fdctrl->result_timer); 914 /* FIFO state */ 915 fdctrl->data_pos = 0; 916 fdctrl->data_len = 0; 917 fdctrl->data_state = 0; 918 fdctrl->data_dir = FD_DIR_WRITE; 919 for (i = 0; i < MAX_FD; i++) 920 fd_recalibrate(&fdctrl->drives[i]); 921 fdctrl_reset_fifo(fdctrl); 922 if (do_irq) { 923 fdctrl->status0 |= FD_SR0_RDYCHG; 924 fdctrl_raise_irq(fdctrl); 925 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT; 926 } 927 } 928 929 static inline FDrive *drv0(FDCtrl *fdctrl) 930 { 931 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2]; 932 } 933 934 static inline FDrive *drv1(FDCtrl *fdctrl) 935 { 936 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2)) 937 return &fdctrl->drives[1]; 938 else 939 return &fdctrl->drives[0]; 940 } 941 942 #if MAX_FD == 4 943 static inline FDrive *drv2(FDCtrl *fdctrl) 944 { 945 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2)) 946 return &fdctrl->drives[2]; 947 else 948 return &fdctrl->drives[1]; 949 } 950 951 static inline FDrive *drv3(FDCtrl *fdctrl) 952 { 953 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2)) 954 return &fdctrl->drives[3]; 955 else 956 return &fdctrl->drives[2]; 957 } 958 #endif 959 960 static FDrive *get_cur_drv(FDCtrl *fdctrl) 961 { 962 switch (fdctrl->cur_drv) { 963 case 0: return drv0(fdctrl); 964 case 1: return drv1(fdctrl); 965 #if MAX_FD == 4 966 case 2: return drv2(fdctrl); 967 case 3: return drv3(fdctrl); 968 #endif 969 default: return NULL; 970 } 971 } 972 973 /* Status A register : 0x00 (read-only) */ 974 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl) 975 { 976 uint32_t retval = fdctrl->sra; 977 978 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval); 979 980 return retval; 981 } 982 983 /* Status B register : 0x01 (read-only) */ 984 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl) 985 { 986 uint32_t retval = fdctrl->srb; 987 988 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval); 989 990 return retval; 991 } 992 993 /* Digital output register : 0x02 */ 994 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl) 995 { 996 uint32_t retval = fdctrl->dor; 997 998 /* Selected drive */ 999 retval |= fdctrl->cur_drv; 1000 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval); 1001 1002 return retval; 1003 } 1004 1005 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value) 1006 { 1007 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value); 1008 1009 /* Motors */ 1010 if (value & FD_DOR_MOTEN0) 1011 fdctrl->srb |= FD_SRB_MTR0; 1012 else 1013 fdctrl->srb &= ~FD_SRB_MTR0; 1014 if (value & FD_DOR_MOTEN1) 1015 fdctrl->srb |= FD_SRB_MTR1; 1016 else 1017 fdctrl->srb &= ~FD_SRB_MTR1; 1018 1019 /* Drive */ 1020 if (value & 1) 1021 fdctrl->srb |= FD_SRB_DR0; 1022 else 1023 fdctrl->srb &= ~FD_SRB_DR0; 1024 1025 /* Reset */ 1026 if (!(value & FD_DOR_nRESET)) { 1027 if (fdctrl->dor & FD_DOR_nRESET) { 1028 FLOPPY_DPRINTF("controller enter RESET state\n"); 1029 } 1030 } else { 1031 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1032 FLOPPY_DPRINTF("controller out of RESET state\n"); 1033 fdctrl_reset(fdctrl, 1); 1034 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1035 } 1036 } 1037 /* Selected drive */ 1038 fdctrl->cur_drv = value & FD_DOR_SELMASK; 1039 1040 fdctrl->dor = value; 1041 } 1042 1043 /* Tape drive register : 0x03 */ 1044 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl) 1045 { 1046 uint32_t retval = fdctrl->tdr; 1047 1048 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval); 1049 1050 return retval; 1051 } 1052 1053 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value) 1054 { 1055 /* Reset mode */ 1056 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1057 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1058 return; 1059 } 1060 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value); 1061 /* Disk boot selection indicator */ 1062 fdctrl->tdr = value & FD_TDR_BOOTSEL; 1063 /* Tape indicators: never allow */ 1064 } 1065 1066 /* Main status register : 0x04 (read) */ 1067 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl) 1068 { 1069 uint32_t retval = fdctrl->msr; 1070 1071 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1072 fdctrl->dor |= FD_DOR_nRESET; 1073 1074 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval); 1075 1076 return retval; 1077 } 1078 1079 /* Data select rate register : 0x04 (write) */ 1080 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value) 1081 { 1082 /* Reset mode */ 1083 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1084 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1085 return; 1086 } 1087 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value); 1088 /* Reset: autoclear */ 1089 if (value & FD_DSR_SWRESET) { 1090 fdctrl->dor &= ~FD_DOR_nRESET; 1091 fdctrl_reset(fdctrl, 1); 1092 fdctrl->dor |= FD_DOR_nRESET; 1093 } 1094 if (value & FD_DSR_PWRDOWN) { 1095 fdctrl_reset(fdctrl, 1); 1096 } 1097 fdctrl->dsr = value; 1098 } 1099 1100 /* Configuration control register: 0x07 (write) */ 1101 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value) 1102 { 1103 /* Reset mode */ 1104 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1105 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1106 return; 1107 } 1108 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value); 1109 1110 /* Only the rate selection bits used in AT mode, and we 1111 * store those in the DSR. 1112 */ 1113 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) | 1114 (value & FD_DSR_DRATEMASK); 1115 } 1116 1117 static int fdctrl_media_changed(FDrive *drv) 1118 { 1119 return drv->media_changed; 1120 } 1121 1122 /* Digital input register : 0x07 (read-only) */ 1123 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl) 1124 { 1125 uint32_t retval = 0; 1126 1127 if (fdctrl_media_changed(get_cur_drv(fdctrl))) { 1128 retval |= FD_DIR_DSKCHG; 1129 } 1130 if (retval != 0) { 1131 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval); 1132 } 1133 1134 return retval; 1135 } 1136 1137 /* FIFO state control */ 1138 static void fdctrl_reset_fifo(FDCtrl *fdctrl) 1139 { 1140 fdctrl->data_dir = FD_DIR_WRITE; 1141 fdctrl->data_pos = 0; 1142 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO); 1143 } 1144 1145 /* Set FIFO status for the host to read */ 1146 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len) 1147 { 1148 fdctrl->data_dir = FD_DIR_READ; 1149 fdctrl->data_len = fifo_len; 1150 fdctrl->data_pos = 0; 1151 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO; 1152 } 1153 1154 /* Set an error: unimplemented/unknown command */ 1155 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction) 1156 { 1157 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n", 1158 fdctrl->fifo[0]); 1159 fdctrl->fifo[0] = FD_SR0_INVCMD; 1160 fdctrl_set_fifo(fdctrl, 1); 1161 } 1162 1163 /* Seek to next sector 1164 * returns 0 when end of track reached (for DBL_SIDES on head 1) 1165 * otherwise returns 1 1166 */ 1167 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv) 1168 { 1169 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n", 1170 cur_drv->head, cur_drv->track, cur_drv->sect, 1171 fd_sector(cur_drv)); 1172 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an 1173 error in fact */ 1174 uint8_t new_head = cur_drv->head; 1175 uint8_t new_track = cur_drv->track; 1176 uint8_t new_sect = cur_drv->sect; 1177 1178 int ret = 1; 1179 1180 if (new_sect >= cur_drv->last_sect || 1181 new_sect == fdctrl->eot) { 1182 new_sect = 1; 1183 if (FD_MULTI_TRACK(fdctrl->data_state)) { 1184 if (new_head == 0 && 1185 (cur_drv->flags & FDISK_DBL_SIDES) != 0) { 1186 new_head = 1; 1187 } else { 1188 new_head = 0; 1189 new_track++; 1190 fdctrl->status0 |= FD_SR0_SEEK; 1191 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) { 1192 ret = 0; 1193 } 1194 } 1195 } else { 1196 fdctrl->status0 |= FD_SR0_SEEK; 1197 new_track++; 1198 ret = 0; 1199 } 1200 if (ret == 1) { 1201 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n", 1202 new_head, new_track, new_sect, fd_sector(cur_drv)); 1203 } 1204 } else { 1205 new_sect++; 1206 } 1207 fd_seek(cur_drv, new_head, new_track, new_sect, 1); 1208 return ret; 1209 } 1210 1211 /* Callback for transfer end (stop or abort) */ 1212 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0, 1213 uint8_t status1, uint8_t status2) 1214 { 1215 FDrive *cur_drv; 1216 cur_drv = get_cur_drv(fdctrl); 1217 1218 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD); 1219 fdctrl->status0 |= GET_CUR_DRV(fdctrl); 1220 if (cur_drv->head) { 1221 fdctrl->status0 |= FD_SR0_HEAD; 1222 } 1223 fdctrl->status0 |= status0; 1224 1225 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n", 1226 status0, status1, status2, fdctrl->status0); 1227 fdctrl->fifo[0] = fdctrl->status0; 1228 fdctrl->fifo[1] = status1; 1229 fdctrl->fifo[2] = status2; 1230 fdctrl->fifo[3] = cur_drv->track; 1231 fdctrl->fifo[4] = cur_drv->head; 1232 fdctrl->fifo[5] = cur_drv->sect; 1233 fdctrl->fifo[6] = FD_SECTOR_SC; 1234 fdctrl->data_dir = FD_DIR_READ; 1235 if (!(fdctrl->msr & FD_MSR_NONDMA)) { 1236 DMA_release_DREQ(fdctrl->dma_chann); 1237 } 1238 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; 1239 fdctrl->msr &= ~FD_MSR_NONDMA; 1240 1241 fdctrl_set_fifo(fdctrl, 7); 1242 fdctrl_raise_irq(fdctrl); 1243 } 1244 1245 /* Prepare a data transfer (either DMA or FIFO) */ 1246 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction) 1247 { 1248 FDrive *cur_drv; 1249 uint8_t kh, kt, ks; 1250 1251 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1252 cur_drv = get_cur_drv(fdctrl); 1253 kt = fdctrl->fifo[2]; 1254 kh = fdctrl->fifo[3]; 1255 ks = fdctrl->fifo[4]; 1256 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n", 1257 GET_CUR_DRV(fdctrl), kh, kt, ks, 1258 fd_sector_calc(kh, kt, ks, cur_drv->last_sect, 1259 NUM_SIDES(cur_drv))); 1260 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { 1261 case 2: 1262 /* sect too big */ 1263 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1264 fdctrl->fifo[3] = kt; 1265 fdctrl->fifo[4] = kh; 1266 fdctrl->fifo[5] = ks; 1267 return; 1268 case 3: 1269 /* track too big */ 1270 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); 1271 fdctrl->fifo[3] = kt; 1272 fdctrl->fifo[4] = kh; 1273 fdctrl->fifo[5] = ks; 1274 return; 1275 case 4: 1276 /* No seek enabled */ 1277 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1278 fdctrl->fifo[3] = kt; 1279 fdctrl->fifo[4] = kh; 1280 fdctrl->fifo[5] = ks; 1281 return; 1282 case 1: 1283 fdctrl->status0 |= FD_SR0_SEEK; 1284 break; 1285 default: 1286 break; 1287 } 1288 1289 /* Check the data rate. If the programmed data rate does not match 1290 * the currently inserted medium, the operation has to fail. */ 1291 if (fdctrl->check_media_rate && 1292 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) { 1293 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n", 1294 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate); 1295 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); 1296 fdctrl->fifo[3] = kt; 1297 fdctrl->fifo[4] = kh; 1298 fdctrl->fifo[5] = ks; 1299 return; 1300 } 1301 1302 /* Set the FIFO state */ 1303 fdctrl->data_dir = direction; 1304 fdctrl->data_pos = 0; 1305 assert(fdctrl->msr & FD_MSR_CMDBUSY); 1306 if (fdctrl->fifo[0] & 0x80) 1307 fdctrl->data_state |= FD_STATE_MULTI; 1308 else 1309 fdctrl->data_state &= ~FD_STATE_MULTI; 1310 if (fdctrl->fifo[5] == 0) { 1311 fdctrl->data_len = fdctrl->fifo[8]; 1312 } else { 1313 int tmp; 1314 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]); 1315 tmp = (fdctrl->fifo[6] - ks + 1); 1316 if (fdctrl->fifo[0] & 0x80) 1317 tmp += fdctrl->fifo[6]; 1318 fdctrl->data_len *= tmp; 1319 } 1320 fdctrl->eot = fdctrl->fifo[6]; 1321 if (fdctrl->dor & FD_DOR_DMAEN) { 1322 int dma_mode; 1323 /* DMA transfer are enabled. Check if DMA channel is well programmed */ 1324 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann); 1325 dma_mode = (dma_mode >> 2) & 3; 1326 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n", 1327 dma_mode, direction, 1328 (128 << fdctrl->fifo[5]) * 1329 (cur_drv->last_sect - ks + 1), fdctrl->data_len); 1330 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL || 1331 direction == FD_DIR_SCANH) && dma_mode == 0) || 1332 (direction == FD_DIR_WRITE && dma_mode == 2) || 1333 (direction == FD_DIR_READ && dma_mode == 1) || 1334 (direction == FD_DIR_VERIFY)) { 1335 /* No access is allowed until DMA transfer has completed */ 1336 fdctrl->msr &= ~FD_MSR_RQM; 1337 if (direction != FD_DIR_VERIFY) { 1338 /* Now, we just have to wait for the DMA controller to 1339 * recall us... 1340 */ 1341 DMA_hold_DREQ(fdctrl->dma_chann); 1342 DMA_schedule(fdctrl->dma_chann); 1343 } else { 1344 /* Start transfer */ 1345 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0, 1346 fdctrl->data_len); 1347 } 1348 return; 1349 } else { 1350 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode, 1351 direction); 1352 } 1353 } 1354 FLOPPY_DPRINTF("start non-DMA transfer\n"); 1355 fdctrl->msr |= FD_MSR_NONDMA; 1356 if (direction != FD_DIR_WRITE) 1357 fdctrl->msr |= FD_MSR_DIO; 1358 /* IO based transfer: calculate len */ 1359 fdctrl_raise_irq(fdctrl); 1360 } 1361 1362 /* Prepare a transfer of deleted data */ 1363 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction) 1364 { 1365 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n"); 1366 1367 /* We don't handle deleted data, 1368 * so we don't return *ANYTHING* 1369 */ 1370 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1371 } 1372 1373 /* handlers for DMA transfers */ 1374 static int fdctrl_transfer_handler (void *opaque, int nchan, 1375 int dma_pos, int dma_len) 1376 { 1377 FDCtrl *fdctrl; 1378 FDrive *cur_drv; 1379 int len, start_pos, rel_pos; 1380 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00; 1381 1382 fdctrl = opaque; 1383 if (fdctrl->msr & FD_MSR_RQM) { 1384 FLOPPY_DPRINTF("Not in DMA transfer mode !\n"); 1385 return 0; 1386 } 1387 cur_drv = get_cur_drv(fdctrl); 1388 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL || 1389 fdctrl->data_dir == FD_DIR_SCANH) 1390 status2 = FD_SR2_SNS; 1391 if (dma_len > fdctrl->data_len) 1392 dma_len = fdctrl->data_len; 1393 if (cur_drv->blk == NULL) { 1394 if (fdctrl->data_dir == FD_DIR_WRITE) 1395 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1396 else 1397 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1398 len = 0; 1399 goto transfer_error; 1400 } 1401 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; 1402 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) { 1403 len = dma_len - fdctrl->data_pos; 1404 if (len + rel_pos > FD_SECTOR_LEN) 1405 len = FD_SECTOR_LEN - rel_pos; 1406 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x " 1407 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos, 1408 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head, 1409 cur_drv->track, cur_drv->sect, fd_sector(cur_drv), 1410 fd_sector(cur_drv) * FD_SECTOR_LEN); 1411 if (fdctrl->data_dir != FD_DIR_WRITE || 1412 len < FD_SECTOR_LEN || rel_pos != 0) { 1413 /* READ & SCAN commands and realign to a sector for WRITE */ 1414 if (blk_read(cur_drv->blk, fd_sector(cur_drv), 1415 fdctrl->fifo, 1) < 0) { 1416 FLOPPY_DPRINTF("Floppy: error getting sector %d\n", 1417 fd_sector(cur_drv)); 1418 /* Sure, image size is too small... */ 1419 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1420 } 1421 } 1422 switch (fdctrl->data_dir) { 1423 case FD_DIR_READ: 1424 /* READ commands */ 1425 DMA_write_memory (nchan, fdctrl->fifo + rel_pos, 1426 fdctrl->data_pos, len); 1427 break; 1428 case FD_DIR_WRITE: 1429 /* WRITE commands */ 1430 if (cur_drv->ro) { 1431 /* Handle readonly medium early, no need to do DMA, touch the 1432 * LED or attempt any writes. A real floppy doesn't attempt 1433 * to write to readonly media either. */ 1434 fdctrl_stop_transfer(fdctrl, 1435 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW, 1436 0x00); 1437 goto transfer_error; 1438 } 1439 1440 DMA_read_memory (nchan, fdctrl->fifo + rel_pos, 1441 fdctrl->data_pos, len); 1442 if (blk_write(cur_drv->blk, fd_sector(cur_drv), 1443 fdctrl->fifo, 1) < 0) { 1444 FLOPPY_DPRINTF("error writing sector %d\n", 1445 fd_sector(cur_drv)); 1446 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1447 goto transfer_error; 1448 } 1449 break; 1450 case FD_DIR_VERIFY: 1451 /* VERIFY commands */ 1452 break; 1453 default: 1454 /* SCAN commands */ 1455 { 1456 uint8_t tmpbuf[FD_SECTOR_LEN]; 1457 int ret; 1458 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len); 1459 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len); 1460 if (ret == 0) { 1461 status2 = FD_SR2_SEH; 1462 goto end_transfer; 1463 } 1464 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) || 1465 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) { 1466 status2 = 0x00; 1467 goto end_transfer; 1468 } 1469 } 1470 break; 1471 } 1472 fdctrl->data_pos += len; 1473 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; 1474 if (rel_pos == 0) { 1475 /* Seek to next sector */ 1476 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) 1477 break; 1478 } 1479 } 1480 end_transfer: 1481 len = fdctrl->data_pos - start_pos; 1482 FLOPPY_DPRINTF("end transfer %d %d %d\n", 1483 fdctrl->data_pos, len, fdctrl->data_len); 1484 if (fdctrl->data_dir == FD_DIR_SCANE || 1485 fdctrl->data_dir == FD_DIR_SCANL || 1486 fdctrl->data_dir == FD_DIR_SCANH) 1487 status2 = FD_SR2_SEH; 1488 fdctrl->data_len -= len; 1489 fdctrl_stop_transfer(fdctrl, status0, status1, status2); 1490 transfer_error: 1491 1492 return len; 1493 } 1494 1495 /* Data register : 0x05 */ 1496 static uint32_t fdctrl_read_data(FDCtrl *fdctrl) 1497 { 1498 FDrive *cur_drv; 1499 uint32_t retval = 0; 1500 int pos; 1501 1502 cur_drv = get_cur_drv(fdctrl); 1503 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1504 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) { 1505 FLOPPY_DPRINTF("error: controller not ready for reading\n"); 1506 return 0; 1507 } 1508 pos = fdctrl->data_pos; 1509 if (fdctrl->msr & FD_MSR_NONDMA) { 1510 pos %= FD_SECTOR_LEN; 1511 if (pos == 0) { 1512 if (fdctrl->data_pos != 0) 1513 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { 1514 FLOPPY_DPRINTF("error seeking to next sector %d\n", 1515 fd_sector(cur_drv)); 1516 return 0; 1517 } 1518 if (blk_read(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1) 1519 < 0) { 1520 FLOPPY_DPRINTF("error getting sector %d\n", 1521 fd_sector(cur_drv)); 1522 /* Sure, image size is too small... */ 1523 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1524 } 1525 } 1526 } 1527 retval = fdctrl->fifo[pos]; 1528 if (++fdctrl->data_pos == fdctrl->data_len) { 1529 fdctrl->data_pos = 0; 1530 /* Switch from transfer mode to status mode 1531 * then from status mode to command mode 1532 */ 1533 if (fdctrl->msr & FD_MSR_NONDMA) { 1534 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1535 } else { 1536 fdctrl_reset_fifo(fdctrl); 1537 fdctrl_reset_irq(fdctrl); 1538 } 1539 } 1540 FLOPPY_DPRINTF("data register: 0x%02x\n", retval); 1541 1542 return retval; 1543 } 1544 1545 static void fdctrl_format_sector(FDCtrl *fdctrl) 1546 { 1547 FDrive *cur_drv; 1548 uint8_t kh, kt, ks; 1549 1550 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1551 cur_drv = get_cur_drv(fdctrl); 1552 kt = fdctrl->fifo[6]; 1553 kh = fdctrl->fifo[7]; 1554 ks = fdctrl->fifo[8]; 1555 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n", 1556 GET_CUR_DRV(fdctrl), kh, kt, ks, 1557 fd_sector_calc(kh, kt, ks, cur_drv->last_sect, 1558 NUM_SIDES(cur_drv))); 1559 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { 1560 case 2: 1561 /* sect too big */ 1562 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1563 fdctrl->fifo[3] = kt; 1564 fdctrl->fifo[4] = kh; 1565 fdctrl->fifo[5] = ks; 1566 return; 1567 case 3: 1568 /* track too big */ 1569 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); 1570 fdctrl->fifo[3] = kt; 1571 fdctrl->fifo[4] = kh; 1572 fdctrl->fifo[5] = ks; 1573 return; 1574 case 4: 1575 /* No seek enabled */ 1576 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); 1577 fdctrl->fifo[3] = kt; 1578 fdctrl->fifo[4] = kh; 1579 fdctrl->fifo[5] = ks; 1580 return; 1581 case 1: 1582 fdctrl->status0 |= FD_SR0_SEEK; 1583 break; 1584 default: 1585 break; 1586 } 1587 memset(fdctrl->fifo, 0, FD_SECTOR_LEN); 1588 if (cur_drv->blk == NULL || 1589 blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { 1590 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv)); 1591 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); 1592 } else { 1593 if (cur_drv->sect == cur_drv->last_sect) { 1594 fdctrl->data_state &= ~FD_STATE_FORMAT; 1595 /* Last sector done */ 1596 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1597 } else { 1598 /* More to do */ 1599 fdctrl->data_pos = 0; 1600 fdctrl->data_len = 4; 1601 } 1602 } 1603 } 1604 1605 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction) 1606 { 1607 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0; 1608 fdctrl->fifo[0] = fdctrl->lock << 4; 1609 fdctrl_set_fifo(fdctrl, 1); 1610 } 1611 1612 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction) 1613 { 1614 FDrive *cur_drv = get_cur_drv(fdctrl); 1615 1616 /* Drives position */ 1617 fdctrl->fifo[0] = drv0(fdctrl)->track; 1618 fdctrl->fifo[1] = drv1(fdctrl)->track; 1619 #if MAX_FD == 4 1620 fdctrl->fifo[2] = drv2(fdctrl)->track; 1621 fdctrl->fifo[3] = drv3(fdctrl)->track; 1622 #else 1623 fdctrl->fifo[2] = 0; 1624 fdctrl->fifo[3] = 0; 1625 #endif 1626 /* timers */ 1627 fdctrl->fifo[4] = fdctrl->timer0; 1628 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0); 1629 fdctrl->fifo[6] = cur_drv->last_sect; 1630 fdctrl->fifo[7] = (fdctrl->lock << 7) | 1631 (cur_drv->perpendicular << 2); 1632 fdctrl->fifo[8] = fdctrl->config; 1633 fdctrl->fifo[9] = fdctrl->precomp_trk; 1634 fdctrl_set_fifo(fdctrl, 10); 1635 } 1636 1637 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction) 1638 { 1639 /* Controller's version */ 1640 fdctrl->fifo[0] = fdctrl->version; 1641 fdctrl_set_fifo(fdctrl, 1); 1642 } 1643 1644 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction) 1645 { 1646 fdctrl->fifo[0] = 0x41; /* Stepping 1 */ 1647 fdctrl_set_fifo(fdctrl, 1); 1648 } 1649 1650 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction) 1651 { 1652 FDrive *cur_drv = get_cur_drv(fdctrl); 1653 1654 /* Drives position */ 1655 drv0(fdctrl)->track = fdctrl->fifo[3]; 1656 drv1(fdctrl)->track = fdctrl->fifo[4]; 1657 #if MAX_FD == 4 1658 drv2(fdctrl)->track = fdctrl->fifo[5]; 1659 drv3(fdctrl)->track = fdctrl->fifo[6]; 1660 #endif 1661 /* timers */ 1662 fdctrl->timer0 = fdctrl->fifo[7]; 1663 fdctrl->timer1 = fdctrl->fifo[8]; 1664 cur_drv->last_sect = fdctrl->fifo[9]; 1665 fdctrl->lock = fdctrl->fifo[10] >> 7; 1666 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF; 1667 fdctrl->config = fdctrl->fifo[11]; 1668 fdctrl->precomp_trk = fdctrl->fifo[12]; 1669 fdctrl->pwrd = fdctrl->fifo[13]; 1670 fdctrl_reset_fifo(fdctrl); 1671 } 1672 1673 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction) 1674 { 1675 FDrive *cur_drv = get_cur_drv(fdctrl); 1676 1677 fdctrl->fifo[0] = 0; 1678 fdctrl->fifo[1] = 0; 1679 /* Drives position */ 1680 fdctrl->fifo[2] = drv0(fdctrl)->track; 1681 fdctrl->fifo[3] = drv1(fdctrl)->track; 1682 #if MAX_FD == 4 1683 fdctrl->fifo[4] = drv2(fdctrl)->track; 1684 fdctrl->fifo[5] = drv3(fdctrl)->track; 1685 #else 1686 fdctrl->fifo[4] = 0; 1687 fdctrl->fifo[5] = 0; 1688 #endif 1689 /* timers */ 1690 fdctrl->fifo[6] = fdctrl->timer0; 1691 fdctrl->fifo[7] = fdctrl->timer1; 1692 fdctrl->fifo[8] = cur_drv->last_sect; 1693 fdctrl->fifo[9] = (fdctrl->lock << 7) | 1694 (cur_drv->perpendicular << 2); 1695 fdctrl->fifo[10] = fdctrl->config; 1696 fdctrl->fifo[11] = fdctrl->precomp_trk; 1697 fdctrl->fifo[12] = fdctrl->pwrd; 1698 fdctrl->fifo[13] = 0; 1699 fdctrl->fifo[14] = 0; 1700 fdctrl_set_fifo(fdctrl, 15); 1701 } 1702 1703 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction) 1704 { 1705 FDrive *cur_drv = get_cur_drv(fdctrl); 1706 1707 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; 1708 timer_mod(fdctrl->result_timer, 1709 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 50)); 1710 } 1711 1712 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction) 1713 { 1714 FDrive *cur_drv; 1715 1716 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1717 cur_drv = get_cur_drv(fdctrl); 1718 fdctrl->data_state |= FD_STATE_FORMAT; 1719 if (fdctrl->fifo[0] & 0x80) 1720 fdctrl->data_state |= FD_STATE_MULTI; 1721 else 1722 fdctrl->data_state &= ~FD_STATE_MULTI; 1723 cur_drv->bps = 1724 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2]; 1725 #if 0 1726 cur_drv->last_sect = 1727 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] : 1728 fdctrl->fifo[3] / 2; 1729 #else 1730 cur_drv->last_sect = fdctrl->fifo[3]; 1731 #endif 1732 /* TODO: implement format using DMA expected by the Bochs BIOS 1733 * and Linux fdformat (read 3 bytes per sector via DMA and fill 1734 * the sector with the specified fill byte 1735 */ 1736 fdctrl->data_state &= ~FD_STATE_FORMAT; 1737 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1738 } 1739 1740 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction) 1741 { 1742 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF; 1743 fdctrl->timer1 = fdctrl->fifo[2] >> 1; 1744 if (fdctrl->fifo[2] & 1) 1745 fdctrl->dor &= ~FD_DOR_DMAEN; 1746 else 1747 fdctrl->dor |= FD_DOR_DMAEN; 1748 /* No result back */ 1749 fdctrl_reset_fifo(fdctrl); 1750 } 1751 1752 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction) 1753 { 1754 FDrive *cur_drv; 1755 1756 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1757 cur_drv = get_cur_drv(fdctrl); 1758 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; 1759 /* 1 Byte status back */ 1760 fdctrl->fifo[0] = (cur_drv->ro << 6) | 1761 (cur_drv->track == 0 ? 0x10 : 0x00) | 1762 (cur_drv->head << 2) | 1763 GET_CUR_DRV(fdctrl) | 1764 0x28; 1765 fdctrl_set_fifo(fdctrl, 1); 1766 } 1767 1768 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction) 1769 { 1770 FDrive *cur_drv; 1771 1772 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1773 cur_drv = get_cur_drv(fdctrl); 1774 fd_recalibrate(cur_drv); 1775 fdctrl_reset_fifo(fdctrl); 1776 /* Raise Interrupt */ 1777 fdctrl->status0 |= FD_SR0_SEEK; 1778 fdctrl_raise_irq(fdctrl); 1779 } 1780 1781 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction) 1782 { 1783 FDrive *cur_drv = get_cur_drv(fdctrl); 1784 1785 if (fdctrl->reset_sensei > 0) { 1786 fdctrl->fifo[0] = 1787 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei; 1788 fdctrl->reset_sensei--; 1789 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) { 1790 fdctrl->fifo[0] = FD_SR0_INVCMD; 1791 fdctrl_set_fifo(fdctrl, 1); 1792 return; 1793 } else { 1794 fdctrl->fifo[0] = 1795 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0)) 1796 | GET_CUR_DRV(fdctrl); 1797 } 1798 1799 fdctrl->fifo[1] = cur_drv->track; 1800 fdctrl_set_fifo(fdctrl, 2); 1801 fdctrl_reset_irq(fdctrl); 1802 fdctrl->status0 = FD_SR0_RDYCHG; 1803 } 1804 1805 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction) 1806 { 1807 FDrive *cur_drv; 1808 1809 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1810 cur_drv = get_cur_drv(fdctrl); 1811 fdctrl_reset_fifo(fdctrl); 1812 /* The seek command just sends step pulses to the drive and doesn't care if 1813 * there is a medium inserted of if it's banging the head against the drive. 1814 */ 1815 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1); 1816 /* Raise Interrupt */ 1817 fdctrl->status0 |= FD_SR0_SEEK; 1818 fdctrl_raise_irq(fdctrl); 1819 } 1820 1821 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction) 1822 { 1823 FDrive *cur_drv = get_cur_drv(fdctrl); 1824 1825 if (fdctrl->fifo[1] & 0x80) 1826 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7; 1827 /* No result back */ 1828 fdctrl_reset_fifo(fdctrl); 1829 } 1830 1831 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction) 1832 { 1833 fdctrl->config = fdctrl->fifo[2]; 1834 fdctrl->precomp_trk = fdctrl->fifo[3]; 1835 /* No result back */ 1836 fdctrl_reset_fifo(fdctrl); 1837 } 1838 1839 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction) 1840 { 1841 fdctrl->pwrd = fdctrl->fifo[1]; 1842 fdctrl->fifo[0] = fdctrl->fifo[1]; 1843 fdctrl_set_fifo(fdctrl, 1); 1844 } 1845 1846 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction) 1847 { 1848 /* No result back */ 1849 fdctrl_reset_fifo(fdctrl); 1850 } 1851 1852 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction) 1853 { 1854 FDrive *cur_drv = get_cur_drv(fdctrl); 1855 1856 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) { 1857 /* Command parameters done */ 1858 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) { 1859 fdctrl->fifo[0] = fdctrl->fifo[1]; 1860 fdctrl->fifo[2] = 0; 1861 fdctrl->fifo[3] = 0; 1862 fdctrl_set_fifo(fdctrl, 4); 1863 } else { 1864 fdctrl_reset_fifo(fdctrl); 1865 } 1866 } else if (fdctrl->data_len > 7) { 1867 /* ERROR */ 1868 fdctrl->fifo[0] = 0x80 | 1869 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl); 1870 fdctrl_set_fifo(fdctrl, 1); 1871 } 1872 } 1873 1874 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction) 1875 { 1876 FDrive *cur_drv; 1877 1878 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1879 cur_drv = get_cur_drv(fdctrl); 1880 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) { 1881 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1, 1882 cur_drv->sect, 1); 1883 } else { 1884 fd_seek(cur_drv, cur_drv->head, 1885 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1); 1886 } 1887 fdctrl_reset_fifo(fdctrl); 1888 /* Raise Interrupt */ 1889 fdctrl->status0 |= FD_SR0_SEEK; 1890 fdctrl_raise_irq(fdctrl); 1891 } 1892 1893 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction) 1894 { 1895 FDrive *cur_drv; 1896 1897 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); 1898 cur_drv = get_cur_drv(fdctrl); 1899 if (fdctrl->fifo[2] > cur_drv->track) { 1900 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1); 1901 } else { 1902 fd_seek(cur_drv, cur_drv->head, 1903 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1); 1904 } 1905 fdctrl_reset_fifo(fdctrl); 1906 /* Raise Interrupt */ 1907 fdctrl->status0 |= FD_SR0_SEEK; 1908 fdctrl_raise_irq(fdctrl); 1909 } 1910 1911 static const struct { 1912 uint8_t value; 1913 uint8_t mask; 1914 const char* name; 1915 int parameters; 1916 void (*handler)(FDCtrl *fdctrl, int direction); 1917 int direction; 1918 } handlers[] = { 1919 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ }, 1920 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE }, 1921 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek }, 1922 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status }, 1923 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate }, 1924 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track }, 1925 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ }, 1926 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */ 1927 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */ 1928 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ }, 1929 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE }, 1930 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY }, 1931 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL }, 1932 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH }, 1933 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE }, 1934 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid }, 1935 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify }, 1936 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status }, 1937 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode }, 1938 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure }, 1939 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode }, 1940 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option }, 1941 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command }, 1942 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out }, 1943 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented }, 1944 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in }, 1945 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock }, 1946 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg }, 1947 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version }, 1948 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid }, 1949 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */ 1950 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */ 1951 }; 1952 /* Associate command to an index in the 'handlers' array */ 1953 static uint8_t command_to_handler[256]; 1954 1955 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value) 1956 { 1957 FDrive *cur_drv; 1958 int pos; 1959 1960 /* Reset mode */ 1961 if (!(fdctrl->dor & FD_DOR_nRESET)) { 1962 FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); 1963 return; 1964 } 1965 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) { 1966 FLOPPY_DPRINTF("error: controller not ready for writing\n"); 1967 return; 1968 } 1969 fdctrl->dsr &= ~FD_DSR_PWRDOWN; 1970 /* Is it write command time ? */ 1971 if (fdctrl->msr & FD_MSR_NONDMA) { 1972 /* FIFO data write */ 1973 pos = fdctrl->data_pos++; 1974 pos %= FD_SECTOR_LEN; 1975 fdctrl->fifo[pos] = value; 1976 if (pos == FD_SECTOR_LEN - 1 || 1977 fdctrl->data_pos == fdctrl->data_len) { 1978 cur_drv = get_cur_drv(fdctrl); 1979 if (blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1) 1980 < 0) { 1981 FLOPPY_DPRINTF("error writing sector %d\n", 1982 fd_sector(cur_drv)); 1983 return; 1984 } 1985 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { 1986 FLOPPY_DPRINTF("error seeking to next sector %d\n", 1987 fd_sector(cur_drv)); 1988 return; 1989 } 1990 } 1991 /* Switch from transfer mode to status mode 1992 * then from status mode to command mode 1993 */ 1994 if (fdctrl->data_pos == fdctrl->data_len) 1995 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 1996 return; 1997 } 1998 if (fdctrl->data_pos == 0) { 1999 /* Command */ 2000 pos = command_to_handler[value & 0xff]; 2001 FLOPPY_DPRINTF("%s command\n", handlers[pos].name); 2002 fdctrl->data_len = handlers[pos].parameters + 1; 2003 fdctrl->msr |= FD_MSR_CMDBUSY; 2004 } 2005 2006 FLOPPY_DPRINTF("%s: %02x\n", __func__, value); 2007 fdctrl->fifo[fdctrl->data_pos++] = value; 2008 if (fdctrl->data_pos == fdctrl->data_len) { 2009 /* We now have all parameters 2010 * and will be able to treat the command 2011 */ 2012 if (fdctrl->data_state & FD_STATE_FORMAT) { 2013 fdctrl_format_sector(fdctrl); 2014 return; 2015 } 2016 2017 pos = command_to_handler[fdctrl->fifo[0] & 0xff]; 2018 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name); 2019 (*handlers[pos].handler)(fdctrl, handlers[pos].direction); 2020 } 2021 } 2022 2023 static void fdctrl_result_timer(void *opaque) 2024 { 2025 FDCtrl *fdctrl = opaque; 2026 FDrive *cur_drv = get_cur_drv(fdctrl); 2027 2028 /* Pretend we are spinning. 2029 * This is needed for Coherent, which uses READ ID to check for 2030 * sector interleaving. 2031 */ 2032 if (cur_drv->last_sect != 0) { 2033 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1; 2034 } 2035 /* READ_ID can't automatically succeed! */ 2036 if (fdctrl->check_media_rate && 2037 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) { 2038 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n", 2039 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate); 2040 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); 2041 } else { 2042 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); 2043 } 2044 } 2045 2046 static void fdctrl_change_cb(void *opaque, bool load) 2047 { 2048 FDrive *drive = opaque; 2049 2050 drive->media_changed = 1; 2051 fd_revalidate(drive); 2052 } 2053 2054 static const BlockDevOps fdctrl_block_ops = { 2055 .change_media_cb = fdctrl_change_cb, 2056 }; 2057 2058 /* Init functions */ 2059 static void fdctrl_connect_drives(FDCtrl *fdctrl, Error **errp) 2060 { 2061 unsigned int i; 2062 FDrive *drive; 2063 2064 for (i = 0; i < MAX_FD; i++) { 2065 drive = &fdctrl->drives[i]; 2066 drive->fdctrl = fdctrl; 2067 2068 if (drive->blk) { 2069 if (blk_get_on_error(drive->blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC) { 2070 error_setg(errp, "fdc doesn't support drive option werror"); 2071 return; 2072 } 2073 if (blk_get_on_error(drive->blk, 1) != BLOCKDEV_ON_ERROR_REPORT) { 2074 error_setg(errp, "fdc doesn't support drive option rerror"); 2075 return; 2076 } 2077 } 2078 2079 fd_init(drive); 2080 fdctrl_change_cb(drive, 0); 2081 if (drive->blk) { 2082 blk_set_dev_ops(drive->blk, &fdctrl_block_ops, drive); 2083 } 2084 } 2085 } 2086 2087 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds) 2088 { 2089 DeviceState *dev; 2090 ISADevice *isadev; 2091 2092 isadev = isa_try_create(bus, TYPE_ISA_FDC); 2093 if (!isadev) { 2094 return NULL; 2095 } 2096 dev = DEVICE(isadev); 2097 2098 if (fds[0]) { 2099 qdev_prop_set_drive_nofail(dev, "driveA", blk_by_legacy_dinfo(fds[0])); 2100 } 2101 if (fds[1]) { 2102 qdev_prop_set_drive_nofail(dev, "driveB", blk_by_legacy_dinfo(fds[1])); 2103 } 2104 qdev_init_nofail(dev); 2105 2106 return isadev; 2107 } 2108 2109 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann, 2110 hwaddr mmio_base, DriveInfo **fds) 2111 { 2112 FDCtrl *fdctrl; 2113 DeviceState *dev; 2114 SysBusDevice *sbd; 2115 FDCtrlSysBus *sys; 2116 2117 dev = qdev_create(NULL, "sysbus-fdc"); 2118 sys = SYSBUS_FDC(dev); 2119 fdctrl = &sys->state; 2120 fdctrl->dma_chann = dma_chann; /* FIXME */ 2121 if (fds[0]) { 2122 qdev_prop_set_drive_nofail(dev, "driveA", blk_by_legacy_dinfo(fds[0])); 2123 } 2124 if (fds[1]) { 2125 qdev_prop_set_drive_nofail(dev, "driveB", blk_by_legacy_dinfo(fds[1])); 2126 } 2127 qdev_init_nofail(dev); 2128 sbd = SYS_BUS_DEVICE(dev); 2129 sysbus_connect_irq(sbd, 0, irq); 2130 sysbus_mmio_map(sbd, 0, mmio_base); 2131 } 2132 2133 void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base, 2134 DriveInfo **fds, qemu_irq *fdc_tc) 2135 { 2136 DeviceState *dev; 2137 FDCtrlSysBus *sys; 2138 2139 dev = qdev_create(NULL, "SUNW,fdtwo"); 2140 if (fds[0]) { 2141 qdev_prop_set_drive_nofail(dev, "drive", blk_by_legacy_dinfo(fds[0])); 2142 } 2143 qdev_init_nofail(dev); 2144 sys = SYSBUS_FDC(dev); 2145 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq); 2146 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base); 2147 *fdc_tc = qdev_get_gpio_in(dev, 0); 2148 } 2149 2150 static void fdctrl_realize_common(FDCtrl *fdctrl, Error **errp) 2151 { 2152 int i, j; 2153 static int command_tables_inited = 0; 2154 2155 /* Fill 'command_to_handler' lookup table */ 2156 if (!command_tables_inited) { 2157 command_tables_inited = 1; 2158 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) { 2159 for (j = 0; j < sizeof(command_to_handler); j++) { 2160 if ((j & handlers[i].mask) == handlers[i].value) { 2161 command_to_handler[j] = i; 2162 } 2163 } 2164 } 2165 } 2166 2167 FLOPPY_DPRINTF("init controller\n"); 2168 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN); 2169 fdctrl->fifo_size = 512; 2170 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 2171 fdctrl_result_timer, fdctrl); 2172 2173 fdctrl->version = 0x90; /* Intel 82078 controller */ 2174 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */ 2175 fdctrl->num_floppies = MAX_FD; 2176 2177 if (fdctrl->dma_chann != -1) { 2178 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl); 2179 } 2180 fdctrl_connect_drives(fdctrl, errp); 2181 } 2182 2183 static const MemoryRegionPortio fdc_portio_list[] = { 2184 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write }, 2185 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write }, 2186 PORTIO_END_OF_LIST(), 2187 }; 2188 2189 static void isabus_fdc_realize(DeviceState *dev, Error **errp) 2190 { 2191 ISADevice *isadev = ISA_DEVICE(dev); 2192 FDCtrlISABus *isa = ISA_FDC(dev); 2193 FDCtrl *fdctrl = &isa->state; 2194 Error *err = NULL; 2195 2196 isa_register_portio_list(isadev, isa->iobase, fdc_portio_list, fdctrl, 2197 "fdc"); 2198 2199 isa_init_irq(isadev, &fdctrl->irq, isa->irq); 2200 fdctrl->dma_chann = isa->dma; 2201 2202 qdev_set_legacy_instance_id(dev, isa->iobase, 2); 2203 fdctrl_realize_common(fdctrl, &err); 2204 if (err != NULL) { 2205 error_propagate(errp, err); 2206 return; 2207 } 2208 } 2209 2210 static void sysbus_fdc_initfn(Object *obj) 2211 { 2212 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 2213 FDCtrlSysBus *sys = SYSBUS_FDC(obj); 2214 FDCtrl *fdctrl = &sys->state; 2215 2216 fdctrl->dma_chann = -1; 2217 2218 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl, 2219 "fdc", 0x08); 2220 sysbus_init_mmio(sbd, &fdctrl->iomem); 2221 } 2222 2223 static void sun4m_fdc_initfn(Object *obj) 2224 { 2225 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 2226 FDCtrlSysBus *sys = SYSBUS_FDC(obj); 2227 FDCtrl *fdctrl = &sys->state; 2228 2229 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops, 2230 fdctrl, "fdctrl", 0x08); 2231 sysbus_init_mmio(sbd, &fdctrl->iomem); 2232 } 2233 2234 static void sysbus_fdc_common_initfn(Object *obj) 2235 { 2236 DeviceState *dev = DEVICE(obj); 2237 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 2238 FDCtrlSysBus *sys = SYSBUS_FDC(obj); 2239 FDCtrl *fdctrl = &sys->state; 2240 2241 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */ 2242 2243 sysbus_init_irq(sbd, &fdctrl->irq); 2244 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1); 2245 } 2246 2247 static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp) 2248 { 2249 FDCtrlSysBus *sys = SYSBUS_FDC(dev); 2250 FDCtrl *fdctrl = &sys->state; 2251 2252 fdctrl_realize_common(fdctrl, errp); 2253 } 2254 2255 FDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i) 2256 { 2257 FDCtrlISABus *isa = ISA_FDC(fdc); 2258 2259 return isa->state.drives[i].drive; 2260 } 2261 2262 static const VMStateDescription vmstate_isa_fdc ={ 2263 .name = "fdc", 2264 .version_id = 2, 2265 .minimum_version_id = 2, 2266 .fields = (VMStateField[]) { 2267 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl), 2268 VMSTATE_END_OF_LIST() 2269 } 2270 }; 2271 2272 static Property isa_fdc_properties[] = { 2273 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0), 2274 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6), 2275 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2), 2276 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].blk), 2277 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].blk), 2278 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate, 2279 0, true), 2280 DEFINE_PROP_END_OF_LIST(), 2281 }; 2282 2283 static void isabus_fdc_class_init(ObjectClass *klass, void *data) 2284 { 2285 DeviceClass *dc = DEVICE_CLASS(klass); 2286 2287 dc->realize = isabus_fdc_realize; 2288 dc->fw_name = "fdc"; 2289 dc->reset = fdctrl_external_reset_isa; 2290 dc->vmsd = &vmstate_isa_fdc; 2291 dc->props = isa_fdc_properties; 2292 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2293 } 2294 2295 static void isabus_fdc_instance_init(Object *obj) 2296 { 2297 FDCtrlISABus *isa = ISA_FDC(obj); 2298 2299 device_add_bootindex_property(obj, &isa->bootindexA, 2300 "bootindexA", "/floppy@0", 2301 DEVICE(obj), NULL); 2302 device_add_bootindex_property(obj, &isa->bootindexB, 2303 "bootindexB", "/floppy@1", 2304 DEVICE(obj), NULL); 2305 } 2306 2307 static const TypeInfo isa_fdc_info = { 2308 .name = TYPE_ISA_FDC, 2309 .parent = TYPE_ISA_DEVICE, 2310 .instance_size = sizeof(FDCtrlISABus), 2311 .class_init = isabus_fdc_class_init, 2312 .instance_init = isabus_fdc_instance_init, 2313 }; 2314 2315 static const VMStateDescription vmstate_sysbus_fdc ={ 2316 .name = "fdc", 2317 .version_id = 2, 2318 .minimum_version_id = 2, 2319 .fields = (VMStateField[]) { 2320 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl), 2321 VMSTATE_END_OF_LIST() 2322 } 2323 }; 2324 2325 static Property sysbus_fdc_properties[] = { 2326 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].blk), 2327 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].blk), 2328 DEFINE_PROP_END_OF_LIST(), 2329 }; 2330 2331 static void sysbus_fdc_class_init(ObjectClass *klass, void *data) 2332 { 2333 DeviceClass *dc = DEVICE_CLASS(klass); 2334 2335 dc->props = sysbus_fdc_properties; 2336 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2337 } 2338 2339 static const TypeInfo sysbus_fdc_info = { 2340 .name = "sysbus-fdc", 2341 .parent = TYPE_SYSBUS_FDC, 2342 .instance_init = sysbus_fdc_initfn, 2343 .class_init = sysbus_fdc_class_init, 2344 }; 2345 2346 static Property sun4m_fdc_properties[] = { 2347 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].blk), 2348 DEFINE_PROP_END_OF_LIST(), 2349 }; 2350 2351 static void sun4m_fdc_class_init(ObjectClass *klass, void *data) 2352 { 2353 DeviceClass *dc = DEVICE_CLASS(klass); 2354 2355 dc->props = sun4m_fdc_properties; 2356 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 2357 } 2358 2359 static const TypeInfo sun4m_fdc_info = { 2360 .name = "SUNW,fdtwo", 2361 .parent = TYPE_SYSBUS_FDC, 2362 .instance_init = sun4m_fdc_initfn, 2363 .class_init = sun4m_fdc_class_init, 2364 }; 2365 2366 static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data) 2367 { 2368 DeviceClass *dc = DEVICE_CLASS(klass); 2369 2370 dc->realize = sysbus_fdc_common_realize; 2371 dc->reset = fdctrl_external_reset_sysbus; 2372 dc->vmsd = &vmstate_sysbus_fdc; 2373 } 2374 2375 static const TypeInfo sysbus_fdc_type_info = { 2376 .name = TYPE_SYSBUS_FDC, 2377 .parent = TYPE_SYS_BUS_DEVICE, 2378 .instance_size = sizeof(FDCtrlSysBus), 2379 .instance_init = sysbus_fdc_common_initfn, 2380 .abstract = true, 2381 .class_init = sysbus_fdc_common_class_init, 2382 }; 2383 2384 static void fdc_register_types(void) 2385 { 2386 type_register_static(&isa_fdc_info); 2387 type_register_static(&sysbus_fdc_type_info); 2388 type_register_static(&sysbus_fdc_info); 2389 type_register_static(&sun4m_fdc_info); 2390 } 2391 2392 type_init(fdc_register_types) 2393