1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/datadir.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "hw/sysbus.h" 37 #include "hw/arm/boot.h" 38 #include "hw/arm/primecell.h" 39 #include "hw/arm/virt.h" 40 #include "hw/block/flash.h" 41 #include "hw/vfio/vfio-calxeda-xgmac.h" 42 #include "hw/vfio/vfio-amd-xgbe.h" 43 #include "hw/display/ramfb.h" 44 #include "net/net.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/numa.h" 47 #include "sysemu/runstate.h" 48 #include "sysemu/tpm.h" 49 #include "sysemu/tcg.h" 50 #include "sysemu/kvm.h" 51 #include "sysemu/hvf.h" 52 #include "sysemu/qtest.h" 53 #include "hw/loader.h" 54 #include "qapi/error.h" 55 #include "qemu/bitops.h" 56 #include "qemu/error-report.h" 57 #include "qemu/module.h" 58 #include "hw/pci-host/gpex.h" 59 #include "hw/virtio/virtio-pci.h" 60 #include "hw/core/sysbus-fdt.h" 61 #include "hw/platform-bus.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/arm/fdt.h" 64 #include "hw/intc/arm_gic.h" 65 #include "hw/intc/arm_gicv3_common.h" 66 #include "hw/intc/arm_gicv3_its_common.h" 67 #include "hw/irq.h" 68 #include "kvm_arm.h" 69 #include "hw/firmware/smbios.h" 70 #include "qapi/visitor.h" 71 #include "qapi/qapi-visit-common.h" 72 #include "qapi/qmp/qlist.h" 73 #include "standard-headers/linux/input.h" 74 #include "hw/arm/smmuv3.h" 75 #include "hw/acpi/acpi.h" 76 #include "target/arm/cpu-qom.h" 77 #include "target/arm/internals.h" 78 #include "target/arm/multiprocessing.h" 79 #include "hw/mem/pc-dimm.h" 80 #include "hw/mem/nvdimm.h" 81 #include "hw/acpi/generic_event_device.h" 82 #include "hw/virtio/virtio-md-pci.h" 83 #include "hw/virtio/virtio-iommu.h" 84 #include "hw/char/pl011.h" 85 #include "qemu/guest-random.h" 86 87 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 88 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 89 void *data) \ 90 { \ 91 MachineClass *mc = MACHINE_CLASS(oc); \ 92 virt_machine_##major##_##minor##_options(mc); \ 93 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 94 if (latest) { \ 95 mc->alias = "virt"; \ 96 } \ 97 } \ 98 static const TypeInfo machvirt_##major##_##minor##_info = { \ 99 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 100 .parent = TYPE_VIRT_MACHINE, \ 101 .class_init = virt_##major##_##minor##_class_init, \ 102 }; \ 103 static void machvirt_machine_##major##_##minor##_init(void) \ 104 { \ 105 type_register_static(&machvirt_##major##_##minor##_info); \ 106 } \ 107 type_init(machvirt_machine_##major##_##minor##_init); 108 109 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 110 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 111 #define DEFINE_VIRT_MACHINE(major, minor) \ 112 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 113 114 115 /* Number of external interrupt lines to configure the GIC with */ 116 #define NUM_IRQS 256 117 118 #define PLATFORM_BUS_NUM_IRQS 64 119 120 /* Legacy RAM limit in GB (< version 4.0) */ 121 #define LEGACY_RAMLIMIT_GB 255 122 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 123 124 /* Addresses and sizes of our components. 125 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 126 * 128MB..256MB is used for miscellaneous device I/O. 127 * 256MB..1GB is reserved for possible future PCI support (ie where the 128 * PCI memory window will go if we add a PCI host controller). 129 * 1GB and up is RAM (which may happily spill over into the 130 * high memory region beyond 4GB). 131 * This represents a compromise between how much RAM can be given to 132 * a 32 bit VM and leaving space for expansion and in particular for PCI. 133 * Note that devices should generally be placed at multiples of 0x10000, 134 * to accommodate guests using 64K pages. 135 */ 136 static const MemMapEntry base_memmap[] = { 137 /* Space up to 0x8000000 is reserved for a boot ROM */ 138 [VIRT_FLASH] = { 0, 0x08000000 }, 139 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 140 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 141 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 142 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 143 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 144 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 145 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 146 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 147 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 148 /* This redistributor space allows up to 2*64kB*123 CPUs */ 149 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 150 [VIRT_UART] = { 0x09000000, 0x00001000 }, 151 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 152 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 153 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 154 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 155 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 156 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 157 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 158 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 159 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 160 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 161 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 162 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 163 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 164 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 165 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 166 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 167 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 168 /* Actual RAM size depends on initial RAM and device memory settings */ 169 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 170 }; 171 172 /* 173 * Highmem IO Regions: This memory map is floating, located after the RAM. 174 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 175 * top of the RAM, so that its base get the same alignment as the size, 176 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 177 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 178 * Note the extended_memmap is sized so that it eventually also includes the 179 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 180 * index of base_memmap). 181 * 182 * The memory map for these Highmem IO Regions can be in legacy or compact 183 * layout, depending on 'compact-highmem' property. With legacy layout, the 184 * PA space for one specific region is always reserved, even if the region 185 * has been disabled or doesn't fit into the PA space. However, the PA space 186 * for the region won't be reserved in these circumstances with compact layout. 187 */ 188 static MemMapEntry extended_memmap[] = { 189 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 190 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 191 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 192 /* Second PCIe window */ 193 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 194 }; 195 196 static const int a15irqmap[] = { 197 [VIRT_UART] = 1, 198 [VIRT_RTC] = 2, 199 [VIRT_PCIE] = 3, /* ... to 6 */ 200 [VIRT_GPIO] = 7, 201 [VIRT_SECURE_UART] = 8, 202 [VIRT_ACPI_GED] = 9, 203 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 204 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 205 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 206 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 207 }; 208 209 static void create_randomness(MachineState *ms, const char *node) 210 { 211 struct { 212 uint64_t kaslr; 213 uint8_t rng[32]; 214 } seed; 215 216 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 217 return; 218 } 219 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr); 220 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); 221 } 222 223 static void create_fdt(VirtMachineState *vms) 224 { 225 MachineState *ms = MACHINE(vms); 226 int nb_numa_nodes = ms->numa_state->num_nodes; 227 void *fdt = create_device_tree(&vms->fdt_size); 228 229 if (!fdt) { 230 error_report("create_device_tree() failed"); 231 exit(1); 232 } 233 234 ms->fdt = fdt; 235 236 /* Header */ 237 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 238 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 239 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 240 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt"); 241 242 /* /chosen must exist for load_dtb to fill in necessary properties later */ 243 qemu_fdt_add_subnode(fdt, "/chosen"); 244 if (vms->dtb_randomness) { 245 create_randomness(ms, "/chosen"); 246 } 247 248 if (vms->secure) { 249 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 250 if (vms->dtb_randomness) { 251 create_randomness(ms, "/secure-chosen"); 252 } 253 } 254 255 /* Clock node, for the benefit of the UART. The kernel device tree 256 * binding documentation claims the PL011 node clock properties are 257 * optional but in practice if you omit them the kernel refuses to 258 * probe for the device. 259 */ 260 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 261 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 262 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 263 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 264 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 265 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 266 "clk24mhz"); 267 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 268 269 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 270 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 271 uint32_t *matrix = g_malloc0(size); 272 int idx, i, j; 273 274 for (i = 0; i < nb_numa_nodes; i++) { 275 for (j = 0; j < nb_numa_nodes; j++) { 276 idx = (i * nb_numa_nodes + j) * 3; 277 matrix[idx + 0] = cpu_to_be32(i); 278 matrix[idx + 1] = cpu_to_be32(j); 279 matrix[idx + 2] = 280 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 281 } 282 } 283 284 qemu_fdt_add_subnode(fdt, "/distance-map"); 285 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 286 "numa-distance-map-v1"); 287 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 288 matrix, size); 289 g_free(matrix); 290 } 291 } 292 293 static void fdt_add_timer_nodes(const VirtMachineState *vms) 294 { 295 /* On real hardware these interrupts are level-triggered. 296 * On KVM they were edge-triggered before host kernel version 4.4, 297 * and level-triggered afterwards. 298 * On emulated QEMU they are level-triggered. 299 * 300 * Getting the DTB info about them wrong is awkward for some 301 * guest kernels: 302 * pre-4.8 ignore the DT and leave the interrupt configured 303 * with whatever the GIC reset value (or the bootloader) left it at 304 * 4.8 before rc6 honour the incorrect data by programming it back 305 * into the GIC, causing problems 306 * 4.8rc6 and later ignore the DT and always write "level triggered" 307 * into the GIC 308 * 309 * For backwards-compatibility, virt-2.8 and earlier will continue 310 * to say these are edge-triggered, but later machines will report 311 * the correct information. 312 */ 313 ARMCPU *armcpu; 314 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 315 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 316 MachineState *ms = MACHINE(vms); 317 318 if (vmc->claim_edge_triggered_timers) { 319 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 320 } 321 322 if (vms->gic_version == VIRT_GIC_VERSION_2) { 323 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 324 GIC_FDT_IRQ_PPI_CPU_WIDTH, 325 (1 << MACHINE(vms)->smp.cpus) - 1); 326 } 327 328 qemu_fdt_add_subnode(ms->fdt, "/timer"); 329 330 armcpu = ARM_CPU(qemu_get_cpu(0)); 331 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 332 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 333 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 334 compat, sizeof(compat)); 335 } else { 336 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 337 "arm,armv7-timer"); 338 } 339 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 340 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 341 GIC_FDT_IRQ_TYPE_PPI, 342 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, 343 GIC_FDT_IRQ_TYPE_PPI, 344 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, 345 GIC_FDT_IRQ_TYPE_PPI, 346 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, 347 GIC_FDT_IRQ_TYPE_PPI, 348 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags); 349 } 350 351 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 352 { 353 int cpu; 354 int addr_cells = 1; 355 const MachineState *ms = MACHINE(vms); 356 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 357 int smp_cpus = ms->smp.cpus; 358 359 /* 360 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml 361 * On ARM v8 64-bit systems value should be set to 2, 362 * that corresponds to the MPIDR_EL1 register size. 363 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 364 * in the system, #address-cells can be set to 1, since 365 * MPIDR_EL1[63:32] bits are not used for CPUs 366 * identification. 367 * 368 * Here we actually don't know whether our system is 32- or 64-bit one. 369 * The simplest way to go is to examine affinity IDs of all our CPUs. If 370 * at least one of them has Aff3 populated, we set #address-cells to 2. 371 */ 372 for (cpu = 0; cpu < smp_cpus; cpu++) { 373 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 374 375 if (arm_cpu_mp_affinity(armcpu) & ARM_AFF3_MASK) { 376 addr_cells = 2; 377 break; 378 } 379 } 380 381 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 382 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 383 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 384 385 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 386 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 387 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 388 CPUState *cs = CPU(armcpu); 389 390 qemu_fdt_add_subnode(ms->fdt, nodename); 391 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 392 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 393 armcpu->dtb_compatible); 394 395 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 396 qemu_fdt_setprop_string(ms->fdt, nodename, 397 "enable-method", "psci"); 398 } 399 400 if (addr_cells == 2) { 401 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 402 arm_cpu_mp_affinity(armcpu)); 403 } else { 404 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 405 arm_cpu_mp_affinity(armcpu)); 406 } 407 408 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 409 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 410 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 411 } 412 413 if (!vmc->no_cpu_topology) { 414 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 415 qemu_fdt_alloc_phandle(ms->fdt)); 416 } 417 418 g_free(nodename); 419 } 420 421 if (!vmc->no_cpu_topology) { 422 /* 423 * Add vCPU topology description through fdt node cpu-map. 424 * 425 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt 426 * In a SMP system, the hierarchy of CPUs can be defined through 427 * four entities that are used to describe the layout of CPUs in 428 * the system: socket/cluster/core/thread. 429 * 430 * A socket node represents the boundary of system physical package 431 * and its child nodes must be one or more cluster nodes. A system 432 * can contain several layers of clustering within a single physical 433 * package and cluster nodes can be contained in parent cluster nodes. 434 * 435 * Note: currently we only support one layer of clustering within 436 * each physical package. 437 */ 438 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 439 440 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 441 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); 442 char *map_path; 443 444 if (ms->smp.threads > 1) { 445 map_path = g_strdup_printf( 446 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", 447 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), 448 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, 449 (cpu / ms->smp.threads) % ms->smp.cores, 450 cpu % ms->smp.threads); 451 } else { 452 map_path = g_strdup_printf( 453 "/cpus/cpu-map/socket%d/cluster%d/core%d", 454 cpu / (ms->smp.clusters * ms->smp.cores), 455 (cpu / ms->smp.cores) % ms->smp.clusters, 456 cpu % ms->smp.cores); 457 } 458 qemu_fdt_add_path(ms->fdt, map_path); 459 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 460 461 g_free(map_path); 462 g_free(cpu_path); 463 } 464 } 465 } 466 467 static void fdt_add_its_gic_node(VirtMachineState *vms) 468 { 469 char *nodename; 470 MachineState *ms = MACHINE(vms); 471 472 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 473 nodename = g_strdup_printf("/intc/its@%" PRIx64, 474 vms->memmap[VIRT_GIC_ITS].base); 475 qemu_fdt_add_subnode(ms->fdt, nodename); 476 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 477 "arm,gic-v3-its"); 478 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 479 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1); 480 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 481 2, vms->memmap[VIRT_GIC_ITS].base, 482 2, vms->memmap[VIRT_GIC_ITS].size); 483 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 484 g_free(nodename); 485 } 486 487 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 488 { 489 MachineState *ms = MACHINE(vms); 490 char *nodename; 491 492 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 493 vms->memmap[VIRT_GIC_V2M].base); 494 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 495 qemu_fdt_add_subnode(ms->fdt, nodename); 496 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 497 "arm,gic-v2m-frame"); 498 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 499 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 500 2, vms->memmap[VIRT_GIC_V2M].base, 501 2, vms->memmap[VIRT_GIC_V2M].size); 502 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 503 g_free(nodename); 504 } 505 506 static void fdt_add_gic_node(VirtMachineState *vms) 507 { 508 MachineState *ms = MACHINE(vms); 509 char *nodename; 510 511 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 512 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 513 514 nodename = g_strdup_printf("/intc@%" PRIx64, 515 vms->memmap[VIRT_GIC_DIST].base); 516 qemu_fdt_add_subnode(ms->fdt, nodename); 517 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 518 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 519 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 520 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 521 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 522 if (vms->gic_version != VIRT_GIC_VERSION_2) { 523 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 524 525 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 526 "arm,gic-v3"); 527 528 qemu_fdt_setprop_cell(ms->fdt, nodename, 529 "#redistributor-regions", nb_redist_regions); 530 531 if (nb_redist_regions == 1) { 532 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 533 2, vms->memmap[VIRT_GIC_DIST].base, 534 2, vms->memmap[VIRT_GIC_DIST].size, 535 2, vms->memmap[VIRT_GIC_REDIST].base, 536 2, vms->memmap[VIRT_GIC_REDIST].size); 537 } else { 538 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 539 2, vms->memmap[VIRT_GIC_DIST].base, 540 2, vms->memmap[VIRT_GIC_DIST].size, 541 2, vms->memmap[VIRT_GIC_REDIST].base, 542 2, vms->memmap[VIRT_GIC_REDIST].size, 543 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 544 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 545 } 546 547 if (vms->virt) { 548 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 549 GIC_FDT_IRQ_TYPE_PPI, 550 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), 551 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 552 } 553 } else { 554 /* 'cortex-a15-gic' means 'GIC v2' */ 555 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 556 "arm,cortex-a15-gic"); 557 if (!vms->virt) { 558 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 559 2, vms->memmap[VIRT_GIC_DIST].base, 560 2, vms->memmap[VIRT_GIC_DIST].size, 561 2, vms->memmap[VIRT_GIC_CPU].base, 562 2, vms->memmap[VIRT_GIC_CPU].size); 563 } else { 564 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 565 2, vms->memmap[VIRT_GIC_DIST].base, 566 2, vms->memmap[VIRT_GIC_DIST].size, 567 2, vms->memmap[VIRT_GIC_CPU].base, 568 2, vms->memmap[VIRT_GIC_CPU].size, 569 2, vms->memmap[VIRT_GIC_HYP].base, 570 2, vms->memmap[VIRT_GIC_HYP].size, 571 2, vms->memmap[VIRT_GIC_VCPU].base, 572 2, vms->memmap[VIRT_GIC_VCPU].size); 573 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 574 GIC_FDT_IRQ_TYPE_PPI, 575 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ), 576 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 577 } 578 } 579 580 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 581 g_free(nodename); 582 } 583 584 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 585 { 586 ARMCPU *armcpu = ARM_CPU(first_cpu); 587 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 588 MachineState *ms = MACHINE(vms); 589 590 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 591 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 592 return; 593 } 594 595 if (vms->gic_version == VIRT_GIC_VERSION_2) { 596 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 597 GIC_FDT_IRQ_PPI_CPU_WIDTH, 598 (1 << MACHINE(vms)->smp.cpus) - 1); 599 } 600 601 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 602 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 603 const char compat[] = "arm,armv8-pmuv3"; 604 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 605 compat, sizeof(compat)); 606 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 607 GIC_FDT_IRQ_TYPE_PPI, 608 INTID_TO_PPI(VIRTUAL_PMU_IRQ), irqflags); 609 } 610 } 611 612 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 613 { 614 DeviceState *dev; 615 MachineState *ms = MACHINE(vms); 616 int irq = vms->irqmap[VIRT_ACPI_GED]; 617 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 618 619 if (ms->ram_slots) { 620 event |= ACPI_GED_MEM_HOTPLUG_EVT; 621 } 622 623 if (ms->nvdimms_state->is_enabled) { 624 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 625 } 626 627 dev = qdev_new(TYPE_ACPI_GED); 628 qdev_prop_set_uint32(dev, "ged-event", event); 629 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 630 631 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 632 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 633 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 634 635 return dev; 636 } 637 638 static void create_its(VirtMachineState *vms) 639 { 640 const char *itsclass = its_class_name(); 641 DeviceState *dev; 642 643 if (!strcmp(itsclass, "arm-gicv3-its")) { 644 if (!vms->tcg_its) { 645 itsclass = NULL; 646 } 647 } 648 649 if (!itsclass) { 650 /* Do nothing if not supported */ 651 return; 652 } 653 654 dev = qdev_new(itsclass); 655 656 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 657 &error_abort); 658 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 659 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 660 661 fdt_add_its_gic_node(vms); 662 vms->msi_controller = VIRT_MSI_CTRL_ITS; 663 } 664 665 static void create_v2m(VirtMachineState *vms) 666 { 667 int i; 668 int irq = vms->irqmap[VIRT_GIC_V2M]; 669 DeviceState *dev; 670 671 dev = qdev_new("arm-gicv2m"); 672 qdev_prop_set_uint32(dev, "base-spi", irq); 673 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 674 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 675 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 676 677 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 678 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 679 qdev_get_gpio_in(vms->gic, irq + i)); 680 } 681 682 fdt_add_v2m_gic_node(vms); 683 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 684 } 685 686 static void create_gic(VirtMachineState *vms, MemoryRegion *mem) 687 { 688 MachineState *ms = MACHINE(vms); 689 /* We create a standalone GIC */ 690 SysBusDevice *gicbusdev; 691 const char *gictype; 692 int i; 693 unsigned int smp_cpus = ms->smp.cpus; 694 uint32_t nb_redist_regions = 0; 695 int revision; 696 697 if (vms->gic_version == VIRT_GIC_VERSION_2) { 698 gictype = gic_class_name(); 699 } else { 700 gictype = gicv3_class_name(); 701 } 702 703 switch (vms->gic_version) { 704 case VIRT_GIC_VERSION_2: 705 revision = 2; 706 break; 707 case VIRT_GIC_VERSION_3: 708 revision = 3; 709 break; 710 case VIRT_GIC_VERSION_4: 711 revision = 4; 712 break; 713 default: 714 g_assert_not_reached(); 715 } 716 vms->gic = qdev_new(gictype); 717 qdev_prop_set_uint32(vms->gic, "revision", revision); 718 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 719 /* Note that the num-irq property counts both internal and external 720 * interrupts; there are always 32 of the former (mandated by GIC spec). 721 */ 722 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 723 if (!kvm_irqchip_in_kernel()) { 724 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 725 } 726 727 if (vms->gic_version != VIRT_GIC_VERSION_2) { 728 QList *redist_region_count; 729 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); 730 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 731 732 nb_redist_regions = virt_gicv3_redist_region_count(vms); 733 734 redist_region_count = qlist_new(); 735 qlist_append_int(redist_region_count, redist0_count); 736 if (nb_redist_regions == 2) { 737 uint32_t redist1_capacity = 738 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 739 740 qlist_append_int(redist_region_count, 741 MIN(smp_cpus - redist0_count, redist1_capacity)); 742 } 743 qdev_prop_set_array(vms->gic, "redist-region-count", 744 redist_region_count); 745 746 if (!kvm_irqchip_in_kernel()) { 747 if (vms->tcg_its) { 748 object_property_set_link(OBJECT(vms->gic), "sysmem", 749 OBJECT(mem), &error_fatal); 750 qdev_prop_set_bit(vms->gic, "has-lpi", true); 751 } 752 } 753 } else { 754 if (!kvm_irqchip_in_kernel()) { 755 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 756 vms->virt); 757 } 758 } 759 gicbusdev = SYS_BUS_DEVICE(vms->gic); 760 sysbus_realize_and_unref(gicbusdev, &error_fatal); 761 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 762 if (vms->gic_version != VIRT_GIC_VERSION_2) { 763 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 764 if (nb_redist_regions == 2) { 765 sysbus_mmio_map(gicbusdev, 2, 766 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 767 } 768 } else { 769 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 770 if (vms->virt) { 771 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 772 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 773 } 774 } 775 776 /* Wire the outputs from each CPU's generic timer and the GICv3 777 * maintenance interrupt signal to the appropriate GIC PPI inputs, 778 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 779 */ 780 for (i = 0; i < smp_cpus; i++) { 781 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 782 int intidbase = NUM_IRQS + i * GIC_INTERNAL; 783 /* Mapping from the output timer irq lines from the CPU to the 784 * GIC PPI inputs we use for the virt board. 785 */ 786 const int timer_irq[] = { 787 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 788 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 789 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 790 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 791 }; 792 793 for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 794 qdev_connect_gpio_out(cpudev, irq, 795 qdev_get_gpio_in(vms->gic, 796 intidbase + timer_irq[irq])); 797 } 798 799 if (vms->gic_version != VIRT_GIC_VERSION_2) { 800 qemu_irq irq = qdev_get_gpio_in(vms->gic, 801 intidbase + ARCH_GIC_MAINT_IRQ); 802 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 803 0, irq); 804 } else if (vms->virt) { 805 qemu_irq irq = qdev_get_gpio_in(vms->gic, 806 intidbase + ARCH_GIC_MAINT_IRQ); 807 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 808 } 809 810 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 811 qdev_get_gpio_in(vms->gic, intidbase 812 + VIRTUAL_PMU_IRQ)); 813 814 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 815 sysbus_connect_irq(gicbusdev, i + smp_cpus, 816 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 817 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 818 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 819 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 820 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 821 } 822 823 fdt_add_gic_node(vms); 824 825 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { 826 create_its(vms); 827 } else if (vms->gic_version == VIRT_GIC_VERSION_2) { 828 create_v2m(vms); 829 } 830 } 831 832 static void create_uart(const VirtMachineState *vms, int uart, 833 MemoryRegion *mem, Chardev *chr) 834 { 835 char *nodename; 836 hwaddr base = vms->memmap[uart].base; 837 hwaddr size = vms->memmap[uart].size; 838 int irq = vms->irqmap[uart]; 839 const char compat[] = "arm,pl011\0arm,primecell"; 840 const char clocknames[] = "uartclk\0apb_pclk"; 841 DeviceState *dev = qdev_new(TYPE_PL011); 842 SysBusDevice *s = SYS_BUS_DEVICE(dev); 843 MachineState *ms = MACHINE(vms); 844 845 qdev_prop_set_chr(dev, "chardev", chr); 846 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 847 memory_region_add_subregion(mem, base, 848 sysbus_mmio_get_region(s, 0)); 849 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 850 851 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 852 qemu_fdt_add_subnode(ms->fdt, nodename); 853 /* Note that we can't use setprop_string because of the embedded NUL */ 854 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 855 compat, sizeof(compat)); 856 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 857 2, base, 2, size); 858 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 859 GIC_FDT_IRQ_TYPE_SPI, irq, 860 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 861 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 862 vms->clock_phandle, vms->clock_phandle); 863 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 864 clocknames, sizeof(clocknames)); 865 866 if (uart == VIRT_UART) { 867 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 868 } else { 869 /* Mark as not usable by the normal world */ 870 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 871 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 872 873 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 874 nodename); 875 } 876 877 g_free(nodename); 878 } 879 880 static void create_rtc(const VirtMachineState *vms) 881 { 882 char *nodename; 883 hwaddr base = vms->memmap[VIRT_RTC].base; 884 hwaddr size = vms->memmap[VIRT_RTC].size; 885 int irq = vms->irqmap[VIRT_RTC]; 886 const char compat[] = "arm,pl031\0arm,primecell"; 887 MachineState *ms = MACHINE(vms); 888 889 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 890 891 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 892 qemu_fdt_add_subnode(ms->fdt, nodename); 893 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 894 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 895 2, base, 2, size); 896 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 897 GIC_FDT_IRQ_TYPE_SPI, irq, 898 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 899 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 900 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 901 g_free(nodename); 902 } 903 904 static DeviceState *gpio_key_dev; 905 static void virt_powerdown_req(Notifier *n, void *opaque) 906 { 907 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 908 909 if (s->acpi_dev) { 910 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 911 } else { 912 /* use gpio Pin 3 for power button event */ 913 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 914 } 915 } 916 917 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 918 uint32_t phandle) 919 { 920 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 921 qdev_get_gpio_in(pl061_dev, 3)); 922 923 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 924 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 925 926 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 927 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 928 "label", "GPIO Key Poweroff"); 929 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 930 KEY_POWER); 931 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 932 "gpios", phandle, 3, 0); 933 } 934 935 #define SECURE_GPIO_POWEROFF 0 936 #define SECURE_GPIO_RESET 1 937 938 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 939 uint32_t phandle) 940 { 941 DeviceState *gpio_pwr_dev; 942 943 /* gpio-pwr */ 944 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 945 946 /* connect secure pl061 to gpio-pwr */ 947 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 948 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 949 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 950 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 951 952 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 953 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 954 "gpio-poweroff"); 955 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 956 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 957 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 958 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 959 "okay"); 960 961 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 962 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 963 "gpio-restart"); 964 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 965 "gpios", phandle, SECURE_GPIO_RESET, 0); 966 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 967 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 968 "okay"); 969 } 970 971 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 972 MemoryRegion *mem) 973 { 974 char *nodename; 975 DeviceState *pl061_dev; 976 hwaddr base = vms->memmap[gpio].base; 977 hwaddr size = vms->memmap[gpio].size; 978 int irq = vms->irqmap[gpio]; 979 const char compat[] = "arm,pl061\0arm,primecell"; 980 SysBusDevice *s; 981 MachineState *ms = MACHINE(vms); 982 983 pl061_dev = qdev_new("pl061"); 984 /* Pull lines down to 0 if not driven by the PL061 */ 985 qdev_prop_set_uint32(pl061_dev, "pullups", 0); 986 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); 987 s = SYS_BUS_DEVICE(pl061_dev); 988 sysbus_realize_and_unref(s, &error_fatal); 989 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 990 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 991 992 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 993 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 994 qemu_fdt_add_subnode(ms->fdt, nodename); 995 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 996 2, base, 2, size); 997 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 998 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 999 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 1000 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1001 GIC_FDT_IRQ_TYPE_SPI, irq, 1002 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1003 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1004 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1005 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 1006 1007 if (gpio != VIRT_GPIO) { 1008 /* Mark as not usable by the normal world */ 1009 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1010 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1011 } 1012 g_free(nodename); 1013 1014 /* Child gpio devices */ 1015 if (gpio == VIRT_GPIO) { 1016 create_gpio_keys(ms->fdt, pl061_dev, phandle); 1017 } else { 1018 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 1019 } 1020 } 1021 1022 static void create_virtio_devices(const VirtMachineState *vms) 1023 { 1024 int i; 1025 hwaddr size = vms->memmap[VIRT_MMIO].size; 1026 MachineState *ms = MACHINE(vms); 1027 1028 /* We create the transports in forwards order. Since qbus_realize() 1029 * prepends (not appends) new child buses, the incrementing loop below will 1030 * create a list of virtio-mmio buses with decreasing base addresses. 1031 * 1032 * When a -device option is processed from the command line, 1033 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 1034 * order. The upshot is that -device options in increasing command line 1035 * order are mapped to virtio-mmio buses with decreasing base addresses. 1036 * 1037 * When this code was originally written, that arrangement ensured that the 1038 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 1039 * the first -device on the command line. (The end-to-end order is a 1040 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 1041 * guest kernel's name-to-address assignment strategy.) 1042 * 1043 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 1044 * the message, if not necessarily the code, of commit 70161ff336. 1045 * Therefore the loop now establishes the inverse of the original intent. 1046 * 1047 * Unfortunately, we can't counteract the kernel change by reversing the 1048 * loop; it would break existing command lines. 1049 * 1050 * In any case, the kernel makes no guarantee about the stability of 1051 * enumeration order of virtio devices (as demonstrated by it changing 1052 * between kernel versions). For reliable and stable identification 1053 * of disks users must use UUIDs or similar mechanisms. 1054 */ 1055 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 1056 int irq = vms->irqmap[VIRT_MMIO] + i; 1057 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1058 1059 sysbus_create_simple("virtio-mmio", base, 1060 qdev_get_gpio_in(vms->gic, irq)); 1061 } 1062 1063 /* We add dtb nodes in reverse order so that they appear in the finished 1064 * device tree lowest address first. 1065 * 1066 * Note that this mapping is independent of the loop above. The previous 1067 * loop influences virtio device to virtio transport assignment, whereas 1068 * this loop controls how virtio transports are laid out in the dtb. 1069 */ 1070 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 1071 char *nodename; 1072 int irq = vms->irqmap[VIRT_MMIO] + i; 1073 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1074 1075 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 1076 qemu_fdt_add_subnode(ms->fdt, nodename); 1077 qemu_fdt_setprop_string(ms->fdt, nodename, 1078 "compatible", "virtio,mmio"); 1079 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1080 2, base, 2, size); 1081 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1082 GIC_FDT_IRQ_TYPE_SPI, irq, 1083 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1084 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1085 g_free(nodename); 1086 } 1087 } 1088 1089 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1090 1091 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1092 const char *name, 1093 const char *alias_prop_name) 1094 { 1095 /* 1096 * Create a single flash device. We use the same parameters as 1097 * the flash devices on the Versatile Express board. 1098 */ 1099 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1100 1101 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1102 qdev_prop_set_uint8(dev, "width", 4); 1103 qdev_prop_set_uint8(dev, "device-width", 2); 1104 qdev_prop_set_bit(dev, "big-endian", false); 1105 qdev_prop_set_uint16(dev, "id0", 0x89); 1106 qdev_prop_set_uint16(dev, "id1", 0x18); 1107 qdev_prop_set_uint16(dev, "id2", 0x00); 1108 qdev_prop_set_uint16(dev, "id3", 0x00); 1109 qdev_prop_set_string(dev, "name", name); 1110 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1111 object_property_add_alias(OBJECT(vms), alias_prop_name, 1112 OBJECT(dev), "drive"); 1113 return PFLASH_CFI01(dev); 1114 } 1115 1116 static void virt_flash_create(VirtMachineState *vms) 1117 { 1118 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1119 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1120 } 1121 1122 static void virt_flash_map1(PFlashCFI01 *flash, 1123 hwaddr base, hwaddr size, 1124 MemoryRegion *sysmem) 1125 { 1126 DeviceState *dev = DEVICE(flash); 1127 1128 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1129 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1130 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1131 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1132 1133 memory_region_add_subregion(sysmem, base, 1134 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1135 0)); 1136 } 1137 1138 static void virt_flash_map(VirtMachineState *vms, 1139 MemoryRegion *sysmem, 1140 MemoryRegion *secure_sysmem) 1141 { 1142 /* 1143 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1144 * sysmem is the system memory space. secure_sysmem is the secure view 1145 * of the system, and the first flash device should be made visible only 1146 * there. The second flash device is visible to both secure and nonsecure. 1147 * If sysmem == secure_sysmem this means there is no separate Secure 1148 * address space and both flash devices are generally visible. 1149 */ 1150 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1151 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1152 1153 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1154 secure_sysmem); 1155 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1156 sysmem); 1157 } 1158 1159 static void virt_flash_fdt(VirtMachineState *vms, 1160 MemoryRegion *sysmem, 1161 MemoryRegion *secure_sysmem) 1162 { 1163 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1164 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1165 MachineState *ms = MACHINE(vms); 1166 char *nodename; 1167 1168 if (sysmem == secure_sysmem) { 1169 /* Report both flash devices as a single node in the DT */ 1170 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1171 qemu_fdt_add_subnode(ms->fdt, nodename); 1172 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1173 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1174 2, flashbase, 2, flashsize, 1175 2, flashbase + flashsize, 2, flashsize); 1176 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1177 g_free(nodename); 1178 } else { 1179 /* 1180 * Report the devices as separate nodes so we can mark one as 1181 * only visible to the secure world. 1182 */ 1183 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1184 qemu_fdt_add_subnode(ms->fdt, nodename); 1185 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1186 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1187 2, flashbase, 2, flashsize); 1188 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1189 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1190 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1191 g_free(nodename); 1192 1193 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize); 1194 qemu_fdt_add_subnode(ms->fdt, nodename); 1195 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1196 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1197 2, flashbase + flashsize, 2, flashsize); 1198 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1199 g_free(nodename); 1200 } 1201 } 1202 1203 static bool virt_firmware_init(VirtMachineState *vms, 1204 MemoryRegion *sysmem, 1205 MemoryRegion *secure_sysmem) 1206 { 1207 int i; 1208 const char *bios_name; 1209 BlockBackend *pflash_blk0; 1210 1211 /* Map legacy -drive if=pflash to machine properties */ 1212 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1213 pflash_cfi01_legacy_drive(vms->flash[i], 1214 drive_get(IF_PFLASH, 0, i)); 1215 } 1216 1217 virt_flash_map(vms, sysmem, secure_sysmem); 1218 1219 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1220 1221 bios_name = MACHINE(vms)->firmware; 1222 if (bios_name) { 1223 char *fname; 1224 MemoryRegion *mr; 1225 int image_size; 1226 1227 if (pflash_blk0) { 1228 error_report("The contents of the first flash device may be " 1229 "specified with -bios or with -drive if=pflash... " 1230 "but you cannot use both options at once"); 1231 exit(1); 1232 } 1233 1234 /* Fall back to -bios */ 1235 1236 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1237 if (!fname) { 1238 error_report("Could not find ROM image '%s'", bios_name); 1239 exit(1); 1240 } 1241 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1242 image_size = load_image_mr(fname, mr); 1243 g_free(fname); 1244 if (image_size < 0) { 1245 error_report("Could not load ROM image '%s'", bios_name); 1246 exit(1); 1247 } 1248 } 1249 1250 return pflash_blk0 || bios_name; 1251 } 1252 1253 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1254 { 1255 MachineState *ms = MACHINE(vms); 1256 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1257 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1258 FWCfgState *fw_cfg; 1259 char *nodename; 1260 1261 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1262 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1263 1264 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1265 qemu_fdt_add_subnode(ms->fdt, nodename); 1266 qemu_fdt_setprop_string(ms->fdt, nodename, 1267 "compatible", "qemu,fw-cfg-mmio"); 1268 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1269 2, base, 2, size); 1270 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1271 g_free(nodename); 1272 return fw_cfg; 1273 } 1274 1275 static void create_pcie_irq_map(const MachineState *ms, 1276 uint32_t gic_phandle, 1277 int first_irq, const char *nodename) 1278 { 1279 int devfn, pin; 1280 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1281 uint32_t *irq_map = full_irq_map; 1282 1283 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1284 for (pin = 0; pin < 4; pin++) { 1285 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1286 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1287 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1288 int i; 1289 1290 uint32_t map[] = { 1291 devfn << 8, 0, 0, /* devfn */ 1292 pin + 1, /* PCI pin */ 1293 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1294 1295 /* Convert map to big endian */ 1296 for (i = 0; i < 10; i++) { 1297 irq_map[i] = cpu_to_be32(map[i]); 1298 } 1299 irq_map += 10; 1300 } 1301 } 1302 1303 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1304 full_irq_map, sizeof(full_irq_map)); 1305 1306 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1307 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1308 0, 0, 1309 0x7 /* PCI irq */); 1310 } 1311 1312 static void create_smmu(const VirtMachineState *vms, 1313 PCIBus *bus) 1314 { 1315 char *node; 1316 const char compat[] = "arm,smmu-v3"; 1317 int irq = vms->irqmap[VIRT_SMMU]; 1318 int i; 1319 hwaddr base = vms->memmap[VIRT_SMMU].base; 1320 hwaddr size = vms->memmap[VIRT_SMMU].size; 1321 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1322 DeviceState *dev; 1323 MachineState *ms = MACHINE(vms); 1324 1325 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1326 return; 1327 } 1328 1329 dev = qdev_new(TYPE_ARM_SMMUV3); 1330 1331 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1332 &error_abort); 1333 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1334 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1335 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1336 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1337 qdev_get_gpio_in(vms->gic, irq + i)); 1338 } 1339 1340 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1341 qemu_fdt_add_subnode(ms->fdt, node); 1342 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1343 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1344 1345 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1346 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1347 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1348 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1349 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1350 1351 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1352 sizeof(irq_names)); 1353 1354 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1355 1356 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1357 1358 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1359 g_free(node); 1360 } 1361 1362 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1363 { 1364 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1365 uint16_t bdf = vms->virtio_iommu_bdf; 1366 MachineState *ms = MACHINE(vms); 1367 char *node; 1368 1369 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1370 1371 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename, 1372 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1373 qemu_fdt_add_subnode(ms->fdt, node); 1374 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1375 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1376 1, bdf << 8, 1, 0, 1, 0, 1377 1, 0, 1, 0); 1378 1379 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1380 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1381 g_free(node); 1382 1383 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1384 0x0, vms->iommu_phandle, 0x0, bdf, 1385 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1386 } 1387 1388 static void create_pcie(VirtMachineState *vms) 1389 { 1390 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1391 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1392 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1393 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1394 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1395 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1396 hwaddr base_ecam, size_ecam; 1397 hwaddr base = base_mmio; 1398 int nr_pcie_buses; 1399 int irq = vms->irqmap[VIRT_PCIE]; 1400 MemoryRegion *mmio_alias; 1401 MemoryRegion *mmio_reg; 1402 MemoryRegion *ecam_alias; 1403 MemoryRegion *ecam_reg; 1404 DeviceState *dev; 1405 char *nodename; 1406 int i, ecam_id; 1407 PCIHostState *pci; 1408 MachineState *ms = MACHINE(vms); 1409 MachineClass *mc = MACHINE_GET_CLASS(ms); 1410 1411 dev = qdev_new(TYPE_GPEX_HOST); 1412 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1413 1414 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1415 base_ecam = vms->memmap[ecam_id].base; 1416 size_ecam = vms->memmap[ecam_id].size; 1417 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1418 /* Map only the first size_ecam bytes of ECAM space */ 1419 ecam_alias = g_new0(MemoryRegion, 1); 1420 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1421 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1422 ecam_reg, 0, size_ecam); 1423 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1424 1425 /* Map the MMIO window into system address space so as to expose 1426 * the section of PCI MMIO space which starts at the same base address 1427 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1428 * the window). 1429 */ 1430 mmio_alias = g_new0(MemoryRegion, 1); 1431 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1432 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1433 mmio_reg, base_mmio, size_mmio); 1434 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1435 1436 if (vms->highmem_mmio) { 1437 /* Map high MMIO space */ 1438 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1439 1440 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1441 mmio_reg, base_mmio_high, size_mmio_high); 1442 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1443 high_mmio_alias); 1444 } 1445 1446 /* Map IO port space */ 1447 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1448 1449 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1450 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1451 qdev_get_gpio_in(vms->gic, irq + i)); 1452 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1453 } 1454 1455 pci = PCI_HOST_BRIDGE(dev); 1456 pci->bypass_iommu = vms->default_bus_bypass_iommu; 1457 vms->bus = pci->bus; 1458 if (vms->bus) { 1459 for (i = 0; i < nb_nics; i++) { 1460 pci_nic_init_nofail(&nd_table[i], pci->bus, mc->default_nic, NULL); 1461 } 1462 } 1463 1464 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1465 qemu_fdt_add_subnode(ms->fdt, nodename); 1466 qemu_fdt_setprop_string(ms->fdt, nodename, 1467 "compatible", "pci-host-ecam-generic"); 1468 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1469 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1470 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1471 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1472 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1473 nr_pcie_buses - 1); 1474 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1475 1476 if (vms->msi_phandle) { 1477 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 1478 0, vms->msi_phandle, 0, 0x10000); 1479 } 1480 1481 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1482 2, base_ecam, 2, size_ecam); 1483 1484 if (vms->highmem_mmio) { 1485 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1486 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1487 2, base_pio, 2, size_pio, 1488 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1489 2, base_mmio, 2, size_mmio, 1490 1, FDT_PCI_RANGE_MMIO_64BIT, 1491 2, base_mmio_high, 1492 2, base_mmio_high, 2, size_mmio_high); 1493 } else { 1494 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1495 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1496 2, base_pio, 2, size_pio, 1497 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1498 2, base_mmio, 2, size_mmio); 1499 } 1500 1501 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1502 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1503 1504 if (vms->iommu) { 1505 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1506 1507 switch (vms->iommu) { 1508 case VIRT_IOMMU_SMMUV3: 1509 create_smmu(vms, vms->bus); 1510 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1511 0x0, vms->iommu_phandle, 0x0, 0x10000); 1512 break; 1513 default: 1514 g_assert_not_reached(); 1515 } 1516 } 1517 } 1518 1519 static void create_platform_bus(VirtMachineState *vms) 1520 { 1521 DeviceState *dev; 1522 SysBusDevice *s; 1523 int i; 1524 MemoryRegion *sysmem = get_system_memory(); 1525 1526 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1527 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1528 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1529 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1530 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1531 vms->platform_bus_dev = dev; 1532 1533 s = SYS_BUS_DEVICE(dev); 1534 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1535 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1536 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1537 } 1538 1539 memory_region_add_subregion(sysmem, 1540 vms->memmap[VIRT_PLATFORM_BUS].base, 1541 sysbus_mmio_get_region(s, 0)); 1542 } 1543 1544 static void create_tag_ram(MemoryRegion *tag_sysmem, 1545 hwaddr base, hwaddr size, 1546 const char *name) 1547 { 1548 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1549 1550 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1551 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1552 } 1553 1554 static void create_secure_ram(VirtMachineState *vms, 1555 MemoryRegion *secure_sysmem, 1556 MemoryRegion *secure_tag_sysmem) 1557 { 1558 MemoryRegion *secram = g_new(MemoryRegion, 1); 1559 char *nodename; 1560 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1561 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1562 MachineState *ms = MACHINE(vms); 1563 1564 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1565 &error_fatal); 1566 memory_region_add_subregion(secure_sysmem, base, secram); 1567 1568 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1569 qemu_fdt_add_subnode(ms->fdt, nodename); 1570 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1571 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1572 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1573 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1574 1575 if (secure_tag_sysmem) { 1576 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1577 } 1578 1579 g_free(nodename); 1580 } 1581 1582 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1583 { 1584 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1585 bootinfo); 1586 MachineState *ms = MACHINE(board); 1587 1588 1589 *fdt_size = board->fdt_size; 1590 return ms->fdt; 1591 } 1592 1593 static void virt_build_smbios(VirtMachineState *vms) 1594 { 1595 MachineClass *mc = MACHINE_GET_CLASS(vms); 1596 MachineState *ms = MACHINE(vms); 1597 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1598 uint8_t *smbios_tables, *smbios_anchor; 1599 size_t smbios_tables_len, smbios_anchor_len; 1600 struct smbios_phys_mem_area mem_array; 1601 const char *product = "QEMU Virtual Machine"; 1602 1603 if (kvm_enabled()) { 1604 product = "KVM Virtual Machine"; 1605 } 1606 1607 smbios_set_defaults("QEMU", product, 1608 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1609 true, SMBIOS_ENTRY_POINT_TYPE_64); 1610 1611 /* build the array of physical mem area from base_memmap */ 1612 mem_array.address = vms->memmap[VIRT_MEM].base; 1613 mem_array.length = ms->ram_size; 1614 1615 smbios_get_tables(ms, &mem_array, 1, 1616 &smbios_tables, &smbios_tables_len, 1617 &smbios_anchor, &smbios_anchor_len, 1618 &error_fatal); 1619 1620 if (smbios_anchor) { 1621 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1622 smbios_tables, smbios_tables_len); 1623 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1624 smbios_anchor, smbios_anchor_len); 1625 } 1626 } 1627 1628 static 1629 void virt_machine_done(Notifier *notifier, void *data) 1630 { 1631 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1632 machine_done); 1633 MachineState *ms = MACHINE(vms); 1634 ARMCPU *cpu = ARM_CPU(first_cpu); 1635 struct arm_boot_info *info = &vms->bootinfo; 1636 AddressSpace *as = arm_boot_address_space(cpu, info); 1637 1638 /* 1639 * If the user provided a dtb, we assume the dynamic sysbus nodes 1640 * already are integrated there. This corresponds to a use case where 1641 * the dynamic sysbus nodes are complex and their generation is not yet 1642 * supported. In that case the user can take charge of the guest dt 1643 * while qemu takes charge of the qom stuff. 1644 */ 1645 if (info->dtb_filename == NULL) { 1646 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1647 vms->memmap[VIRT_PLATFORM_BUS].base, 1648 vms->memmap[VIRT_PLATFORM_BUS].size, 1649 vms->irqmap[VIRT_PLATFORM_BUS]); 1650 } 1651 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1652 exit(1); 1653 } 1654 1655 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg); 1656 1657 virt_acpi_setup(vms); 1658 virt_build_smbios(vms); 1659 } 1660 1661 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1662 { 1663 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1664 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1665 1666 if (!vmc->disallow_affinity_adjustment) { 1667 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1668 * GIC's target-list limitations. 32-bit KVM hosts currently 1669 * always create clusters of 4 CPUs, but that is expected to 1670 * change when they gain support for gicv3. When KVM is enabled 1671 * it will override the changes we make here, therefore our 1672 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1673 * and to improve SGI efficiency. 1674 */ 1675 if (vms->gic_version == VIRT_GIC_VERSION_2) { 1676 clustersz = GIC_TARGETLIST_BITS; 1677 } else { 1678 clustersz = GICV3_TARGETLIST_BITS; 1679 } 1680 } 1681 return arm_build_mp_affinity(idx, clustersz); 1682 } 1683 1684 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, 1685 int index) 1686 { 1687 bool *enabled_array[] = { 1688 &vms->highmem_redists, 1689 &vms->highmem_ecam, 1690 &vms->highmem_mmio, 1691 }; 1692 1693 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST == 1694 ARRAY_SIZE(enabled_array)); 1695 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array)); 1696 1697 return enabled_array[index - VIRT_LOWMEMMAP_LAST]; 1698 } 1699 1700 static void virt_set_high_memmap(VirtMachineState *vms, 1701 hwaddr base, int pa_bits) 1702 { 1703 hwaddr region_base, region_size; 1704 bool *region_enabled, fits; 1705 int i; 1706 1707 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1708 region_enabled = virt_get_high_memmap_enabled(vms, i); 1709 region_base = ROUND_UP(base, extended_memmap[i].size); 1710 region_size = extended_memmap[i].size; 1711 1712 vms->memmap[i].base = region_base; 1713 vms->memmap[i].size = region_size; 1714 1715 /* 1716 * Check each device to see if it fits in the PA space, 1717 * moving highest_gpa as we go. For compatibility, move 1718 * highest_gpa for disabled fitting devices as well, if 1719 * the compact layout has been disabled. 1720 * 1721 * For each device that doesn't fit, disable it. 1722 */ 1723 fits = (region_base + region_size) <= BIT_ULL(pa_bits); 1724 *region_enabled &= fits; 1725 if (vms->highmem_compact && !*region_enabled) { 1726 continue; 1727 } 1728 1729 base = region_base + region_size; 1730 if (fits) { 1731 vms->highest_gpa = base - 1; 1732 } 1733 } 1734 } 1735 1736 static void virt_set_memmap(VirtMachineState *vms, int pa_bits) 1737 { 1738 MachineState *ms = MACHINE(vms); 1739 hwaddr base, device_memory_base, device_memory_size, memtop; 1740 int i; 1741 1742 vms->memmap = extended_memmap; 1743 1744 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1745 vms->memmap[i] = base_memmap[i]; 1746 } 1747 1748 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1749 error_report("unsupported number of memory slots: %"PRIu64, 1750 ms->ram_slots); 1751 exit(EXIT_FAILURE); 1752 } 1753 1754 /* 1755 * !highmem is exactly the same as limiting the PA space to 32bit, 1756 * irrespective of the underlying capabilities of the HW. 1757 */ 1758 if (!vms->highmem) { 1759 pa_bits = 32; 1760 } 1761 1762 /* 1763 * We compute the base of the high IO region depending on the 1764 * amount of initial and device memory. The device memory start/size 1765 * is aligned on 1GiB. We never put the high IO region below 256GiB 1766 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1767 * The device region size assumes 1GiB page max alignment per slot. 1768 */ 1769 device_memory_base = 1770 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1771 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1772 1773 /* Base address of the high IO region */ 1774 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1775 if (memtop > BIT_ULL(pa_bits)) { 1776 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes", 1777 pa_bits, memtop - BIT_ULL(pa_bits)); 1778 exit(EXIT_FAILURE); 1779 } 1780 if (base < device_memory_base) { 1781 error_report("maxmem/slots too huge"); 1782 exit(EXIT_FAILURE); 1783 } 1784 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1785 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1786 } 1787 1788 /* We know for sure that at least the memory fits in the PA space */ 1789 vms->highest_gpa = memtop - 1; 1790 1791 virt_set_high_memmap(vms, base, pa_bits); 1792 1793 if (device_memory_size > 0) { 1794 machine_memory_devices_init(ms, device_memory_base, device_memory_size); 1795 } 1796 } 1797 1798 static VirtGICType finalize_gic_version_do(const char *accel_name, 1799 VirtGICType gic_version, 1800 int gics_supported, 1801 unsigned int max_cpus) 1802 { 1803 /* Convert host/max/nosel to GIC version number */ 1804 switch (gic_version) { 1805 case VIRT_GIC_VERSION_HOST: 1806 if (!kvm_enabled()) { 1807 error_report("gic-version=host requires KVM"); 1808 exit(1); 1809 } 1810 1811 /* For KVM, gic-version=host means gic-version=max */ 1812 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX, 1813 gics_supported, max_cpus); 1814 case VIRT_GIC_VERSION_MAX: 1815 if (gics_supported & VIRT_GIC_VERSION_4_MASK) { 1816 gic_version = VIRT_GIC_VERSION_4; 1817 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1818 gic_version = VIRT_GIC_VERSION_3; 1819 } else { 1820 gic_version = VIRT_GIC_VERSION_2; 1821 } 1822 break; 1823 case VIRT_GIC_VERSION_NOSEL: 1824 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) && 1825 max_cpus <= GIC_NCPU) { 1826 gic_version = VIRT_GIC_VERSION_2; 1827 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1828 /* 1829 * in case the host does not support v2 emulation or 1830 * the end-user requested more than 8 VCPUs we now default 1831 * to v3. In any case defaulting to v2 would be broken. 1832 */ 1833 gic_version = VIRT_GIC_VERSION_3; 1834 } else if (max_cpus > GIC_NCPU) { 1835 error_report("%s only supports GICv2 emulation but more than 8 " 1836 "vcpus are requested", accel_name); 1837 exit(1); 1838 } 1839 break; 1840 case VIRT_GIC_VERSION_2: 1841 case VIRT_GIC_VERSION_3: 1842 case VIRT_GIC_VERSION_4: 1843 break; 1844 } 1845 1846 /* Check chosen version is effectively supported */ 1847 switch (gic_version) { 1848 case VIRT_GIC_VERSION_2: 1849 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) { 1850 error_report("%s does not support GICv2 emulation", accel_name); 1851 exit(1); 1852 } 1853 break; 1854 case VIRT_GIC_VERSION_3: 1855 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) { 1856 error_report("%s does not support GICv3 emulation", accel_name); 1857 exit(1); 1858 } 1859 break; 1860 case VIRT_GIC_VERSION_4: 1861 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) { 1862 error_report("%s does not support GICv4 emulation, is virtualization=on?", 1863 accel_name); 1864 exit(1); 1865 } 1866 break; 1867 default: 1868 error_report("logic error in finalize_gic_version"); 1869 exit(1); 1870 break; 1871 } 1872 1873 return gic_version; 1874 } 1875 1876 /* 1877 * finalize_gic_version - Determines the final gic_version 1878 * according to the gic-version property 1879 * 1880 * Default GIC type is v2 1881 */ 1882 static void finalize_gic_version(VirtMachineState *vms) 1883 { 1884 const char *accel_name = current_accel_name(); 1885 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1886 int gics_supported = 0; 1887 1888 /* Determine which GIC versions the current environment supports */ 1889 if (kvm_enabled() && kvm_irqchip_in_kernel()) { 1890 int probe_bitmap = kvm_arm_vgic_probe(); 1891 1892 if (!probe_bitmap) { 1893 error_report("Unable to determine GIC version supported by host"); 1894 exit(1); 1895 } 1896 1897 if (probe_bitmap & KVM_ARM_VGIC_V2) { 1898 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1899 } 1900 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1901 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1902 } 1903 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) { 1904 /* KVM w/o kernel irqchip can only deal with GICv2 */ 1905 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1906 accel_name = "KVM with kernel-irqchip=off"; 1907 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { 1908 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1909 if (module_object_class_by_name("arm-gicv3")) { 1910 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1911 if (vms->virt) { 1912 /* GICv4 only makes sense if CPU has EL2 */ 1913 gics_supported |= VIRT_GIC_VERSION_4_MASK; 1914 } 1915 } 1916 } else { 1917 error_report("Unsupported accelerator, can not determine GIC support"); 1918 exit(1); 1919 } 1920 1921 /* 1922 * Then convert helpers like host/max to concrete GIC versions and ensure 1923 * the desired version is supported 1924 */ 1925 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version, 1926 gics_supported, max_cpus); 1927 } 1928 1929 /* 1930 * virt_cpu_post_init() must be called after the CPUs have 1931 * been realized and the GIC has been created. 1932 */ 1933 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) 1934 { 1935 int max_cpus = MACHINE(vms)->smp.max_cpus; 1936 bool aarch64, pmu, steal_time; 1937 CPUState *cpu; 1938 1939 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 1940 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 1941 steal_time = object_property_get_bool(OBJECT(first_cpu), 1942 "kvm-steal-time", NULL); 1943 1944 if (kvm_enabled()) { 1945 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 1946 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 1947 1948 if (steal_time) { 1949 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 1950 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 1951 1952 /* The memory region size must be a multiple of host page size. */ 1953 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 1954 1955 if (pvtime_size > pvtime_reg_size) { 1956 error_report("pvtime requires a %" HWADDR_PRId 1957 " byte memory region for %d CPUs," 1958 " but only %" HWADDR_PRId " has been reserved", 1959 pvtime_size, max_cpus, pvtime_reg_size); 1960 exit(1); 1961 } 1962 1963 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 1964 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 1965 } 1966 1967 CPU_FOREACH(cpu) { 1968 if (pmu) { 1969 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 1970 if (kvm_irqchip_in_kernel()) { 1971 kvm_arm_pmu_set_irq(ARM_CPU(cpu), VIRTUAL_PMU_IRQ); 1972 } 1973 kvm_arm_pmu_init(ARM_CPU(cpu)); 1974 } 1975 if (steal_time) { 1976 kvm_arm_pvtime_init(ARM_CPU(cpu), pvtime_reg_base 1977 + cpu->cpu_index 1978 * PVTIME_SIZE_PER_CPU); 1979 } 1980 } 1981 } else { 1982 if (aarch64 && vms->highmem) { 1983 int requested_pa_size = 64 - clz64(vms->highest_gpa); 1984 int pamax = arm_pamax(ARM_CPU(first_cpu)); 1985 1986 if (pamax < requested_pa_size) { 1987 error_report("VCPU supports less PA bits (%d) than " 1988 "requested by the memory map (%d)", 1989 pamax, requested_pa_size); 1990 exit(1); 1991 } 1992 } 1993 } 1994 } 1995 1996 static void machvirt_init(MachineState *machine) 1997 { 1998 VirtMachineState *vms = VIRT_MACHINE(machine); 1999 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 2000 MachineClass *mc = MACHINE_GET_CLASS(machine); 2001 const CPUArchIdList *possible_cpus; 2002 MemoryRegion *sysmem = get_system_memory(); 2003 MemoryRegion *secure_sysmem = NULL; 2004 MemoryRegion *tag_sysmem = NULL; 2005 MemoryRegion *secure_tag_sysmem = NULL; 2006 int n, virt_max_cpus; 2007 bool firmware_loaded; 2008 bool aarch64 = true; 2009 bool has_ged = !vmc->no_ged; 2010 unsigned int smp_cpus = machine->smp.cpus; 2011 unsigned int max_cpus = machine->smp.max_cpus; 2012 2013 possible_cpus = mc->possible_cpu_arch_ids(machine); 2014 2015 /* 2016 * In accelerated mode, the memory map is computed earlier in kvm_type() 2017 * to create a VM with the right number of IPA bits. 2018 */ 2019 if (!vms->memmap) { 2020 Object *cpuobj; 2021 ARMCPU *armcpu; 2022 int pa_bits; 2023 2024 /* 2025 * Instantiate a temporary CPU object to find out about what 2026 * we are about to deal with. Once this is done, get rid of 2027 * the object. 2028 */ 2029 cpuobj = object_new(possible_cpus->cpus[0].type); 2030 armcpu = ARM_CPU(cpuobj); 2031 2032 pa_bits = arm_pamax(armcpu); 2033 2034 object_unref(cpuobj); 2035 2036 virt_set_memmap(vms, pa_bits); 2037 } 2038 2039 /* We can probe only here because during property set 2040 * KVM is not available yet 2041 */ 2042 finalize_gic_version(vms); 2043 2044 if (vms->secure) { 2045 /* 2046 * The Secure view of the world is the same as the NonSecure, 2047 * but with a few extra devices. Create it as a container region 2048 * containing the system memory at low priority; any secure-only 2049 * devices go in at higher priority and take precedence. 2050 */ 2051 secure_sysmem = g_new(MemoryRegion, 1); 2052 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 2053 UINT64_MAX); 2054 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 2055 } 2056 2057 firmware_loaded = virt_firmware_init(vms, sysmem, 2058 secure_sysmem ?: sysmem); 2059 2060 /* If we have an EL3 boot ROM then the assumption is that it will 2061 * implement PSCI itself, so disable QEMU's internal implementation 2062 * so it doesn't get in the way. Instead of starting secondary 2063 * CPUs in PSCI powerdown state we will start them all running and 2064 * let the boot ROM sort them out. 2065 * The usual case is that we do use QEMU's PSCI implementation; 2066 * if the guest has EL2 then we will use SMC as the conduit, 2067 * and otherwise we will use HVC (for backwards compatibility and 2068 * because if we're using KVM then we must use HVC). 2069 */ 2070 if (vms->secure && firmware_loaded) { 2071 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 2072 } else if (vms->virt) { 2073 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 2074 } else { 2075 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 2076 } 2077 2078 /* 2079 * The maximum number of CPUs depends on the GIC version, or on how 2080 * many redistributors we can fit into the memory map (which in turn 2081 * depends on whether this is a GICv3 or v4). 2082 */ 2083 if (vms->gic_version == VIRT_GIC_VERSION_2) { 2084 virt_max_cpus = GIC_NCPU; 2085 } else { 2086 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST); 2087 if (vms->highmem_redists) { 2088 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 2089 } 2090 } 2091 2092 if (max_cpus > virt_max_cpus) { 2093 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 2094 "supported by machine 'mach-virt' (%d)", 2095 max_cpus, virt_max_cpus); 2096 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) { 2097 error_printf("Try 'highmem-redists=on' for more CPUs\n"); 2098 } 2099 2100 exit(1); 2101 } 2102 2103 if (vms->secure && (kvm_enabled() || hvf_enabled())) { 2104 error_report("mach-virt: %s does not support providing " 2105 "Security extensions (TrustZone) to the guest CPU", 2106 current_accel_name()); 2107 exit(1); 2108 } 2109 2110 if (vms->virt && (kvm_enabled() || hvf_enabled())) { 2111 error_report("mach-virt: %s does not support providing " 2112 "Virtualization extensions to the guest CPU", 2113 current_accel_name()); 2114 exit(1); 2115 } 2116 2117 if (vms->mte && (kvm_enabled() || hvf_enabled())) { 2118 error_report("mach-virt: %s does not support providing " 2119 "MTE to the guest CPU", 2120 current_accel_name()); 2121 exit(1); 2122 } 2123 2124 create_fdt(vms); 2125 2126 assert(possible_cpus->len == max_cpus); 2127 for (n = 0; n < possible_cpus->len; n++) { 2128 Object *cpuobj; 2129 CPUState *cs; 2130 2131 if (n >= smp_cpus) { 2132 break; 2133 } 2134 2135 cpuobj = object_new(possible_cpus->cpus[n].type); 2136 object_property_set_int(cpuobj, "mp-affinity", 2137 possible_cpus->cpus[n].arch_id, NULL); 2138 2139 cs = CPU(cpuobj); 2140 cs->cpu_index = n; 2141 2142 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 2143 &error_fatal); 2144 2145 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 2146 2147 if (!vms->secure) { 2148 object_property_set_bool(cpuobj, "has_el3", false, NULL); 2149 } 2150 2151 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 2152 object_property_set_bool(cpuobj, "has_el2", false, NULL); 2153 } 2154 2155 if (vmc->kvm_no_adjvtime && 2156 object_property_find(cpuobj, "kvm-no-adjvtime")) { 2157 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 2158 } 2159 2160 if (vmc->no_kvm_steal_time && 2161 object_property_find(cpuobj, "kvm-steal-time")) { 2162 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 2163 } 2164 2165 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { 2166 object_property_set_bool(cpuobj, "pmu", false, NULL); 2167 } 2168 2169 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { 2170 object_property_set_bool(cpuobj, "lpa2", false, NULL); 2171 } 2172 2173 if (object_property_find(cpuobj, "reset-cbar")) { 2174 object_property_set_int(cpuobj, "reset-cbar", 2175 vms->memmap[VIRT_CPUPERIPHS].base, 2176 &error_abort); 2177 } 2178 2179 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 2180 &error_abort); 2181 if (vms->secure) { 2182 object_property_set_link(cpuobj, "secure-memory", 2183 OBJECT(secure_sysmem), &error_abort); 2184 } 2185 2186 if (vms->mte) { 2187 /* Create the memory region only once, but link to all cpus. */ 2188 if (!tag_sysmem) { 2189 /* 2190 * The property exists only if MemTag is supported. 2191 * If it is, we must allocate the ram to back that up. 2192 */ 2193 if (!object_property_find(cpuobj, "tag-memory")) { 2194 error_report("MTE requested, but not supported " 2195 "by the guest CPU"); 2196 exit(1); 2197 } 2198 2199 tag_sysmem = g_new(MemoryRegion, 1); 2200 memory_region_init(tag_sysmem, OBJECT(machine), 2201 "tag-memory", UINT64_MAX / 32); 2202 2203 if (vms->secure) { 2204 secure_tag_sysmem = g_new(MemoryRegion, 1); 2205 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2206 "secure-tag-memory", UINT64_MAX / 32); 2207 2208 /* As with ram, secure-tag takes precedence over tag. */ 2209 memory_region_add_subregion_overlap(secure_tag_sysmem, 0, 2210 tag_sysmem, -1); 2211 } 2212 } 2213 2214 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), 2215 &error_abort); 2216 if (vms->secure) { 2217 object_property_set_link(cpuobj, "secure-tag-memory", 2218 OBJECT(secure_tag_sysmem), 2219 &error_abort); 2220 } 2221 } 2222 2223 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2224 object_unref(cpuobj); 2225 } 2226 fdt_add_timer_nodes(vms); 2227 fdt_add_cpu_nodes(vms); 2228 2229 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2230 machine->ram); 2231 2232 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2233 2234 create_gic(vms, sysmem); 2235 2236 virt_cpu_post_init(vms, sysmem); 2237 2238 fdt_add_pmu_nodes(vms); 2239 2240 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 2241 2242 if (vms->secure) { 2243 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2244 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 2245 } 2246 2247 if (tag_sysmem) { 2248 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2249 machine->ram_size, "mach-virt.tag"); 2250 } 2251 2252 vms->highmem_ecam &= (!firmware_loaded || aarch64); 2253 2254 create_rtc(vms); 2255 2256 create_pcie(vms); 2257 2258 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2259 vms->acpi_dev = create_acpi_ged(vms); 2260 } else { 2261 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2262 } 2263 2264 if (vms->secure && !vmc->no_secure_gpio) { 2265 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2266 } 2267 2268 /* connect powerdown request */ 2269 vms->powerdown_notifier.notify = virt_powerdown_req; 2270 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2271 2272 /* Create mmio transports, so the user can create virtio backends 2273 * (which will be automatically plugged in to the transports). If 2274 * no backend is created the transport will just sit harmlessly idle. 2275 */ 2276 create_virtio_devices(vms); 2277 2278 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2279 rom_set_fw(vms->fw_cfg); 2280 2281 create_platform_bus(vms); 2282 2283 if (machine->nvdimms_state->is_enabled) { 2284 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2285 .space_id = AML_AS_SYSTEM_MEMORY, 2286 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2287 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2288 }; 2289 2290 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2291 arm_virt_nvdimm_acpi_dsmio, 2292 vms->fw_cfg, OBJECT(vms)); 2293 } 2294 2295 vms->bootinfo.ram_size = machine->ram_size; 2296 vms->bootinfo.board_id = -1; 2297 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2298 vms->bootinfo.get_dtb = machvirt_dtb; 2299 vms->bootinfo.skip_dtb_autoload = true; 2300 vms->bootinfo.firmware_loaded = firmware_loaded; 2301 vms->bootinfo.psci_conduit = vms->psci_conduit; 2302 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2303 2304 vms->machine_done.notify = virt_machine_done; 2305 qemu_add_machine_init_done_notifier(&vms->machine_done); 2306 } 2307 2308 static bool virt_get_secure(Object *obj, Error **errp) 2309 { 2310 VirtMachineState *vms = VIRT_MACHINE(obj); 2311 2312 return vms->secure; 2313 } 2314 2315 static void virt_set_secure(Object *obj, bool value, Error **errp) 2316 { 2317 VirtMachineState *vms = VIRT_MACHINE(obj); 2318 2319 vms->secure = value; 2320 } 2321 2322 static bool virt_get_virt(Object *obj, Error **errp) 2323 { 2324 VirtMachineState *vms = VIRT_MACHINE(obj); 2325 2326 return vms->virt; 2327 } 2328 2329 static void virt_set_virt(Object *obj, bool value, Error **errp) 2330 { 2331 VirtMachineState *vms = VIRT_MACHINE(obj); 2332 2333 vms->virt = value; 2334 } 2335 2336 static bool virt_get_highmem(Object *obj, Error **errp) 2337 { 2338 VirtMachineState *vms = VIRT_MACHINE(obj); 2339 2340 return vms->highmem; 2341 } 2342 2343 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2344 { 2345 VirtMachineState *vms = VIRT_MACHINE(obj); 2346 2347 vms->highmem = value; 2348 } 2349 2350 static bool virt_get_compact_highmem(Object *obj, Error **errp) 2351 { 2352 VirtMachineState *vms = VIRT_MACHINE(obj); 2353 2354 return vms->highmem_compact; 2355 } 2356 2357 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) 2358 { 2359 VirtMachineState *vms = VIRT_MACHINE(obj); 2360 2361 vms->highmem_compact = value; 2362 } 2363 2364 static bool virt_get_highmem_redists(Object *obj, Error **errp) 2365 { 2366 VirtMachineState *vms = VIRT_MACHINE(obj); 2367 2368 return vms->highmem_redists; 2369 } 2370 2371 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp) 2372 { 2373 VirtMachineState *vms = VIRT_MACHINE(obj); 2374 2375 vms->highmem_redists = value; 2376 } 2377 2378 static bool virt_get_highmem_ecam(Object *obj, Error **errp) 2379 { 2380 VirtMachineState *vms = VIRT_MACHINE(obj); 2381 2382 return vms->highmem_ecam; 2383 } 2384 2385 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp) 2386 { 2387 VirtMachineState *vms = VIRT_MACHINE(obj); 2388 2389 vms->highmem_ecam = value; 2390 } 2391 2392 static bool virt_get_highmem_mmio(Object *obj, Error **errp) 2393 { 2394 VirtMachineState *vms = VIRT_MACHINE(obj); 2395 2396 return vms->highmem_mmio; 2397 } 2398 2399 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) 2400 { 2401 VirtMachineState *vms = VIRT_MACHINE(obj); 2402 2403 vms->highmem_mmio = value; 2404 } 2405 2406 2407 static bool virt_get_its(Object *obj, Error **errp) 2408 { 2409 VirtMachineState *vms = VIRT_MACHINE(obj); 2410 2411 return vms->its; 2412 } 2413 2414 static void virt_set_its(Object *obj, bool value, Error **errp) 2415 { 2416 VirtMachineState *vms = VIRT_MACHINE(obj); 2417 2418 vms->its = value; 2419 } 2420 2421 static bool virt_get_dtb_randomness(Object *obj, Error **errp) 2422 { 2423 VirtMachineState *vms = VIRT_MACHINE(obj); 2424 2425 return vms->dtb_randomness; 2426 } 2427 2428 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp) 2429 { 2430 VirtMachineState *vms = VIRT_MACHINE(obj); 2431 2432 vms->dtb_randomness = value; 2433 } 2434 2435 static char *virt_get_oem_id(Object *obj, Error **errp) 2436 { 2437 VirtMachineState *vms = VIRT_MACHINE(obj); 2438 2439 return g_strdup(vms->oem_id); 2440 } 2441 2442 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2443 { 2444 VirtMachineState *vms = VIRT_MACHINE(obj); 2445 size_t len = strlen(value); 2446 2447 if (len > 6) { 2448 error_setg(errp, 2449 "User specified oem-id value is bigger than 6 bytes in size"); 2450 return; 2451 } 2452 2453 strncpy(vms->oem_id, value, 6); 2454 } 2455 2456 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2457 { 2458 VirtMachineState *vms = VIRT_MACHINE(obj); 2459 2460 return g_strdup(vms->oem_table_id); 2461 } 2462 2463 static void virt_set_oem_table_id(Object *obj, const char *value, 2464 Error **errp) 2465 { 2466 VirtMachineState *vms = VIRT_MACHINE(obj); 2467 size_t len = strlen(value); 2468 2469 if (len > 8) { 2470 error_setg(errp, 2471 "User specified oem-table-id value is bigger than 8 bytes in size"); 2472 return; 2473 } 2474 strncpy(vms->oem_table_id, value, 8); 2475 } 2476 2477 2478 bool virt_is_acpi_enabled(VirtMachineState *vms) 2479 { 2480 if (vms->acpi == ON_OFF_AUTO_OFF) { 2481 return false; 2482 } 2483 return true; 2484 } 2485 2486 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2487 void *opaque, Error **errp) 2488 { 2489 VirtMachineState *vms = VIRT_MACHINE(obj); 2490 OnOffAuto acpi = vms->acpi; 2491 2492 visit_type_OnOffAuto(v, name, &acpi, errp); 2493 } 2494 2495 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2496 void *opaque, Error **errp) 2497 { 2498 VirtMachineState *vms = VIRT_MACHINE(obj); 2499 2500 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2501 } 2502 2503 static bool virt_get_ras(Object *obj, Error **errp) 2504 { 2505 VirtMachineState *vms = VIRT_MACHINE(obj); 2506 2507 return vms->ras; 2508 } 2509 2510 static void virt_set_ras(Object *obj, bool value, Error **errp) 2511 { 2512 VirtMachineState *vms = VIRT_MACHINE(obj); 2513 2514 vms->ras = value; 2515 } 2516 2517 static bool virt_get_mte(Object *obj, Error **errp) 2518 { 2519 VirtMachineState *vms = VIRT_MACHINE(obj); 2520 2521 return vms->mte; 2522 } 2523 2524 static void virt_set_mte(Object *obj, bool value, Error **errp) 2525 { 2526 VirtMachineState *vms = VIRT_MACHINE(obj); 2527 2528 vms->mte = value; 2529 } 2530 2531 static char *virt_get_gic_version(Object *obj, Error **errp) 2532 { 2533 VirtMachineState *vms = VIRT_MACHINE(obj); 2534 const char *val; 2535 2536 switch (vms->gic_version) { 2537 case VIRT_GIC_VERSION_4: 2538 val = "4"; 2539 break; 2540 case VIRT_GIC_VERSION_3: 2541 val = "3"; 2542 break; 2543 default: 2544 val = "2"; 2545 break; 2546 } 2547 return g_strdup(val); 2548 } 2549 2550 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2551 { 2552 VirtMachineState *vms = VIRT_MACHINE(obj); 2553 2554 if (!strcmp(value, "4")) { 2555 vms->gic_version = VIRT_GIC_VERSION_4; 2556 } else if (!strcmp(value, "3")) { 2557 vms->gic_version = VIRT_GIC_VERSION_3; 2558 } else if (!strcmp(value, "2")) { 2559 vms->gic_version = VIRT_GIC_VERSION_2; 2560 } else if (!strcmp(value, "host")) { 2561 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2562 } else if (!strcmp(value, "max")) { 2563 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2564 } else { 2565 error_setg(errp, "Invalid gic-version value"); 2566 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2567 } 2568 } 2569 2570 static char *virt_get_iommu(Object *obj, Error **errp) 2571 { 2572 VirtMachineState *vms = VIRT_MACHINE(obj); 2573 2574 switch (vms->iommu) { 2575 case VIRT_IOMMU_NONE: 2576 return g_strdup("none"); 2577 case VIRT_IOMMU_SMMUV3: 2578 return g_strdup("smmuv3"); 2579 default: 2580 g_assert_not_reached(); 2581 } 2582 } 2583 2584 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2585 { 2586 VirtMachineState *vms = VIRT_MACHINE(obj); 2587 2588 if (!strcmp(value, "smmuv3")) { 2589 vms->iommu = VIRT_IOMMU_SMMUV3; 2590 } else if (!strcmp(value, "none")) { 2591 vms->iommu = VIRT_IOMMU_NONE; 2592 } else { 2593 error_setg(errp, "Invalid iommu value"); 2594 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2595 } 2596 } 2597 2598 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) 2599 { 2600 VirtMachineState *vms = VIRT_MACHINE(obj); 2601 2602 return vms->default_bus_bypass_iommu; 2603 } 2604 2605 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, 2606 Error **errp) 2607 { 2608 VirtMachineState *vms = VIRT_MACHINE(obj); 2609 2610 vms->default_bus_bypass_iommu = value; 2611 } 2612 2613 static CpuInstanceProperties 2614 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2615 { 2616 MachineClass *mc = MACHINE_GET_CLASS(ms); 2617 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2618 2619 assert(cpu_index < possible_cpus->len); 2620 return possible_cpus->cpus[cpu_index].props; 2621 } 2622 2623 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2624 { 2625 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 2626 2627 return socket_id % ms->numa_state->num_nodes; 2628 } 2629 2630 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2631 { 2632 int n; 2633 unsigned int max_cpus = ms->smp.max_cpus; 2634 VirtMachineState *vms = VIRT_MACHINE(ms); 2635 MachineClass *mc = MACHINE_GET_CLASS(vms); 2636 2637 if (ms->possible_cpus) { 2638 assert(ms->possible_cpus->len == max_cpus); 2639 return ms->possible_cpus; 2640 } 2641 2642 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2643 sizeof(CPUArchId) * max_cpus); 2644 ms->possible_cpus->len = max_cpus; 2645 for (n = 0; n < ms->possible_cpus->len; n++) { 2646 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2647 ms->possible_cpus->cpus[n].arch_id = 2648 virt_cpu_mp_affinity(vms, n); 2649 2650 assert(!mc->smp_props.dies_supported); 2651 ms->possible_cpus->cpus[n].props.has_socket_id = true; 2652 ms->possible_cpus->cpus[n].props.socket_id = 2653 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); 2654 ms->possible_cpus->cpus[n].props.has_cluster_id = true; 2655 ms->possible_cpus->cpus[n].props.cluster_id = 2656 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; 2657 ms->possible_cpus->cpus[n].props.has_core_id = true; 2658 ms->possible_cpus->cpus[n].props.core_id = 2659 (n / ms->smp.threads) % ms->smp.cores; 2660 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2661 ms->possible_cpus->cpus[n].props.thread_id = 2662 n % ms->smp.threads; 2663 } 2664 return ms->possible_cpus; 2665 } 2666 2667 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2668 Error **errp) 2669 { 2670 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2671 const MachineState *ms = MACHINE(hotplug_dev); 2672 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2673 2674 if (!vms->acpi_dev) { 2675 error_setg(errp, 2676 "memory hotplug is not enabled: missing acpi-ged device"); 2677 return; 2678 } 2679 2680 if (vms->mte) { 2681 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2682 return; 2683 } 2684 2685 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2686 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2687 return; 2688 } 2689 2690 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2691 } 2692 2693 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2694 DeviceState *dev, Error **errp) 2695 { 2696 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2697 MachineState *ms = MACHINE(hotplug_dev); 2698 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2699 2700 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2701 2702 if (is_nvdimm) { 2703 nvdimm_plug(ms->nvdimms_state); 2704 } 2705 2706 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2707 dev, &error_abort); 2708 } 2709 2710 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2711 DeviceState *dev, Error **errp) 2712 { 2713 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2714 2715 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2716 virt_memory_pre_plug(hotplug_dev, dev, errp); 2717 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2718 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2719 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2720 hwaddr db_start = 0, db_end = 0; 2721 QList *reserved_regions; 2722 char *resv_prop_str; 2723 2724 if (vms->iommu != VIRT_IOMMU_NONE) { 2725 error_setg(errp, "virt machine does not support multiple IOMMUs"); 2726 return; 2727 } 2728 2729 switch (vms->msi_controller) { 2730 case VIRT_MSI_CTRL_NONE: 2731 return; 2732 case VIRT_MSI_CTRL_ITS: 2733 /* GITS_TRANSLATER page */ 2734 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2735 db_end = base_memmap[VIRT_GIC_ITS].base + 2736 base_memmap[VIRT_GIC_ITS].size - 1; 2737 break; 2738 case VIRT_MSI_CTRL_GICV2M: 2739 /* MSI_SETSPI_NS page */ 2740 db_start = base_memmap[VIRT_GIC_V2M].base; 2741 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2742 break; 2743 } 2744 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2745 db_start, db_end, 2746 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2747 2748 reserved_regions = qlist_new(); 2749 qlist_append_str(reserved_regions, resv_prop_str); 2750 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 2751 g_free(resv_prop_str); 2752 } 2753 } 2754 2755 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2756 DeviceState *dev, Error **errp) 2757 { 2758 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2759 2760 if (vms->platform_bus_dev) { 2761 MachineClass *mc = MACHINE_GET_CLASS(vms); 2762 2763 if (device_is_dynamic_sysbus(mc, dev)) { 2764 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2765 SYS_BUS_DEVICE(dev)); 2766 } 2767 } 2768 2769 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2770 virt_memory_plug(hotplug_dev, dev, errp); 2771 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2772 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2773 } 2774 2775 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2776 PCIDevice *pdev = PCI_DEVICE(dev); 2777 2778 vms->iommu = VIRT_IOMMU_VIRTIO; 2779 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2780 create_virtio_iommu_dt_bindings(vms); 2781 } 2782 } 2783 2784 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 2785 DeviceState *dev, Error **errp) 2786 { 2787 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2788 2789 if (!vms->acpi_dev) { 2790 error_setg(errp, 2791 "memory hotplug is not enabled: missing acpi-ged device"); 2792 return; 2793 } 2794 2795 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2796 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 2797 return; 2798 } 2799 2800 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 2801 errp); 2802 } 2803 2804 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 2805 DeviceState *dev, Error **errp) 2806 { 2807 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2808 Error *local_err = NULL; 2809 2810 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 2811 if (local_err) { 2812 goto out; 2813 } 2814 2815 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 2816 qdev_unrealize(dev); 2817 2818 out: 2819 error_propagate(errp, local_err); 2820 } 2821 2822 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2823 DeviceState *dev, Error **errp) 2824 { 2825 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2826 virt_dimm_unplug_request(hotplug_dev, dev, errp); 2827 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2828 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 2829 errp); 2830 } else { 2831 error_setg(errp, "device unplug request for unsupported device" 2832 " type: %s", object_get_typename(OBJECT(dev))); 2833 } 2834 } 2835 2836 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2837 DeviceState *dev, Error **errp) 2838 { 2839 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2840 virt_dimm_unplug(hotplug_dev, dev, errp); 2841 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2842 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2843 } else { 2844 error_setg(errp, "virt: device unplug for unsupported device" 2845 " type: %s", object_get_typename(OBJECT(dev))); 2846 } 2847 } 2848 2849 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2850 DeviceState *dev) 2851 { 2852 MachineClass *mc = MACHINE_GET_CLASS(machine); 2853 2854 if (device_is_dynamic_sysbus(mc, dev) || 2855 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2856 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 2857 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2858 return HOTPLUG_HANDLER(machine); 2859 } 2860 return NULL; 2861 } 2862 2863 /* 2864 * for arm64 kvm_type [7-0] encodes the requested number of bits 2865 * in the IPA address space 2866 */ 2867 static int virt_kvm_type(MachineState *ms, const char *type_str) 2868 { 2869 VirtMachineState *vms = VIRT_MACHINE(ms); 2870 int max_vm_pa_size, requested_pa_size; 2871 bool fixed_ipa; 2872 2873 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 2874 2875 /* we freeze the memory map to compute the highest gpa */ 2876 virt_set_memmap(vms, max_vm_pa_size); 2877 2878 requested_pa_size = 64 - clz64(vms->highest_gpa); 2879 2880 /* 2881 * KVM requires the IPA size to be at least 32 bits. 2882 */ 2883 if (requested_pa_size < 32) { 2884 requested_pa_size = 32; 2885 } 2886 2887 if (requested_pa_size > max_vm_pa_size) { 2888 error_report("-m and ,maxmem option values " 2889 "require an IPA range (%d bits) larger than " 2890 "the one supported by the host (%d bits)", 2891 requested_pa_size, max_vm_pa_size); 2892 return -1; 2893 } 2894 /* 2895 * We return the requested PA log size, unless KVM only supports 2896 * the implicit legacy 40b IPA setting, in which case the kvm_type 2897 * must be 0. 2898 */ 2899 return fixed_ipa ? 0 : requested_pa_size; 2900 } 2901 2902 static void virt_machine_class_init(ObjectClass *oc, void *data) 2903 { 2904 MachineClass *mc = MACHINE_CLASS(oc); 2905 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2906 static const char * const valid_cpu_types[] = { 2907 #ifdef CONFIG_TCG 2908 ARM_CPU_TYPE_NAME("cortex-a7"), 2909 ARM_CPU_TYPE_NAME("cortex-a15"), 2910 #ifdef TARGET_AARCH64 2911 ARM_CPU_TYPE_NAME("cortex-a35"), 2912 ARM_CPU_TYPE_NAME("cortex-a55"), 2913 ARM_CPU_TYPE_NAME("cortex-a72"), 2914 ARM_CPU_TYPE_NAME("cortex-a76"), 2915 ARM_CPU_TYPE_NAME("cortex-a710"), 2916 ARM_CPU_TYPE_NAME("a64fx"), 2917 ARM_CPU_TYPE_NAME("neoverse-n1"), 2918 ARM_CPU_TYPE_NAME("neoverse-v1"), 2919 ARM_CPU_TYPE_NAME("neoverse-n2"), 2920 #endif /* TARGET_AARCH64 */ 2921 #endif /* CONFIG_TCG */ 2922 #ifdef TARGET_AARCH64 2923 ARM_CPU_TYPE_NAME("cortex-a53"), 2924 ARM_CPU_TYPE_NAME("cortex-a57"), 2925 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 2926 ARM_CPU_TYPE_NAME("host"), 2927 #endif /* CONFIG_KVM || CONFIG_HVF */ 2928 #endif /* TARGET_AARCH64 */ 2929 ARM_CPU_TYPE_NAME("max"), 2930 NULL 2931 }; 2932 2933 mc->init = machvirt_init; 2934 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 2935 * The value may be reduced later when we have more information about the 2936 * configuration of the particular instance. 2937 */ 2938 mc->max_cpus = 512; 2939 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 2940 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 2941 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 2942 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 2943 #ifdef CONFIG_TPM 2944 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 2945 #endif 2946 mc->block_default_type = IF_VIRTIO; 2947 mc->no_cdrom = 1; 2948 mc->pci_allow_0_address = true; 2949 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 2950 mc->minimum_page_bits = 12; 2951 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 2952 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 2953 #ifdef CONFIG_TCG 2954 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 2955 #else 2956 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); 2957 #endif 2958 mc->valid_cpu_types = valid_cpu_types; 2959 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 2960 mc->kvm_type = virt_kvm_type; 2961 assert(!mc->get_hotplug_handler); 2962 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 2963 hc->pre_plug = virt_machine_device_pre_plug_cb; 2964 hc->plug = virt_machine_device_plug_cb; 2965 hc->unplug_request = virt_machine_device_unplug_request_cb; 2966 hc->unplug = virt_machine_device_unplug_cb; 2967 mc->nvdimm_supported = true; 2968 mc->smp_props.clusters_supported = true; 2969 mc->auto_enable_numa_with_memhp = true; 2970 mc->auto_enable_numa_with_memdev = true; 2971 /* platform instead of architectural choice */ 2972 mc->cpu_cluster_has_numa_boundary = true; 2973 mc->default_ram_id = "mach-virt.ram"; 2974 mc->default_nic = "virtio-net-pci"; 2975 2976 object_class_property_add(oc, "acpi", "OnOffAuto", 2977 virt_get_acpi, virt_set_acpi, 2978 NULL, NULL); 2979 object_class_property_set_description(oc, "acpi", 2980 "Enable ACPI"); 2981 object_class_property_add_bool(oc, "secure", virt_get_secure, 2982 virt_set_secure); 2983 object_class_property_set_description(oc, "secure", 2984 "Set on/off to enable/disable the ARM " 2985 "Security Extensions (TrustZone)"); 2986 2987 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 2988 virt_set_virt); 2989 object_class_property_set_description(oc, "virtualization", 2990 "Set on/off to enable/disable emulating a " 2991 "guest CPU which implements the ARM " 2992 "Virtualization Extensions"); 2993 2994 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 2995 virt_set_highmem); 2996 object_class_property_set_description(oc, "highmem", 2997 "Set on/off to enable/disable using " 2998 "physical address space above 32 bits"); 2999 3000 object_class_property_add_bool(oc, "compact-highmem", 3001 virt_get_compact_highmem, 3002 virt_set_compact_highmem); 3003 object_class_property_set_description(oc, "compact-highmem", 3004 "Set on/off to enable/disable compact " 3005 "layout for high memory regions"); 3006 3007 object_class_property_add_bool(oc, "highmem-redists", 3008 virt_get_highmem_redists, 3009 virt_set_highmem_redists); 3010 object_class_property_set_description(oc, "highmem-redists", 3011 "Set on/off to enable/disable high " 3012 "memory region for GICv3 or GICv4 " 3013 "redistributor"); 3014 3015 object_class_property_add_bool(oc, "highmem-ecam", 3016 virt_get_highmem_ecam, 3017 virt_set_highmem_ecam); 3018 object_class_property_set_description(oc, "highmem-ecam", 3019 "Set on/off to enable/disable high " 3020 "memory region for PCI ECAM"); 3021 3022 object_class_property_add_bool(oc, "highmem-mmio", 3023 virt_get_highmem_mmio, 3024 virt_set_highmem_mmio); 3025 object_class_property_set_description(oc, "highmem-mmio", 3026 "Set on/off to enable/disable high " 3027 "memory region for PCI MMIO"); 3028 3029 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 3030 virt_set_gic_version); 3031 object_class_property_set_description(oc, "gic-version", 3032 "Set GIC version. " 3033 "Valid values are 2, 3, 4, host and max"); 3034 3035 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 3036 object_class_property_set_description(oc, "iommu", 3037 "Set the IOMMU type. " 3038 "Valid values are none and smmuv3"); 3039 3040 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 3041 virt_get_default_bus_bypass_iommu, 3042 virt_set_default_bus_bypass_iommu); 3043 object_class_property_set_description(oc, "default-bus-bypass-iommu", 3044 "Set on/off to enable/disable " 3045 "bypass_iommu for default root bus"); 3046 3047 object_class_property_add_bool(oc, "ras", virt_get_ras, 3048 virt_set_ras); 3049 object_class_property_set_description(oc, "ras", 3050 "Set on/off to enable/disable reporting host memory errors " 3051 "to a KVM guest using ACPI and guest external abort exceptions"); 3052 3053 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 3054 object_class_property_set_description(oc, "mte", 3055 "Set on/off to enable/disable emulating a " 3056 "guest CPU which implements the ARM " 3057 "Memory Tagging Extension"); 3058 3059 object_class_property_add_bool(oc, "its", virt_get_its, 3060 virt_set_its); 3061 object_class_property_set_description(oc, "its", 3062 "Set on/off to enable/disable " 3063 "ITS instantiation"); 3064 3065 object_class_property_add_bool(oc, "dtb-randomness", 3066 virt_get_dtb_randomness, 3067 virt_set_dtb_randomness); 3068 object_class_property_set_description(oc, "dtb-randomness", 3069 "Set off to disable passing random or " 3070 "non-deterministic dtb nodes to guest"); 3071 3072 object_class_property_add_bool(oc, "dtb-kaslr-seed", 3073 virt_get_dtb_randomness, 3074 virt_set_dtb_randomness); 3075 object_class_property_set_description(oc, "dtb-kaslr-seed", 3076 "Deprecated synonym of dtb-randomness"); 3077 3078 object_class_property_add_str(oc, "x-oem-id", 3079 virt_get_oem_id, 3080 virt_set_oem_id); 3081 object_class_property_set_description(oc, "x-oem-id", 3082 "Override the default value of field OEMID " 3083 "in ACPI table header." 3084 "The string may be up to 6 bytes in size"); 3085 3086 3087 object_class_property_add_str(oc, "x-oem-table-id", 3088 virt_get_oem_table_id, 3089 virt_set_oem_table_id); 3090 object_class_property_set_description(oc, "x-oem-table-id", 3091 "Override the default value of field OEM Table ID " 3092 "in ACPI table header." 3093 "The string may be up to 8 bytes in size"); 3094 3095 } 3096 3097 static void virt_instance_init(Object *obj) 3098 { 3099 VirtMachineState *vms = VIRT_MACHINE(obj); 3100 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 3101 3102 /* EL3 is disabled by default on virt: this makes us consistent 3103 * between KVM and TCG for this board, and it also allows us to 3104 * boot UEFI blobs which assume no TrustZone support. 3105 */ 3106 vms->secure = false; 3107 3108 /* EL2 is also disabled by default, for similar reasons */ 3109 vms->virt = false; 3110 3111 /* High memory is enabled by default */ 3112 vms->highmem = true; 3113 vms->highmem_compact = !vmc->no_highmem_compact; 3114 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 3115 3116 vms->highmem_ecam = !vmc->no_highmem_ecam; 3117 vms->highmem_mmio = true; 3118 vms->highmem_redists = true; 3119 3120 if (vmc->no_its) { 3121 vms->its = false; 3122 } else { 3123 /* Default allows ITS instantiation */ 3124 vms->its = true; 3125 3126 if (vmc->no_tcg_its) { 3127 vms->tcg_its = false; 3128 } else { 3129 vms->tcg_its = true; 3130 } 3131 } 3132 3133 /* Default disallows iommu instantiation */ 3134 vms->iommu = VIRT_IOMMU_NONE; 3135 3136 /* The default root bus is attached to iommu by default */ 3137 vms->default_bus_bypass_iommu = false; 3138 3139 /* Default disallows RAS instantiation */ 3140 vms->ras = false; 3141 3142 /* MTE is disabled by default. */ 3143 vms->mte = false; 3144 3145 /* Supply kaslr-seed and rng-seed by default */ 3146 vms->dtb_randomness = true; 3147 3148 vms->irqmap = a15irqmap; 3149 3150 virt_flash_create(vms); 3151 3152 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 3153 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 3154 } 3155 3156 static const TypeInfo virt_machine_info = { 3157 .name = TYPE_VIRT_MACHINE, 3158 .parent = TYPE_MACHINE, 3159 .abstract = true, 3160 .instance_size = sizeof(VirtMachineState), 3161 .class_size = sizeof(VirtMachineClass), 3162 .class_init = virt_machine_class_init, 3163 .instance_init = virt_instance_init, 3164 .interfaces = (InterfaceInfo[]) { 3165 { TYPE_HOTPLUG_HANDLER }, 3166 { } 3167 }, 3168 }; 3169 3170 static void machvirt_machine_init(void) 3171 { 3172 type_register_static(&virt_machine_info); 3173 } 3174 type_init(machvirt_machine_init); 3175 3176 static void virt_machine_9_0_options(MachineClass *mc) 3177 { 3178 } 3179 DEFINE_VIRT_MACHINE_AS_LATEST(9, 0) 3180 3181 static void virt_machine_8_2_options(MachineClass *mc) 3182 { 3183 virt_machine_9_0_options(mc); 3184 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len); 3185 } 3186 DEFINE_VIRT_MACHINE(8, 2) 3187 3188 static void virt_machine_8_1_options(MachineClass *mc) 3189 { 3190 virt_machine_8_2_options(mc); 3191 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len); 3192 } 3193 DEFINE_VIRT_MACHINE(8, 1) 3194 3195 static void virt_machine_8_0_options(MachineClass *mc) 3196 { 3197 virt_machine_8_1_options(mc); 3198 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 3199 } 3200 DEFINE_VIRT_MACHINE(8, 0) 3201 3202 static void virt_machine_7_2_options(MachineClass *mc) 3203 { 3204 virt_machine_8_0_options(mc); 3205 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 3206 } 3207 DEFINE_VIRT_MACHINE(7, 2) 3208 3209 static void virt_machine_7_1_options(MachineClass *mc) 3210 { 3211 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3212 3213 virt_machine_7_2_options(mc); 3214 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 3215 /* Compact layout for high memory regions was introduced with 7.2 */ 3216 vmc->no_highmem_compact = true; 3217 } 3218 DEFINE_VIRT_MACHINE(7, 1) 3219 3220 static void virt_machine_7_0_options(MachineClass *mc) 3221 { 3222 virt_machine_7_1_options(mc); 3223 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 3224 } 3225 DEFINE_VIRT_MACHINE(7, 0) 3226 3227 static void virt_machine_6_2_options(MachineClass *mc) 3228 { 3229 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3230 3231 virt_machine_7_0_options(mc); 3232 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 3233 vmc->no_tcg_lpa2 = true; 3234 } 3235 DEFINE_VIRT_MACHINE(6, 2) 3236 3237 static void virt_machine_6_1_options(MachineClass *mc) 3238 { 3239 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3240 3241 virt_machine_6_2_options(mc); 3242 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 3243 mc->smp_props.prefer_sockets = true; 3244 vmc->no_cpu_topology = true; 3245 3246 /* qemu ITS was introduced with 6.2 */ 3247 vmc->no_tcg_its = true; 3248 } 3249 DEFINE_VIRT_MACHINE(6, 1) 3250 3251 static void virt_machine_6_0_options(MachineClass *mc) 3252 { 3253 virt_machine_6_1_options(mc); 3254 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 3255 } 3256 DEFINE_VIRT_MACHINE(6, 0) 3257 3258 static void virt_machine_5_2_options(MachineClass *mc) 3259 { 3260 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3261 3262 virt_machine_6_0_options(mc); 3263 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 3264 vmc->no_secure_gpio = true; 3265 } 3266 DEFINE_VIRT_MACHINE(5, 2) 3267 3268 static void virt_machine_5_1_options(MachineClass *mc) 3269 { 3270 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3271 3272 virt_machine_5_2_options(mc); 3273 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 3274 vmc->no_kvm_steal_time = true; 3275 } 3276 DEFINE_VIRT_MACHINE(5, 1) 3277 3278 static void virt_machine_5_0_options(MachineClass *mc) 3279 { 3280 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3281 3282 virt_machine_5_1_options(mc); 3283 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 3284 mc->numa_mem_supported = true; 3285 vmc->acpi_expose_flash = true; 3286 mc->auto_enable_numa_with_memdev = false; 3287 } 3288 DEFINE_VIRT_MACHINE(5, 0) 3289 3290 static void virt_machine_4_2_options(MachineClass *mc) 3291 { 3292 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3293 3294 virt_machine_5_0_options(mc); 3295 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 3296 vmc->kvm_no_adjvtime = true; 3297 } 3298 DEFINE_VIRT_MACHINE(4, 2) 3299 3300 static void virt_machine_4_1_options(MachineClass *mc) 3301 { 3302 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3303 3304 virt_machine_4_2_options(mc); 3305 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 3306 vmc->no_ged = true; 3307 mc->auto_enable_numa_with_memhp = false; 3308 } 3309 DEFINE_VIRT_MACHINE(4, 1) 3310 3311 static void virt_machine_4_0_options(MachineClass *mc) 3312 { 3313 virt_machine_4_1_options(mc); 3314 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 3315 } 3316 DEFINE_VIRT_MACHINE(4, 0) 3317 3318 static void virt_machine_3_1_options(MachineClass *mc) 3319 { 3320 virt_machine_4_0_options(mc); 3321 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 3322 } 3323 DEFINE_VIRT_MACHINE(3, 1) 3324 3325 static void virt_machine_3_0_options(MachineClass *mc) 3326 { 3327 virt_machine_3_1_options(mc); 3328 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 3329 } 3330 DEFINE_VIRT_MACHINE(3, 0) 3331 3332 static void virt_machine_2_12_options(MachineClass *mc) 3333 { 3334 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3335 3336 virt_machine_3_0_options(mc); 3337 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 3338 vmc->no_highmem_ecam = true; 3339 mc->max_cpus = 255; 3340 } 3341 DEFINE_VIRT_MACHINE(2, 12) 3342 3343 static void virt_machine_2_11_options(MachineClass *mc) 3344 { 3345 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3346 3347 virt_machine_2_12_options(mc); 3348 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 3349 vmc->smbios_old_sys_ver = true; 3350 } 3351 DEFINE_VIRT_MACHINE(2, 11) 3352 3353 static void virt_machine_2_10_options(MachineClass *mc) 3354 { 3355 virt_machine_2_11_options(mc); 3356 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 3357 /* before 2.11 we never faulted accesses to bad addresses */ 3358 mc->ignore_memory_transaction_failures = true; 3359 } 3360 DEFINE_VIRT_MACHINE(2, 10) 3361 3362 static void virt_machine_2_9_options(MachineClass *mc) 3363 { 3364 virt_machine_2_10_options(mc); 3365 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 3366 } 3367 DEFINE_VIRT_MACHINE(2, 9) 3368 3369 static void virt_machine_2_8_options(MachineClass *mc) 3370 { 3371 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3372 3373 virt_machine_2_9_options(mc); 3374 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 3375 /* For 2.8 and earlier we falsely claimed in the DT that 3376 * our timers were edge-triggered, not level-triggered. 3377 */ 3378 vmc->claim_edge_triggered_timers = true; 3379 } 3380 DEFINE_VIRT_MACHINE(2, 8) 3381 3382 static void virt_machine_2_7_options(MachineClass *mc) 3383 { 3384 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3385 3386 virt_machine_2_8_options(mc); 3387 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 3388 /* ITS was introduced with 2.8 */ 3389 vmc->no_its = true; 3390 /* Stick with 1K pages for migration compatibility */ 3391 mc->minimum_page_bits = 0; 3392 } 3393 DEFINE_VIRT_MACHINE(2, 7) 3394 3395 static void virt_machine_2_6_options(MachineClass *mc) 3396 { 3397 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3398 3399 virt_machine_2_7_options(mc); 3400 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 3401 vmc->disallow_affinity_adjustment = true; 3402 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 3403 vmc->no_pmu = true; 3404 } 3405 DEFINE_VIRT_MACHINE(2, 6) 3406