1 /* 2 * ARM mach-virt emulation 3 * 4 * Copyright (c) 2013 Linaro Limited 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * Emulate a virtual board which works by passing Linux all the information 19 * it needs about what devices are present via the device tree. 20 * There are some restrictions about what we can do here: 21 * + we can only present devices whose Linux drivers will work based 22 * purely on the device tree with no platform data at all 23 * + we want to present a very stripped-down minimalist platform, 24 * both because this reduces the security attack surface from the guest 25 * and also because it reduces our exposure to being broken when 26 * the kernel updates its device tree bindings and requires further 27 * information in a device binding that we aren't providing. 28 * This is essentially the same approach kvmtool uses. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/datadir.h" 33 #include "qemu/units.h" 34 #include "qemu/option.h" 35 #include "monitor/qdev.h" 36 #include "hw/sysbus.h" 37 #include "hw/arm/boot.h" 38 #include "hw/arm/primecell.h" 39 #include "hw/arm/virt.h" 40 #include "hw/block/flash.h" 41 #include "hw/vfio/vfio-calxeda-xgmac.h" 42 #include "hw/vfio/vfio-amd-xgbe.h" 43 #include "hw/display/ramfb.h" 44 #include "net/net.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/numa.h" 47 #include "sysemu/runstate.h" 48 #include "sysemu/tpm.h" 49 #include "sysemu/tcg.h" 50 #include "sysemu/kvm.h" 51 #include "sysemu/hvf.h" 52 #include "sysemu/qtest.h" 53 #include "hw/loader.h" 54 #include "qapi/error.h" 55 #include "qemu/bitops.h" 56 #include "qemu/error-report.h" 57 #include "qemu/module.h" 58 #include "hw/pci-host/gpex.h" 59 #include "hw/virtio/virtio-pci.h" 60 #include "hw/core/sysbus-fdt.h" 61 #include "hw/platform-bus.h" 62 #include "hw/qdev-properties.h" 63 #include "hw/arm/fdt.h" 64 #include "hw/intc/arm_gic.h" 65 #include "hw/intc/arm_gicv3_common.h" 66 #include "hw/intc/arm_gicv3_its_common.h" 67 #include "hw/irq.h" 68 #include "kvm_arm.h" 69 #include "hw/firmware/smbios.h" 70 #include "qapi/visitor.h" 71 #include "qapi/qapi-visit-common.h" 72 #include "standard-headers/linux/input.h" 73 #include "hw/arm/smmuv3.h" 74 #include "hw/acpi/acpi.h" 75 #include "target/arm/internals.h" 76 #include "hw/mem/pc-dimm.h" 77 #include "hw/mem/nvdimm.h" 78 #include "hw/acpi/generic_event_device.h" 79 #include "hw/virtio/virtio-md-pci.h" 80 #include "hw/virtio/virtio-iommu.h" 81 #include "hw/char/pl011.h" 82 #include "qemu/guest-random.h" 83 84 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ 85 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ 86 void *data) \ 87 { \ 88 MachineClass *mc = MACHINE_CLASS(oc); \ 89 virt_machine_##major##_##minor##_options(mc); \ 90 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ 91 if (latest) { \ 92 mc->alias = "virt"; \ 93 } \ 94 } \ 95 static const TypeInfo machvirt_##major##_##minor##_info = { \ 96 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ 97 .parent = TYPE_VIRT_MACHINE, \ 98 .class_init = virt_##major##_##minor##_class_init, \ 99 }; \ 100 static void machvirt_machine_##major##_##minor##_init(void) \ 101 { \ 102 type_register_static(&machvirt_##major##_##minor##_info); \ 103 } \ 104 type_init(machvirt_machine_##major##_##minor##_init); 105 106 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ 107 DEFINE_VIRT_MACHINE_LATEST(major, minor, true) 108 #define DEFINE_VIRT_MACHINE(major, minor) \ 109 DEFINE_VIRT_MACHINE_LATEST(major, minor, false) 110 111 112 /* Number of external interrupt lines to configure the GIC with */ 113 #define NUM_IRQS 256 114 115 #define PLATFORM_BUS_NUM_IRQS 64 116 117 /* Legacy RAM limit in GB (< version 4.0) */ 118 #define LEGACY_RAMLIMIT_GB 255 119 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) 120 121 /* Addresses and sizes of our components. 122 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. 123 * 128MB..256MB is used for miscellaneous device I/O. 124 * 256MB..1GB is reserved for possible future PCI support (ie where the 125 * PCI memory window will go if we add a PCI host controller). 126 * 1GB and up is RAM (which may happily spill over into the 127 * high memory region beyond 4GB). 128 * This represents a compromise between how much RAM can be given to 129 * a 32 bit VM and leaving space for expansion and in particular for PCI. 130 * Note that devices should generally be placed at multiples of 0x10000, 131 * to accommodate guests using 64K pages. 132 */ 133 static const MemMapEntry base_memmap[] = { 134 /* Space up to 0x8000000 is reserved for a boot ROM */ 135 [VIRT_FLASH] = { 0, 0x08000000 }, 136 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, 137 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ 138 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, 139 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, 140 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, 141 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, 142 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, 143 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ 144 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, 145 /* This redistributor space allows up to 2*64kB*123 CPUs */ 146 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, 147 [VIRT_UART] = { 0x09000000, 0x00001000 }, 148 [VIRT_RTC] = { 0x09010000, 0x00001000 }, 149 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, 150 [VIRT_GPIO] = { 0x09030000, 0x00001000 }, 151 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, 152 [VIRT_SMMU] = { 0x09050000, 0x00020000 }, 153 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, 154 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, 155 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, 156 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, 157 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, 158 [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, 159 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ 160 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, 161 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, 162 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, 163 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, 164 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, 165 /* Actual RAM size depends on initial RAM and device memory settings */ 166 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, 167 }; 168 169 /* 170 * Highmem IO Regions: This memory map is floating, located after the RAM. 171 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the 172 * top of the RAM, so that its base get the same alignment as the size, 173 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is 174 * less than 256GiB of RAM, the floating area starts at the 256GiB mark. 175 * Note the extended_memmap is sized so that it eventually also includes the 176 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last 177 * index of base_memmap). 178 * 179 * The memory map for these Highmem IO Regions can be in legacy or compact 180 * layout, depending on 'compact-highmem' property. With legacy layout, the 181 * PA space for one specific region is always reserved, even if the region 182 * has been disabled or doesn't fit into the PA space. However, the PA space 183 * for the region won't be reserved in these circumstances with compact layout. 184 */ 185 static MemMapEntry extended_memmap[] = { 186 /* Additional 64 MB redist region (can contain up to 512 redistributors) */ 187 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, 188 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, 189 /* Second PCIe window */ 190 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, 191 }; 192 193 static const int a15irqmap[] = { 194 [VIRT_UART] = 1, 195 [VIRT_RTC] = 2, 196 [VIRT_PCIE] = 3, /* ... to 6 */ 197 [VIRT_GPIO] = 7, 198 [VIRT_SECURE_UART] = 8, 199 [VIRT_ACPI_GED] = 9, 200 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ 201 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ 202 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ 203 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ 204 }; 205 206 static const char *valid_cpus[] = { 207 #ifdef CONFIG_TCG 208 ARM_CPU_TYPE_NAME("cortex-a7"), 209 ARM_CPU_TYPE_NAME("cortex-a15"), 210 ARM_CPU_TYPE_NAME("cortex-a35"), 211 ARM_CPU_TYPE_NAME("cortex-a55"), 212 ARM_CPU_TYPE_NAME("cortex-a72"), 213 ARM_CPU_TYPE_NAME("cortex-a76"), 214 ARM_CPU_TYPE_NAME("cortex-a710"), 215 ARM_CPU_TYPE_NAME("a64fx"), 216 ARM_CPU_TYPE_NAME("neoverse-n1"), 217 ARM_CPU_TYPE_NAME("neoverse-v1"), 218 #endif 219 ARM_CPU_TYPE_NAME("cortex-a53"), 220 ARM_CPU_TYPE_NAME("cortex-a57"), 221 ARM_CPU_TYPE_NAME("host"), 222 ARM_CPU_TYPE_NAME("max"), 223 }; 224 225 static bool cpu_type_valid(const char *cpu) 226 { 227 int i; 228 229 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { 230 if (strcmp(cpu, valid_cpus[i]) == 0) { 231 return true; 232 } 233 } 234 return false; 235 } 236 237 static void create_randomness(MachineState *ms, const char *node) 238 { 239 struct { 240 uint64_t kaslr; 241 uint8_t rng[32]; 242 } seed; 243 244 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { 245 return; 246 } 247 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr); 248 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); 249 } 250 251 static void create_fdt(VirtMachineState *vms) 252 { 253 MachineState *ms = MACHINE(vms); 254 int nb_numa_nodes = ms->numa_state->num_nodes; 255 void *fdt = create_device_tree(&vms->fdt_size); 256 257 if (!fdt) { 258 error_report("create_device_tree() failed"); 259 exit(1); 260 } 261 262 ms->fdt = fdt; 263 264 /* Header */ 265 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); 266 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 267 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 268 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt"); 269 270 /* /chosen must exist for load_dtb to fill in necessary properties later */ 271 qemu_fdt_add_subnode(fdt, "/chosen"); 272 if (vms->dtb_randomness) { 273 create_randomness(ms, "/chosen"); 274 } 275 276 if (vms->secure) { 277 qemu_fdt_add_subnode(fdt, "/secure-chosen"); 278 if (vms->dtb_randomness) { 279 create_randomness(ms, "/secure-chosen"); 280 } 281 } 282 283 /* Clock node, for the benefit of the UART. The kernel device tree 284 * binding documentation claims the PL011 node clock properties are 285 * optional but in practice if you omit them the kernel refuses to 286 * probe for the device. 287 */ 288 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); 289 qemu_fdt_add_subnode(fdt, "/apb-pclk"); 290 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); 291 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); 292 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); 293 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", 294 "clk24mhz"); 295 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); 296 297 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { 298 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); 299 uint32_t *matrix = g_malloc0(size); 300 int idx, i, j; 301 302 for (i = 0; i < nb_numa_nodes; i++) { 303 for (j = 0; j < nb_numa_nodes; j++) { 304 idx = (i * nb_numa_nodes + j) * 3; 305 matrix[idx + 0] = cpu_to_be32(i); 306 matrix[idx + 1] = cpu_to_be32(j); 307 matrix[idx + 2] = 308 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); 309 } 310 } 311 312 qemu_fdt_add_subnode(fdt, "/distance-map"); 313 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", 314 "numa-distance-map-v1"); 315 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", 316 matrix, size); 317 g_free(matrix); 318 } 319 } 320 321 static void fdt_add_timer_nodes(const VirtMachineState *vms) 322 { 323 /* On real hardware these interrupts are level-triggered. 324 * On KVM they were edge-triggered before host kernel version 4.4, 325 * and level-triggered afterwards. 326 * On emulated QEMU they are level-triggered. 327 * 328 * Getting the DTB info about them wrong is awkward for some 329 * guest kernels: 330 * pre-4.8 ignore the DT and leave the interrupt configured 331 * with whatever the GIC reset value (or the bootloader) left it at 332 * 4.8 before rc6 honour the incorrect data by programming it back 333 * into the GIC, causing problems 334 * 4.8rc6 and later ignore the DT and always write "level triggered" 335 * into the GIC 336 * 337 * For backwards-compatibility, virt-2.8 and earlier will continue 338 * to say these are edge-triggered, but later machines will report 339 * the correct information. 340 */ 341 ARMCPU *armcpu; 342 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 343 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 344 MachineState *ms = MACHINE(vms); 345 346 if (vmc->claim_edge_triggered_timers) { 347 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; 348 } 349 350 if (vms->gic_version == VIRT_GIC_VERSION_2) { 351 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 352 GIC_FDT_IRQ_PPI_CPU_WIDTH, 353 (1 << MACHINE(vms)->smp.cpus) - 1); 354 } 355 356 qemu_fdt_add_subnode(ms->fdt, "/timer"); 357 358 armcpu = ARM_CPU(qemu_get_cpu(0)); 359 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 360 const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; 361 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", 362 compat, sizeof(compat)); 363 } else { 364 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", 365 "arm,armv7-timer"); 366 } 367 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); 368 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", 369 GIC_FDT_IRQ_TYPE_PPI, 370 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, 371 GIC_FDT_IRQ_TYPE_PPI, 372 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, 373 GIC_FDT_IRQ_TYPE_PPI, 374 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, 375 GIC_FDT_IRQ_TYPE_PPI, 376 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags); 377 } 378 379 static void fdt_add_cpu_nodes(const VirtMachineState *vms) 380 { 381 int cpu; 382 int addr_cells = 1; 383 const MachineState *ms = MACHINE(vms); 384 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 385 int smp_cpus = ms->smp.cpus; 386 387 /* 388 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml 389 * On ARM v8 64-bit systems value should be set to 2, 390 * that corresponds to the MPIDR_EL1 register size. 391 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs 392 * in the system, #address-cells can be set to 1, since 393 * MPIDR_EL1[63:32] bits are not used for CPUs 394 * identification. 395 * 396 * Here we actually don't know whether our system is 32- or 64-bit one. 397 * The simplest way to go is to examine affinity IDs of all our CPUs. If 398 * at least one of them has Aff3 populated, we set #address-cells to 2. 399 */ 400 for (cpu = 0; cpu < smp_cpus; cpu++) { 401 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 402 403 if (armcpu->mp_affinity & ARM_AFF3_MASK) { 404 addr_cells = 2; 405 break; 406 } 407 } 408 409 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 410 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); 411 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 412 413 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 414 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 415 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); 416 CPUState *cs = CPU(armcpu); 417 418 qemu_fdt_add_subnode(ms->fdt, nodename); 419 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 420 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 421 armcpu->dtb_compatible); 422 423 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { 424 qemu_fdt_setprop_string(ms->fdt, nodename, 425 "enable-method", "psci"); 426 } 427 428 if (addr_cells == 2) { 429 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", 430 armcpu->mp_affinity); 431 } else { 432 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", 433 armcpu->mp_affinity); 434 } 435 436 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 437 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 438 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 439 } 440 441 if (!vmc->no_cpu_topology) { 442 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 443 qemu_fdt_alloc_phandle(ms->fdt)); 444 } 445 446 g_free(nodename); 447 } 448 449 if (!vmc->no_cpu_topology) { 450 /* 451 * Add vCPU topology description through fdt node cpu-map. 452 * 453 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt 454 * In a SMP system, the hierarchy of CPUs can be defined through 455 * four entities that are used to describe the layout of CPUs in 456 * the system: socket/cluster/core/thread. 457 * 458 * A socket node represents the boundary of system physical package 459 * and its child nodes must be one or more cluster nodes. A system 460 * can contain several layers of clustering within a single physical 461 * package and cluster nodes can be contained in parent cluster nodes. 462 * 463 * Note: currently we only support one layer of clustering within 464 * each physical package. 465 */ 466 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 467 468 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { 469 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); 470 char *map_path; 471 472 if (ms->smp.threads > 1) { 473 map_path = g_strdup_printf( 474 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", 475 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), 476 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, 477 (cpu / ms->smp.threads) % ms->smp.cores, 478 cpu % ms->smp.threads); 479 } else { 480 map_path = g_strdup_printf( 481 "/cpus/cpu-map/socket%d/cluster%d/core%d", 482 cpu / (ms->smp.clusters * ms->smp.cores), 483 (cpu / ms->smp.cores) % ms->smp.clusters, 484 cpu % ms->smp.cores); 485 } 486 qemu_fdt_add_path(ms->fdt, map_path); 487 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 488 489 g_free(map_path); 490 g_free(cpu_path); 491 } 492 } 493 } 494 495 static void fdt_add_its_gic_node(VirtMachineState *vms) 496 { 497 char *nodename; 498 MachineState *ms = MACHINE(vms); 499 500 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 501 nodename = g_strdup_printf("/intc/its@%" PRIx64, 502 vms->memmap[VIRT_GIC_ITS].base); 503 qemu_fdt_add_subnode(ms->fdt, nodename); 504 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 505 "arm,gic-v3-its"); 506 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 507 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1); 508 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 509 2, vms->memmap[VIRT_GIC_ITS].base, 510 2, vms->memmap[VIRT_GIC_ITS].size); 511 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 512 g_free(nodename); 513 } 514 515 static void fdt_add_v2m_gic_node(VirtMachineState *vms) 516 { 517 MachineState *ms = MACHINE(vms); 518 char *nodename; 519 520 nodename = g_strdup_printf("/intc/v2m@%" PRIx64, 521 vms->memmap[VIRT_GIC_V2M].base); 522 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 523 qemu_fdt_add_subnode(ms->fdt, nodename); 524 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 525 "arm,gic-v2m-frame"); 526 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); 527 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 528 2, vms->memmap[VIRT_GIC_V2M].base, 529 2, vms->memmap[VIRT_GIC_V2M].size); 530 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); 531 g_free(nodename); 532 } 533 534 static void fdt_add_gic_node(VirtMachineState *vms) 535 { 536 MachineState *ms = MACHINE(vms); 537 char *nodename; 538 539 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 540 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); 541 542 nodename = g_strdup_printf("/intc@%" PRIx64, 543 vms->memmap[VIRT_GIC_DIST].base); 544 qemu_fdt_add_subnode(ms->fdt, nodename); 545 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 546 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 547 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 548 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 549 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 550 if (vms->gic_version != VIRT_GIC_VERSION_2) { 551 int nb_redist_regions = virt_gicv3_redist_region_count(vms); 552 553 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 554 "arm,gic-v3"); 555 556 qemu_fdt_setprop_cell(ms->fdt, nodename, 557 "#redistributor-regions", nb_redist_regions); 558 559 if (nb_redist_regions == 1) { 560 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 561 2, vms->memmap[VIRT_GIC_DIST].base, 562 2, vms->memmap[VIRT_GIC_DIST].size, 563 2, vms->memmap[VIRT_GIC_REDIST].base, 564 2, vms->memmap[VIRT_GIC_REDIST].size); 565 } else { 566 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 567 2, vms->memmap[VIRT_GIC_DIST].base, 568 2, vms->memmap[VIRT_GIC_DIST].size, 569 2, vms->memmap[VIRT_GIC_REDIST].base, 570 2, vms->memmap[VIRT_GIC_REDIST].size, 571 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, 572 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); 573 } 574 575 if (vms->virt) { 576 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 577 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 578 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 579 } 580 } else { 581 /* 'cortex-a15-gic' means 'GIC v2' */ 582 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 583 "arm,cortex-a15-gic"); 584 if (!vms->virt) { 585 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 586 2, vms->memmap[VIRT_GIC_DIST].base, 587 2, vms->memmap[VIRT_GIC_DIST].size, 588 2, vms->memmap[VIRT_GIC_CPU].base, 589 2, vms->memmap[VIRT_GIC_CPU].size); 590 } else { 591 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 592 2, vms->memmap[VIRT_GIC_DIST].base, 593 2, vms->memmap[VIRT_GIC_DIST].size, 594 2, vms->memmap[VIRT_GIC_CPU].base, 595 2, vms->memmap[VIRT_GIC_CPU].size, 596 2, vms->memmap[VIRT_GIC_HYP].base, 597 2, vms->memmap[VIRT_GIC_HYP].size, 598 2, vms->memmap[VIRT_GIC_VCPU].base, 599 2, vms->memmap[VIRT_GIC_VCPU].size); 600 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 601 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, 602 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 603 } 604 } 605 606 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); 607 g_free(nodename); 608 } 609 610 static void fdt_add_pmu_nodes(const VirtMachineState *vms) 611 { 612 ARMCPU *armcpu = ARM_CPU(first_cpu); 613 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 614 MachineState *ms = MACHINE(vms); 615 616 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { 617 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); 618 return; 619 } 620 621 if (vms->gic_version == VIRT_GIC_VERSION_2) { 622 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, 623 GIC_FDT_IRQ_PPI_CPU_WIDTH, 624 (1 << MACHINE(vms)->smp.cpus) - 1); 625 } 626 627 qemu_fdt_add_subnode(ms->fdt, "/pmu"); 628 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { 629 const char compat[] = "arm,armv8-pmuv3"; 630 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", 631 compat, sizeof(compat)); 632 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", 633 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); 634 } 635 } 636 637 static inline DeviceState *create_acpi_ged(VirtMachineState *vms) 638 { 639 DeviceState *dev; 640 MachineState *ms = MACHINE(vms); 641 int irq = vms->irqmap[VIRT_ACPI_GED]; 642 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 643 644 if (ms->ram_slots) { 645 event |= ACPI_GED_MEM_HOTPLUG_EVT; 646 } 647 648 if (ms->nvdimms_state->is_enabled) { 649 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; 650 } 651 652 dev = qdev_new(TYPE_ACPI_GED); 653 qdev_prop_set_uint32(dev, "ged-event", event); 654 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 655 656 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); 657 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); 658 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); 659 660 return dev; 661 } 662 663 static void create_its(VirtMachineState *vms) 664 { 665 const char *itsclass = its_class_name(); 666 DeviceState *dev; 667 668 if (!strcmp(itsclass, "arm-gicv3-its")) { 669 if (!vms->tcg_its) { 670 itsclass = NULL; 671 } 672 } 673 674 if (!itsclass) { 675 /* Do nothing if not supported */ 676 return; 677 } 678 679 dev = qdev_new(itsclass); 680 681 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), 682 &error_abort); 683 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 684 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); 685 686 fdt_add_its_gic_node(vms); 687 vms->msi_controller = VIRT_MSI_CTRL_ITS; 688 } 689 690 static void create_v2m(VirtMachineState *vms) 691 { 692 int i; 693 int irq = vms->irqmap[VIRT_GIC_V2M]; 694 DeviceState *dev; 695 696 dev = qdev_new("arm-gicv2m"); 697 qdev_prop_set_uint32(dev, "base-spi", irq); 698 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); 699 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 700 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); 701 702 for (i = 0; i < NUM_GICV2M_SPIS; i++) { 703 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 704 qdev_get_gpio_in(vms->gic, irq + i)); 705 } 706 707 fdt_add_v2m_gic_node(vms); 708 vms->msi_controller = VIRT_MSI_CTRL_GICV2M; 709 } 710 711 static void create_gic(VirtMachineState *vms, MemoryRegion *mem) 712 { 713 MachineState *ms = MACHINE(vms); 714 /* We create a standalone GIC */ 715 SysBusDevice *gicbusdev; 716 const char *gictype; 717 int i; 718 unsigned int smp_cpus = ms->smp.cpus; 719 uint32_t nb_redist_regions = 0; 720 int revision; 721 722 if (vms->gic_version == VIRT_GIC_VERSION_2) { 723 gictype = gic_class_name(); 724 } else { 725 gictype = gicv3_class_name(); 726 } 727 728 switch (vms->gic_version) { 729 case VIRT_GIC_VERSION_2: 730 revision = 2; 731 break; 732 case VIRT_GIC_VERSION_3: 733 revision = 3; 734 break; 735 case VIRT_GIC_VERSION_4: 736 revision = 4; 737 break; 738 default: 739 g_assert_not_reached(); 740 } 741 vms->gic = qdev_new(gictype); 742 qdev_prop_set_uint32(vms->gic, "revision", revision); 743 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); 744 /* Note that the num-irq property counts both internal and external 745 * interrupts; there are always 32 of the former (mandated by GIC spec). 746 */ 747 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); 748 if (!kvm_irqchip_in_kernel()) { 749 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); 750 } 751 752 if (vms->gic_version != VIRT_GIC_VERSION_2) { 753 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); 754 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); 755 756 nb_redist_regions = virt_gicv3_redist_region_count(vms); 757 758 qdev_prop_set_uint32(vms->gic, "len-redist-region-count", 759 nb_redist_regions); 760 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count); 761 762 if (!kvm_irqchip_in_kernel()) { 763 if (vms->tcg_its) { 764 object_property_set_link(OBJECT(vms->gic), "sysmem", 765 OBJECT(mem), &error_fatal); 766 qdev_prop_set_bit(vms->gic, "has-lpi", true); 767 } 768 } 769 770 if (nb_redist_regions == 2) { 771 uint32_t redist1_capacity = 772 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 773 774 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", 775 MIN(smp_cpus - redist0_count, redist1_capacity)); 776 } 777 } else { 778 if (!kvm_irqchip_in_kernel()) { 779 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", 780 vms->virt); 781 } 782 } 783 gicbusdev = SYS_BUS_DEVICE(vms->gic); 784 sysbus_realize_and_unref(gicbusdev, &error_fatal); 785 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); 786 if (vms->gic_version != VIRT_GIC_VERSION_2) { 787 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); 788 if (nb_redist_regions == 2) { 789 sysbus_mmio_map(gicbusdev, 2, 790 vms->memmap[VIRT_HIGH_GIC_REDIST2].base); 791 } 792 } else { 793 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); 794 if (vms->virt) { 795 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); 796 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); 797 } 798 } 799 800 /* Wire the outputs from each CPU's generic timer and the GICv3 801 * maintenance interrupt signal to the appropriate GIC PPI inputs, 802 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 803 */ 804 for (i = 0; i < smp_cpus; i++) { 805 DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); 806 int intidbase = NUM_IRQS + i * GIC_INTERNAL; 807 /* Mapping from the output timer irq lines from the CPU to the 808 * GIC PPI inputs we use for the virt board. 809 */ 810 const int timer_irq[] = { 811 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, 812 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, 813 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, 814 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, 815 }; 816 817 for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 818 qdev_connect_gpio_out(cpudev, irq, 819 qdev_get_gpio_in(vms->gic, 820 intidbase + timer_irq[irq])); 821 } 822 823 if (vms->gic_version != VIRT_GIC_VERSION_2) { 824 qemu_irq irq = qdev_get_gpio_in(vms->gic, 825 intidbase + ARCH_GIC_MAINT_IRQ); 826 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 827 0, irq); 828 } else if (vms->virt) { 829 qemu_irq irq = qdev_get_gpio_in(vms->gic, 830 intidbase + ARCH_GIC_MAINT_IRQ); 831 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); 832 } 833 834 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, 835 qdev_get_gpio_in(vms->gic, intidbase 836 + VIRTUAL_PMU_IRQ)); 837 838 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 839 sysbus_connect_irq(gicbusdev, i + smp_cpus, 840 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 841 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, 842 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 843 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, 844 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 845 } 846 847 fdt_add_gic_node(vms); 848 849 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { 850 create_its(vms); 851 } else if (vms->gic_version == VIRT_GIC_VERSION_2) { 852 create_v2m(vms); 853 } 854 } 855 856 static void create_uart(const VirtMachineState *vms, int uart, 857 MemoryRegion *mem, Chardev *chr) 858 { 859 char *nodename; 860 hwaddr base = vms->memmap[uart].base; 861 hwaddr size = vms->memmap[uart].size; 862 int irq = vms->irqmap[uart]; 863 const char compat[] = "arm,pl011\0arm,primecell"; 864 const char clocknames[] = "uartclk\0apb_pclk"; 865 DeviceState *dev = qdev_new(TYPE_PL011); 866 SysBusDevice *s = SYS_BUS_DEVICE(dev); 867 MachineState *ms = MACHINE(vms); 868 869 qdev_prop_set_chr(dev, "chardev", chr); 870 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 871 memory_region_add_subregion(mem, base, 872 sysbus_mmio_get_region(s, 0)); 873 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 874 875 nodename = g_strdup_printf("/pl011@%" PRIx64, base); 876 qemu_fdt_add_subnode(ms->fdt, nodename); 877 /* Note that we can't use setprop_string because of the embedded NUL */ 878 qemu_fdt_setprop(ms->fdt, nodename, "compatible", 879 compat, sizeof(compat)); 880 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 881 2, base, 2, size); 882 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 883 GIC_FDT_IRQ_TYPE_SPI, irq, 884 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 885 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", 886 vms->clock_phandle, vms->clock_phandle); 887 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", 888 clocknames, sizeof(clocknames)); 889 890 if (uart == VIRT_UART) { 891 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 892 } else { 893 /* Mark as not usable by the normal world */ 894 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 895 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 896 897 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", 898 nodename); 899 } 900 901 g_free(nodename); 902 } 903 904 static void create_rtc(const VirtMachineState *vms) 905 { 906 char *nodename; 907 hwaddr base = vms->memmap[VIRT_RTC].base; 908 hwaddr size = vms->memmap[VIRT_RTC].size; 909 int irq = vms->irqmap[VIRT_RTC]; 910 const char compat[] = "arm,pl031\0arm,primecell"; 911 MachineState *ms = MACHINE(vms); 912 913 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); 914 915 nodename = g_strdup_printf("/pl031@%" PRIx64, base); 916 qemu_fdt_add_subnode(ms->fdt, nodename); 917 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 918 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 919 2, base, 2, size); 920 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 921 GIC_FDT_IRQ_TYPE_SPI, irq, 922 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 923 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 924 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 925 g_free(nodename); 926 } 927 928 static DeviceState *gpio_key_dev; 929 static void virt_powerdown_req(Notifier *n, void *opaque) 930 { 931 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); 932 933 if (s->acpi_dev) { 934 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); 935 } else { 936 /* use gpio Pin 3 for power button event */ 937 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); 938 } 939 } 940 941 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, 942 uint32_t phandle) 943 { 944 gpio_key_dev = sysbus_create_simple("gpio-key", -1, 945 qdev_get_gpio_in(pl061_dev, 3)); 946 947 qemu_fdt_add_subnode(fdt, "/gpio-keys"); 948 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); 949 950 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); 951 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", 952 "label", "GPIO Key Poweroff"); 953 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", 954 KEY_POWER); 955 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", 956 "gpios", phandle, 3, 0); 957 } 958 959 #define SECURE_GPIO_POWEROFF 0 960 #define SECURE_GPIO_RESET 1 961 962 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, 963 uint32_t phandle) 964 { 965 DeviceState *gpio_pwr_dev; 966 967 /* gpio-pwr */ 968 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); 969 970 /* connect secure pl061 to gpio-pwr */ 971 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, 972 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); 973 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, 974 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); 975 976 qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); 977 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", 978 "gpio-poweroff"); 979 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", 980 "gpios", phandle, SECURE_GPIO_POWEROFF, 0); 981 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); 982 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", 983 "okay"); 984 985 qemu_fdt_add_subnode(fdt, "/gpio-restart"); 986 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", 987 "gpio-restart"); 988 qemu_fdt_setprop_cells(fdt, "/gpio-restart", 989 "gpios", phandle, SECURE_GPIO_RESET, 0); 990 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); 991 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", 992 "okay"); 993 } 994 995 static void create_gpio_devices(const VirtMachineState *vms, int gpio, 996 MemoryRegion *mem) 997 { 998 char *nodename; 999 DeviceState *pl061_dev; 1000 hwaddr base = vms->memmap[gpio].base; 1001 hwaddr size = vms->memmap[gpio].size; 1002 int irq = vms->irqmap[gpio]; 1003 const char compat[] = "arm,pl061\0arm,primecell"; 1004 SysBusDevice *s; 1005 MachineState *ms = MACHINE(vms); 1006 1007 pl061_dev = qdev_new("pl061"); 1008 /* Pull lines down to 0 if not driven by the PL061 */ 1009 qdev_prop_set_uint32(pl061_dev, "pullups", 0); 1010 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); 1011 s = SYS_BUS_DEVICE(pl061_dev); 1012 sysbus_realize_and_unref(s, &error_fatal); 1013 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); 1014 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); 1015 1016 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); 1017 nodename = g_strdup_printf("/pl061@%" PRIx64, base); 1018 qemu_fdt_add_subnode(ms->fdt, nodename); 1019 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1020 2, base, 2, size); 1021 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); 1022 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); 1023 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); 1024 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1025 GIC_FDT_IRQ_TYPE_SPI, irq, 1026 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 1027 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); 1028 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); 1029 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); 1030 1031 if (gpio != VIRT_GPIO) { 1032 /* Mark as not usable by the normal world */ 1033 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1034 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1035 } 1036 g_free(nodename); 1037 1038 /* Child gpio devices */ 1039 if (gpio == VIRT_GPIO) { 1040 create_gpio_keys(ms->fdt, pl061_dev, phandle); 1041 } else { 1042 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); 1043 } 1044 } 1045 1046 static void create_virtio_devices(const VirtMachineState *vms) 1047 { 1048 int i; 1049 hwaddr size = vms->memmap[VIRT_MMIO].size; 1050 MachineState *ms = MACHINE(vms); 1051 1052 /* We create the transports in forwards order. Since qbus_realize() 1053 * prepends (not appends) new child buses, the incrementing loop below will 1054 * create a list of virtio-mmio buses with decreasing base addresses. 1055 * 1056 * When a -device option is processed from the command line, 1057 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 1058 * order. The upshot is that -device options in increasing command line 1059 * order are mapped to virtio-mmio buses with decreasing base addresses. 1060 * 1061 * When this code was originally written, that arrangement ensured that the 1062 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to 1063 * the first -device on the command line. (The end-to-end order is a 1064 * function of this loop, qbus_realize(), qbus_find_recursive(), and the 1065 * guest kernel's name-to-address assignment strategy.) 1066 * 1067 * Meanwhile, the kernel's traversal seems to have been reversed; see eg. 1068 * the message, if not necessarily the code, of commit 70161ff336. 1069 * Therefore the loop now establishes the inverse of the original intent. 1070 * 1071 * Unfortunately, we can't counteract the kernel change by reversing the 1072 * loop; it would break existing command lines. 1073 * 1074 * In any case, the kernel makes no guarantee about the stability of 1075 * enumeration order of virtio devices (as demonstrated by it changing 1076 * between kernel versions). For reliable and stable identification 1077 * of disks users must use UUIDs or similar mechanisms. 1078 */ 1079 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { 1080 int irq = vms->irqmap[VIRT_MMIO] + i; 1081 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1082 1083 sysbus_create_simple("virtio-mmio", base, 1084 qdev_get_gpio_in(vms->gic, irq)); 1085 } 1086 1087 /* We add dtb nodes in reverse order so that they appear in the finished 1088 * device tree lowest address first. 1089 * 1090 * Note that this mapping is independent of the loop above. The previous 1091 * loop influences virtio device to virtio transport assignment, whereas 1092 * this loop controls how virtio transports are laid out in the dtb. 1093 */ 1094 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { 1095 char *nodename; 1096 int irq = vms->irqmap[VIRT_MMIO] + i; 1097 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; 1098 1099 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 1100 qemu_fdt_add_subnode(ms->fdt, nodename); 1101 qemu_fdt_setprop_string(ms->fdt, nodename, 1102 "compatible", "virtio,mmio"); 1103 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1104 2, base, 2, size); 1105 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 1106 GIC_FDT_IRQ_TYPE_SPI, irq, 1107 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1108 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1109 g_free(nodename); 1110 } 1111 } 1112 1113 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 1114 1115 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, 1116 const char *name, 1117 const char *alias_prop_name) 1118 { 1119 /* 1120 * Create a single flash device. We use the same parameters as 1121 * the flash devices on the Versatile Express board. 1122 */ 1123 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 1124 1125 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 1126 qdev_prop_set_uint8(dev, "width", 4); 1127 qdev_prop_set_uint8(dev, "device-width", 2); 1128 qdev_prop_set_bit(dev, "big-endian", false); 1129 qdev_prop_set_uint16(dev, "id0", 0x89); 1130 qdev_prop_set_uint16(dev, "id1", 0x18); 1131 qdev_prop_set_uint16(dev, "id2", 0x00); 1132 qdev_prop_set_uint16(dev, "id3", 0x00); 1133 qdev_prop_set_string(dev, "name", name); 1134 object_property_add_child(OBJECT(vms), name, OBJECT(dev)); 1135 object_property_add_alias(OBJECT(vms), alias_prop_name, 1136 OBJECT(dev), "drive"); 1137 return PFLASH_CFI01(dev); 1138 } 1139 1140 static void virt_flash_create(VirtMachineState *vms) 1141 { 1142 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); 1143 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); 1144 } 1145 1146 static void virt_flash_map1(PFlashCFI01 *flash, 1147 hwaddr base, hwaddr size, 1148 MemoryRegion *sysmem) 1149 { 1150 DeviceState *dev = DEVICE(flash); 1151 1152 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 1153 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 1154 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 1155 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1156 1157 memory_region_add_subregion(sysmem, base, 1158 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1159 0)); 1160 } 1161 1162 static void virt_flash_map(VirtMachineState *vms, 1163 MemoryRegion *sysmem, 1164 MemoryRegion *secure_sysmem) 1165 { 1166 /* 1167 * Map two flash devices to fill the VIRT_FLASH space in the memmap. 1168 * sysmem is the system memory space. secure_sysmem is the secure view 1169 * of the system, and the first flash device should be made visible only 1170 * there. The second flash device is visible to both secure and nonsecure. 1171 * If sysmem == secure_sysmem this means there is no separate Secure 1172 * address space and both flash devices are generally visible. 1173 */ 1174 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1175 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1176 1177 virt_flash_map1(vms->flash[0], flashbase, flashsize, 1178 secure_sysmem); 1179 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, 1180 sysmem); 1181 } 1182 1183 static void virt_flash_fdt(VirtMachineState *vms, 1184 MemoryRegion *sysmem, 1185 MemoryRegion *secure_sysmem) 1186 { 1187 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; 1188 hwaddr flashbase = vms->memmap[VIRT_FLASH].base; 1189 MachineState *ms = MACHINE(vms); 1190 char *nodename; 1191 1192 if (sysmem == secure_sysmem) { 1193 /* Report both flash devices as a single node in the DT */ 1194 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); 1195 qemu_fdt_add_subnode(ms->fdt, nodename); 1196 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1197 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1198 2, flashbase, 2, flashsize, 1199 2, flashbase + flashsize, 2, flashsize); 1200 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1201 g_free(nodename); 1202 } else { 1203 /* 1204 * Report the devices as separate nodes so we can mark one as 1205 * only visible to the secure world. 1206 */ 1207 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); 1208 qemu_fdt_add_subnode(ms->fdt, nodename); 1209 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1210 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1211 2, flashbase, 2, flashsize); 1212 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1213 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1214 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1215 g_free(nodename); 1216 1217 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize); 1218 qemu_fdt_add_subnode(ms->fdt, nodename); 1219 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 1220 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1221 2, flashbase + flashsize, 2, flashsize); 1222 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 1223 g_free(nodename); 1224 } 1225 } 1226 1227 static bool virt_firmware_init(VirtMachineState *vms, 1228 MemoryRegion *sysmem, 1229 MemoryRegion *secure_sysmem) 1230 { 1231 int i; 1232 const char *bios_name; 1233 BlockBackend *pflash_blk0; 1234 1235 /* Map legacy -drive if=pflash to machine properties */ 1236 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { 1237 pflash_cfi01_legacy_drive(vms->flash[i], 1238 drive_get(IF_PFLASH, 0, i)); 1239 } 1240 1241 virt_flash_map(vms, sysmem, secure_sysmem); 1242 1243 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); 1244 1245 bios_name = MACHINE(vms)->firmware; 1246 if (bios_name) { 1247 char *fname; 1248 MemoryRegion *mr; 1249 int image_size; 1250 1251 if (pflash_blk0) { 1252 error_report("The contents of the first flash device may be " 1253 "specified with -bios or with -drive if=pflash... " 1254 "but you cannot use both options at once"); 1255 exit(1); 1256 } 1257 1258 /* Fall back to -bios */ 1259 1260 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1261 if (!fname) { 1262 error_report("Could not find ROM image '%s'", bios_name); 1263 exit(1); 1264 } 1265 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); 1266 image_size = load_image_mr(fname, mr); 1267 g_free(fname); 1268 if (image_size < 0) { 1269 error_report("Could not load ROM image '%s'", bios_name); 1270 exit(1); 1271 } 1272 } 1273 1274 return pflash_blk0 || bios_name; 1275 } 1276 1277 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) 1278 { 1279 MachineState *ms = MACHINE(vms); 1280 hwaddr base = vms->memmap[VIRT_FW_CFG].base; 1281 hwaddr size = vms->memmap[VIRT_FW_CFG].size; 1282 FWCfgState *fw_cfg; 1283 char *nodename; 1284 1285 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); 1286 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); 1287 1288 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1289 qemu_fdt_add_subnode(ms->fdt, nodename); 1290 qemu_fdt_setprop_string(ms->fdt, nodename, 1291 "compatible", "qemu,fw-cfg-mmio"); 1292 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1293 2, base, 2, size); 1294 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1295 g_free(nodename); 1296 return fw_cfg; 1297 } 1298 1299 static void create_pcie_irq_map(const MachineState *ms, 1300 uint32_t gic_phandle, 1301 int first_irq, const char *nodename) 1302 { 1303 int devfn, pin; 1304 uint32_t full_irq_map[4 * 4 * 10] = { 0 }; 1305 uint32_t *irq_map = full_irq_map; 1306 1307 for (devfn = 0; devfn <= 0x18; devfn += 0x8) { 1308 for (pin = 0; pin < 4; pin++) { 1309 int irq_type = GIC_FDT_IRQ_TYPE_SPI; 1310 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); 1311 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 1312 int i; 1313 1314 uint32_t map[] = { 1315 devfn << 8, 0, 0, /* devfn */ 1316 pin + 1, /* PCI pin */ 1317 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ 1318 1319 /* Convert map to big endian */ 1320 for (i = 0; i < 10; i++) { 1321 irq_map[i] = cpu_to_be32(map[i]); 1322 } 1323 irq_map += 10; 1324 } 1325 } 1326 1327 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", 1328 full_irq_map, sizeof(full_irq_map)); 1329 1330 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 1331 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ 1332 0, 0, 1333 0x7 /* PCI irq */); 1334 } 1335 1336 static void create_smmu(const VirtMachineState *vms, 1337 PCIBus *bus) 1338 { 1339 char *node; 1340 const char compat[] = "arm,smmu-v3"; 1341 int irq = vms->irqmap[VIRT_SMMU]; 1342 int i; 1343 hwaddr base = vms->memmap[VIRT_SMMU].base; 1344 hwaddr size = vms->memmap[VIRT_SMMU].size; 1345 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; 1346 DeviceState *dev; 1347 MachineState *ms = MACHINE(vms); 1348 1349 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { 1350 return; 1351 } 1352 1353 dev = qdev_new(TYPE_ARM_SMMUV3); 1354 1355 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), 1356 &error_abort); 1357 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1358 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); 1359 for (i = 0; i < NUM_SMMU_IRQS; i++) { 1360 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1361 qdev_get_gpio_in(vms->gic, irq + i)); 1362 } 1363 1364 node = g_strdup_printf("/smmuv3@%" PRIx64, base); 1365 qemu_fdt_add_subnode(ms->fdt, node); 1366 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1367 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); 1368 1369 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", 1370 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1371 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1372 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, 1373 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 1374 1375 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, 1376 sizeof(irq_names)); 1377 1378 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); 1379 1380 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1381 1382 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1383 g_free(node); 1384 } 1385 1386 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) 1387 { 1388 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; 1389 uint16_t bdf = vms->virtio_iommu_bdf; 1390 MachineState *ms = MACHINE(vms); 1391 char *node; 1392 1393 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1394 1395 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename, 1396 PCI_SLOT(bdf), PCI_FUNC(bdf)); 1397 qemu_fdt_add_subnode(ms->fdt, node); 1398 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); 1399 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 1400 1, bdf << 8, 1, 0, 1, 0, 1401 1, 0, 1, 0); 1402 1403 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); 1404 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); 1405 g_free(node); 1406 1407 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", 1408 0x0, vms->iommu_phandle, 0x0, bdf, 1409 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); 1410 } 1411 1412 static void create_pcie(VirtMachineState *vms) 1413 { 1414 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; 1415 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; 1416 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; 1417 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; 1418 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; 1419 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; 1420 hwaddr base_ecam, size_ecam; 1421 hwaddr base = base_mmio; 1422 int nr_pcie_buses; 1423 int irq = vms->irqmap[VIRT_PCIE]; 1424 MemoryRegion *mmio_alias; 1425 MemoryRegion *mmio_reg; 1426 MemoryRegion *ecam_alias; 1427 MemoryRegion *ecam_reg; 1428 DeviceState *dev; 1429 char *nodename; 1430 int i, ecam_id; 1431 PCIHostState *pci; 1432 MachineState *ms = MACHINE(vms); 1433 MachineClass *mc = MACHINE_GET_CLASS(ms); 1434 1435 dev = qdev_new(TYPE_GPEX_HOST); 1436 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1437 1438 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); 1439 base_ecam = vms->memmap[ecam_id].base; 1440 size_ecam = vms->memmap[ecam_id].size; 1441 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; 1442 /* Map only the first size_ecam bytes of ECAM space */ 1443 ecam_alias = g_new0(MemoryRegion, 1); 1444 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1445 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1446 ecam_reg, 0, size_ecam); 1447 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 1448 1449 /* Map the MMIO window into system address space so as to expose 1450 * the section of PCI MMIO space which starts at the same base address 1451 * (ie 1:1 mapping for that part of PCI MMIO space visible through 1452 * the window). 1453 */ 1454 mmio_alias = g_new0(MemoryRegion, 1); 1455 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1456 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1457 mmio_reg, base_mmio, size_mmio); 1458 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 1459 1460 if (vms->highmem_mmio) { 1461 /* Map high MMIO space */ 1462 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); 1463 1464 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1465 mmio_reg, base_mmio_high, size_mmio_high); 1466 memory_region_add_subregion(get_system_memory(), base_mmio_high, 1467 high_mmio_alias); 1468 } 1469 1470 /* Map IO port space */ 1471 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); 1472 1473 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1474 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, 1475 qdev_get_gpio_in(vms->gic, irq + i)); 1476 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); 1477 } 1478 1479 pci = PCI_HOST_BRIDGE(dev); 1480 pci->bypass_iommu = vms->default_bus_bypass_iommu; 1481 vms->bus = pci->bus; 1482 if (vms->bus) { 1483 for (i = 0; i < nb_nics; i++) { 1484 pci_nic_init_nofail(&nd_table[i], pci->bus, mc->default_nic, NULL); 1485 } 1486 } 1487 1488 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); 1489 qemu_fdt_add_subnode(ms->fdt, nodename); 1490 qemu_fdt_setprop_string(ms->fdt, nodename, 1491 "compatible", "pci-host-ecam-generic"); 1492 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 1493 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 1494 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 1495 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 1496 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 1497 nr_pcie_buses - 1); 1498 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 1499 1500 if (vms->msi_phandle) { 1501 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 1502 0, vms->msi_phandle, 0, 0x10000); 1503 } 1504 1505 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 1506 2, base_ecam, 2, size_ecam); 1507 1508 if (vms->highmem_mmio) { 1509 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1510 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1511 2, base_pio, 2, size_pio, 1512 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1513 2, base_mmio, 2, size_mmio, 1514 1, FDT_PCI_RANGE_MMIO_64BIT, 1515 2, base_mmio_high, 1516 2, base_mmio_high, 2, size_mmio_high); 1517 } else { 1518 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 1519 1, FDT_PCI_RANGE_IOPORT, 2, 0, 1520 2, base_pio, 2, size_pio, 1521 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 1522 2, base_mmio, 2, size_mmio); 1523 } 1524 1525 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 1526 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); 1527 1528 if (vms->iommu) { 1529 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); 1530 1531 switch (vms->iommu) { 1532 case VIRT_IOMMU_SMMUV3: 1533 create_smmu(vms, vms->bus); 1534 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 1535 0x0, vms->iommu_phandle, 0x0, 0x10000); 1536 break; 1537 default: 1538 g_assert_not_reached(); 1539 } 1540 } 1541 } 1542 1543 static void create_platform_bus(VirtMachineState *vms) 1544 { 1545 DeviceState *dev; 1546 SysBusDevice *s; 1547 int i; 1548 MemoryRegion *sysmem = get_system_memory(); 1549 1550 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1551 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1552 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); 1553 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); 1554 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1555 vms->platform_bus_dev = dev; 1556 1557 s = SYS_BUS_DEVICE(dev); 1558 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { 1559 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; 1560 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); 1561 } 1562 1563 memory_region_add_subregion(sysmem, 1564 vms->memmap[VIRT_PLATFORM_BUS].base, 1565 sysbus_mmio_get_region(s, 0)); 1566 } 1567 1568 static void create_tag_ram(MemoryRegion *tag_sysmem, 1569 hwaddr base, hwaddr size, 1570 const char *name) 1571 { 1572 MemoryRegion *tagram = g_new(MemoryRegion, 1); 1573 1574 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); 1575 memory_region_add_subregion(tag_sysmem, base / 32, tagram); 1576 } 1577 1578 static void create_secure_ram(VirtMachineState *vms, 1579 MemoryRegion *secure_sysmem, 1580 MemoryRegion *secure_tag_sysmem) 1581 { 1582 MemoryRegion *secram = g_new(MemoryRegion, 1); 1583 char *nodename; 1584 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; 1585 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; 1586 MachineState *ms = MACHINE(vms); 1587 1588 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, 1589 &error_fatal); 1590 memory_region_add_subregion(secure_sysmem, base, secram); 1591 1592 nodename = g_strdup_printf("/secram@%" PRIx64, base); 1593 qemu_fdt_add_subnode(ms->fdt, nodename); 1594 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 1595 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 1596 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); 1597 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); 1598 1599 if (secure_tag_sysmem) { 1600 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); 1601 } 1602 1603 g_free(nodename); 1604 } 1605 1606 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) 1607 { 1608 const VirtMachineState *board = container_of(binfo, VirtMachineState, 1609 bootinfo); 1610 MachineState *ms = MACHINE(board); 1611 1612 1613 *fdt_size = board->fdt_size; 1614 return ms->fdt; 1615 } 1616 1617 static void virt_build_smbios(VirtMachineState *vms) 1618 { 1619 MachineClass *mc = MACHINE_GET_CLASS(vms); 1620 MachineState *ms = MACHINE(vms); 1621 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1622 uint8_t *smbios_tables, *smbios_anchor; 1623 size_t smbios_tables_len, smbios_anchor_len; 1624 struct smbios_phys_mem_area mem_array; 1625 const char *product = "QEMU Virtual Machine"; 1626 1627 if (kvm_enabled()) { 1628 product = "KVM Virtual Machine"; 1629 } 1630 1631 smbios_set_defaults("QEMU", product, 1632 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, 1633 true, SMBIOS_ENTRY_POINT_TYPE_64); 1634 1635 /* build the array of physical mem area from base_memmap */ 1636 mem_array.address = vms->memmap[VIRT_MEM].base; 1637 mem_array.length = ms->ram_size; 1638 1639 smbios_get_tables(ms, &mem_array, 1, 1640 &smbios_tables, &smbios_tables_len, 1641 &smbios_anchor, &smbios_anchor_len, 1642 &error_fatal); 1643 1644 if (smbios_anchor) { 1645 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", 1646 smbios_tables, smbios_tables_len); 1647 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", 1648 smbios_anchor, smbios_anchor_len); 1649 } 1650 } 1651 1652 static 1653 void virt_machine_done(Notifier *notifier, void *data) 1654 { 1655 VirtMachineState *vms = container_of(notifier, VirtMachineState, 1656 machine_done); 1657 MachineState *ms = MACHINE(vms); 1658 ARMCPU *cpu = ARM_CPU(first_cpu); 1659 struct arm_boot_info *info = &vms->bootinfo; 1660 AddressSpace *as = arm_boot_address_space(cpu, info); 1661 1662 /* 1663 * If the user provided a dtb, we assume the dynamic sysbus nodes 1664 * already are integrated there. This corresponds to a use case where 1665 * the dynamic sysbus nodes are complex and their generation is not yet 1666 * supported. In that case the user can take charge of the guest dt 1667 * while qemu takes charge of the qom stuff. 1668 */ 1669 if (info->dtb_filename == NULL) { 1670 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", 1671 vms->memmap[VIRT_PLATFORM_BUS].base, 1672 vms->memmap[VIRT_PLATFORM_BUS].size, 1673 vms->irqmap[VIRT_PLATFORM_BUS]); 1674 } 1675 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { 1676 exit(1); 1677 } 1678 1679 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg); 1680 1681 virt_acpi_setup(vms); 1682 virt_build_smbios(vms); 1683 } 1684 1685 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) 1686 { 1687 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; 1688 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 1689 1690 if (!vmc->disallow_affinity_adjustment) { 1691 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the 1692 * GIC's target-list limitations. 32-bit KVM hosts currently 1693 * always create clusters of 4 CPUs, but that is expected to 1694 * change when they gain support for gicv3. When KVM is enabled 1695 * it will override the changes we make here, therefore our 1696 * purposes are to make TCG consistent (with 64-bit KVM hosts) 1697 * and to improve SGI efficiency. 1698 */ 1699 if (vms->gic_version == VIRT_GIC_VERSION_2) { 1700 clustersz = GIC_TARGETLIST_BITS; 1701 } else { 1702 clustersz = GICV3_TARGETLIST_BITS; 1703 } 1704 } 1705 return arm_cpu_mp_affinity(idx, clustersz); 1706 } 1707 1708 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, 1709 int index) 1710 { 1711 bool *enabled_array[] = { 1712 &vms->highmem_redists, 1713 &vms->highmem_ecam, 1714 &vms->highmem_mmio, 1715 }; 1716 1717 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST == 1718 ARRAY_SIZE(enabled_array)); 1719 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array)); 1720 1721 return enabled_array[index - VIRT_LOWMEMMAP_LAST]; 1722 } 1723 1724 static void virt_set_high_memmap(VirtMachineState *vms, 1725 hwaddr base, int pa_bits) 1726 { 1727 hwaddr region_base, region_size; 1728 bool *region_enabled, fits; 1729 int i; 1730 1731 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { 1732 region_enabled = virt_get_high_memmap_enabled(vms, i); 1733 region_base = ROUND_UP(base, extended_memmap[i].size); 1734 region_size = extended_memmap[i].size; 1735 1736 vms->memmap[i].base = region_base; 1737 vms->memmap[i].size = region_size; 1738 1739 /* 1740 * Check each device to see if it fits in the PA space, 1741 * moving highest_gpa as we go. For compatibility, move 1742 * highest_gpa for disabled fitting devices as well, if 1743 * the compact layout has been disabled. 1744 * 1745 * For each device that doesn't fit, disable it. 1746 */ 1747 fits = (region_base + region_size) <= BIT_ULL(pa_bits); 1748 *region_enabled &= fits; 1749 if (vms->highmem_compact && !*region_enabled) { 1750 continue; 1751 } 1752 1753 base = region_base + region_size; 1754 if (fits) { 1755 vms->highest_gpa = base - 1; 1756 } 1757 } 1758 } 1759 1760 static void virt_set_memmap(VirtMachineState *vms, int pa_bits) 1761 { 1762 MachineState *ms = MACHINE(vms); 1763 hwaddr base, device_memory_base, device_memory_size, memtop; 1764 int i; 1765 1766 vms->memmap = extended_memmap; 1767 1768 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { 1769 vms->memmap[i] = base_memmap[i]; 1770 } 1771 1772 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { 1773 error_report("unsupported number of memory slots: %"PRIu64, 1774 ms->ram_slots); 1775 exit(EXIT_FAILURE); 1776 } 1777 1778 /* 1779 * !highmem is exactly the same as limiting the PA space to 32bit, 1780 * irrespective of the underlying capabilities of the HW. 1781 */ 1782 if (!vms->highmem) { 1783 pa_bits = 32; 1784 } 1785 1786 /* 1787 * We compute the base of the high IO region depending on the 1788 * amount of initial and device memory. The device memory start/size 1789 * is aligned on 1GiB. We never put the high IO region below 256GiB 1790 * so that if maxram_size is < 255GiB we keep the legacy memory map. 1791 * The device region size assumes 1GiB page max alignment per slot. 1792 */ 1793 device_memory_base = 1794 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); 1795 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; 1796 1797 /* Base address of the high IO region */ 1798 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); 1799 if (memtop > BIT_ULL(pa_bits)) { 1800 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n", 1801 pa_bits, memtop - BIT_ULL(pa_bits)); 1802 exit(EXIT_FAILURE); 1803 } 1804 if (base < device_memory_base) { 1805 error_report("maxmem/slots too huge"); 1806 exit(EXIT_FAILURE); 1807 } 1808 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { 1809 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; 1810 } 1811 1812 /* We know for sure that at least the memory fits in the PA space */ 1813 vms->highest_gpa = memtop - 1; 1814 1815 virt_set_high_memmap(vms, base, pa_bits); 1816 1817 if (device_memory_size > 0) { 1818 machine_memory_devices_init(ms, device_memory_base, device_memory_size); 1819 } 1820 } 1821 1822 static VirtGICType finalize_gic_version_do(const char *accel_name, 1823 VirtGICType gic_version, 1824 int gics_supported, 1825 unsigned int max_cpus) 1826 { 1827 /* Convert host/max/nosel to GIC version number */ 1828 switch (gic_version) { 1829 case VIRT_GIC_VERSION_HOST: 1830 if (!kvm_enabled()) { 1831 error_report("gic-version=host requires KVM"); 1832 exit(1); 1833 } 1834 1835 /* For KVM, gic-version=host means gic-version=max */ 1836 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX, 1837 gics_supported, max_cpus); 1838 case VIRT_GIC_VERSION_MAX: 1839 if (gics_supported & VIRT_GIC_VERSION_4_MASK) { 1840 gic_version = VIRT_GIC_VERSION_4; 1841 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1842 gic_version = VIRT_GIC_VERSION_3; 1843 } else { 1844 gic_version = VIRT_GIC_VERSION_2; 1845 } 1846 break; 1847 case VIRT_GIC_VERSION_NOSEL: 1848 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) && 1849 max_cpus <= GIC_NCPU) { 1850 gic_version = VIRT_GIC_VERSION_2; 1851 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { 1852 /* 1853 * in case the host does not support v2 emulation or 1854 * the end-user requested more than 8 VCPUs we now default 1855 * to v3. In any case defaulting to v2 would be broken. 1856 */ 1857 gic_version = VIRT_GIC_VERSION_3; 1858 } else if (max_cpus > GIC_NCPU) { 1859 error_report("%s only supports GICv2 emulation but more than 8 " 1860 "vcpus are requested", accel_name); 1861 exit(1); 1862 } 1863 break; 1864 case VIRT_GIC_VERSION_2: 1865 case VIRT_GIC_VERSION_3: 1866 case VIRT_GIC_VERSION_4: 1867 break; 1868 } 1869 1870 /* Check chosen version is effectively supported */ 1871 switch (gic_version) { 1872 case VIRT_GIC_VERSION_2: 1873 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) { 1874 error_report("%s does not support GICv2 emulation", accel_name); 1875 exit(1); 1876 } 1877 break; 1878 case VIRT_GIC_VERSION_3: 1879 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) { 1880 error_report("%s does not support GICv3 emulation", accel_name); 1881 exit(1); 1882 } 1883 break; 1884 case VIRT_GIC_VERSION_4: 1885 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) { 1886 error_report("%s does not support GICv4 emulation, is virtualization=on?", 1887 accel_name); 1888 exit(1); 1889 } 1890 break; 1891 default: 1892 error_report("logic error in finalize_gic_version"); 1893 exit(1); 1894 break; 1895 } 1896 1897 return gic_version; 1898 } 1899 1900 /* 1901 * finalize_gic_version - Determines the final gic_version 1902 * according to the gic-version property 1903 * 1904 * Default GIC type is v2 1905 */ 1906 static void finalize_gic_version(VirtMachineState *vms) 1907 { 1908 const char *accel_name = current_accel_name(); 1909 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; 1910 int gics_supported = 0; 1911 1912 /* Determine which GIC versions the current environment supports */ 1913 if (kvm_enabled() && kvm_irqchip_in_kernel()) { 1914 int probe_bitmap = kvm_arm_vgic_probe(); 1915 1916 if (!probe_bitmap) { 1917 error_report("Unable to determine GIC version supported by host"); 1918 exit(1); 1919 } 1920 1921 if (probe_bitmap & KVM_ARM_VGIC_V2) { 1922 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1923 } 1924 if (probe_bitmap & KVM_ARM_VGIC_V3) { 1925 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1926 } 1927 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) { 1928 /* KVM w/o kernel irqchip can only deal with GICv2 */ 1929 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1930 accel_name = "KVM with kernel-irqchip=off"; 1931 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { 1932 gics_supported |= VIRT_GIC_VERSION_2_MASK; 1933 if (module_object_class_by_name("arm-gicv3")) { 1934 gics_supported |= VIRT_GIC_VERSION_3_MASK; 1935 if (vms->virt) { 1936 /* GICv4 only makes sense if CPU has EL2 */ 1937 gics_supported |= VIRT_GIC_VERSION_4_MASK; 1938 } 1939 } 1940 } else { 1941 error_report("Unsupported accelerator, can not determine GIC support"); 1942 exit(1); 1943 } 1944 1945 /* 1946 * Then convert helpers like host/max to concrete GIC versions and ensure 1947 * the desired version is supported 1948 */ 1949 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version, 1950 gics_supported, max_cpus); 1951 } 1952 1953 /* 1954 * virt_cpu_post_init() must be called after the CPUs have 1955 * been realized and the GIC has been created. 1956 */ 1957 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) 1958 { 1959 int max_cpus = MACHINE(vms)->smp.max_cpus; 1960 bool aarch64, pmu, steal_time; 1961 CPUState *cpu; 1962 1963 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); 1964 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); 1965 steal_time = object_property_get_bool(OBJECT(first_cpu), 1966 "kvm-steal-time", NULL); 1967 1968 if (kvm_enabled()) { 1969 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; 1970 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; 1971 1972 if (steal_time) { 1973 MemoryRegion *pvtime = g_new(MemoryRegion, 1); 1974 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; 1975 1976 /* The memory region size must be a multiple of host page size. */ 1977 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); 1978 1979 if (pvtime_size > pvtime_reg_size) { 1980 error_report("pvtime requires a %" HWADDR_PRId 1981 " byte memory region for %d CPUs," 1982 " but only %" HWADDR_PRId " has been reserved", 1983 pvtime_size, max_cpus, pvtime_reg_size); 1984 exit(1); 1985 } 1986 1987 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); 1988 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); 1989 } 1990 1991 CPU_FOREACH(cpu) { 1992 if (pmu) { 1993 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); 1994 if (kvm_irqchip_in_kernel()) { 1995 kvm_arm_pmu_set_irq(cpu, VIRTUAL_PMU_IRQ); 1996 } 1997 kvm_arm_pmu_init(cpu); 1998 } 1999 if (steal_time) { 2000 kvm_arm_pvtime_init(cpu, pvtime_reg_base + 2001 cpu->cpu_index * PVTIME_SIZE_PER_CPU); 2002 } 2003 } 2004 } else { 2005 if (aarch64 && vms->highmem) { 2006 int requested_pa_size = 64 - clz64(vms->highest_gpa); 2007 int pamax = arm_pamax(ARM_CPU(first_cpu)); 2008 2009 if (pamax < requested_pa_size) { 2010 error_report("VCPU supports less PA bits (%d) than " 2011 "requested by the memory map (%d)", 2012 pamax, requested_pa_size); 2013 exit(1); 2014 } 2015 } 2016 } 2017 } 2018 2019 static void machvirt_init(MachineState *machine) 2020 { 2021 VirtMachineState *vms = VIRT_MACHINE(machine); 2022 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); 2023 MachineClass *mc = MACHINE_GET_CLASS(machine); 2024 const CPUArchIdList *possible_cpus; 2025 MemoryRegion *sysmem = get_system_memory(); 2026 MemoryRegion *secure_sysmem = NULL; 2027 MemoryRegion *tag_sysmem = NULL; 2028 MemoryRegion *secure_tag_sysmem = NULL; 2029 int n, virt_max_cpus; 2030 bool firmware_loaded; 2031 bool aarch64 = true; 2032 bool has_ged = !vmc->no_ged; 2033 unsigned int smp_cpus = machine->smp.cpus; 2034 unsigned int max_cpus = machine->smp.max_cpus; 2035 2036 if (!cpu_type_valid(machine->cpu_type)) { 2037 error_report("mach-virt: CPU type %s not supported", machine->cpu_type); 2038 exit(1); 2039 } 2040 2041 possible_cpus = mc->possible_cpu_arch_ids(machine); 2042 2043 /* 2044 * In accelerated mode, the memory map is computed earlier in kvm_type() 2045 * to create a VM with the right number of IPA bits. 2046 */ 2047 if (!vms->memmap) { 2048 Object *cpuobj; 2049 ARMCPU *armcpu; 2050 int pa_bits; 2051 2052 /* 2053 * Instantiate a temporary CPU object to find out about what 2054 * we are about to deal with. Once this is done, get rid of 2055 * the object. 2056 */ 2057 cpuobj = object_new(possible_cpus->cpus[0].type); 2058 armcpu = ARM_CPU(cpuobj); 2059 2060 pa_bits = arm_pamax(armcpu); 2061 2062 object_unref(cpuobj); 2063 2064 virt_set_memmap(vms, pa_bits); 2065 } 2066 2067 /* We can probe only here because during property set 2068 * KVM is not available yet 2069 */ 2070 finalize_gic_version(vms); 2071 2072 if (vms->secure) { 2073 /* 2074 * The Secure view of the world is the same as the NonSecure, 2075 * but with a few extra devices. Create it as a container region 2076 * containing the system memory at low priority; any secure-only 2077 * devices go in at higher priority and take precedence. 2078 */ 2079 secure_sysmem = g_new(MemoryRegion, 1); 2080 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", 2081 UINT64_MAX); 2082 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); 2083 } 2084 2085 firmware_loaded = virt_firmware_init(vms, sysmem, 2086 secure_sysmem ?: sysmem); 2087 2088 /* If we have an EL3 boot ROM then the assumption is that it will 2089 * implement PSCI itself, so disable QEMU's internal implementation 2090 * so it doesn't get in the way. Instead of starting secondary 2091 * CPUs in PSCI powerdown state we will start them all running and 2092 * let the boot ROM sort them out. 2093 * The usual case is that we do use QEMU's PSCI implementation; 2094 * if the guest has EL2 then we will use SMC as the conduit, 2095 * and otherwise we will use HVC (for backwards compatibility and 2096 * because if we're using KVM then we must use HVC). 2097 */ 2098 if (vms->secure && firmware_loaded) { 2099 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 2100 } else if (vms->virt) { 2101 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; 2102 } else { 2103 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; 2104 } 2105 2106 /* 2107 * The maximum number of CPUs depends on the GIC version, or on how 2108 * many redistributors we can fit into the memory map (which in turn 2109 * depends on whether this is a GICv3 or v4). 2110 */ 2111 if (vms->gic_version == VIRT_GIC_VERSION_2) { 2112 virt_max_cpus = GIC_NCPU; 2113 } else { 2114 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST); 2115 if (vms->highmem_redists) { 2116 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); 2117 } 2118 } 2119 2120 if (max_cpus > virt_max_cpus) { 2121 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " 2122 "supported by machine 'mach-virt' (%d)", 2123 max_cpus, virt_max_cpus); 2124 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) { 2125 error_printf("Try 'highmem-redists=on' for more CPUs\n"); 2126 } 2127 2128 exit(1); 2129 } 2130 2131 if (vms->secure && (kvm_enabled() || hvf_enabled())) { 2132 error_report("mach-virt: %s does not support providing " 2133 "Security extensions (TrustZone) to the guest CPU", 2134 current_accel_name()); 2135 exit(1); 2136 } 2137 2138 if (vms->virt && (kvm_enabled() || hvf_enabled())) { 2139 error_report("mach-virt: %s does not support providing " 2140 "Virtualization extensions to the guest CPU", 2141 current_accel_name()); 2142 exit(1); 2143 } 2144 2145 if (vms->mte && (kvm_enabled() || hvf_enabled())) { 2146 error_report("mach-virt: %s does not support providing " 2147 "MTE to the guest CPU", 2148 current_accel_name()); 2149 exit(1); 2150 } 2151 2152 create_fdt(vms); 2153 2154 assert(possible_cpus->len == max_cpus); 2155 for (n = 0; n < possible_cpus->len; n++) { 2156 Object *cpuobj; 2157 CPUState *cs; 2158 2159 if (n >= smp_cpus) { 2160 break; 2161 } 2162 2163 cpuobj = object_new(possible_cpus->cpus[n].type); 2164 object_property_set_int(cpuobj, "mp-affinity", 2165 possible_cpus->cpus[n].arch_id, NULL); 2166 2167 cs = CPU(cpuobj); 2168 cs->cpu_index = n; 2169 2170 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), 2171 &error_fatal); 2172 2173 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); 2174 2175 if (!vms->secure) { 2176 object_property_set_bool(cpuobj, "has_el3", false, NULL); 2177 } 2178 2179 if (!vms->virt && object_property_find(cpuobj, "has_el2")) { 2180 object_property_set_bool(cpuobj, "has_el2", false, NULL); 2181 } 2182 2183 if (vmc->kvm_no_adjvtime && 2184 object_property_find(cpuobj, "kvm-no-adjvtime")) { 2185 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); 2186 } 2187 2188 if (vmc->no_kvm_steal_time && 2189 object_property_find(cpuobj, "kvm-steal-time")) { 2190 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); 2191 } 2192 2193 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { 2194 object_property_set_bool(cpuobj, "pmu", false, NULL); 2195 } 2196 2197 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { 2198 object_property_set_bool(cpuobj, "lpa2", false, NULL); 2199 } 2200 2201 if (object_property_find(cpuobj, "reset-cbar")) { 2202 object_property_set_int(cpuobj, "reset-cbar", 2203 vms->memmap[VIRT_CPUPERIPHS].base, 2204 &error_abort); 2205 } 2206 2207 object_property_set_link(cpuobj, "memory", OBJECT(sysmem), 2208 &error_abort); 2209 if (vms->secure) { 2210 object_property_set_link(cpuobj, "secure-memory", 2211 OBJECT(secure_sysmem), &error_abort); 2212 } 2213 2214 if (vms->mte) { 2215 /* Create the memory region only once, but link to all cpus. */ 2216 if (!tag_sysmem) { 2217 /* 2218 * The property exists only if MemTag is supported. 2219 * If it is, we must allocate the ram to back that up. 2220 */ 2221 if (!object_property_find(cpuobj, "tag-memory")) { 2222 error_report("MTE requested, but not supported " 2223 "by the guest CPU"); 2224 exit(1); 2225 } 2226 2227 tag_sysmem = g_new(MemoryRegion, 1); 2228 memory_region_init(tag_sysmem, OBJECT(machine), 2229 "tag-memory", UINT64_MAX / 32); 2230 2231 if (vms->secure) { 2232 secure_tag_sysmem = g_new(MemoryRegion, 1); 2233 memory_region_init(secure_tag_sysmem, OBJECT(machine), 2234 "secure-tag-memory", UINT64_MAX / 32); 2235 2236 /* As with ram, secure-tag takes precedence over tag. */ 2237 memory_region_add_subregion_overlap(secure_tag_sysmem, 0, 2238 tag_sysmem, -1); 2239 } 2240 } 2241 2242 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), 2243 &error_abort); 2244 if (vms->secure) { 2245 object_property_set_link(cpuobj, "secure-tag-memory", 2246 OBJECT(secure_tag_sysmem), 2247 &error_abort); 2248 } 2249 } 2250 2251 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); 2252 object_unref(cpuobj); 2253 } 2254 fdt_add_timer_nodes(vms); 2255 fdt_add_cpu_nodes(vms); 2256 2257 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, 2258 machine->ram); 2259 2260 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); 2261 2262 create_gic(vms, sysmem); 2263 2264 virt_cpu_post_init(vms, sysmem); 2265 2266 fdt_add_pmu_nodes(vms); 2267 2268 create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); 2269 2270 if (vms->secure) { 2271 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); 2272 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); 2273 } 2274 2275 if (tag_sysmem) { 2276 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, 2277 machine->ram_size, "mach-virt.tag"); 2278 } 2279 2280 vms->highmem_ecam &= (!firmware_loaded || aarch64); 2281 2282 create_rtc(vms); 2283 2284 create_pcie(vms); 2285 2286 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { 2287 vms->acpi_dev = create_acpi_ged(vms); 2288 } else { 2289 create_gpio_devices(vms, VIRT_GPIO, sysmem); 2290 } 2291 2292 if (vms->secure && !vmc->no_secure_gpio) { 2293 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); 2294 } 2295 2296 /* connect powerdown request */ 2297 vms->powerdown_notifier.notify = virt_powerdown_req; 2298 qemu_register_powerdown_notifier(&vms->powerdown_notifier); 2299 2300 /* Create mmio transports, so the user can create virtio backends 2301 * (which will be automatically plugged in to the transports). If 2302 * no backend is created the transport will just sit harmlessly idle. 2303 */ 2304 create_virtio_devices(vms); 2305 2306 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); 2307 rom_set_fw(vms->fw_cfg); 2308 2309 create_platform_bus(vms); 2310 2311 if (machine->nvdimms_state->is_enabled) { 2312 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { 2313 .space_id = AML_AS_SYSTEM_MEMORY, 2314 .address = vms->memmap[VIRT_NVDIMM_ACPI].base, 2315 .bit_width = NVDIMM_ACPI_IO_LEN << 3 2316 }; 2317 2318 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, 2319 arm_virt_nvdimm_acpi_dsmio, 2320 vms->fw_cfg, OBJECT(vms)); 2321 } 2322 2323 vms->bootinfo.ram_size = machine->ram_size; 2324 vms->bootinfo.board_id = -1; 2325 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; 2326 vms->bootinfo.get_dtb = machvirt_dtb; 2327 vms->bootinfo.skip_dtb_autoload = true; 2328 vms->bootinfo.firmware_loaded = firmware_loaded; 2329 vms->bootinfo.psci_conduit = vms->psci_conduit; 2330 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); 2331 2332 vms->machine_done.notify = virt_machine_done; 2333 qemu_add_machine_init_done_notifier(&vms->machine_done); 2334 } 2335 2336 static bool virt_get_secure(Object *obj, Error **errp) 2337 { 2338 VirtMachineState *vms = VIRT_MACHINE(obj); 2339 2340 return vms->secure; 2341 } 2342 2343 static void virt_set_secure(Object *obj, bool value, Error **errp) 2344 { 2345 VirtMachineState *vms = VIRT_MACHINE(obj); 2346 2347 vms->secure = value; 2348 } 2349 2350 static bool virt_get_virt(Object *obj, Error **errp) 2351 { 2352 VirtMachineState *vms = VIRT_MACHINE(obj); 2353 2354 return vms->virt; 2355 } 2356 2357 static void virt_set_virt(Object *obj, bool value, Error **errp) 2358 { 2359 VirtMachineState *vms = VIRT_MACHINE(obj); 2360 2361 vms->virt = value; 2362 } 2363 2364 static bool virt_get_highmem(Object *obj, Error **errp) 2365 { 2366 VirtMachineState *vms = VIRT_MACHINE(obj); 2367 2368 return vms->highmem; 2369 } 2370 2371 static void virt_set_highmem(Object *obj, bool value, Error **errp) 2372 { 2373 VirtMachineState *vms = VIRT_MACHINE(obj); 2374 2375 vms->highmem = value; 2376 } 2377 2378 static bool virt_get_compact_highmem(Object *obj, Error **errp) 2379 { 2380 VirtMachineState *vms = VIRT_MACHINE(obj); 2381 2382 return vms->highmem_compact; 2383 } 2384 2385 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) 2386 { 2387 VirtMachineState *vms = VIRT_MACHINE(obj); 2388 2389 vms->highmem_compact = value; 2390 } 2391 2392 static bool virt_get_highmem_redists(Object *obj, Error **errp) 2393 { 2394 VirtMachineState *vms = VIRT_MACHINE(obj); 2395 2396 return vms->highmem_redists; 2397 } 2398 2399 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp) 2400 { 2401 VirtMachineState *vms = VIRT_MACHINE(obj); 2402 2403 vms->highmem_redists = value; 2404 } 2405 2406 static bool virt_get_highmem_ecam(Object *obj, Error **errp) 2407 { 2408 VirtMachineState *vms = VIRT_MACHINE(obj); 2409 2410 return vms->highmem_ecam; 2411 } 2412 2413 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp) 2414 { 2415 VirtMachineState *vms = VIRT_MACHINE(obj); 2416 2417 vms->highmem_ecam = value; 2418 } 2419 2420 static bool virt_get_highmem_mmio(Object *obj, Error **errp) 2421 { 2422 VirtMachineState *vms = VIRT_MACHINE(obj); 2423 2424 return vms->highmem_mmio; 2425 } 2426 2427 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) 2428 { 2429 VirtMachineState *vms = VIRT_MACHINE(obj); 2430 2431 vms->highmem_mmio = value; 2432 } 2433 2434 2435 static bool virt_get_its(Object *obj, Error **errp) 2436 { 2437 VirtMachineState *vms = VIRT_MACHINE(obj); 2438 2439 return vms->its; 2440 } 2441 2442 static void virt_set_its(Object *obj, bool value, Error **errp) 2443 { 2444 VirtMachineState *vms = VIRT_MACHINE(obj); 2445 2446 vms->its = value; 2447 } 2448 2449 static bool virt_get_dtb_randomness(Object *obj, Error **errp) 2450 { 2451 VirtMachineState *vms = VIRT_MACHINE(obj); 2452 2453 return vms->dtb_randomness; 2454 } 2455 2456 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp) 2457 { 2458 VirtMachineState *vms = VIRT_MACHINE(obj); 2459 2460 vms->dtb_randomness = value; 2461 } 2462 2463 static char *virt_get_oem_id(Object *obj, Error **errp) 2464 { 2465 VirtMachineState *vms = VIRT_MACHINE(obj); 2466 2467 return g_strdup(vms->oem_id); 2468 } 2469 2470 static void virt_set_oem_id(Object *obj, const char *value, Error **errp) 2471 { 2472 VirtMachineState *vms = VIRT_MACHINE(obj); 2473 size_t len = strlen(value); 2474 2475 if (len > 6) { 2476 error_setg(errp, 2477 "User specified oem-id value is bigger than 6 bytes in size"); 2478 return; 2479 } 2480 2481 strncpy(vms->oem_id, value, 6); 2482 } 2483 2484 static char *virt_get_oem_table_id(Object *obj, Error **errp) 2485 { 2486 VirtMachineState *vms = VIRT_MACHINE(obj); 2487 2488 return g_strdup(vms->oem_table_id); 2489 } 2490 2491 static void virt_set_oem_table_id(Object *obj, const char *value, 2492 Error **errp) 2493 { 2494 VirtMachineState *vms = VIRT_MACHINE(obj); 2495 size_t len = strlen(value); 2496 2497 if (len > 8) { 2498 error_setg(errp, 2499 "User specified oem-table-id value is bigger than 8 bytes in size"); 2500 return; 2501 } 2502 strncpy(vms->oem_table_id, value, 8); 2503 } 2504 2505 2506 bool virt_is_acpi_enabled(VirtMachineState *vms) 2507 { 2508 if (vms->acpi == ON_OFF_AUTO_OFF) { 2509 return false; 2510 } 2511 return true; 2512 } 2513 2514 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 2515 void *opaque, Error **errp) 2516 { 2517 VirtMachineState *vms = VIRT_MACHINE(obj); 2518 OnOffAuto acpi = vms->acpi; 2519 2520 visit_type_OnOffAuto(v, name, &acpi, errp); 2521 } 2522 2523 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 2524 void *opaque, Error **errp) 2525 { 2526 VirtMachineState *vms = VIRT_MACHINE(obj); 2527 2528 visit_type_OnOffAuto(v, name, &vms->acpi, errp); 2529 } 2530 2531 static bool virt_get_ras(Object *obj, Error **errp) 2532 { 2533 VirtMachineState *vms = VIRT_MACHINE(obj); 2534 2535 return vms->ras; 2536 } 2537 2538 static void virt_set_ras(Object *obj, bool value, Error **errp) 2539 { 2540 VirtMachineState *vms = VIRT_MACHINE(obj); 2541 2542 vms->ras = value; 2543 } 2544 2545 static bool virt_get_mte(Object *obj, Error **errp) 2546 { 2547 VirtMachineState *vms = VIRT_MACHINE(obj); 2548 2549 return vms->mte; 2550 } 2551 2552 static void virt_set_mte(Object *obj, bool value, Error **errp) 2553 { 2554 VirtMachineState *vms = VIRT_MACHINE(obj); 2555 2556 vms->mte = value; 2557 } 2558 2559 static char *virt_get_gic_version(Object *obj, Error **errp) 2560 { 2561 VirtMachineState *vms = VIRT_MACHINE(obj); 2562 const char *val; 2563 2564 switch (vms->gic_version) { 2565 case VIRT_GIC_VERSION_4: 2566 val = "4"; 2567 break; 2568 case VIRT_GIC_VERSION_3: 2569 val = "3"; 2570 break; 2571 default: 2572 val = "2"; 2573 break; 2574 } 2575 return g_strdup(val); 2576 } 2577 2578 static void virt_set_gic_version(Object *obj, const char *value, Error **errp) 2579 { 2580 VirtMachineState *vms = VIRT_MACHINE(obj); 2581 2582 if (!strcmp(value, "4")) { 2583 vms->gic_version = VIRT_GIC_VERSION_4; 2584 } else if (!strcmp(value, "3")) { 2585 vms->gic_version = VIRT_GIC_VERSION_3; 2586 } else if (!strcmp(value, "2")) { 2587 vms->gic_version = VIRT_GIC_VERSION_2; 2588 } else if (!strcmp(value, "host")) { 2589 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ 2590 } else if (!strcmp(value, "max")) { 2591 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ 2592 } else { 2593 error_setg(errp, "Invalid gic-version value"); 2594 error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); 2595 } 2596 } 2597 2598 static char *virt_get_iommu(Object *obj, Error **errp) 2599 { 2600 VirtMachineState *vms = VIRT_MACHINE(obj); 2601 2602 switch (vms->iommu) { 2603 case VIRT_IOMMU_NONE: 2604 return g_strdup("none"); 2605 case VIRT_IOMMU_SMMUV3: 2606 return g_strdup("smmuv3"); 2607 default: 2608 g_assert_not_reached(); 2609 } 2610 } 2611 2612 static void virt_set_iommu(Object *obj, const char *value, Error **errp) 2613 { 2614 VirtMachineState *vms = VIRT_MACHINE(obj); 2615 2616 if (!strcmp(value, "smmuv3")) { 2617 vms->iommu = VIRT_IOMMU_SMMUV3; 2618 } else if (!strcmp(value, "none")) { 2619 vms->iommu = VIRT_IOMMU_NONE; 2620 } else { 2621 error_setg(errp, "Invalid iommu value"); 2622 error_append_hint(errp, "Valid values are none, smmuv3.\n"); 2623 } 2624 } 2625 2626 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) 2627 { 2628 VirtMachineState *vms = VIRT_MACHINE(obj); 2629 2630 return vms->default_bus_bypass_iommu; 2631 } 2632 2633 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, 2634 Error **errp) 2635 { 2636 VirtMachineState *vms = VIRT_MACHINE(obj); 2637 2638 vms->default_bus_bypass_iommu = value; 2639 } 2640 2641 static CpuInstanceProperties 2642 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2643 { 2644 MachineClass *mc = MACHINE_GET_CLASS(ms); 2645 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2646 2647 assert(cpu_index < possible_cpus->len); 2648 return possible_cpus->cpus[cpu_index].props; 2649 } 2650 2651 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 2652 { 2653 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 2654 2655 return socket_id % ms->numa_state->num_nodes; 2656 } 2657 2658 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 2659 { 2660 int n; 2661 unsigned int max_cpus = ms->smp.max_cpus; 2662 VirtMachineState *vms = VIRT_MACHINE(ms); 2663 MachineClass *mc = MACHINE_GET_CLASS(vms); 2664 2665 if (ms->possible_cpus) { 2666 assert(ms->possible_cpus->len == max_cpus); 2667 return ms->possible_cpus; 2668 } 2669 2670 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2671 sizeof(CPUArchId) * max_cpus); 2672 ms->possible_cpus->len = max_cpus; 2673 for (n = 0; n < ms->possible_cpus->len; n++) { 2674 ms->possible_cpus->cpus[n].type = ms->cpu_type; 2675 ms->possible_cpus->cpus[n].arch_id = 2676 virt_cpu_mp_affinity(vms, n); 2677 2678 assert(!mc->smp_props.dies_supported); 2679 ms->possible_cpus->cpus[n].props.has_socket_id = true; 2680 ms->possible_cpus->cpus[n].props.socket_id = 2681 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); 2682 ms->possible_cpus->cpus[n].props.has_cluster_id = true; 2683 ms->possible_cpus->cpus[n].props.cluster_id = 2684 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; 2685 ms->possible_cpus->cpus[n].props.has_core_id = true; 2686 ms->possible_cpus->cpus[n].props.core_id = 2687 (n / ms->smp.threads) % ms->smp.cores; 2688 ms->possible_cpus->cpus[n].props.has_thread_id = true; 2689 ms->possible_cpus->cpus[n].props.thread_id = 2690 n % ms->smp.threads; 2691 } 2692 return ms->possible_cpus; 2693 } 2694 2695 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2696 Error **errp) 2697 { 2698 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2699 const MachineState *ms = MACHINE(hotplug_dev); 2700 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2701 2702 if (!vms->acpi_dev) { 2703 error_setg(errp, 2704 "memory hotplug is not enabled: missing acpi-ged device"); 2705 return; 2706 } 2707 2708 if (vms->mte) { 2709 error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); 2710 return; 2711 } 2712 2713 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2714 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); 2715 return; 2716 } 2717 2718 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 2719 } 2720 2721 static void virt_memory_plug(HotplugHandler *hotplug_dev, 2722 DeviceState *dev, Error **errp) 2723 { 2724 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2725 MachineState *ms = MACHINE(hotplug_dev); 2726 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2727 2728 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); 2729 2730 if (is_nvdimm) { 2731 nvdimm_plug(ms->nvdimms_state); 2732 } 2733 2734 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), 2735 dev, &error_abort); 2736 } 2737 2738 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2739 DeviceState *dev, Error **errp) 2740 { 2741 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2742 2743 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2744 virt_memory_pre_plug(hotplug_dev, dev, errp); 2745 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2746 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2747 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2748 hwaddr db_start = 0, db_end = 0; 2749 char *resv_prop_str; 2750 2751 if (vms->iommu != VIRT_IOMMU_NONE) { 2752 error_setg(errp, "virt machine does not support multiple IOMMUs"); 2753 return; 2754 } 2755 2756 switch (vms->msi_controller) { 2757 case VIRT_MSI_CTRL_NONE: 2758 return; 2759 case VIRT_MSI_CTRL_ITS: 2760 /* GITS_TRANSLATER page */ 2761 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; 2762 db_end = base_memmap[VIRT_GIC_ITS].base + 2763 base_memmap[VIRT_GIC_ITS].size - 1; 2764 break; 2765 case VIRT_MSI_CTRL_GICV2M: 2766 /* MSI_SETSPI_NS page */ 2767 db_start = base_memmap[VIRT_GIC_V2M].base; 2768 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; 2769 break; 2770 } 2771 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", 2772 db_start, db_end, 2773 VIRTIO_IOMMU_RESV_MEM_T_MSI); 2774 2775 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 2776 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 2777 resv_prop_str, errp); 2778 g_free(resv_prop_str); 2779 } 2780 } 2781 2782 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2783 DeviceState *dev, Error **errp) 2784 { 2785 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2786 2787 if (vms->platform_bus_dev) { 2788 MachineClass *mc = MACHINE_GET_CLASS(vms); 2789 2790 if (device_is_dynamic_sysbus(mc, dev)) { 2791 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), 2792 SYS_BUS_DEVICE(dev)); 2793 } 2794 } 2795 2796 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2797 virt_memory_plug(hotplug_dev, dev, errp); 2798 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2799 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2800 } 2801 2802 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2803 PCIDevice *pdev = PCI_DEVICE(dev); 2804 2805 vms->iommu = VIRT_IOMMU_VIRTIO; 2806 vms->virtio_iommu_bdf = pci_get_bdf(pdev); 2807 create_virtio_iommu_dt_bindings(vms); 2808 } 2809 } 2810 2811 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, 2812 DeviceState *dev, Error **errp) 2813 { 2814 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2815 2816 if (!vms->acpi_dev) { 2817 error_setg(errp, 2818 "memory hotplug is not enabled: missing acpi-ged device"); 2819 return; 2820 } 2821 2822 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2823 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 2824 return; 2825 } 2826 2827 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, 2828 errp); 2829 } 2830 2831 static void virt_dimm_unplug(HotplugHandler *hotplug_dev, 2832 DeviceState *dev, Error **errp) 2833 { 2834 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); 2835 Error *local_err = NULL; 2836 2837 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); 2838 if (local_err) { 2839 goto out; 2840 } 2841 2842 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); 2843 qdev_unrealize(dev); 2844 2845 out: 2846 error_propagate(errp, local_err); 2847 } 2848 2849 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2850 DeviceState *dev, Error **errp) 2851 { 2852 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2853 virt_dimm_unplug_request(hotplug_dev, dev, errp); 2854 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2855 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 2856 errp); 2857 } else { 2858 error_setg(errp, "device unplug request for unsupported device" 2859 " type: %s", object_get_typename(OBJECT(dev))); 2860 } 2861 } 2862 2863 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2864 DeviceState *dev, Error **errp) 2865 { 2866 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2867 virt_dimm_unplug(hotplug_dev, dev, errp); 2868 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 2869 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 2870 } else { 2871 error_setg(errp, "virt: device unplug for unsupported device" 2872 " type: %s", object_get_typename(OBJECT(dev))); 2873 } 2874 } 2875 2876 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 2877 DeviceState *dev) 2878 { 2879 MachineClass *mc = MACHINE_GET_CLASS(machine); 2880 2881 if (device_is_dynamic_sysbus(mc, dev) || 2882 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2883 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 2884 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 2885 return HOTPLUG_HANDLER(machine); 2886 } 2887 return NULL; 2888 } 2889 2890 /* 2891 * for arm64 kvm_type [7-0] encodes the requested number of bits 2892 * in the IPA address space 2893 */ 2894 static int virt_kvm_type(MachineState *ms, const char *type_str) 2895 { 2896 VirtMachineState *vms = VIRT_MACHINE(ms); 2897 int max_vm_pa_size, requested_pa_size; 2898 bool fixed_ipa; 2899 2900 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); 2901 2902 /* we freeze the memory map to compute the highest gpa */ 2903 virt_set_memmap(vms, max_vm_pa_size); 2904 2905 requested_pa_size = 64 - clz64(vms->highest_gpa); 2906 2907 /* 2908 * KVM requires the IPA size to be at least 32 bits. 2909 */ 2910 if (requested_pa_size < 32) { 2911 requested_pa_size = 32; 2912 } 2913 2914 if (requested_pa_size > max_vm_pa_size) { 2915 error_report("-m and ,maxmem option values " 2916 "require an IPA range (%d bits) larger than " 2917 "the one supported by the host (%d bits)", 2918 requested_pa_size, max_vm_pa_size); 2919 return -1; 2920 } 2921 /* 2922 * We return the requested PA log size, unless KVM only supports 2923 * the implicit legacy 40b IPA setting, in which case the kvm_type 2924 * must be 0. 2925 */ 2926 return fixed_ipa ? 0 : requested_pa_size; 2927 } 2928 2929 static void virt_machine_class_init(ObjectClass *oc, void *data) 2930 { 2931 MachineClass *mc = MACHINE_CLASS(oc); 2932 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2933 2934 mc->init = machvirt_init; 2935 /* Start with max_cpus set to 512, which is the maximum supported by KVM. 2936 * The value may be reduced later when we have more information about the 2937 * configuration of the particular instance. 2938 */ 2939 mc->max_cpus = 512; 2940 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); 2941 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); 2942 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 2943 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); 2944 #ifdef CONFIG_TPM 2945 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 2946 #endif 2947 mc->block_default_type = IF_VIRTIO; 2948 mc->no_cdrom = 1; 2949 mc->pci_allow_0_address = true; 2950 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ 2951 mc->minimum_page_bits = 12; 2952 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 2953 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 2954 #ifdef CONFIG_TCG 2955 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); 2956 #else 2957 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); 2958 #endif 2959 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 2960 mc->kvm_type = virt_kvm_type; 2961 assert(!mc->get_hotplug_handler); 2962 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 2963 hc->pre_plug = virt_machine_device_pre_plug_cb; 2964 hc->plug = virt_machine_device_plug_cb; 2965 hc->unplug_request = virt_machine_device_unplug_request_cb; 2966 hc->unplug = virt_machine_device_unplug_cb; 2967 mc->nvdimm_supported = true; 2968 mc->smp_props.clusters_supported = true; 2969 mc->auto_enable_numa_with_memhp = true; 2970 mc->auto_enable_numa_with_memdev = true; 2971 /* platform instead of architectural choice */ 2972 mc->cpu_cluster_has_numa_boundary = true; 2973 mc->default_ram_id = "mach-virt.ram"; 2974 mc->default_nic = "virtio-net-pci"; 2975 2976 object_class_property_add(oc, "acpi", "OnOffAuto", 2977 virt_get_acpi, virt_set_acpi, 2978 NULL, NULL); 2979 object_class_property_set_description(oc, "acpi", 2980 "Enable ACPI"); 2981 object_class_property_add_bool(oc, "secure", virt_get_secure, 2982 virt_set_secure); 2983 object_class_property_set_description(oc, "secure", 2984 "Set on/off to enable/disable the ARM " 2985 "Security Extensions (TrustZone)"); 2986 2987 object_class_property_add_bool(oc, "virtualization", virt_get_virt, 2988 virt_set_virt); 2989 object_class_property_set_description(oc, "virtualization", 2990 "Set on/off to enable/disable emulating a " 2991 "guest CPU which implements the ARM " 2992 "Virtualization Extensions"); 2993 2994 object_class_property_add_bool(oc, "highmem", virt_get_highmem, 2995 virt_set_highmem); 2996 object_class_property_set_description(oc, "highmem", 2997 "Set on/off to enable/disable using " 2998 "physical address space above 32 bits"); 2999 3000 object_class_property_add_bool(oc, "compact-highmem", 3001 virt_get_compact_highmem, 3002 virt_set_compact_highmem); 3003 object_class_property_set_description(oc, "compact-highmem", 3004 "Set on/off to enable/disable compact " 3005 "layout for high memory regions"); 3006 3007 object_class_property_add_bool(oc, "highmem-redists", 3008 virt_get_highmem_redists, 3009 virt_set_highmem_redists); 3010 object_class_property_set_description(oc, "highmem-redists", 3011 "Set on/off to enable/disable high " 3012 "memory region for GICv3 or GICv4 " 3013 "redistributor"); 3014 3015 object_class_property_add_bool(oc, "highmem-ecam", 3016 virt_get_highmem_ecam, 3017 virt_set_highmem_ecam); 3018 object_class_property_set_description(oc, "highmem-ecam", 3019 "Set on/off to enable/disable high " 3020 "memory region for PCI ECAM"); 3021 3022 object_class_property_add_bool(oc, "highmem-mmio", 3023 virt_get_highmem_mmio, 3024 virt_set_highmem_mmio); 3025 object_class_property_set_description(oc, "highmem-mmio", 3026 "Set on/off to enable/disable high " 3027 "memory region for PCI MMIO"); 3028 3029 object_class_property_add_str(oc, "gic-version", virt_get_gic_version, 3030 virt_set_gic_version); 3031 object_class_property_set_description(oc, "gic-version", 3032 "Set GIC version. " 3033 "Valid values are 2, 3, 4, host and max"); 3034 3035 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); 3036 object_class_property_set_description(oc, "iommu", 3037 "Set the IOMMU type. " 3038 "Valid values are none and smmuv3"); 3039 3040 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 3041 virt_get_default_bus_bypass_iommu, 3042 virt_set_default_bus_bypass_iommu); 3043 object_class_property_set_description(oc, "default-bus-bypass-iommu", 3044 "Set on/off to enable/disable " 3045 "bypass_iommu for default root bus"); 3046 3047 object_class_property_add_bool(oc, "ras", virt_get_ras, 3048 virt_set_ras); 3049 object_class_property_set_description(oc, "ras", 3050 "Set on/off to enable/disable reporting host memory errors " 3051 "to a KVM guest using ACPI and guest external abort exceptions"); 3052 3053 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); 3054 object_class_property_set_description(oc, "mte", 3055 "Set on/off to enable/disable emulating a " 3056 "guest CPU which implements the ARM " 3057 "Memory Tagging Extension"); 3058 3059 object_class_property_add_bool(oc, "its", virt_get_its, 3060 virt_set_its); 3061 object_class_property_set_description(oc, "its", 3062 "Set on/off to enable/disable " 3063 "ITS instantiation"); 3064 3065 object_class_property_add_bool(oc, "dtb-randomness", 3066 virt_get_dtb_randomness, 3067 virt_set_dtb_randomness); 3068 object_class_property_set_description(oc, "dtb-randomness", 3069 "Set off to disable passing random or " 3070 "non-deterministic dtb nodes to guest"); 3071 3072 object_class_property_add_bool(oc, "dtb-kaslr-seed", 3073 virt_get_dtb_randomness, 3074 virt_set_dtb_randomness); 3075 object_class_property_set_description(oc, "dtb-kaslr-seed", 3076 "Deprecated synonym of dtb-randomness"); 3077 3078 object_class_property_add_str(oc, "x-oem-id", 3079 virt_get_oem_id, 3080 virt_set_oem_id); 3081 object_class_property_set_description(oc, "x-oem-id", 3082 "Override the default value of field OEMID " 3083 "in ACPI table header." 3084 "The string may be up to 6 bytes in size"); 3085 3086 3087 object_class_property_add_str(oc, "x-oem-table-id", 3088 virt_get_oem_table_id, 3089 virt_set_oem_table_id); 3090 object_class_property_set_description(oc, "x-oem-table-id", 3091 "Override the default value of field OEM Table ID " 3092 "in ACPI table header." 3093 "The string may be up to 8 bytes in size"); 3094 3095 } 3096 3097 static void virt_instance_init(Object *obj) 3098 { 3099 VirtMachineState *vms = VIRT_MACHINE(obj); 3100 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); 3101 3102 /* EL3 is disabled by default on virt: this makes us consistent 3103 * between KVM and TCG for this board, and it also allows us to 3104 * boot UEFI blobs which assume no TrustZone support. 3105 */ 3106 vms->secure = false; 3107 3108 /* EL2 is also disabled by default, for similar reasons */ 3109 vms->virt = false; 3110 3111 /* High memory is enabled by default */ 3112 vms->highmem = true; 3113 vms->highmem_compact = !vmc->no_highmem_compact; 3114 vms->gic_version = VIRT_GIC_VERSION_NOSEL; 3115 3116 vms->highmem_ecam = !vmc->no_highmem_ecam; 3117 vms->highmem_mmio = true; 3118 vms->highmem_redists = true; 3119 3120 if (vmc->no_its) { 3121 vms->its = false; 3122 } else { 3123 /* Default allows ITS instantiation */ 3124 vms->its = true; 3125 3126 if (vmc->no_tcg_its) { 3127 vms->tcg_its = false; 3128 } else { 3129 vms->tcg_its = true; 3130 } 3131 } 3132 3133 /* Default disallows iommu instantiation */ 3134 vms->iommu = VIRT_IOMMU_NONE; 3135 3136 /* The default root bus is attached to iommu by default */ 3137 vms->default_bus_bypass_iommu = false; 3138 3139 /* Default disallows RAS instantiation */ 3140 vms->ras = false; 3141 3142 /* MTE is disabled by default. */ 3143 vms->mte = false; 3144 3145 /* Supply kaslr-seed and rng-seed by default */ 3146 vms->dtb_randomness = true; 3147 3148 vms->irqmap = a15irqmap; 3149 3150 virt_flash_create(vms); 3151 3152 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 3153 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 3154 } 3155 3156 static const TypeInfo virt_machine_info = { 3157 .name = TYPE_VIRT_MACHINE, 3158 .parent = TYPE_MACHINE, 3159 .abstract = true, 3160 .instance_size = sizeof(VirtMachineState), 3161 .class_size = sizeof(VirtMachineClass), 3162 .class_init = virt_machine_class_init, 3163 .instance_init = virt_instance_init, 3164 .interfaces = (InterfaceInfo[]) { 3165 { TYPE_HOTPLUG_HANDLER }, 3166 { } 3167 }, 3168 }; 3169 3170 static void machvirt_machine_init(void) 3171 { 3172 type_register_static(&virt_machine_info); 3173 } 3174 type_init(machvirt_machine_init); 3175 3176 static void virt_machine_8_2_options(MachineClass *mc) 3177 { 3178 } 3179 DEFINE_VIRT_MACHINE_AS_LATEST(8, 2) 3180 3181 static void virt_machine_8_1_options(MachineClass *mc) 3182 { 3183 virt_machine_8_2_options(mc); 3184 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len); 3185 } 3186 DEFINE_VIRT_MACHINE(8, 1) 3187 3188 static void virt_machine_8_0_options(MachineClass *mc) 3189 { 3190 virt_machine_8_1_options(mc); 3191 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); 3192 } 3193 DEFINE_VIRT_MACHINE(8, 0) 3194 3195 static void virt_machine_7_2_options(MachineClass *mc) 3196 { 3197 virt_machine_8_0_options(mc); 3198 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); 3199 } 3200 DEFINE_VIRT_MACHINE(7, 2) 3201 3202 static void virt_machine_7_1_options(MachineClass *mc) 3203 { 3204 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3205 3206 virt_machine_7_2_options(mc); 3207 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); 3208 /* Compact layout for high memory regions was introduced with 7.2 */ 3209 vmc->no_highmem_compact = true; 3210 } 3211 DEFINE_VIRT_MACHINE(7, 1) 3212 3213 static void virt_machine_7_0_options(MachineClass *mc) 3214 { 3215 virt_machine_7_1_options(mc); 3216 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 3217 } 3218 DEFINE_VIRT_MACHINE(7, 0) 3219 3220 static void virt_machine_6_2_options(MachineClass *mc) 3221 { 3222 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3223 3224 virt_machine_7_0_options(mc); 3225 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 3226 vmc->no_tcg_lpa2 = true; 3227 } 3228 DEFINE_VIRT_MACHINE(6, 2) 3229 3230 static void virt_machine_6_1_options(MachineClass *mc) 3231 { 3232 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3233 3234 virt_machine_6_2_options(mc); 3235 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 3236 mc->smp_props.prefer_sockets = true; 3237 vmc->no_cpu_topology = true; 3238 3239 /* qemu ITS was introduced with 6.2 */ 3240 vmc->no_tcg_its = true; 3241 } 3242 DEFINE_VIRT_MACHINE(6, 1) 3243 3244 static void virt_machine_6_0_options(MachineClass *mc) 3245 { 3246 virt_machine_6_1_options(mc); 3247 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 3248 } 3249 DEFINE_VIRT_MACHINE(6, 0) 3250 3251 static void virt_machine_5_2_options(MachineClass *mc) 3252 { 3253 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3254 3255 virt_machine_6_0_options(mc); 3256 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 3257 vmc->no_secure_gpio = true; 3258 } 3259 DEFINE_VIRT_MACHINE(5, 2) 3260 3261 static void virt_machine_5_1_options(MachineClass *mc) 3262 { 3263 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3264 3265 virt_machine_5_2_options(mc); 3266 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 3267 vmc->no_kvm_steal_time = true; 3268 } 3269 DEFINE_VIRT_MACHINE(5, 1) 3270 3271 static void virt_machine_5_0_options(MachineClass *mc) 3272 { 3273 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3274 3275 virt_machine_5_1_options(mc); 3276 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 3277 mc->numa_mem_supported = true; 3278 vmc->acpi_expose_flash = true; 3279 mc->auto_enable_numa_with_memdev = false; 3280 } 3281 DEFINE_VIRT_MACHINE(5, 0) 3282 3283 static void virt_machine_4_2_options(MachineClass *mc) 3284 { 3285 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3286 3287 virt_machine_5_0_options(mc); 3288 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 3289 vmc->kvm_no_adjvtime = true; 3290 } 3291 DEFINE_VIRT_MACHINE(4, 2) 3292 3293 static void virt_machine_4_1_options(MachineClass *mc) 3294 { 3295 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3296 3297 virt_machine_4_2_options(mc); 3298 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 3299 vmc->no_ged = true; 3300 mc->auto_enable_numa_with_memhp = false; 3301 } 3302 DEFINE_VIRT_MACHINE(4, 1) 3303 3304 static void virt_machine_4_0_options(MachineClass *mc) 3305 { 3306 virt_machine_4_1_options(mc); 3307 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 3308 } 3309 DEFINE_VIRT_MACHINE(4, 0) 3310 3311 static void virt_machine_3_1_options(MachineClass *mc) 3312 { 3313 virt_machine_4_0_options(mc); 3314 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 3315 } 3316 DEFINE_VIRT_MACHINE(3, 1) 3317 3318 static void virt_machine_3_0_options(MachineClass *mc) 3319 { 3320 virt_machine_3_1_options(mc); 3321 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 3322 } 3323 DEFINE_VIRT_MACHINE(3, 0) 3324 3325 static void virt_machine_2_12_options(MachineClass *mc) 3326 { 3327 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3328 3329 virt_machine_3_0_options(mc); 3330 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 3331 vmc->no_highmem_ecam = true; 3332 mc->max_cpus = 255; 3333 } 3334 DEFINE_VIRT_MACHINE(2, 12) 3335 3336 static void virt_machine_2_11_options(MachineClass *mc) 3337 { 3338 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3339 3340 virt_machine_2_12_options(mc); 3341 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 3342 vmc->smbios_old_sys_ver = true; 3343 } 3344 DEFINE_VIRT_MACHINE(2, 11) 3345 3346 static void virt_machine_2_10_options(MachineClass *mc) 3347 { 3348 virt_machine_2_11_options(mc); 3349 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 3350 /* before 2.11 we never faulted accesses to bad addresses */ 3351 mc->ignore_memory_transaction_failures = true; 3352 } 3353 DEFINE_VIRT_MACHINE(2, 10) 3354 3355 static void virt_machine_2_9_options(MachineClass *mc) 3356 { 3357 virt_machine_2_10_options(mc); 3358 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 3359 } 3360 DEFINE_VIRT_MACHINE(2, 9) 3361 3362 static void virt_machine_2_8_options(MachineClass *mc) 3363 { 3364 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3365 3366 virt_machine_2_9_options(mc); 3367 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 3368 /* For 2.8 and earlier we falsely claimed in the DT that 3369 * our timers were edge-triggered, not level-triggered. 3370 */ 3371 vmc->claim_edge_triggered_timers = true; 3372 } 3373 DEFINE_VIRT_MACHINE(2, 8) 3374 3375 static void virt_machine_2_7_options(MachineClass *mc) 3376 { 3377 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3378 3379 virt_machine_2_8_options(mc); 3380 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 3381 /* ITS was introduced with 2.8 */ 3382 vmc->no_its = true; 3383 /* Stick with 1K pages for migration compatibility */ 3384 mc->minimum_page_bits = 0; 3385 } 3386 DEFINE_VIRT_MACHINE(2, 7) 3387 3388 static void virt_machine_2_6_options(MachineClass *mc) 3389 { 3390 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); 3391 3392 virt_machine_2_7_options(mc); 3393 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 3394 vmc->disallow_affinity_adjustment = true; 3395 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ 3396 vmc->no_pmu = true; 3397 } 3398 DEFINE_VIRT_MACHINE(2, 6) 3399