12a6a4076SMarkus Armbruster #ifndef STRONGARM_H 22a6a4076SMarkus Armbruster #define STRONGARM_H 347b43a1fSPaolo Bonzini 447b43a1fSPaolo Bonzini #include "exec/memory.h" 5fcf5ef2aSThomas Huth #include "target/arm/cpu-qom.h" 647b43a1fSPaolo Bonzini 747b43a1fSPaolo Bonzini #define SA_CS0 0x00000000 847b43a1fSPaolo Bonzini #define SA_CS1 0x08000000 947b43a1fSPaolo Bonzini #define SA_CS2 0x10000000 1047b43a1fSPaolo Bonzini #define SA_CS3 0x18000000 1147b43a1fSPaolo Bonzini #define SA_PCMCIA_CS0 0x20000000 1247b43a1fSPaolo Bonzini #define SA_PCMCIA_CS1 0x30000000 1347b43a1fSPaolo Bonzini #define SA_CS4 0x40000000 1447b43a1fSPaolo Bonzini #define SA_CS5 0x48000000 1547b43a1fSPaolo Bonzini /* system registers here */ 1647b43a1fSPaolo Bonzini #define SA_SDCS0 0xc0000000 1747b43a1fSPaolo Bonzini #define SA_SDCS1 0xc8000000 1847b43a1fSPaolo Bonzini #define SA_SDCS2 0xd0000000 1947b43a1fSPaolo Bonzini #define SA_SDCS3 0xd8000000 2047b43a1fSPaolo Bonzini 2147b43a1fSPaolo Bonzini enum { 2247b43a1fSPaolo Bonzini SA_PIC_GPIO0_EDGE = 0, 2347b43a1fSPaolo Bonzini SA_PIC_GPIO1_EDGE, 2447b43a1fSPaolo Bonzini SA_PIC_GPIO2_EDGE, 2547b43a1fSPaolo Bonzini SA_PIC_GPIO3_EDGE, 2647b43a1fSPaolo Bonzini SA_PIC_GPIO4_EDGE, 2747b43a1fSPaolo Bonzini SA_PIC_GPIO5_EDGE, 2847b43a1fSPaolo Bonzini SA_PIC_GPIO6_EDGE, 2947b43a1fSPaolo Bonzini SA_PIC_GPIO7_EDGE, 3047b43a1fSPaolo Bonzini SA_PIC_GPIO8_EDGE, 3147b43a1fSPaolo Bonzini SA_PIC_GPIO9_EDGE, 3247b43a1fSPaolo Bonzini SA_PIC_GPIO10_EDGE, 3347b43a1fSPaolo Bonzini SA_PIC_GPIOX_EDGE, 3447b43a1fSPaolo Bonzini SA_PIC_LCD, 3547b43a1fSPaolo Bonzini SA_PIC_UDC, 3647b43a1fSPaolo Bonzini SA_PIC_RSVD1, 3747b43a1fSPaolo Bonzini SA_PIC_UART1, 3847b43a1fSPaolo Bonzini SA_PIC_UART2, 3947b43a1fSPaolo Bonzini SA_PIC_UART3, 4047b43a1fSPaolo Bonzini SA_PIC_MCP, 4147b43a1fSPaolo Bonzini SA_PIC_SSP, 4247b43a1fSPaolo Bonzini SA_PIC_DMA_CH0, 4347b43a1fSPaolo Bonzini SA_PIC_DMA_CH1, 4447b43a1fSPaolo Bonzini SA_PIC_DMA_CH2, 4547b43a1fSPaolo Bonzini SA_PIC_DMA_CH3, 4647b43a1fSPaolo Bonzini SA_PIC_DMA_CH4, 4747b43a1fSPaolo Bonzini SA_PIC_DMA_CH5, 4847b43a1fSPaolo Bonzini SA_PIC_OSTC0, 4947b43a1fSPaolo Bonzini SA_PIC_OSTC1, 5047b43a1fSPaolo Bonzini SA_PIC_OSTC2, 5147b43a1fSPaolo Bonzini SA_PIC_OSTC3, 5247b43a1fSPaolo Bonzini SA_PIC_RTC_HZ, 5347b43a1fSPaolo Bonzini SA_PIC_RTC_ALARM, 5447b43a1fSPaolo Bonzini }; 5547b43a1fSPaolo Bonzini 5647b43a1fSPaolo Bonzini typedef struct { 5747b43a1fSPaolo Bonzini ARMCPU *cpu; 5847b43a1fSPaolo Bonzini DeviceState *pic; 5947b43a1fSPaolo Bonzini DeviceState *gpio; 6047b43a1fSPaolo Bonzini DeviceState *ppc; 6147b43a1fSPaolo Bonzini DeviceState *ssp; 6247b43a1fSPaolo Bonzini SSIBus *ssp_bus; 6347b43a1fSPaolo Bonzini } StrongARMState; 6447b43a1fSPaolo Bonzini 65*3cd892daSPhilippe Mathieu-Daudé StrongARMState *sa1110_init(const char *cpu_type); 6647b43a1fSPaolo Bonzini 6747b43a1fSPaolo Bonzini #endif 68