1 /* 2 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX6 SOC emulation. 5 * 6 * Based on hw/arm/fsl-imx31.c 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "hw/arm/fsl-imx6.h" 25 #include "hw/usb/imx-usb-phy.h" 26 #include "hw/boards.h" 27 #include "hw/qdev-properties.h" 28 #include "sysemu/sysemu.h" 29 #include "chardev/char.h" 30 #include "qemu/error-report.h" 31 #include "qemu/module.h" 32 33 #define IMX6_ESDHC_CAPABILITIES 0x057834b4 34 35 #define NAME_SIZE 20 36 37 static void fsl_imx6_init(Object *obj) 38 { 39 MachineState *ms = MACHINE(qdev_get_machine()); 40 FslIMX6State *s = FSL_IMX6(obj); 41 char name[NAME_SIZE]; 42 int i; 43 44 for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) { 45 snprintf(name, NAME_SIZE, "cpu%d", i); 46 object_initialize_child(obj, name, &s->cpu[i], 47 ARM_CPU_TYPE_NAME("cortex-a9")); 48 } 49 50 sysbus_init_child_obj(obj, "a9mpcore", &s->a9mpcore, sizeof(s->a9mpcore), 51 TYPE_A9MPCORE_PRIV); 52 53 sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX6_CCM); 54 55 sysbus_init_child_obj(obj, "src", &s->src, sizeof(s->src), TYPE_IMX6_SRC); 56 57 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { 58 snprintf(name, NAME_SIZE, "uart%d", i + 1); 59 sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]), 60 TYPE_IMX_SERIAL); 61 } 62 63 sysbus_init_child_obj(obj, "gpt", &s->gpt, sizeof(s->gpt), TYPE_IMX6_GPT); 64 65 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { 66 snprintf(name, NAME_SIZE, "epit%d", i + 1); 67 sysbus_init_child_obj(obj, name, &s->epit[i], sizeof(s->epit[i]), 68 TYPE_IMX_EPIT); 69 } 70 71 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { 72 snprintf(name, NAME_SIZE, "i2c%d", i + 1); 73 sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]), 74 TYPE_IMX_I2C); 75 } 76 77 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { 78 snprintf(name, NAME_SIZE, "gpio%d", i + 1); 79 sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]), 80 TYPE_IMX_GPIO); 81 } 82 83 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { 84 snprintf(name, NAME_SIZE, "sdhc%d", i + 1); 85 sysbus_init_child_obj(obj, name, &s->esdhc[i], sizeof(s->esdhc[i]), 86 TYPE_IMX_USDHC); 87 } 88 89 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) { 90 snprintf(name, NAME_SIZE, "usbphy%d", i); 91 sysbus_init_child_obj(obj, name, &s->usbphy[i], sizeof(s->usbphy[i]), 92 TYPE_IMX_USBPHY); 93 } 94 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) { 95 snprintf(name, NAME_SIZE, "usb%d", i); 96 sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]), 97 TYPE_CHIPIDEA); 98 } 99 100 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { 101 snprintf(name, NAME_SIZE, "spi%d", i + 1); 102 sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]), 103 TYPE_IMX_SPI); 104 } 105 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) { 106 snprintf(name, NAME_SIZE, "wdt%d", i); 107 sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]), 108 TYPE_IMX2_WDT); 109 } 110 111 112 sysbus_init_child_obj(obj, "eth", &s->eth, sizeof(s->eth), TYPE_IMX_ENET); 113 } 114 115 static void fsl_imx6_realize(DeviceState *dev, Error **errp) 116 { 117 MachineState *ms = MACHINE(qdev_get_machine()); 118 FslIMX6State *s = FSL_IMX6(dev); 119 uint16_t i; 120 Error *err = NULL; 121 unsigned int smp_cpus = ms->smp.cpus; 122 123 if (smp_cpus > FSL_IMX6_NUM_CPUS) { 124 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", 125 TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus); 126 return; 127 } 128 129 for (i = 0; i < smp_cpus; i++) { 130 131 /* On uniprocessor, the CBAR is set to 0 */ 132 if (smp_cpus > 1) { 133 object_property_set_int(OBJECT(&s->cpu[i]), FSL_IMX6_A9MPCORE_ADDR, 134 "reset-cbar", &error_abort); 135 } 136 137 /* All CPU but CPU 0 start in power off mode */ 138 if (i) { 139 object_property_set_bool(OBJECT(&s->cpu[i]), true, 140 "start-powered-off", &error_abort); 141 } 142 143 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); 144 if (err) { 145 error_propagate(errp, err); 146 return; 147 } 148 } 149 150 object_property_set_int(OBJECT(&s->a9mpcore), smp_cpus, "num-cpu", 151 &error_abort); 152 153 object_property_set_int(OBJECT(&s->a9mpcore), 154 FSL_IMX6_MAX_IRQ + GIC_INTERNAL, "num-irq", 155 &error_abort); 156 157 object_property_set_bool(OBJECT(&s->a9mpcore), true, "realized", &err); 158 if (err) { 159 error_propagate(errp, err); 160 return; 161 } 162 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR); 163 164 for (i = 0; i < smp_cpus; i++) { 165 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, 166 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); 167 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus, 168 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); 169 } 170 171 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err); 172 if (err) { 173 error_propagate(errp, err); 174 return; 175 } 176 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR); 177 178 object_property_set_bool(OBJECT(&s->src), true, "realized", &err); 179 if (err) { 180 error_propagate(errp, err); 181 return; 182 } 183 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR); 184 185 /* Initialize all UARTs */ 186 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { 187 static const struct { 188 hwaddr addr; 189 unsigned int irq; 190 } serial_table[FSL_IMX6_NUM_UARTS] = { 191 { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ }, 192 { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ }, 193 { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ }, 194 { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ }, 195 { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ }, 196 }; 197 198 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 199 200 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 201 if (err) { 202 error_propagate(errp, err); 203 return; 204 } 205 206 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 207 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 208 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 209 serial_table[i].irq)); 210 } 211 212 s->gpt.ccm = IMX_CCM(&s->ccm); 213 214 object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err); 215 if (err) { 216 error_propagate(errp, err); 217 return; 218 } 219 220 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR); 221 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, 222 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 223 FSL_IMX6_GPT_IRQ)); 224 225 /* Initialize all EPIT timers */ 226 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { 227 static const struct { 228 hwaddr addr; 229 unsigned int irq; 230 } epit_table[FSL_IMX6_NUM_EPITS] = { 231 { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ }, 232 { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ }, 233 }; 234 235 s->epit[i].ccm = IMX_CCM(&s->ccm); 236 237 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err); 238 if (err) { 239 error_propagate(errp, err); 240 return; 241 } 242 243 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 244 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 245 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 246 epit_table[i].irq)); 247 } 248 249 /* Initialize all I2C */ 250 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { 251 static const struct { 252 hwaddr addr; 253 unsigned int irq; 254 } i2c_table[FSL_IMX6_NUM_I2CS] = { 255 { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ }, 256 { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ }, 257 { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ } 258 }; 259 260 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err); 261 if (err) { 262 error_propagate(errp, err); 263 return; 264 } 265 266 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 267 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 268 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 269 i2c_table[i].irq)); 270 } 271 272 /* Initialize all GPIOs */ 273 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { 274 static const struct { 275 hwaddr addr; 276 unsigned int irq_low; 277 unsigned int irq_high; 278 } gpio_table[FSL_IMX6_NUM_GPIOS] = { 279 { 280 FSL_IMX6_GPIO1_ADDR, 281 FSL_IMX6_GPIO1_LOW_IRQ, 282 FSL_IMX6_GPIO1_HIGH_IRQ 283 }, 284 { 285 FSL_IMX6_GPIO2_ADDR, 286 FSL_IMX6_GPIO2_LOW_IRQ, 287 FSL_IMX6_GPIO2_HIGH_IRQ 288 }, 289 { 290 FSL_IMX6_GPIO3_ADDR, 291 FSL_IMX6_GPIO3_LOW_IRQ, 292 FSL_IMX6_GPIO3_HIGH_IRQ 293 }, 294 { 295 FSL_IMX6_GPIO4_ADDR, 296 FSL_IMX6_GPIO4_LOW_IRQ, 297 FSL_IMX6_GPIO4_HIGH_IRQ 298 }, 299 { 300 FSL_IMX6_GPIO5_ADDR, 301 FSL_IMX6_GPIO5_LOW_IRQ, 302 FSL_IMX6_GPIO5_HIGH_IRQ 303 }, 304 { 305 FSL_IMX6_GPIO6_ADDR, 306 FSL_IMX6_GPIO6_LOW_IRQ, 307 FSL_IMX6_GPIO6_HIGH_IRQ 308 }, 309 { 310 FSL_IMX6_GPIO7_ADDR, 311 FSL_IMX6_GPIO7_LOW_IRQ, 312 FSL_IMX6_GPIO7_HIGH_IRQ 313 }, 314 }; 315 316 object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-edge-sel", 317 &error_abort); 318 object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-upper-pin-irq", 319 &error_abort); 320 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err); 321 if (err) { 322 error_propagate(errp, err); 323 return; 324 } 325 326 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); 327 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 328 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 329 gpio_table[i].irq_low)); 330 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, 331 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 332 gpio_table[i].irq_high)); 333 } 334 335 /* Initialize all SDHC */ 336 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { 337 static const struct { 338 hwaddr addr; 339 unsigned int irq; 340 } esdhc_table[FSL_IMX6_NUM_ESDHCS] = { 341 { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ }, 342 { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ }, 343 { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ }, 344 { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ }, 345 }; 346 347 /* UHS-I SDIO3.0 SDR104 1.8V ADMA */ 348 object_property_set_uint(OBJECT(&s->esdhc[i]), 3, "sd-spec-version", 349 &err); 350 object_property_set_uint(OBJECT(&s->esdhc[i]), IMX6_ESDHC_CAPABILITIES, 351 "capareg", &err); 352 object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err); 353 if (err) { 354 error_propagate(errp, err); 355 return; 356 } 357 sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); 358 sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, 359 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 360 esdhc_table[i].irq)); 361 } 362 363 /* USB */ 364 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) { 365 object_property_set_bool(OBJECT(&s->usbphy[i]), true, "realized", 366 &error_abort); 367 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0, 368 FSL_IMX6_USBPHY1_ADDR + i * 0x1000); 369 } 370 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) { 371 static const int FSL_IMX6_USBn_IRQ[] = { 372 FSL_IMX6_USB_OTG_IRQ, 373 FSL_IMX6_USB_HOST1_IRQ, 374 FSL_IMX6_USB_HOST2_IRQ, 375 FSL_IMX6_USB_HOST3_IRQ, 376 }; 377 378 object_property_set_bool(OBJECT(&s->usb[i]), true, "realized", 379 &error_abort); 380 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, 381 FSL_IMX6_USBOH3_USB_ADDR + i * 0x200); 382 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, 383 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 384 FSL_IMX6_USBn_IRQ[i])); 385 } 386 387 /* Initialize all ECSPI */ 388 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { 389 static const struct { 390 hwaddr addr; 391 unsigned int irq; 392 } spi_table[FSL_IMX6_NUM_ECSPIS] = { 393 { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ }, 394 { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ }, 395 { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ }, 396 { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ }, 397 { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ }, 398 }; 399 400 /* Initialize the SPI */ 401 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); 402 if (err) { 403 error_propagate(errp, err); 404 return; 405 } 406 407 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr); 408 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 409 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 410 spi_table[i].irq)); 411 } 412 413 qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]); 414 object_property_set_bool(OBJECT(&s->eth), true, "realized", &err); 415 if (err) { 416 error_propagate(errp, err); 417 return; 418 } 419 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR); 420 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0, 421 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 422 FSL_IMX6_ENET_MAC_IRQ)); 423 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1, 424 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 425 FSL_IMX6_ENET_MAC_1588_IRQ)); 426 427 /* 428 * Watchdog 429 */ 430 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) { 431 static const hwaddr FSL_IMX6_WDOGn_ADDR[FSL_IMX6_NUM_WDTS] = { 432 FSL_IMX6_WDOG1_ADDR, 433 FSL_IMX6_WDOG2_ADDR, 434 }; 435 static const int FSL_IMX6_WDOGn_IRQ[FSL_IMX6_NUM_WDTS] = { 436 FSL_IMX6_WDOG1_IRQ, 437 FSL_IMX6_WDOG2_IRQ, 438 }; 439 440 object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support", 441 &error_abort); 442 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", 443 &error_abort); 444 445 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]); 446 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, 447 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 448 FSL_IMX6_WDOGn_IRQ[i])); 449 } 450 451 /* ROM memory */ 452 memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom", 453 FSL_IMX6_ROM_SIZE, &err); 454 if (err) { 455 error_propagate(errp, err); 456 return; 457 } 458 memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR, 459 &s->rom); 460 461 /* CAAM memory */ 462 memory_region_init_rom(&s->caam, OBJECT(dev), "imx6.caam", 463 FSL_IMX6_CAAM_MEM_SIZE, &err); 464 if (err) { 465 error_propagate(errp, err); 466 return; 467 } 468 memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR, 469 &s->caam); 470 471 /* OCRAM memory */ 472 memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE, 473 &err); 474 if (err) { 475 error_propagate(errp, err); 476 return; 477 } 478 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR, 479 &s->ocram); 480 481 /* internal OCRAM (256 KB) is aliased over 1 MB */ 482 memory_region_init_alias(&s->ocram_alias, OBJECT(dev), "imx6.ocram_alias", 483 &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE); 484 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR, 485 &s->ocram_alias); 486 } 487 488 static void fsl_imx6_class_init(ObjectClass *oc, void *data) 489 { 490 DeviceClass *dc = DEVICE_CLASS(oc); 491 492 dc->realize = fsl_imx6_realize; 493 dc->desc = "i.MX6 SOC"; 494 /* Reason: Uses serial_hd() in the realize() function */ 495 dc->user_creatable = false; 496 } 497 498 static const TypeInfo fsl_imx6_type_info = { 499 .name = TYPE_FSL_IMX6, 500 .parent = TYPE_DEVICE, 501 .instance_size = sizeof(FslIMX6State), 502 .instance_init = fsl_imx6_init, 503 .class_init = fsl_imx6_class_init, 504 }; 505 506 static void fsl_imx6_register_types(void) 507 { 508 type_register_static(&fsl_imx6_type_info); 509 } 510 511 type_init(fsl_imx6_register_types) 512