1 /* 2 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX6 SOC emulation. 5 * 6 * Based on hw/arm/fsl-imx31.c 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "qemu-common.h" 25 #include "hw/arm/fsl-imx6.h" 26 #include "sysemu/sysemu.h" 27 #include "chardev/char.h" 28 #include "qemu/error-report.h" 29 30 #define IMX6_ESDHC_CAPABILITIES 0x057834b4 31 32 #define NAME_SIZE 20 33 34 static void fsl_imx6_init(Object *obj) 35 { 36 FslIMX6State *s = FSL_IMX6(obj); 37 char name[NAME_SIZE]; 38 int i; 39 40 for (i = 0; i < MIN(smp_cpus, FSL_IMX6_NUM_CPUS); i++) { 41 object_initialize(&s->cpu[i], sizeof(s->cpu[i]), 42 "cortex-a9-" TYPE_ARM_CPU); 43 snprintf(name, NAME_SIZE, "cpu%d", i); 44 object_property_add_child(obj, name, OBJECT(&s->cpu[i]), NULL); 45 } 46 47 object_initialize(&s->a9mpcore, sizeof(s->a9mpcore), TYPE_A9MPCORE_PRIV); 48 qdev_set_parent_bus(DEVICE(&s->a9mpcore), sysbus_get_default()); 49 object_property_add_child(obj, "a9mpcore", OBJECT(&s->a9mpcore), NULL); 50 51 object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX6_CCM); 52 qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default()); 53 object_property_add_child(obj, "ccm", OBJECT(&s->ccm), NULL); 54 55 object_initialize(&s->src, sizeof(s->src), TYPE_IMX6_SRC); 56 qdev_set_parent_bus(DEVICE(&s->src), sysbus_get_default()); 57 object_property_add_child(obj, "src", OBJECT(&s->src), NULL); 58 59 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { 60 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL); 61 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); 62 snprintf(name, NAME_SIZE, "uart%d", i + 1); 63 object_property_add_child(obj, name, OBJECT(&s->uart[i]), NULL); 64 } 65 66 object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX6_GPT); 67 qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default()); 68 object_property_add_child(obj, "gpt", OBJECT(&s->gpt), NULL); 69 70 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { 71 object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT); 72 qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default()); 73 snprintf(name, NAME_SIZE, "epit%d", i + 1); 74 object_property_add_child(obj, name, OBJECT(&s->epit[i]), NULL); 75 } 76 77 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { 78 object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C); 79 qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default()); 80 snprintf(name, NAME_SIZE, "i2c%d", i + 1); 81 object_property_add_child(obj, name, OBJECT(&s->i2c[i]), NULL); 82 } 83 84 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { 85 object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO); 86 qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default()); 87 snprintf(name, NAME_SIZE, "gpio%d", i + 1); 88 object_property_add_child(obj, name, OBJECT(&s->gpio[i]), NULL); 89 } 90 91 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { 92 object_initialize(&s->esdhc[i], sizeof(s->esdhc[i]), TYPE_IMX_USDHC); 93 qdev_set_parent_bus(DEVICE(&s->esdhc[i]), sysbus_get_default()); 94 snprintf(name, NAME_SIZE, "sdhc%d", i + 1); 95 object_property_add_child(obj, name, OBJECT(&s->esdhc[i]), NULL); 96 } 97 98 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { 99 object_initialize(&s->spi[i], sizeof(s->spi[i]), TYPE_IMX_SPI); 100 qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); 101 snprintf(name, NAME_SIZE, "spi%d", i + 1); 102 object_property_add_child(obj, name, OBJECT(&s->spi[i]), NULL); 103 } 104 105 object_initialize(&s->eth, sizeof(s->eth), TYPE_IMX_ENET); 106 qdev_set_parent_bus(DEVICE(&s->eth), sysbus_get_default()); 107 object_property_add_child(obj, "eth", OBJECT(&s->eth), NULL); 108 } 109 110 static void fsl_imx6_realize(DeviceState *dev, Error **errp) 111 { 112 FslIMX6State *s = FSL_IMX6(dev); 113 uint16_t i; 114 Error *err = NULL; 115 116 if (smp_cpus > FSL_IMX6_NUM_CPUS) { 117 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", 118 TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus); 119 return; 120 } 121 122 for (i = 0; i < smp_cpus; i++) { 123 124 /* On uniprocessor, the CBAR is set to 0 */ 125 if (smp_cpus > 1) { 126 object_property_set_int(OBJECT(&s->cpu[i]), FSL_IMX6_A9MPCORE_ADDR, 127 "reset-cbar", &error_abort); 128 } 129 130 /* All CPU but CPU 0 start in power off mode */ 131 if (i) { 132 object_property_set_bool(OBJECT(&s->cpu[i]), true, 133 "start-powered-off", &error_abort); 134 } 135 136 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); 137 if (err) { 138 error_propagate(errp, err); 139 return; 140 } 141 } 142 143 object_property_set_int(OBJECT(&s->a9mpcore), smp_cpus, "num-cpu", 144 &error_abort); 145 146 object_property_set_int(OBJECT(&s->a9mpcore), 147 FSL_IMX6_MAX_IRQ + GIC_INTERNAL, "num-irq", 148 &error_abort); 149 150 object_property_set_bool(OBJECT(&s->a9mpcore), true, "realized", &err); 151 if (err) { 152 error_propagate(errp, err); 153 return; 154 } 155 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR); 156 157 for (i = 0; i < smp_cpus; i++) { 158 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, 159 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); 160 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus, 161 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); 162 } 163 164 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err); 165 if (err) { 166 error_propagate(errp, err); 167 return; 168 } 169 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR); 170 171 object_property_set_bool(OBJECT(&s->src), true, "realized", &err); 172 if (err) { 173 error_propagate(errp, err); 174 return; 175 } 176 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR); 177 178 /* Initialize all UARTs */ 179 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { 180 static const struct { 181 hwaddr addr; 182 unsigned int irq; 183 } serial_table[FSL_IMX6_NUM_UARTS] = { 184 { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ }, 185 { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ }, 186 { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ }, 187 { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ }, 188 { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ }, 189 }; 190 191 if (i < MAX_SERIAL_PORTS) { 192 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 193 } 194 195 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 196 if (err) { 197 error_propagate(errp, err); 198 return; 199 } 200 201 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 202 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 203 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 204 serial_table[i].irq)); 205 } 206 207 s->gpt.ccm = IMX_CCM(&s->ccm); 208 209 object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err); 210 if (err) { 211 error_propagate(errp, err); 212 return; 213 } 214 215 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR); 216 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, 217 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 218 FSL_IMX6_GPT_IRQ)); 219 220 /* Initialize all EPIT timers */ 221 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { 222 static const struct { 223 hwaddr addr; 224 unsigned int irq; 225 } epit_table[FSL_IMX6_NUM_EPITS] = { 226 { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ }, 227 { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ }, 228 }; 229 230 s->epit[i].ccm = IMX_CCM(&s->ccm); 231 232 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err); 233 if (err) { 234 error_propagate(errp, err); 235 return; 236 } 237 238 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 239 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 240 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 241 epit_table[i].irq)); 242 } 243 244 /* Initialize all I2C */ 245 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { 246 static const struct { 247 hwaddr addr; 248 unsigned int irq; 249 } i2c_table[FSL_IMX6_NUM_I2CS] = { 250 { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ }, 251 { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ }, 252 { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ } 253 }; 254 255 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err); 256 if (err) { 257 error_propagate(errp, err); 258 return; 259 } 260 261 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 262 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 263 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 264 i2c_table[i].irq)); 265 } 266 267 /* Initialize all GPIOs */ 268 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { 269 static const struct { 270 hwaddr addr; 271 unsigned int irq_low; 272 unsigned int irq_high; 273 } gpio_table[FSL_IMX6_NUM_GPIOS] = { 274 { 275 FSL_IMX6_GPIO1_ADDR, 276 FSL_IMX6_GPIO1_LOW_IRQ, 277 FSL_IMX6_GPIO1_HIGH_IRQ 278 }, 279 { 280 FSL_IMX6_GPIO2_ADDR, 281 FSL_IMX6_GPIO2_LOW_IRQ, 282 FSL_IMX6_GPIO2_HIGH_IRQ 283 }, 284 { 285 FSL_IMX6_GPIO3_ADDR, 286 FSL_IMX6_GPIO3_LOW_IRQ, 287 FSL_IMX6_GPIO3_HIGH_IRQ 288 }, 289 { 290 FSL_IMX6_GPIO4_ADDR, 291 FSL_IMX6_GPIO4_LOW_IRQ, 292 FSL_IMX6_GPIO4_HIGH_IRQ 293 }, 294 { 295 FSL_IMX6_GPIO5_ADDR, 296 FSL_IMX6_GPIO5_LOW_IRQ, 297 FSL_IMX6_GPIO5_HIGH_IRQ 298 }, 299 { 300 FSL_IMX6_GPIO6_ADDR, 301 FSL_IMX6_GPIO6_LOW_IRQ, 302 FSL_IMX6_GPIO6_HIGH_IRQ 303 }, 304 { 305 FSL_IMX6_GPIO7_ADDR, 306 FSL_IMX6_GPIO7_LOW_IRQ, 307 FSL_IMX6_GPIO7_HIGH_IRQ 308 }, 309 }; 310 311 object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-edge-sel", 312 &error_abort); 313 object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-upper-pin-irq", 314 &error_abort); 315 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err); 316 if (err) { 317 error_propagate(errp, err); 318 return; 319 } 320 321 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); 322 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 323 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 324 gpio_table[i].irq_low)); 325 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, 326 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 327 gpio_table[i].irq_high)); 328 } 329 330 /* Initialize all SDHC */ 331 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { 332 static const struct { 333 hwaddr addr; 334 unsigned int irq; 335 } esdhc_table[FSL_IMX6_NUM_ESDHCS] = { 336 { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ }, 337 { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ }, 338 { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ }, 339 { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ }, 340 }; 341 342 /* UHS-I SDIO3.0 SDR104 1.8V ADMA */ 343 object_property_set_uint(OBJECT(&s->esdhc[i]), 3, "sd-spec-version", 344 &err); 345 object_property_set_uint(OBJECT(&s->esdhc[i]), IMX6_ESDHC_CAPABILITIES, 346 "capareg", &err); 347 object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err); 348 if (err) { 349 error_propagate(errp, err); 350 return; 351 } 352 sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); 353 sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, 354 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 355 esdhc_table[i].irq)); 356 } 357 358 /* Initialize all ECSPI */ 359 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { 360 static const struct { 361 hwaddr addr; 362 unsigned int irq; 363 } spi_table[FSL_IMX6_NUM_ECSPIS] = { 364 { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ }, 365 { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ }, 366 { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ }, 367 { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ }, 368 { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ }, 369 }; 370 371 /* Initialize the SPI */ 372 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); 373 if (err) { 374 error_propagate(errp, err); 375 return; 376 } 377 378 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr); 379 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 380 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 381 spi_table[i].irq)); 382 } 383 384 qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]); 385 object_property_set_bool(OBJECT(&s->eth), true, "realized", &err); 386 if (err) { 387 error_propagate(errp, err); 388 return; 389 } 390 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR); 391 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0, 392 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 393 FSL_IMX6_ENET_MAC_IRQ)); 394 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1, 395 qdev_get_gpio_in(DEVICE(&s->a9mpcore), 396 FSL_IMX6_ENET_MAC_1588_IRQ)); 397 398 /* ROM memory */ 399 memory_region_init_rom(&s->rom, NULL, "imx6.rom", 400 FSL_IMX6_ROM_SIZE, &err); 401 if (err) { 402 error_propagate(errp, err); 403 return; 404 } 405 memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR, 406 &s->rom); 407 408 /* CAAM memory */ 409 memory_region_init_rom(&s->caam, NULL, "imx6.caam", 410 FSL_IMX6_CAAM_MEM_SIZE, &err); 411 if (err) { 412 error_propagate(errp, err); 413 return; 414 } 415 memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR, 416 &s->caam); 417 418 /* OCRAM memory */ 419 memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE, 420 &err); 421 if (err) { 422 error_propagate(errp, err); 423 return; 424 } 425 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR, 426 &s->ocram); 427 428 /* internal OCRAM (256 KB) is aliased over 1 MB */ 429 memory_region_init_alias(&s->ocram_alias, NULL, "imx6.ocram_alias", 430 &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE); 431 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR, 432 &s->ocram_alias); 433 } 434 435 static void fsl_imx6_class_init(ObjectClass *oc, void *data) 436 { 437 DeviceClass *dc = DEVICE_CLASS(oc); 438 439 dc->realize = fsl_imx6_realize; 440 dc->desc = "i.MX6 SOC"; 441 /* Reason: Uses serial_hd() in the realize() function */ 442 dc->user_creatable = false; 443 } 444 445 static const TypeInfo fsl_imx6_type_info = { 446 .name = TYPE_FSL_IMX6, 447 .parent = TYPE_DEVICE, 448 .instance_size = sizeof(FslIMX6State), 449 .instance_init = fsl_imx6_init, 450 .class_init = fsl_imx6_class_init, 451 }; 452 453 static void fsl_imx6_register_types(void) 454 { 455 type_register_static(&fsl_imx6_type_info); 456 } 457 458 type_init(fsl_imx6_register_types) 459