1 /* 2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX31 SOC emulation. 5 * 6 * Based on hw/arm/fsl-imx31.c 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "qemu-common.h" 25 #include "cpu.h" 26 #include "hw/arm/fsl-imx31.h" 27 #include "sysemu/sysemu.h" 28 #include "exec/address-spaces.h" 29 #include "hw/boards.h" 30 #include "chardev/char.h" 31 32 static void fsl_imx31_init(Object *obj) 33 { 34 FslIMX31State *s = FSL_IMX31(obj); 35 int i; 36 37 object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU); 38 39 object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC); 40 qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default()); 41 42 object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX31_CCM); 43 qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default()); 44 45 for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) { 46 object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL); 47 qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); 48 } 49 50 object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX31_GPT); 51 qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default()); 52 53 for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) { 54 object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT); 55 qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default()); 56 } 57 58 for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) { 59 object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C); 60 qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default()); 61 } 62 63 for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) { 64 object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO); 65 qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default()); 66 } 67 } 68 69 static void fsl_imx31_realize(DeviceState *dev, Error **errp) 70 { 71 FslIMX31State *s = FSL_IMX31(dev); 72 uint16_t i; 73 Error *err = NULL; 74 75 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); 76 if (err) { 77 error_propagate(errp, err); 78 return; 79 } 80 81 object_property_set_bool(OBJECT(&s->avic), true, "realized", &err); 82 if (err) { 83 error_propagate(errp, err); 84 return; 85 } 86 sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR); 87 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0, 88 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); 89 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1, 90 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); 91 92 object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err); 93 if (err) { 94 error_propagate(errp, err); 95 return; 96 } 97 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR); 98 99 /* Initialize all UARTS */ 100 for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) { 101 static const struct { 102 hwaddr addr; 103 unsigned int irq; 104 } serial_table[FSL_IMX31_NUM_UARTS] = { 105 { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ }, 106 { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ }, 107 }; 108 109 if (i < MAX_SERIAL_PORTS) { 110 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 111 } 112 113 object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); 114 if (err) { 115 error_propagate(errp, err); 116 return; 117 } 118 119 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); 120 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 121 qdev_get_gpio_in(DEVICE(&s->avic), 122 serial_table[i].irq)); 123 } 124 125 s->gpt.ccm = IMX_CCM(&s->ccm); 126 127 object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err); 128 if (err) { 129 error_propagate(errp, err); 130 return; 131 } 132 133 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR); 134 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, 135 qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ)); 136 137 /* Initialize all EPIT timers */ 138 for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) { 139 static const struct { 140 hwaddr addr; 141 unsigned int irq; 142 } epit_table[FSL_IMX31_NUM_EPITS] = { 143 { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ }, 144 { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ }, 145 }; 146 147 s->epit[i].ccm = IMX_CCM(&s->ccm); 148 149 object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err); 150 if (err) { 151 error_propagate(errp, err); 152 return; 153 } 154 155 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); 156 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 157 qdev_get_gpio_in(DEVICE(&s->avic), 158 epit_table[i].irq)); 159 } 160 161 /* Initialize all I2C */ 162 for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) { 163 static const struct { 164 hwaddr addr; 165 unsigned int irq; 166 } i2c_table[FSL_IMX31_NUM_I2CS] = { 167 { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ }, 168 { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ }, 169 { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ } 170 }; 171 172 /* Initialize the I2C */ 173 object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err); 174 if (err) { 175 error_propagate(errp, err); 176 return; 177 } 178 /* Map I2C memory */ 179 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); 180 /* Connect I2C IRQ to PIC */ 181 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 182 qdev_get_gpio_in(DEVICE(&s->avic), 183 i2c_table[i].irq)); 184 } 185 186 /* Initialize all GPIOs */ 187 for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) { 188 static const struct { 189 hwaddr addr; 190 unsigned int irq; 191 } gpio_table[FSL_IMX31_NUM_GPIOS] = { 192 { FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ }, 193 { FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ }, 194 { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ } 195 }; 196 197 object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel", 198 &error_abort); 199 object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err); 200 if (err) { 201 error_propagate(errp, err); 202 return; 203 } 204 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); 205 /* Connect GPIO IRQ to PIC */ 206 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 207 qdev_get_gpio_in(DEVICE(&s->avic), 208 gpio_table[i].irq)); 209 } 210 211 /* On a real system, the first 16k is a `secure boot rom' */ 212 memory_region_init_rom(&s->secure_rom, NULL, "imx31.secure_rom", 213 FSL_IMX31_SECURE_ROM_SIZE, &err); 214 if (err) { 215 error_propagate(errp, err); 216 return; 217 } 218 memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR, 219 &s->secure_rom); 220 221 /* There is also a 16k ROM */ 222 memory_region_init_rom(&s->rom, NULL, "imx31.rom", 223 FSL_IMX31_ROM_SIZE, &err); 224 if (err) { 225 error_propagate(errp, err); 226 return; 227 } 228 memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR, 229 &s->rom); 230 231 /* initialize internal RAM (16 KB) */ 232 memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE, 233 &err); 234 if (err) { 235 error_propagate(errp, err); 236 return; 237 } 238 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR, 239 &s->iram); 240 241 /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */ 242 memory_region_init_alias(&s->iram_alias, NULL, "imx31.iram_alias", 243 &s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE); 244 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR, 245 &s->iram_alias); 246 } 247 248 static void fsl_imx31_class_init(ObjectClass *oc, void *data) 249 { 250 DeviceClass *dc = DEVICE_CLASS(oc); 251 252 dc->realize = fsl_imx31_realize; 253 dc->desc = "i.MX31 SOC"; 254 /* 255 * Reason: uses serial_hds in realize and the kzm board does not 256 * support multiple CPUs 257 */ 258 dc->user_creatable = false; 259 } 260 261 static const TypeInfo fsl_imx31_type_info = { 262 .name = TYPE_FSL_IMX31, 263 .parent = TYPE_DEVICE, 264 .instance_size = sizeof(FslIMX31State), 265 .instance_init = fsl_imx31_init, 266 .class_init = fsl_imx31_class_init, 267 }; 268 269 static void fsl_imx31_register_types(void) 270 { 271 type_register_static(&fsl_imx31_type_info); 272 } 273 274 type_init(fsl_imx31_register_types) 275