1 /* 2 * Raspberry Pi emulation (c) 2012 Gregory Estrade 3 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous 4 * 5 * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft 6 * Written by Andrew Baumann 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "qemu/module.h" 15 #include "cpu.h" 16 #include "hw/arm/bcm2836.h" 17 #include "hw/arm/raspi_platform.h" 18 #include "hw/sysbus.h" 19 20 struct BCM283XInfo { 21 const char *name; 22 const char *cpu_type; 23 hwaddr peri_base; /* Peripheral base address seen by the CPU */ 24 hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */ 25 int clusterid; 26 }; 27 28 static const BCM283XInfo bcm283x_socs[] = { 29 { 30 .name = TYPE_BCM2836, 31 .cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"), 32 .peri_base = 0x3f000000, 33 .ctrl_base = 0x40000000, 34 .clusterid = 0xf, 35 }, 36 #ifdef TARGET_AARCH64 37 { 38 .name = TYPE_BCM2837, 39 .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"), 40 .peri_base = 0x3f000000, 41 .ctrl_base = 0x40000000, 42 .clusterid = 0x0, 43 }, 44 #endif 45 }; 46 47 static void bcm2836_init(Object *obj) 48 { 49 BCM283XState *s = BCM283X(obj); 50 BCM283XClass *bc = BCM283X_GET_CLASS(obj); 51 const BCM283XInfo *info = bc->info; 52 int n; 53 54 for (n = 0; n < BCM283X_NCPUS; n++) { 55 object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, 56 info->cpu_type); 57 } 58 59 sysbus_init_child_obj(obj, "control", &s->control, sizeof(s->control), 60 TYPE_BCM2836_CONTROL); 61 62 sysbus_init_child_obj(obj, "peripherals", &s->peripherals, 63 sizeof(s->peripherals), TYPE_BCM2835_PERIPHERALS); 64 object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals), 65 "board-rev"); 66 object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals), 67 "vcram-size"); 68 } 69 70 static void bcm2836_realize(DeviceState *dev, Error **errp) 71 { 72 BCM283XState *s = BCM283X(dev); 73 BCM283XClass *bc = BCM283X_GET_CLASS(dev); 74 const BCM283XInfo *info = bc->info; 75 Object *obj; 76 Error *err = NULL; 77 int n; 78 79 /* common peripherals from bcm2835 */ 80 81 obj = object_property_get_link(OBJECT(dev), "ram", &err); 82 if (obj == NULL) { 83 error_setg(errp, "%s: required ram link not found: %s", 84 __func__, error_get_pretty(err)); 85 return; 86 } 87 88 object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj); 89 90 object_property_set_bool(OBJECT(&s->peripherals), true, "realized", &err); 91 if (err) { 92 error_propagate(errp, err); 93 return; 94 } 95 96 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals), 97 "sd-bus"); 98 99 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0, 100 info->peri_base, 1); 101 102 /* bcm2836 interrupt controller (and mailboxes, etc.) */ 103 object_property_set_bool(OBJECT(&s->control), true, "realized", &err); 104 if (err) { 105 error_propagate(errp, err); 106 return; 107 } 108 109 sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, info->ctrl_base); 110 111 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, 112 qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0)); 113 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, 114 qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); 115 116 for (n = 0; n < BCM283X_NCPUS; n++) { 117 /* TODO: this should be converted to a property of ARM_CPU */ 118 s->cpu[n].core.mp_affinity = (info->clusterid << 8) | n; 119 120 /* set periphbase/CBAR value for CPU-local registers */ 121 object_property_set_int(OBJECT(&s->cpu[n].core), 122 info->peri_base, 123 "reset-cbar", &err); 124 if (err) { 125 error_propagate(errp, err); 126 return; 127 } 128 129 /* start powered off if not enabled */ 130 object_property_set_bool(OBJECT(&s->cpu[n].core), n >= s->enabled_cpus, 131 "start-powered-off", &err); 132 if (err) { 133 error_propagate(errp, err); 134 return; 135 } 136 137 object_property_set_bool(OBJECT(&s->cpu[n].core), true, 138 "realized", &err); 139 if (err) { 140 error_propagate(errp, err); 141 return; 142 } 143 144 /* Connect irq/fiq outputs from the interrupt controller. */ 145 qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n, 146 qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ)); 147 qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n, 148 qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ)); 149 150 /* Connect timers from the CPU to the interrupt controller */ 151 qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS, 152 qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n)); 153 qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT, 154 qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n)); 155 qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP, 156 qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n)); 157 qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC, 158 qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n)); 159 } 160 } 161 162 static Property bcm2836_props[] = { 163 DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 164 BCM283X_NCPUS), 165 DEFINE_PROP_END_OF_LIST() 166 }; 167 168 static void bcm283x_class_init(ObjectClass *oc, void *data) 169 { 170 DeviceClass *dc = DEVICE_CLASS(oc); 171 BCM283XClass *bc = BCM283X_CLASS(oc); 172 173 bc->info = data; 174 dc->realize = bcm2836_realize; 175 device_class_set_props(dc, bcm2836_props); 176 /* Reason: Must be wired up in code (see raspi_init() function) */ 177 dc->user_creatable = false; 178 } 179 180 static const TypeInfo bcm283x_type_info = { 181 .name = TYPE_BCM283X, 182 .parent = TYPE_DEVICE, 183 .instance_size = sizeof(BCM283XState), 184 .instance_init = bcm2836_init, 185 .class_size = sizeof(BCM283XClass), 186 .abstract = true, 187 }; 188 189 static void bcm2836_register_types(void) 190 { 191 int i; 192 193 type_register_static(&bcm283x_type_info); 194 for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) { 195 TypeInfo ti = { 196 .name = bcm283x_socs[i].name, 197 .parent = TYPE_BCM283X, 198 .class_init = bcm283x_class_init, 199 .class_data = (void *) &bcm283x_socs[i], 200 }; 201 type_register(&ti); 202 } 203 } 204 205 type_init(bcm2836_register_types) 206