1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * Jeremy Kerr <jk@ozlabs.org> 6 * 7 * Copyright 2016 IBM Corp. 8 * 9 * This code is licensed under the GPL version 2 or later. See 10 * the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/units.h" 15 #include "qapi/error.h" 16 #include "hw/misc/unimp.h" 17 #include "hw/arm/aspeed_soc.h" 18 #include "hw/char/serial-mm.h" 19 #include "qemu/module.h" 20 #include "qemu/error-report.h" 21 #include "hw/i2c/aspeed_i2c.h" 22 #include "net/net.h" 23 #include "sysemu/sysemu.h" 24 #include "target/arm/cpu-qom.h" 25 26 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 27 28 static const hwaddr aspeed_soc_ast2400_memmap[] = { 29 [ASPEED_DEV_SPI_BOOT] = 0x00000000, 30 [ASPEED_DEV_IOMEM] = 0x1E600000, 31 [ASPEED_DEV_FMC] = 0x1E620000, 32 [ASPEED_DEV_SPI1] = 0x1E630000, 33 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 34 [ASPEED_DEV_UHCI] = 0x1E6B0000, 35 [ASPEED_DEV_VIC] = 0x1E6C0000, 36 [ASPEED_DEV_SDMC] = 0x1E6E0000, 37 [ASPEED_DEV_SCU] = 0x1E6E2000, 38 [ASPEED_DEV_HACE] = 0x1E6E3000, 39 [ASPEED_DEV_GFX] = 0x1E6E6000, 40 [ASPEED_DEV_XDMA] = 0x1E6E7000, 41 [ASPEED_DEV_VIDEO] = 0x1E700000, 42 [ASPEED_DEV_ADC] = 0x1E6E9000, 43 [ASPEED_DEV_SRAM] = 0x1E720000, 44 [ASPEED_DEV_SDHCI] = 0x1E740000, 45 [ASPEED_DEV_GPIO] = 0x1E780000, 46 [ASPEED_DEV_RTC] = 0x1E781000, 47 [ASPEED_DEV_TIMER1] = 0x1E782000, 48 [ASPEED_DEV_WDT] = 0x1E785000, 49 [ASPEED_DEV_PWM] = 0x1E786000, 50 [ASPEED_DEV_LPC] = 0x1E789000, 51 [ASPEED_DEV_IBT] = 0x1E789140, 52 [ASPEED_DEV_I2C] = 0x1E78A000, 53 [ASPEED_DEV_PECI] = 0x1E78B000, 54 [ASPEED_DEV_ETH1] = 0x1E660000, 55 [ASPEED_DEV_ETH2] = 0x1E680000, 56 [ASPEED_DEV_UART1] = 0x1E783000, 57 [ASPEED_DEV_UART2] = 0x1E78D000, 58 [ASPEED_DEV_UART3] = 0x1E78E000, 59 [ASPEED_DEV_UART4] = 0x1E78F000, 60 [ASPEED_DEV_UART5] = 0x1E784000, 61 [ASPEED_DEV_VUART] = 0x1E787000, 62 [ASPEED_DEV_SDRAM] = 0x40000000, 63 }; 64 65 static const hwaddr aspeed_soc_ast2500_memmap[] = { 66 [ASPEED_DEV_SPI_BOOT] = 0x00000000, 67 [ASPEED_DEV_IOMEM] = 0x1E600000, 68 [ASPEED_DEV_FMC] = 0x1E620000, 69 [ASPEED_DEV_SPI1] = 0x1E630000, 70 [ASPEED_DEV_SPI2] = 0x1E631000, 71 [ASPEED_DEV_EHCI1] = 0x1E6A1000, 72 [ASPEED_DEV_EHCI2] = 0x1E6A3000, 73 [ASPEED_DEV_UHCI] = 0x1E6B0000, 74 [ASPEED_DEV_VIC] = 0x1E6C0000, 75 [ASPEED_DEV_SDMC] = 0x1E6E0000, 76 [ASPEED_DEV_SCU] = 0x1E6E2000, 77 [ASPEED_DEV_HACE] = 0x1E6E3000, 78 [ASPEED_DEV_GFX] = 0x1E6E6000, 79 [ASPEED_DEV_XDMA] = 0x1E6E7000, 80 [ASPEED_DEV_ADC] = 0x1E6E9000, 81 [ASPEED_DEV_VIDEO] = 0x1E700000, 82 [ASPEED_DEV_SRAM] = 0x1E720000, 83 [ASPEED_DEV_SDHCI] = 0x1E740000, 84 [ASPEED_DEV_GPIO] = 0x1E780000, 85 [ASPEED_DEV_RTC] = 0x1E781000, 86 [ASPEED_DEV_TIMER1] = 0x1E782000, 87 [ASPEED_DEV_WDT] = 0x1E785000, 88 [ASPEED_DEV_PWM] = 0x1E786000, 89 [ASPEED_DEV_LPC] = 0x1E789000, 90 [ASPEED_DEV_IBT] = 0x1E789140, 91 [ASPEED_DEV_I2C] = 0x1E78A000, 92 [ASPEED_DEV_PECI] = 0x1E78B000, 93 [ASPEED_DEV_ETH1] = 0x1E660000, 94 [ASPEED_DEV_ETH2] = 0x1E680000, 95 [ASPEED_DEV_UART1] = 0x1E783000, 96 [ASPEED_DEV_UART2] = 0x1E78D000, 97 [ASPEED_DEV_UART3] = 0x1E78E000, 98 [ASPEED_DEV_UART4] = 0x1E78F000, 99 [ASPEED_DEV_UART5] = 0x1E784000, 100 [ASPEED_DEV_VUART] = 0x1E787000, 101 [ASPEED_DEV_SDRAM] = 0x80000000, 102 }; 103 104 static const int aspeed_soc_ast2400_irqmap[] = { 105 [ASPEED_DEV_UART1] = 9, 106 [ASPEED_DEV_UART2] = 32, 107 [ASPEED_DEV_UART3] = 33, 108 [ASPEED_DEV_UART4] = 34, 109 [ASPEED_DEV_UART5] = 10, 110 [ASPEED_DEV_VUART] = 8, 111 [ASPEED_DEV_FMC] = 19, 112 [ASPEED_DEV_EHCI1] = 5, 113 [ASPEED_DEV_EHCI2] = 13, 114 [ASPEED_DEV_UHCI] = 14, 115 [ASPEED_DEV_SDMC] = 0, 116 [ASPEED_DEV_SCU] = 21, 117 [ASPEED_DEV_ADC] = 31, 118 [ASPEED_DEV_GFX] = 25, 119 [ASPEED_DEV_GPIO] = 20, 120 [ASPEED_DEV_RTC] = 22, 121 [ASPEED_DEV_TIMER1] = 16, 122 [ASPEED_DEV_TIMER2] = 17, 123 [ASPEED_DEV_TIMER3] = 18, 124 [ASPEED_DEV_TIMER4] = 35, 125 [ASPEED_DEV_TIMER5] = 36, 126 [ASPEED_DEV_TIMER6] = 37, 127 [ASPEED_DEV_TIMER7] = 38, 128 [ASPEED_DEV_TIMER8] = 39, 129 [ASPEED_DEV_WDT] = 27, 130 [ASPEED_DEV_PWM] = 28, 131 [ASPEED_DEV_LPC] = 8, 132 [ASPEED_DEV_I2C] = 12, 133 [ASPEED_DEV_PECI] = 15, 134 [ASPEED_DEV_ETH1] = 2, 135 [ASPEED_DEV_ETH2] = 3, 136 [ASPEED_DEV_XDMA] = 6, 137 [ASPEED_DEV_SDHCI] = 26, 138 [ASPEED_DEV_HACE] = 4, 139 }; 140 141 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap 142 143 static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev) 144 { 145 Aspeed2400SoCState *a = ASPEED2400_SOC(s); 146 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 147 148 return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]); 149 } 150 151 static void aspeed_ast2400_soc_init(Object *obj) 152 { 153 Aspeed2400SoCState *a = ASPEED2400_SOC(obj); 154 AspeedSoCState *s = ASPEED_SOC(obj); 155 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 156 int i; 157 char socname[8]; 158 char typename[64]; 159 160 if (sscanf(sc->name, "%7s", socname) != 1) { 161 g_assert_not_reached(); 162 } 163 164 for (i = 0; i < sc->num_cpus; i++) { 165 object_initialize_child(obj, "cpu[*]", &a->cpu[i], 166 aspeed_soc_cpu_type(sc)); 167 } 168 169 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); 170 object_initialize_child(obj, "scu", &s->scu, typename); 171 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", 172 sc->silicon_rev); 173 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), 174 "hw-strap1"); 175 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), 176 "hw-strap2"); 177 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), 178 "hw-prot-key"); 179 180 object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC); 181 182 object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); 183 184 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); 185 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); 186 187 for (i = 0; i < sc->wdts_num; i++) { 188 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); 189 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); 190 } 191 192 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); 193 object_initialize_child(obj, "adc", &s->adc, typename); 194 195 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); 196 object_initialize_child(obj, "i2c", &s->i2c, typename); 197 198 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); 199 200 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); 201 object_initialize_child(obj, "fmc", &s->fmc, typename); 202 203 for (i = 0; i < sc->spis_num; i++) { 204 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); 205 object_initialize_child(obj, "spi[*]", &s->spi[i], typename); 206 } 207 208 for (i = 0; i < sc->ehcis_num; i++) { 209 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 210 TYPE_PLATFORM_EHCI); 211 } 212 213 object_initialize_child(obj, "uhci", &s->uhci, TYPE_ASPEED_UHCI); 214 215 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); 216 object_initialize_child(obj, "sdmc", &s->sdmc, typename); 217 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), 218 "ram-size"); 219 220 for (i = 0; i < sc->macs_num; i++) { 221 object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], 222 TYPE_FTGMAC100); 223 } 224 225 for (i = 0; i < sc->uarts_num; i++) { 226 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); 227 } 228 229 snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); 230 object_initialize_child(obj, "xdma", &s->xdma, typename); 231 232 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); 233 object_initialize_child(obj, "gpio", &s->gpio, typename); 234 235 object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI); 236 237 object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); 238 239 /* Init sd card slot class here so that they're under the correct parent */ 240 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { 241 object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i], 242 TYPE_SYSBUS_SDHCI); 243 } 244 245 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); 246 247 snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); 248 object_initialize_child(obj, "hace", &s->hace, typename); 249 250 object_initialize_child(obj, "gfx", &s->gfx, TYPE_ASPEED_GFX); 251 252 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); 253 object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); 254 255 object_initialize_child(obj, "pwm", &s->pwm, TYPE_ASPEED_PWM); 256 } 257 258 static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp) 259 { 260 int i; 261 Aspeed2400SoCState *a = ASPEED2400_SOC(dev); 262 AspeedSoCState *s = ASPEED_SOC(dev); 263 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 264 g_autofree char *sram_name = NULL; 265 266 /* Default boot region (SPI memory or ROMs) */ 267 memory_region_init(&s->spi_boot_container, OBJECT(s), 268 "aspeed.spi_boot_container", 0x10000000); 269 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], 270 &s->spi_boot_container); 271 272 /* IO space */ 273 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", 274 sc->memmap[ASPEED_DEV_IOMEM], 275 ASPEED_SOC_IOMEM_SIZE); 276 277 /* Video engine stub */ 278 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", 279 sc->memmap[ASPEED_DEV_VIDEO], 0x1000); 280 281 /* CPU */ 282 for (i = 0; i < sc->num_cpus; i++) { 283 object_property_set_link(OBJECT(&a->cpu[i]), "memory", 284 OBJECT(s->memory), &error_abort); 285 if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { 286 return; 287 } 288 } 289 290 /* SRAM */ 291 sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); 292 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, 293 errp)) { 294 return; 295 } 296 memory_region_add_subregion(s->memory, 297 sc->memmap[ASPEED_DEV_SRAM], &s->sram); 298 299 /* SCU */ 300 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { 301 return; 302 } 303 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); 304 305 /* VIC */ 306 if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) { 307 return; 308 } 309 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]); 310 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0, 311 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ)); 312 sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1, 313 qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ)); 314 315 /* RTC */ 316 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { 317 return; 318 } 319 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); 320 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, 321 aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); 322 323 /* Timer */ 324 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), 325 &error_abort); 326 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { 327 return; 328 } 329 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, 330 sc->memmap[ASPEED_DEV_TIMER1]); 331 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 332 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); 333 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); 334 } 335 336 /* Watch dog */ 337 for (i = 0; i < sc->wdts_num; i++) { 338 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); 339 340 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), 341 &error_abort); 342 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { 343 return; 344 } 345 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, 346 sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize); 347 } 348 349 /* ADC */ 350 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { 351 return; 352 } 353 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); 354 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, 355 aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); 356 357 /* UART */ 358 if (!aspeed_soc_uart_realize(s, errp)) { 359 return; 360 } 361 362 /* I2C */ 363 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), 364 &error_abort); 365 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { 366 return; 367 } 368 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); 369 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0, 370 aspeed_soc_get_irq(s, ASPEED_DEV_I2C)); 371 372 /* PECI */ 373 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { 374 return; 375 } 376 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, 377 sc->memmap[ASPEED_DEV_PECI]); 378 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, 379 aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); 380 381 /* FMC, The number of CS is set at the board level */ 382 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), 383 &error_abort); 384 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { 385 return; 386 } 387 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); 388 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, 389 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); 390 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, 391 aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); 392 393 /* Set up an alias on the FMC CE0 region (boot default) */ 394 MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; 395 memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", 396 fmc0_mmio, 0, memory_region_size(fmc0_mmio)); 397 memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); 398 399 /* SPI */ 400 for (i = 0; i < sc->spis_num; i++) { 401 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { 402 return; 403 } 404 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, 405 sc->memmap[ASPEED_DEV_SPI1 + i]); 406 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, 407 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); 408 } 409 410 /* EHCI */ 411 for (i = 0; i < sc->ehcis_num; i++) { 412 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { 413 return; 414 } 415 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, 416 sc->memmap[ASPEED_DEV_EHCI1 + i]); 417 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 418 aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); 419 } 420 421 /* UHCI */ 422 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uhci), errp)) { 423 return; 424 } 425 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->uhci), 0, 426 sc->memmap[ASPEED_DEV_UHCI]); 427 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uhci), 0, 428 aspeed_soc_get_irq(s, ASPEED_DEV_UHCI)); 429 430 /* SDMC - SDRAM Memory Controller */ 431 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { 432 return; 433 } 434 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, 435 sc->memmap[ASPEED_DEV_SDMC]); 436 437 /* RAM */ 438 if (!aspeed_soc_dram_init(s, errp)) { 439 return; 440 } 441 442 /* Net */ 443 for (i = 0; i < sc->macs_num; i++) { 444 object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, 445 &error_abort); 446 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { 447 return; 448 } 449 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 450 sc->memmap[ASPEED_DEV_ETH1 + i]); 451 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, 452 aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); 453 } 454 455 /* XDMA */ 456 if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { 457 return; 458 } 459 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, 460 sc->memmap[ASPEED_DEV_XDMA]); 461 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, 462 aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); 463 464 /* GPIO */ 465 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 466 return; 467 } 468 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, 469 sc->memmap[ASPEED_DEV_GPIO]); 470 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, 471 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); 472 473 /* SDHCI */ 474 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { 475 return; 476 } 477 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, 478 sc->memmap[ASPEED_DEV_SDHCI]); 479 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 480 aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); 481 482 /* LPC */ 483 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { 484 return; 485 } 486 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); 487 488 /* Connect the LPC IRQ to the VIC */ 489 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, 490 aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); 491 492 /* 493 * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the 494 * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by 495 * contrast, on the AST2600, the subdevice IRQs are connected straight to 496 * the GIC). 497 * 498 * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output 499 * to the VIC is at offset 0. 500 */ 501 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, 502 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1)); 503 504 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, 505 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2)); 506 507 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, 508 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3)); 509 510 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, 511 qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4)); 512 513 /* HACE */ 514 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), 515 &error_abort); 516 if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { 517 return; 518 } 519 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, 520 sc->memmap[ASPEED_DEV_HACE]); 521 sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, 522 aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); 523 524 /* GFX */ 525 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gfx), errp)) { 526 return; 527 } 528 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gfx), 0, sc->memmap[ASPEED_DEV_GFX]); 529 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gfx), 0, 530 aspeed_soc_get_irq(s, ASPEED_DEV_GFX)); 531 532 /* PWM */ 533 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm), errp)) { 534 return; 535 } 536 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->pwm), 0, sc->memmap[ASPEED_DEV_PWM]); 537 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm), 0, 538 aspeed_soc_get_irq(s, ASPEED_DEV_PWM)); 539 } 540 541 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) 542 { 543 static const char * const valid_cpu_types[] = { 544 ARM_CPU_TYPE_NAME("arm926"), 545 NULL 546 }; 547 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 548 DeviceClass *dc = DEVICE_CLASS(oc); 549 550 dc->realize = aspeed_ast2400_soc_realize; 551 /* Reason: Uses serial_hds and nd_table in realize() directly */ 552 dc->user_creatable = false; 553 554 sc->name = "ast2400-a1"; 555 sc->valid_cpu_types = valid_cpu_types; 556 sc->silicon_rev = AST2400_A1_SILICON_REV; 557 sc->sram_size = 0x8000; 558 sc->spis_num = 1; 559 sc->ehcis_num = 1; 560 sc->wdts_num = 2; 561 sc->macs_num = 2; 562 sc->uarts_num = 5; 563 sc->uarts_base = ASPEED_DEV_UART1; 564 sc->irqmap = aspeed_soc_ast2400_irqmap; 565 sc->memmap = aspeed_soc_ast2400_memmap; 566 sc->num_cpus = 1; 567 sc->get_irq = aspeed_soc_ast2400_get_irq; 568 } 569 570 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) 571 { 572 static const char * const valid_cpu_types[] = { 573 ARM_CPU_TYPE_NAME("arm1176"), 574 NULL 575 }; 576 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); 577 DeviceClass *dc = DEVICE_CLASS(oc); 578 579 dc->realize = aspeed_ast2400_soc_realize; 580 /* Reason: Uses serial_hds and nd_table in realize() directly */ 581 dc->user_creatable = false; 582 583 sc->name = "ast2500-a1"; 584 sc->valid_cpu_types = valid_cpu_types; 585 sc->silicon_rev = AST2500_A1_SILICON_REV; 586 sc->sram_size = 0x9000; 587 sc->spis_num = 2; 588 sc->ehcis_num = 2; 589 sc->wdts_num = 3; 590 sc->macs_num = 2; 591 sc->uarts_num = 5; 592 sc->uarts_base = ASPEED_DEV_UART1; 593 sc->irqmap = aspeed_soc_ast2500_irqmap; 594 sc->memmap = aspeed_soc_ast2500_memmap; 595 sc->num_cpus = 1; 596 sc->get_irq = aspeed_soc_ast2400_get_irq; 597 } 598 599 static const TypeInfo aspeed_soc_ast2400_types[] = { 600 { 601 .name = TYPE_ASPEED2400_SOC, 602 .parent = TYPE_ASPEED_SOC, 603 .instance_init = aspeed_ast2400_soc_init, 604 .instance_size = sizeof(Aspeed2400SoCState), 605 .abstract = true, 606 }, { 607 .name = "ast2400-a1", 608 .parent = TYPE_ASPEED2400_SOC, 609 .class_init = aspeed_soc_ast2400_class_init, 610 }, { 611 .name = "ast2500-a1", 612 .parent = TYPE_ASPEED2400_SOC, 613 .class_init = aspeed_soc_ast2500_class_init, 614 }, 615 }; 616 617 DEFINE_TYPES(aspeed_soc_ast2400_types) 618