1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/arm/aspeed_eeprom.h" 18 #include "hw/block/flash.h" 19 #include "hw/i2c/i2c_mux_pca954x.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/gpio/pca9552.h" 22 #include "hw/nvram/eeprom_at24c.h" 23 #include "hw/sensor/tmp105.h" 24 #include "hw/misc/led.h" 25 #include "hw/qdev-properties.h" 26 #include "sysemu/block-backend.h" 27 #include "sysemu/reset.h" 28 #include "hw/loader.h" 29 #include "qemu/error-report.h" 30 #include "qemu/units.h" 31 #include "hw/qdev-clock.h" 32 #include "sysemu/sysemu.h" 33 34 static struct arm_boot_info aspeed_board_binfo = { 35 .board_id = -1, /* device-tree-only board */ 36 }; 37 38 struct AspeedMachineState { 39 /* Private */ 40 MachineState parent_obj; 41 /* Public */ 42 43 AspeedSoCState *soc; 44 MemoryRegion boot_rom; 45 bool mmio_exec; 46 uint32_t uart_chosen; 47 char *fmc_model; 48 char *spi_model; 49 uint32_t hw_strap1; 50 }; 51 52 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 53 #if HOST_LONG_BITS == 32 54 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB) 55 #else 56 #define ASPEED_RAM_SIZE(sz) (sz) 57 #endif 58 59 /* Palmetto hardware value: 0x120CE416 */ 60 #define PALMETTO_BMC_HW_STRAP1 ( \ 61 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 62 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 63 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 64 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 65 SCU_HW_STRAP_VGA_CLASS_CODE | \ 66 SCU_HW_STRAP_LPC_RESET_PIN | \ 67 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 68 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 69 SCU_HW_STRAP_SPI_WIDTH | \ 70 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 71 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 72 73 /* TODO: Find the actual hardware value */ 74 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 75 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 76 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 77 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 78 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 79 SCU_HW_STRAP_VGA_CLASS_CODE | \ 80 SCU_HW_STRAP_LPC_RESET_PIN | \ 81 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 82 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 83 SCU_HW_STRAP_SPI_WIDTH | \ 84 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 85 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 86 87 /* TODO: Find the actual hardware value */ 88 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ 89 AST2500_HW_STRAP1_DEFAULTS | \ 90 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 91 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 92 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 93 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 94 SCU_HW_STRAP_SPI_WIDTH | \ 95 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) 96 97 /* AST2500 evb hardware value: 0xF100C2E6 */ 98 #define AST2500_EVB_HW_STRAP1 (( \ 99 AST2500_HW_STRAP1_DEFAULTS | \ 100 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 101 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 102 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 103 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 104 SCU_HW_STRAP_MAC1_RGMII | \ 105 SCU_HW_STRAP_MAC0_RGMII) & \ 106 ~SCU_HW_STRAP_2ND_BOOT_WDT) 107 108 /* Romulus hardware value: 0xF10AD206 */ 109 #define ROMULUS_BMC_HW_STRAP1 ( \ 110 AST2500_HW_STRAP1_DEFAULTS | \ 111 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 112 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 113 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 114 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 115 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 116 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 117 118 /* Sonorapass hardware value: 0xF100D216 */ 119 #define SONORAPASS_BMC_HW_STRAP1 ( \ 120 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 121 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 122 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 123 SCU_AST2500_HW_STRAP_RESERVED28 | \ 124 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 125 SCU_HW_STRAP_VGA_CLASS_CODE | \ 126 SCU_HW_STRAP_LPC_RESET_PIN | \ 127 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 128 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 129 SCU_HW_STRAP_VGA_BIOS_ROM | \ 130 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 131 SCU_AST2500_HW_STRAP_RESERVED1) 132 133 #define G220A_BMC_HW_STRAP1 ( \ 134 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 135 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 136 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 137 SCU_AST2500_HW_STRAP_RESERVED28 | \ 138 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 139 SCU_HW_STRAP_2ND_BOOT_WDT | \ 140 SCU_HW_STRAP_VGA_CLASS_CODE | \ 141 SCU_HW_STRAP_LPC_RESET_PIN | \ 142 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 143 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 144 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 145 SCU_AST2500_HW_STRAP_RESERVED1) 146 147 /* FP5280G2 hardware value: 0XF100D286 */ 148 #define FP5280G2_BMC_HW_STRAP1 ( \ 149 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 150 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 151 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 152 SCU_AST2500_HW_STRAP_RESERVED28 | \ 153 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 154 SCU_HW_STRAP_VGA_CLASS_CODE | \ 155 SCU_HW_STRAP_LPC_RESET_PIN | \ 156 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 157 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 158 SCU_HW_STRAP_MAC1_RGMII | \ 159 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 160 SCU_AST2500_HW_STRAP_RESERVED1) 161 162 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 163 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 164 165 /* Quanta-Q71l hardware value */ 166 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 167 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 168 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 169 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 170 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 171 SCU_HW_STRAP_VGA_CLASS_CODE | \ 172 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 173 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 174 SCU_HW_STRAP_SPI_WIDTH | \ 175 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 176 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 177 178 /* AST2600 evb hardware value */ 179 #define AST2600_EVB_HW_STRAP1 0x000000C0 180 #define AST2600_EVB_HW_STRAP2 0x00000003 181 182 #ifdef TARGET_AARCH64 183 /* AST2700 evb hardware value */ 184 #define AST2700_EVB_HW_STRAP1 0x000000C0 185 #define AST2700_EVB_HW_STRAP2 0x00000003 186 #endif 187 188 /* Rainier hardware value: (QEMU prototype) */ 189 #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC) 190 #define RAINIER_BMC_HW_STRAP2 0x80000848 191 192 /* Fuji hardware value */ 193 #define FUJI_BMC_HW_STRAP1 0x00000000 194 #define FUJI_BMC_HW_STRAP2 0x00000000 195 196 /* Bletchley hardware value */ 197 /* TODO: Leave same as EVB for now. */ 198 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 199 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 200 201 /* Qualcomm DC-SCM hardware value */ 202 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 203 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 204 205 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 206 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 207 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 208 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 209 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 210 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 211 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 212 213 static void aspeed_write_smpboot(ARMCPU *cpu, 214 const struct arm_boot_info *info) 215 { 216 AddressSpace *as = arm_boot_address_space(cpu, info); 217 static const ARMInsnFixup poll_mailbox_ready[] = { 218 /* 219 * r2 = per-cpu go sign value 220 * r1 = AST_SMP_MBOX_FIELD_ENTRY 221 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 222 */ 223 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ 224 { 0xe21000ff }, /* ands r0, r0, #255 */ 225 { 0xe59f201c }, /* ldr r2, [pc, #28] */ 226 { 0xe1822000 }, /* orr r2, r2, r0 */ 227 228 { 0xe59f1018 }, /* ldr r1, [pc, #24] */ 229 { 0xe59f0018 }, /* ldr r0, [pc, #24] */ 230 231 { 0xe320f002 }, /* wfe */ 232 { 0xe5904000 }, /* ldr r4, [r0] */ 233 { 0xe1520004 }, /* cmp r2, r4 */ 234 { 0x1afffffb }, /* bne <wfe> */ 235 { 0xe591f000 }, /* ldr pc, [r1] */ 236 { AST_SMP_MBOX_GOSIGN }, 237 { AST_SMP_MBOX_FIELD_ENTRY }, 238 { AST_SMP_MBOX_FIELD_GOSIGN }, 239 { 0, FIXUP_TERMINATOR } 240 }; 241 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; 242 243 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, 244 poll_mailbox_ready, fixupcontext); 245 } 246 247 static void aspeed_reset_secondary(ARMCPU *cpu, 248 const struct arm_boot_info *info) 249 { 250 AddressSpace *as = arm_boot_address_space(cpu, info); 251 CPUState *cs = CPU(cpu); 252 253 /* info->smp_bootreg_addr */ 254 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 255 MEMTXATTRS_UNSPECIFIED, NULL); 256 cpu_set_pc(cs, info->smp_loader_start); 257 } 258 259 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size, 260 Error **errp) 261 { 262 g_autofree void *storage = NULL; 263 int64_t size; 264 265 /* 266 * The block backend size should have already been 'validated' by 267 * the creation of the m25p80 object. 268 */ 269 size = blk_getlength(blk); 270 if (size <= 0) { 271 error_setg(errp, "failed to get flash size"); 272 return; 273 } 274 275 if (rom_size > size) { 276 rom_size = size; 277 } 278 279 storage = g_malloc0(rom_size); 280 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { 281 error_setg(errp, "failed to read the initial flash content"); 282 return; 283 } 284 285 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 286 } 287 288 /* 289 * Create a ROM and copy the flash contents at the expected address 290 * (0x0). Boots faster than execute-in-place. 291 */ 292 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk, 293 uint64_t rom_size) 294 { 295 AspeedSoCState *soc = bmc->soc; 296 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc); 297 298 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size, 299 &error_abort); 300 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, 301 &bmc->boot_rom, 1); 302 write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT], 303 rom_size, &error_abort); 304 } 305 306 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 307 unsigned int count, int unit0) 308 { 309 int i; 310 311 if (!flashtype) { 312 return; 313 } 314 315 for (i = 0; i < count; ++i) { 316 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 317 DeviceState *dev; 318 319 dev = qdev_new(flashtype); 320 if (dinfo) { 321 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 322 } 323 qdev_prop_set_uint8(dev, "cs", i); 324 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 325 } 326 } 327 328 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc, 329 bool boot_emmc) 330 { 331 DeviceState *card; 332 333 if (!dinfo) { 334 return; 335 } 336 card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD); 337 338 /* 339 * Force the boot properties of the eMMC device only when the 340 * machine is strapped to boot from eMMC. Without these 341 * settings, the machine would not boot. 342 * 343 * This also allows the machine to use an eMMC device without 344 * boot areas when booting from the flash device (or -kernel) 345 * Ideally, the device and its properties should be defined on 346 * the command line. 347 */ 348 if (emmc && boot_emmc) { 349 qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB); 350 qdev_prop_set_uint8(card, "boot-config", 0x1 << 3); 351 } 352 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 353 &error_fatal); 354 qdev_realize_and_unref(card, 355 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 356 &error_fatal); 357 } 358 359 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) 360 { 361 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 362 AspeedSoCState *s = bmc->soc; 363 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 364 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 365 366 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); 367 for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) { 368 if (uart == uart_chosen) { 369 continue; 370 } 371 aspeed_soc_uart_set_chr(s, uart, serial_hd(i)); 372 } 373 } 374 375 static void aspeed_machine_init(MachineState *machine) 376 { 377 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 378 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 379 AspeedSoCClass *sc; 380 int i; 381 DriveInfo *emmc0 = NULL; 382 bool boot_emmc; 383 384 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 385 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 386 object_unref(OBJECT(bmc->soc)); 387 sc = ASPEED_SOC_GET_CLASS(bmc->soc); 388 389 /* 390 * This will error out if the RAM size is not supported by the 391 * memory controller of the SoC. 392 */ 393 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size, 394 &error_fatal); 395 396 for (i = 0; i < sc->macs_num; i++) { 397 if ((amc->macs_mask & (1 << i)) && 398 !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]), 399 true, NULL)) { 400 break; /* No configs left; stop asking */ 401 } 402 } 403 404 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", bmc->hw_strap1, 405 &error_abort); 406 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2, 407 &error_abort); 408 object_property_set_link(OBJECT(bmc->soc), "memory", 409 OBJECT(get_system_memory()), &error_abort); 410 object_property_set_link(OBJECT(bmc->soc), "dram", 411 OBJECT(machine->ram), &error_abort); 412 if (machine->kernel_filename) { 413 /* 414 * When booting with a -kernel command line there is no u-boot 415 * that runs to unlock the SCU. In this case set the default to 416 * be unlocked as the kernel expects 417 */ 418 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key", 419 ASPEED_SCU_PROT_KEY, &error_abort); 420 } 421 connect_serial_hds_to_uarts(bmc); 422 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 423 424 if (defaults_enabled()) { 425 aspeed_board_init_flashes(&bmc->soc->fmc, 426 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 427 amc->num_cs, 0); 428 aspeed_board_init_flashes(&bmc->soc->spi[0], 429 bmc->spi_model ? bmc->spi_model : amc->spi_model, 430 1, amc->num_cs); 431 } 432 433 if (machine->kernel_filename && sc->num_cpus > 1) { 434 /* With no u-boot we must set up a boot stub for the secondary CPU */ 435 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 436 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 437 0x80, &error_abort); 438 memory_region_add_subregion(get_system_memory(), 439 AST_SMP_MAILBOX_BASE, smpboot); 440 441 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 442 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 443 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 444 } 445 446 aspeed_board_binfo.ram_size = machine->ram_size; 447 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 448 449 if (amc->i2c_init) { 450 amc->i2c_init(bmc); 451 } 452 453 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { 454 sdhci_attach_drive(&bmc->soc->sdhci.slots[i], 455 drive_get(IF_SD, 0, i), false, false); 456 } 457 458 boot_emmc = sc->boot_from_emmc(bmc->soc); 459 460 if (bmc->soc->emmc.num_slots) { 461 emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots); 462 sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emmc); 463 } 464 465 if (!bmc->mmio_exec) { 466 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0); 467 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL; 468 469 if (fmc0 && !boot_emmc) { 470 uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot); 471 aspeed_install_boot_rom(bmc, fmc0, rom_size); 472 } else if (emmc0) { 473 aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(emmc0), 64 * KiB); 474 } 475 } 476 477 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 478 } 479 480 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 481 { 482 AspeedSoCState *soc = bmc->soc; 483 DeviceState *dev; 484 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 485 486 /* 487 * The palmetto platform expects a ds3231 RTC but a ds1338 is 488 * enough to provide basic RTC features. Alarms will be missing 489 */ 490 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 491 492 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 493 eeprom_buf); 494 495 /* add a TMP423 temperature sensor */ 496 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 497 "tmp423", 0x4c)); 498 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 499 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 500 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 501 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 502 } 503 504 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 505 { 506 AspeedSoCState *soc = bmc->soc; 507 508 /* 509 * The quanta-q71l platform expects tmp75s which are compatible with 510 * tmp105s. 511 */ 512 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 513 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 514 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 515 516 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 517 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 518 /* TODO: Add Memory Riser i2c mux and eeproms. */ 519 520 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 521 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 522 523 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 524 525 /* i2c-7 */ 526 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 527 /* - i2c@0: pmbus@59 */ 528 /* - i2c@1: pmbus@58 */ 529 /* - i2c@2: pmbus@58 */ 530 /* - i2c@3: pmbus@59 */ 531 532 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 533 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 534 } 535 536 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 537 { 538 AspeedSoCState *soc = bmc->soc; 539 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 540 541 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 542 eeprom_buf); 543 544 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 545 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 546 TYPE_TMP105, 0x4d); 547 } 548 549 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 550 { 551 AspeedSoCState *soc = bmc->soc; 552 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 553 554 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 555 eeprom_buf); 556 557 /* LM75 is compatible with TMP105 driver */ 558 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 559 TYPE_TMP105, 0x4d); 560 } 561 562 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) 563 { 564 AspeedSoCState *soc = bmc->soc; 565 566 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); 567 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB, 568 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len); 569 /* TMP421 */ 570 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f); 571 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e); 572 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f); 573 574 } 575 576 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 577 { 578 AspeedSoCState *soc = bmc->soc; 579 580 /* 581 * The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 582 * good enough 583 */ 584 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 585 } 586 587 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc) 588 { 589 AspeedSoCState *soc = bmc->soc; 590 591 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB); 592 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB, 593 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len); 594 /* TMP421 */ 595 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f); 596 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f); 597 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e); 598 } 599 600 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 601 { 602 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 603 TYPE_PCA9552, addr); 604 } 605 606 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 607 { 608 AspeedSoCState *soc = bmc->soc; 609 610 /* bus 2 : */ 611 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 612 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 613 /* bus 2 : pca9546 @ 0x73 */ 614 615 /* bus 3 : pca9548 @ 0x70 */ 616 617 /* bus 4 : */ 618 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 619 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 620 eeprom4_54); 621 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 622 create_pca9552(soc, 4, 0x76); 623 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 624 create_pca9552(soc, 4, 0x77); 625 626 /* bus 6 : */ 627 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 628 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 629 /* bus 6 : pca9546 @ 0x73 */ 630 631 /* bus 8 : */ 632 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 633 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 634 eeprom8_56); 635 create_pca9552(soc, 8, 0x60); 636 create_pca9552(soc, 8, 0x61); 637 /* bus 8 : adc128d818 @ 0x1d */ 638 /* bus 8 : adc128d818 @ 0x1f */ 639 640 /* 641 * bus 13 : pca9548 @ 0x71 642 * - channel 3: 643 * - tmm421 @ 0x4c 644 * - tmp421 @ 0x4e 645 * - tmp421 @ 0x4f 646 */ 647 648 } 649 650 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 651 { 652 static const struct { 653 unsigned gpio_id; 654 LEDColor color; 655 const char *description; 656 bool gpio_polarity; 657 } pca1_leds[] = { 658 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 659 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 660 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 661 }; 662 AspeedSoCState *soc = bmc->soc; 663 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 664 DeviceState *dev; 665 LEDState *led; 666 667 /* Bus 3: TODO bmp280@77 */ 668 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 669 qdev_prop_set_string(dev, "description", "pca1"); 670 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 671 aspeed_i2c_get_bus(&soc->i2c, 3), 672 &error_fatal); 673 674 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 675 led = led_create_simple(OBJECT(bmc), 676 pca1_leds[i].gpio_polarity, 677 pca1_leds[i].color, 678 pca1_leds[i].description); 679 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 680 qdev_get_gpio_in(DEVICE(led), 0)); 681 } 682 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 683 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52); 684 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 685 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 686 687 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 688 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 689 0x4a); 690 691 /* 692 * The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 693 * good enough 694 */ 695 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 696 697 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 698 eeprom_buf); 699 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 700 qdev_prop_set_string(dev, "description", "pca0"); 701 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 702 aspeed_i2c_get_bus(&soc->i2c, 11), 703 &error_fatal); 704 /* Bus 11: TODO ucd90160@64 */ 705 } 706 707 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 708 { 709 AspeedSoCState *soc = bmc->soc; 710 DeviceState *dev; 711 712 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 713 "emc1413", 0x4c)); 714 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 715 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 716 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 717 718 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 719 "emc1413", 0x4c)); 720 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 721 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 722 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 723 724 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 725 "emc1413", 0x4c)); 726 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 727 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 728 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 729 730 static uint8_t eeprom_buf[2 * 1024] = { 731 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 732 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 733 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 734 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 735 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 736 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 737 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 738 }; 739 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 740 eeprom_buf); 741 } 742 743 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 744 { 745 AspeedSoCState *soc = bmc->soc; 746 I2CSlave *i2c_mux; 747 748 /* The at24c256 */ 749 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 750 751 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 752 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 753 0x48); 754 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 755 0x49); 756 757 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 758 "pca9546", 0x70); 759 /* It expects a TMP112 but a TMP105 is compatible */ 760 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 761 0x4a); 762 763 /* It expects a ds3232 but a ds1338 is good enough */ 764 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 765 766 /* It expects a pca9555 but a pca9552 is compatible */ 767 create_pca9552(soc, 8, 0x30); 768 } 769 770 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 771 { 772 AspeedSoCState *soc = bmc->soc; 773 I2CSlave *i2c_mux; 774 775 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 776 777 create_pca9552(soc, 3, 0x61); 778 779 /* The rainier expects a TMP275 but a TMP105 is compatible */ 780 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 781 0x48); 782 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 783 0x49); 784 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 785 0x4a); 786 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 787 "pca9546", 0x70); 788 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 789 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 790 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 791 create_pca9552(soc, 4, 0x60); 792 793 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 794 0x48); 795 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 796 0x49); 797 create_pca9552(soc, 5, 0x60); 798 create_pca9552(soc, 5, 0x61); 799 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 800 "pca9546", 0x70); 801 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 802 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 803 804 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 805 0x48); 806 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 807 0x4a); 808 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 809 0x4b); 810 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 811 "pca9546", 0x70); 812 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 813 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 814 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 815 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 816 817 create_pca9552(soc, 7, 0x30); 818 create_pca9552(soc, 7, 0x31); 819 create_pca9552(soc, 7, 0x32); 820 create_pca9552(soc, 7, 0x33); 821 create_pca9552(soc, 7, 0x60); 822 create_pca9552(soc, 7, 0x61); 823 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 824 /* Bus 7: TODO si7021-a20@20 */ 825 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 826 0x48); 827 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52); 828 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 829 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 830 831 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 832 0x48); 833 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 834 0x4a); 835 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 836 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len); 837 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 838 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len); 839 create_pca9552(soc, 8, 0x60); 840 create_pca9552(soc, 8, 0x61); 841 /* Bus 8: ucd90320@11 */ 842 /* Bus 8: ucd90320@b */ 843 /* Bus 8: ucd90320@c */ 844 845 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 846 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 847 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 848 849 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 850 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 851 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 852 853 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 854 0x48); 855 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 856 0x49); 857 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 858 "pca9546", 0x70); 859 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 860 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 861 create_pca9552(soc, 11, 0x60); 862 863 864 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 865 create_pca9552(soc, 13, 0x60); 866 867 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 868 create_pca9552(soc, 14, 0x60); 869 870 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 871 create_pca9552(soc, 15, 0x60); 872 } 873 874 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 875 I2CBus **channels) 876 { 877 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 878 for (int i = 0; i < 8; i++) { 879 channels[i] = pca954x_i2c_get_bus(mux, i); 880 } 881 } 882 883 #define TYPE_LM75 TYPE_TMP105 884 #define TYPE_TMP75 TYPE_TMP105 885 #define TYPE_TMP422 "tmp422" 886 887 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 888 { 889 AspeedSoCState *soc = bmc->soc; 890 I2CBus *i2c[144] = {}; 891 892 for (int i = 0; i < 16; i++) { 893 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 894 } 895 I2CBus *i2c180 = i2c[2]; 896 I2CBus *i2c480 = i2c[8]; 897 I2CBus *i2c600 = i2c[11]; 898 899 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 900 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 901 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 902 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 903 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 904 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 905 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 906 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 907 for (int i = 0; i < 8; i++) { 908 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 909 } 910 911 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 912 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 913 914 /* 915 * EEPROM 24c64 size is 64Kbits or 8 Kbytes 916 * 24c02 size is 2Kbits or 256 bytes 917 */ 918 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB); 919 at24c_eeprom_init(i2c[20], 0x50, 256); 920 at24c_eeprom_init(i2c[22], 0x52, 256); 921 922 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 923 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 924 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 925 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 926 927 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB); 928 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 929 930 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 931 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB); 932 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 933 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 934 935 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 936 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 937 938 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB); 939 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 940 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 941 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB); 942 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB); 943 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB); 944 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB); 945 946 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB); 947 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 948 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 949 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB); 950 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB); 951 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB); 952 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB); 953 at24c_eeprom_init(i2c[28], 0x50, 256); 954 955 for (int i = 0; i < 8; i++) { 956 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 957 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 958 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 959 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 960 } 961 } 962 963 #define TYPE_TMP421 "tmp421" 964 965 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 966 { 967 AspeedSoCState *soc = bmc->soc; 968 I2CBus *i2c[13] = {}; 969 for (int i = 0; i < 13; i++) { 970 if ((i == 8) || (i == 11)) { 971 continue; 972 } 973 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 974 } 975 976 /* Bus 0 - 5 all have the same config. */ 977 for (int i = 0; i < 6; i++) { 978 /* Missing model: ti,ina230 @ 0x45 */ 979 /* Missing model: mps,mp5023 @ 0x40 */ 980 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 981 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 982 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 983 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 984 /* Missing model: fsc,fusb302 @ 0x22 */ 985 } 986 987 /* Bus 6 */ 988 at24c_eeprom_init(i2c[6], 0x56, 65536); 989 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 990 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 991 992 993 /* Bus 7 */ 994 at24c_eeprom_init(i2c[7], 0x54, 65536); 995 996 /* Bus 9 */ 997 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 998 999 /* Bus 10 */ 1000 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 1001 /* Missing model: ti,hdc1080 @ 0x40 */ 1002 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 1003 1004 /* Bus 12 */ 1005 /* Missing model: adi,adm1278 @ 0x11 */ 1006 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 1007 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 1008 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 1009 } 1010 1011 static void fby35_i2c_init(AspeedMachineState *bmc) 1012 { 1013 AspeedSoCState *soc = bmc->soc; 1014 I2CBus *i2c[16]; 1015 1016 for (int i = 0; i < 16; i++) { 1017 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1018 } 1019 1020 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); 1021 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); 1022 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ 1023 i2c_slave_create_simple(i2c[11], "adm1272", 0x44); 1024 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); 1025 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); 1026 1027 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB); 1028 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB); 1029 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid, 1030 fby35_nic_fruid_len); 1031 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid, 1032 fby35_bb_fruid_len); 1033 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid, 1034 fby35_bmc_fruid_len); 1035 1036 /* 1037 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on 1038 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on 1039 * each. 1040 */ 1041 } 1042 1043 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) 1044 { 1045 AspeedSoCState *soc = bmc->soc; 1046 1047 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); 1048 } 1049 1050 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) 1051 { 1052 AspeedSoCState *soc = bmc->soc; 1053 I2CSlave *therm_mux, *cpuvr_mux; 1054 1055 /* Create the generic DC-SCM hardware */ 1056 qcom_dc_scm_bmc_i2c_init(bmc); 1057 1058 /* Now create the Firework specific hardware */ 1059 1060 /* I2C7 CPUVR MUX */ 1061 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 1062 "pca9546", 0x70); 1063 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72); 1064 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72); 1065 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72); 1066 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72); 1067 1068 /* I2C8 Thermal Diodes*/ 1069 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 1070 "pca9548", 0x70); 1071 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C); 1072 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C); 1073 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48); 1074 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48); 1075 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48); 1076 1077 /* I2C9 Fan Controller (MAX31785) */ 1078 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52); 1079 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54); 1080 } 1081 1082 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 1083 { 1084 return ASPEED_MACHINE(obj)->mmio_exec; 1085 } 1086 1087 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 1088 { 1089 ASPEED_MACHINE(obj)->mmio_exec = value; 1090 } 1091 1092 static void aspeed_machine_instance_init(Object *obj) 1093 { 1094 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj); 1095 1096 ASPEED_MACHINE(obj)->mmio_exec = false; 1097 ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1; 1098 } 1099 1100 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 1101 { 1102 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1103 return g_strdup(bmc->fmc_model); 1104 } 1105 1106 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 1107 { 1108 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1109 1110 g_free(bmc->fmc_model); 1111 bmc->fmc_model = g_strdup(value); 1112 } 1113 1114 static char *aspeed_get_spi_model(Object *obj, Error **errp) 1115 { 1116 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1117 return g_strdup(bmc->spi_model); 1118 } 1119 1120 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 1121 { 1122 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1123 1124 g_free(bmc->spi_model); 1125 bmc->spi_model = g_strdup(value); 1126 } 1127 1128 static char *aspeed_get_bmc_console(Object *obj, Error **errp) 1129 { 1130 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1131 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1132 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 1133 1134 return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen)); 1135 } 1136 1137 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp) 1138 { 1139 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1140 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1141 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1142 int val; 1143 int uart_first = aspeed_uart_first(sc); 1144 int uart_last = aspeed_uart_last(sc); 1145 1146 if (sscanf(value, "uart%u", &val) != 1) { 1147 error_setg(errp, "Bad value for \"uart\" property"); 1148 return; 1149 } 1150 1151 /* The number of UART depends on the SoC */ 1152 if (val < uart_first || val > uart_last) { 1153 error_setg(errp, "\"uart\" should be in range [%d - %d]", 1154 uart_first, uart_last); 1155 return; 1156 } 1157 bmc->uart_chosen = val + ASPEED_DEV_UART0; 1158 } 1159 1160 static void aspeed_machine_class_props_init(ObjectClass *oc) 1161 { 1162 object_class_property_add_bool(oc, "execute-in-place", 1163 aspeed_get_mmio_exec, 1164 aspeed_set_mmio_exec); 1165 object_class_property_set_description(oc, "execute-in-place", 1166 "boot directly from CE0 flash device"); 1167 1168 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console, 1169 aspeed_set_bmc_console); 1170 object_class_property_set_description(oc, "bmc-console", 1171 "Change the default UART to \"uartX\""); 1172 1173 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1174 aspeed_set_fmc_model); 1175 object_class_property_set_description(oc, "fmc-model", 1176 "Change the FMC Flash model"); 1177 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1178 aspeed_set_spi_model); 1179 object_class_property_set_description(oc, "spi-model", 1180 "Change the SPI Flash model"); 1181 } 1182 1183 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) 1184 { 1185 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc); 1186 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1187 1188 mc->default_cpus = sc->num_cpus; 1189 mc->min_cpus = sc->num_cpus; 1190 mc->max_cpus = sc->num_cpus; 1191 mc->valid_cpu_types = sc->valid_cpu_types; 1192 } 1193 1194 static bool aspeed_machine_ast2600_get_boot_from_emmc(Object *obj, Error **errp) 1195 { 1196 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1197 1198 return !!(bmc->hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); 1199 } 1200 1201 static void aspeed_machine_ast2600_set_boot_from_emmc(Object *obj, bool value, 1202 Error **errp) 1203 { 1204 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1205 1206 if (value) { 1207 bmc->hw_strap1 |= SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 1208 } else { 1209 bmc->hw_strap1 &= ~SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 1210 } 1211 } 1212 1213 static void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc) 1214 { 1215 object_class_property_add_bool(oc, "boot-emmc", 1216 aspeed_machine_ast2600_get_boot_from_emmc, 1217 aspeed_machine_ast2600_set_boot_from_emmc); 1218 object_class_property_set_description(oc, "boot-emmc", 1219 "Set or unset boot from EMMC"); 1220 } 1221 1222 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 1223 { 1224 MachineClass *mc = MACHINE_CLASS(oc); 1225 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1226 1227 mc->init = aspeed_machine_init; 1228 mc->no_floppy = 1; 1229 mc->no_cdrom = 1; 1230 mc->no_parallel = 1; 1231 mc->default_ram_id = "ram"; 1232 amc->macs_mask = ASPEED_MAC0_ON; 1233 amc->uart_default = ASPEED_DEV_UART5; 1234 1235 aspeed_machine_class_props_init(oc); 1236 } 1237 1238 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 1239 { 1240 MachineClass *mc = MACHINE_CLASS(oc); 1241 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1242 1243 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1244 amc->soc_name = "ast2400-a1"; 1245 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1246 amc->fmc_model = "n25q256a"; 1247 amc->spi_model = "mx25l25635f"; 1248 amc->num_cs = 1; 1249 amc->i2c_init = palmetto_bmc_i2c_init; 1250 mc->default_ram_size = 256 * MiB; 1251 aspeed_machine_class_init_cpus_defaults(mc); 1252 }; 1253 1254 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 1255 { 1256 MachineClass *mc = MACHINE_CLASS(oc); 1257 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1258 1259 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1260 amc->soc_name = "ast2400-a1"; 1261 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1262 amc->fmc_model = "n25q256a"; 1263 amc->spi_model = "mx25l25635e"; 1264 amc->num_cs = 1; 1265 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1266 mc->default_ram_size = 128 * MiB; 1267 aspeed_machine_class_init_cpus_defaults(mc); 1268 } 1269 1270 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1271 void *data) 1272 { 1273 MachineClass *mc = MACHINE_CLASS(oc); 1274 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1275 1276 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1277 amc->soc_name = "ast2400-a1"; 1278 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1279 amc->fmc_model = "mx25l25635e"; 1280 amc->spi_model = "mx25l25635e"; 1281 amc->num_cs = 1; 1282 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1283 amc->i2c_init = palmetto_bmc_i2c_init; 1284 mc->default_ram_size = 256 * MiB; 1285 aspeed_machine_class_init_cpus_defaults(mc); 1286 } 1287 1288 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, 1289 void *data) 1290 { 1291 MachineClass *mc = MACHINE_CLASS(oc); 1292 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1293 1294 mc->desc = "Supermicro X11 SPI BMC (ARM1176)"; 1295 amc->soc_name = "ast2500-a1"; 1296 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1; 1297 amc->fmc_model = "mx25l25635e"; 1298 amc->spi_model = "mx25l25635e"; 1299 amc->num_cs = 1; 1300 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1301 amc->i2c_init = palmetto_bmc_i2c_init; 1302 mc->default_ram_size = 512 * MiB; 1303 aspeed_machine_class_init_cpus_defaults(mc); 1304 } 1305 1306 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 1307 { 1308 MachineClass *mc = MACHINE_CLASS(oc); 1309 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1310 1311 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1312 amc->soc_name = "ast2500-a1"; 1313 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1314 amc->fmc_model = "mx25l25635e"; 1315 amc->spi_model = "mx25l25635f"; 1316 amc->num_cs = 1; 1317 amc->i2c_init = ast2500_evb_i2c_init; 1318 mc->default_ram_size = 512 * MiB; 1319 aspeed_machine_class_init_cpus_defaults(mc); 1320 }; 1321 1322 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data) 1323 { 1324 MachineClass *mc = MACHINE_CLASS(oc); 1325 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1326 1327 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)"; 1328 amc->soc_name = "ast2500-a1"; 1329 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1330 amc->hw_strap2 = 0; 1331 amc->fmc_model = "n25q256a"; 1332 amc->spi_model = "mx25l25635e"; 1333 amc->num_cs = 2; 1334 amc->i2c_init = yosemitev2_bmc_i2c_init; 1335 mc->default_ram_size = 512 * MiB; 1336 aspeed_machine_class_init_cpus_defaults(mc); 1337 }; 1338 1339 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 1340 { 1341 MachineClass *mc = MACHINE_CLASS(oc); 1342 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1343 1344 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1345 amc->soc_name = "ast2500-a1"; 1346 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1347 amc->fmc_model = "n25q256a"; 1348 amc->spi_model = "mx66l1g45g"; 1349 amc->num_cs = 2; 1350 amc->i2c_init = romulus_bmc_i2c_init; 1351 mc->default_ram_size = 512 * MiB; 1352 aspeed_machine_class_init_cpus_defaults(mc); 1353 }; 1354 1355 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data) 1356 { 1357 MachineClass *mc = MACHINE_CLASS(oc); 1358 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1359 1360 mc->desc = "Facebook Tiogapass BMC (ARM1176)"; 1361 amc->soc_name = "ast2500-a1"; 1362 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1363 amc->hw_strap2 = 0; 1364 amc->fmc_model = "n25q256a"; 1365 amc->spi_model = "mx25l25635e"; 1366 amc->num_cs = 2; 1367 amc->i2c_init = tiogapass_bmc_i2c_init; 1368 mc->default_ram_size = 1 * GiB; 1369 aspeed_machine_class_init_cpus_defaults(mc); 1370 }; 1371 1372 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 1373 { 1374 MachineClass *mc = MACHINE_CLASS(oc); 1375 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1376 1377 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1378 amc->soc_name = "ast2500-a1"; 1379 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1380 amc->fmc_model = "mx66l1g45g"; 1381 amc->spi_model = "mx66l1g45g"; 1382 amc->num_cs = 2; 1383 amc->i2c_init = sonorapass_bmc_i2c_init; 1384 mc->default_ram_size = 512 * MiB; 1385 aspeed_machine_class_init_cpus_defaults(mc); 1386 }; 1387 1388 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 1389 { 1390 MachineClass *mc = MACHINE_CLASS(oc); 1391 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1392 1393 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1394 amc->soc_name = "ast2500-a1"; 1395 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1396 amc->fmc_model = "mx25l25635f"; 1397 amc->spi_model = "mx66l1g45g"; 1398 amc->num_cs = 2; 1399 amc->i2c_init = witherspoon_bmc_i2c_init; 1400 mc->default_ram_size = 512 * MiB; 1401 aspeed_machine_class_init_cpus_defaults(mc); 1402 }; 1403 1404 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 1405 { 1406 MachineClass *mc = MACHINE_CLASS(oc); 1407 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1408 1409 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1410 amc->soc_name = "ast2600-a3"; 1411 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1412 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1413 amc->fmc_model = "mx66u51235f"; 1414 amc->spi_model = "mx66u51235f"; 1415 amc->num_cs = 1; 1416 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1417 ASPEED_MAC3_ON; 1418 amc->i2c_init = ast2600_evb_i2c_init; 1419 mc->default_ram_size = 1 * GiB; 1420 aspeed_machine_class_init_cpus_defaults(mc); 1421 aspeed_machine_ast2600_class_emmc_init(oc); 1422 }; 1423 1424 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 1425 { 1426 MachineClass *mc = MACHINE_CLASS(oc); 1427 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1428 1429 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1430 amc->soc_name = "ast2500-a1"; 1431 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1432 amc->fmc_model = "n25q512a"; 1433 amc->spi_model = "mx25l25635e"; 1434 amc->num_cs = 2; 1435 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1436 amc->i2c_init = g220a_bmc_i2c_init; 1437 mc->default_ram_size = 1024 * MiB; 1438 aspeed_machine_class_init_cpus_defaults(mc); 1439 }; 1440 1441 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) 1442 { 1443 MachineClass *mc = MACHINE_CLASS(oc); 1444 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1445 1446 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1447 amc->soc_name = "ast2500-a1"; 1448 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1449 amc->fmc_model = "n25q512a"; 1450 amc->spi_model = "mx25l25635e"; 1451 amc->num_cs = 2; 1452 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1453 amc->i2c_init = fp5280g2_bmc_i2c_init; 1454 mc->default_ram_size = 512 * MiB; 1455 aspeed_machine_class_init_cpus_defaults(mc); 1456 }; 1457 1458 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1459 { 1460 MachineClass *mc = MACHINE_CLASS(oc); 1461 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1462 1463 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1464 amc->soc_name = "ast2600-a3"; 1465 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1466 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1467 amc->fmc_model = "mx66l1g45g"; 1468 amc->spi_model = "mx66l1g45g"; 1469 amc->num_cs = 2; 1470 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1471 amc->i2c_init = rainier_bmc_i2c_init; 1472 mc->default_ram_size = 1 * GiB; 1473 aspeed_machine_class_init_cpus_defaults(mc); 1474 aspeed_machine_ast2600_class_emmc_init(oc); 1475 }; 1476 1477 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1478 1479 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) 1480 { 1481 MachineClass *mc = MACHINE_CLASS(oc); 1482 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1483 1484 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1485 amc->soc_name = "ast2600-a3"; 1486 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1487 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1488 amc->fmc_model = "mx66l1g45g"; 1489 amc->spi_model = "mx66l1g45g"; 1490 amc->num_cs = 2; 1491 amc->macs_mask = ASPEED_MAC3_ON; 1492 amc->i2c_init = fuji_bmc_i2c_init; 1493 amc->uart_default = ASPEED_DEV_UART1; 1494 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1495 aspeed_machine_class_init_cpus_defaults(mc); 1496 }; 1497 1498 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1499 1500 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) 1501 { 1502 MachineClass *mc = MACHINE_CLASS(oc); 1503 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1504 1505 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1506 amc->soc_name = "ast2600-a3"; 1507 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1508 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1509 amc->fmc_model = "w25q01jvq"; 1510 amc->spi_model = NULL; 1511 amc->num_cs = 2; 1512 amc->macs_mask = ASPEED_MAC2_ON; 1513 amc->i2c_init = bletchley_bmc_i2c_init; 1514 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE; 1515 aspeed_machine_class_init_cpus_defaults(mc); 1516 } 1517 1518 static void fby35_reset(MachineState *state, ResetType type) 1519 { 1520 AspeedMachineState *bmc = ASPEED_MACHINE(state); 1521 AspeedGPIOState *gpio = &bmc->soc->gpio; 1522 1523 qemu_devices_reset(type); 1524 1525 /* Board ID: 7 (Class-1, 4 slots) */ 1526 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); 1527 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); 1528 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); 1529 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); 1530 1531 /* Slot presence pins, inverse polarity. (False means present) */ 1532 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal); 1533 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal); 1534 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal); 1535 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal); 1536 1537 /* Slot 12v power pins, normal polarity. (True means powered-on) */ 1538 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal); 1539 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal); 1540 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal); 1541 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal); 1542 } 1543 1544 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data) 1545 { 1546 MachineClass *mc = MACHINE_CLASS(oc); 1547 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1548 1549 mc->desc = "Facebook fby35 BMC (Cortex-A7)"; 1550 mc->reset = fby35_reset; 1551 amc->fmc_model = "mx66l1g45g"; 1552 amc->num_cs = 2; 1553 amc->macs_mask = ASPEED_MAC3_ON; 1554 amc->i2c_init = fby35_i2c_init; 1555 /* FIXME: Replace this macro with something more general */ 1556 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1557 aspeed_machine_class_init_cpus_defaults(mc); 1558 } 1559 1560 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) 1561 /* Main SYSCLK frequency in Hz (200MHz) */ 1562 #define SYSCLK_FRQ 200000000ULL 1563 1564 static void aspeed_minibmc_machine_init(MachineState *machine) 1565 { 1566 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 1567 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 1568 Clock *sysclk; 1569 1570 sysclk = clock_new(OBJECT(machine), "SYSCLK"); 1571 clock_set_hz(sysclk, SYSCLK_FRQ); 1572 1573 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 1574 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 1575 object_unref(OBJECT(bmc->soc)); 1576 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk); 1577 1578 object_property_set_link(OBJECT(bmc->soc), "memory", 1579 OBJECT(get_system_memory()), &error_abort); 1580 connect_serial_hds_to_uarts(bmc); 1581 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 1582 1583 if (defaults_enabled()) { 1584 aspeed_board_init_flashes(&bmc->soc->fmc, 1585 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 1586 amc->num_cs, 1587 0); 1588 1589 aspeed_board_init_flashes(&bmc->soc->spi[0], 1590 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1591 amc->num_cs, amc->num_cs); 1592 1593 aspeed_board_init_flashes(&bmc->soc->spi[1], 1594 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1595 amc->num_cs, (amc->num_cs * 2)); 1596 } 1597 1598 if (amc->i2c_init) { 1599 amc->i2c_init(bmc); 1600 } 1601 1602 armv7m_load_kernel(ARM_CPU(first_cpu), 1603 machine->kernel_filename, 1604 0, 1605 AST1030_INTERNAL_FLASH_SIZE); 1606 } 1607 1608 static void ast1030_evb_i2c_init(AspeedMachineState *bmc) 1609 { 1610 AspeedSoCState *soc = bmc->soc; 1611 1612 /* U10 24C08 connects to SDA/SCL Group 1 by default */ 1613 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 1614 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); 1615 1616 /* U11 LM75 connects to SDA/SCL Group 2 by default */ 1617 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d); 1618 } 1619 1620 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, 1621 void *data) 1622 { 1623 MachineClass *mc = MACHINE_CLASS(oc); 1624 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1625 1626 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; 1627 amc->soc_name = "ast1030-a1"; 1628 amc->hw_strap1 = 0; 1629 amc->hw_strap2 = 0; 1630 mc->init = aspeed_minibmc_machine_init; 1631 amc->i2c_init = ast1030_evb_i2c_init; 1632 mc->default_ram_size = 0; 1633 amc->fmc_model = "w25q80bl"; 1634 amc->spi_model = "w25q256"; 1635 amc->num_cs = 2; 1636 amc->macs_mask = 0; 1637 aspeed_machine_class_init_cpus_defaults(mc); 1638 } 1639 1640 #ifdef TARGET_AARCH64 1641 static void ast2700_evb_i2c_init(AspeedMachineState *bmc) 1642 { 1643 AspeedSoCState *soc = bmc->soc; 1644 1645 /* LM75 is compatible with TMP105 driver */ 1646 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), 1647 TYPE_TMP105, 0x4d); 1648 } 1649 1650 static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data) 1651 { 1652 MachineClass *mc = MACHINE_CLASS(oc); 1653 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1654 1655 mc->desc = "Aspeed AST2700 EVB (Cortex-A35)"; 1656 amc->soc_name = "ast2700-a0"; 1657 amc->hw_strap1 = AST2700_EVB_HW_STRAP1; 1658 amc->hw_strap2 = AST2700_EVB_HW_STRAP2; 1659 amc->fmc_model = "w25q01jvq"; 1660 amc->spi_model = "w25q512jv"; 1661 amc->num_cs = 2; 1662 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; 1663 amc->uart_default = ASPEED_DEV_UART12; 1664 amc->i2c_init = ast2700_evb_i2c_init; 1665 mc->default_ram_size = 1 * GiB; 1666 aspeed_machine_class_init_cpus_defaults(mc); 1667 } 1668 #endif 1669 1670 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, 1671 void *data) 1672 { 1673 MachineClass *mc = MACHINE_CLASS(oc); 1674 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1675 1676 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)"; 1677 amc->soc_name = "ast2600-a3"; 1678 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1679 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1680 amc->fmc_model = "n25q512a"; 1681 amc->spi_model = "n25q512a"; 1682 amc->num_cs = 2; 1683 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1684 amc->i2c_init = qcom_dc_scm_bmc_i2c_init; 1685 mc->default_ram_size = 1 * GiB; 1686 aspeed_machine_class_init_cpus_defaults(mc); 1687 }; 1688 1689 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, 1690 void *data) 1691 { 1692 MachineClass *mc = MACHINE_CLASS(oc); 1693 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1694 1695 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; 1696 amc->soc_name = "ast2600-a3"; 1697 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1698 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1699 amc->fmc_model = "n25q512a"; 1700 amc->spi_model = "n25q512a"; 1701 amc->num_cs = 2; 1702 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1703 amc->i2c_init = qcom_dc_scm_firework_i2c_init; 1704 mc->default_ram_size = 1 * GiB; 1705 aspeed_machine_class_init_cpus_defaults(mc); 1706 }; 1707 1708 static const TypeInfo aspeed_machine_types[] = { 1709 { 1710 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1711 .parent = TYPE_ASPEED_MACHINE, 1712 .class_init = aspeed_machine_palmetto_class_init, 1713 }, { 1714 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1715 .parent = TYPE_ASPEED_MACHINE, 1716 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1717 }, { 1718 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), 1719 .parent = TYPE_ASPEED_MACHINE, 1720 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, 1721 }, { 1722 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1723 .parent = TYPE_ASPEED_MACHINE, 1724 .class_init = aspeed_machine_ast2500_evb_class_init, 1725 }, { 1726 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1727 .parent = TYPE_ASPEED_MACHINE, 1728 .class_init = aspeed_machine_romulus_class_init, 1729 }, { 1730 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1731 .parent = TYPE_ASPEED_MACHINE, 1732 .class_init = aspeed_machine_sonorapass_class_init, 1733 }, { 1734 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1735 .parent = TYPE_ASPEED_MACHINE, 1736 .class_init = aspeed_machine_witherspoon_class_init, 1737 }, { 1738 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1739 .parent = TYPE_ASPEED_MACHINE, 1740 .class_init = aspeed_machine_ast2600_evb_class_init, 1741 }, { 1742 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), 1743 .parent = TYPE_ASPEED_MACHINE, 1744 .class_init = aspeed_machine_yosemitev2_class_init, 1745 }, { 1746 .name = MACHINE_TYPE_NAME("tiogapass-bmc"), 1747 .parent = TYPE_ASPEED_MACHINE, 1748 .class_init = aspeed_machine_tiogapass_class_init, 1749 }, { 1750 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1751 .parent = TYPE_ASPEED_MACHINE, 1752 .class_init = aspeed_machine_g220a_class_init, 1753 }, { 1754 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), 1755 .parent = TYPE_ASPEED_MACHINE, 1756 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, 1757 }, { 1758 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), 1759 .parent = TYPE_ASPEED_MACHINE, 1760 .class_init = aspeed_machine_qcom_firework_class_init, 1761 }, { 1762 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1763 .parent = TYPE_ASPEED_MACHINE, 1764 .class_init = aspeed_machine_fp5280g2_class_init, 1765 }, { 1766 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1767 .parent = TYPE_ASPEED_MACHINE, 1768 .class_init = aspeed_machine_quanta_q71l_class_init, 1769 }, { 1770 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1771 .parent = TYPE_ASPEED_MACHINE, 1772 .class_init = aspeed_machine_rainier_class_init, 1773 }, { 1774 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1775 .parent = TYPE_ASPEED_MACHINE, 1776 .class_init = aspeed_machine_fuji_class_init, 1777 }, { 1778 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 1779 .parent = TYPE_ASPEED_MACHINE, 1780 .class_init = aspeed_machine_bletchley_class_init, 1781 }, { 1782 .name = MACHINE_TYPE_NAME("fby35-bmc"), 1783 .parent = MACHINE_TYPE_NAME("ast2600-evb"), 1784 .class_init = aspeed_machine_fby35_class_init, 1785 }, { 1786 .name = MACHINE_TYPE_NAME("ast1030-evb"), 1787 .parent = TYPE_ASPEED_MACHINE, 1788 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, 1789 #ifdef TARGET_AARCH64 1790 }, { 1791 .name = MACHINE_TYPE_NAME("ast2700-evb"), 1792 .parent = TYPE_ASPEED_MACHINE, 1793 .class_init = aspeed_machine_ast2700_evb_class_init, 1794 #endif 1795 }, { 1796 .name = TYPE_ASPEED_MACHINE, 1797 .parent = TYPE_MACHINE, 1798 .instance_size = sizeof(AspeedMachineState), 1799 .instance_init = aspeed_machine_instance_init, 1800 .class_size = sizeof(AspeedMachineClass), 1801 .class_init = aspeed_machine_class_init, 1802 .abstract = true, 1803 } 1804 }; 1805 1806 DEFINE_TYPES(aspeed_machine_types) 1807