1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/arm/aspeed_eeprom.h" 18 #include "hw/block/flash.h" 19 #include "hw/i2c/i2c_mux_pca954x.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/gpio/pca9552.h" 22 #include "hw/nvram/eeprom_at24c.h" 23 #include "hw/sensor/tmp105.h" 24 #include "hw/misc/led.h" 25 #include "hw/qdev-properties.h" 26 #include "sysemu/block-backend.h" 27 #include "sysemu/reset.h" 28 #include "hw/loader.h" 29 #include "qemu/error-report.h" 30 #include "qemu/units.h" 31 #include "hw/qdev-clock.h" 32 #include "sysemu/sysemu.h" 33 34 static struct arm_boot_info aspeed_board_binfo = { 35 .board_id = -1, /* device-tree-only board */ 36 }; 37 38 struct AspeedMachineState { 39 /* Private */ 40 MachineState parent_obj; 41 /* Public */ 42 43 AspeedSoCState *soc; 44 MemoryRegion boot_rom; 45 bool mmio_exec; 46 uint32_t uart_chosen; 47 char *fmc_model; 48 char *spi_model; 49 }; 50 51 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 52 #if HOST_LONG_BITS == 32 53 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB) 54 #else 55 #define ASPEED_RAM_SIZE(sz) (sz) 56 #endif 57 58 /* Palmetto hardware value: 0x120CE416 */ 59 #define PALMETTO_BMC_HW_STRAP1 ( \ 60 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 61 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 62 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 63 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 64 SCU_HW_STRAP_VGA_CLASS_CODE | \ 65 SCU_HW_STRAP_LPC_RESET_PIN | \ 66 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 67 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 68 SCU_HW_STRAP_SPI_WIDTH | \ 69 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 70 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 71 72 /* TODO: Find the actual hardware value */ 73 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 74 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 75 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 76 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 77 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 78 SCU_HW_STRAP_VGA_CLASS_CODE | \ 79 SCU_HW_STRAP_LPC_RESET_PIN | \ 80 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 81 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 82 SCU_HW_STRAP_SPI_WIDTH | \ 83 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 84 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 85 86 /* TODO: Find the actual hardware value */ 87 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ 88 AST2500_HW_STRAP1_DEFAULTS | \ 89 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 90 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 91 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 92 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 93 SCU_HW_STRAP_SPI_WIDTH | \ 94 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) 95 96 /* AST2500 evb hardware value: 0xF100C2E6 */ 97 #define AST2500_EVB_HW_STRAP1 (( \ 98 AST2500_HW_STRAP1_DEFAULTS | \ 99 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 100 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 101 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 102 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 103 SCU_HW_STRAP_MAC1_RGMII | \ 104 SCU_HW_STRAP_MAC0_RGMII) & \ 105 ~SCU_HW_STRAP_2ND_BOOT_WDT) 106 107 /* Romulus hardware value: 0xF10AD206 */ 108 #define ROMULUS_BMC_HW_STRAP1 ( \ 109 AST2500_HW_STRAP1_DEFAULTS | \ 110 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 111 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 112 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 113 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 114 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 115 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 116 117 /* Sonorapass hardware value: 0xF100D216 */ 118 #define SONORAPASS_BMC_HW_STRAP1 ( \ 119 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 120 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 121 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 122 SCU_AST2500_HW_STRAP_RESERVED28 | \ 123 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 124 SCU_HW_STRAP_VGA_CLASS_CODE | \ 125 SCU_HW_STRAP_LPC_RESET_PIN | \ 126 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 127 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 128 SCU_HW_STRAP_VGA_BIOS_ROM | \ 129 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 130 SCU_AST2500_HW_STRAP_RESERVED1) 131 132 #define G220A_BMC_HW_STRAP1 ( \ 133 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 134 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 135 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 136 SCU_AST2500_HW_STRAP_RESERVED28 | \ 137 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 138 SCU_HW_STRAP_2ND_BOOT_WDT | \ 139 SCU_HW_STRAP_VGA_CLASS_CODE | \ 140 SCU_HW_STRAP_LPC_RESET_PIN | \ 141 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 142 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 143 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 144 SCU_AST2500_HW_STRAP_RESERVED1) 145 146 /* FP5280G2 hardware value: 0XF100D286 */ 147 #define FP5280G2_BMC_HW_STRAP1 ( \ 148 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 149 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 150 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 151 SCU_AST2500_HW_STRAP_RESERVED28 | \ 152 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 153 SCU_HW_STRAP_VGA_CLASS_CODE | \ 154 SCU_HW_STRAP_LPC_RESET_PIN | \ 155 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 156 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 157 SCU_HW_STRAP_MAC1_RGMII | \ 158 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 159 SCU_AST2500_HW_STRAP_RESERVED1) 160 161 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 162 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 163 164 /* Quanta-Q71l hardware value */ 165 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 166 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 167 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 168 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 169 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 170 SCU_HW_STRAP_VGA_CLASS_CODE | \ 171 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 172 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 173 SCU_HW_STRAP_SPI_WIDTH | \ 174 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 175 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 176 177 /* AST2600 evb hardware value */ 178 #define AST2600_EVB_HW_STRAP1 0x000000C0 179 #define AST2600_EVB_HW_STRAP2 0x00000003 180 181 #ifdef TARGET_AARCH64 182 /* AST2700 evb hardware value */ 183 #define AST2700_EVB_HW_STRAP1 0x000000C0 184 #define AST2700_EVB_HW_STRAP2 0x00000003 185 #endif 186 187 /* Tacoma hardware value */ 188 #define TACOMA_BMC_HW_STRAP1 0x00000000 189 #define TACOMA_BMC_HW_STRAP2 0x00000040 190 191 /* Rainier hardware value: (QEMU prototype) */ 192 #define RAINIER_BMC_HW_STRAP1 0x00422016 193 #define RAINIER_BMC_HW_STRAP2 0x80000848 194 195 /* Fuji hardware value */ 196 #define FUJI_BMC_HW_STRAP1 0x00000000 197 #define FUJI_BMC_HW_STRAP2 0x00000000 198 199 /* Bletchley hardware value */ 200 /* TODO: Leave same as EVB for now. */ 201 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 202 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 203 204 /* Qualcomm DC-SCM hardware value */ 205 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 206 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 207 208 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 209 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 210 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 211 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 212 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 213 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 214 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 215 216 static void aspeed_write_smpboot(ARMCPU *cpu, 217 const struct arm_boot_info *info) 218 { 219 AddressSpace *as = arm_boot_address_space(cpu, info); 220 static const ARMInsnFixup poll_mailbox_ready[] = { 221 /* 222 * r2 = per-cpu go sign value 223 * r1 = AST_SMP_MBOX_FIELD_ENTRY 224 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 225 */ 226 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ 227 { 0xe21000ff }, /* ands r0, r0, #255 */ 228 { 0xe59f201c }, /* ldr r2, [pc, #28] */ 229 { 0xe1822000 }, /* orr r2, r2, r0 */ 230 231 { 0xe59f1018 }, /* ldr r1, [pc, #24] */ 232 { 0xe59f0018 }, /* ldr r0, [pc, #24] */ 233 234 { 0xe320f002 }, /* wfe */ 235 { 0xe5904000 }, /* ldr r4, [r0] */ 236 { 0xe1520004 }, /* cmp r2, r4 */ 237 { 0x1afffffb }, /* bne <wfe> */ 238 { 0xe591f000 }, /* ldr pc, [r1] */ 239 { AST_SMP_MBOX_GOSIGN }, 240 { AST_SMP_MBOX_FIELD_ENTRY }, 241 { AST_SMP_MBOX_FIELD_GOSIGN }, 242 { 0, FIXUP_TERMINATOR } 243 }; 244 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; 245 246 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, 247 poll_mailbox_ready, fixupcontext); 248 } 249 250 static void aspeed_reset_secondary(ARMCPU *cpu, 251 const struct arm_boot_info *info) 252 { 253 AddressSpace *as = arm_boot_address_space(cpu, info); 254 CPUState *cs = CPU(cpu); 255 256 /* info->smp_bootreg_addr */ 257 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 258 MEMTXATTRS_UNSPECIFIED, NULL); 259 cpu_set_pc(cs, info->smp_loader_start); 260 } 261 262 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size, 263 Error **errp) 264 { 265 g_autofree void *storage = NULL; 266 int64_t size; 267 268 /* The block backend size should have already been 'validated' by 269 * the creation of the m25p80 object. 270 */ 271 size = blk_getlength(blk); 272 if (size <= 0) { 273 error_setg(errp, "failed to get flash size"); 274 return; 275 } 276 277 if (rom_size > size) { 278 rom_size = size; 279 } 280 281 storage = g_malloc0(rom_size); 282 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { 283 error_setg(errp, "failed to read the initial flash content"); 284 return; 285 } 286 287 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 288 } 289 290 /* 291 * Create a ROM and copy the flash contents at the expected address 292 * (0x0). Boots faster than execute-in-place. 293 */ 294 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk, 295 uint64_t rom_size) 296 { 297 AspeedSoCState *soc = bmc->soc; 298 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc); 299 300 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size, 301 &error_abort); 302 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, 303 &bmc->boot_rom, 1); 304 write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT], 305 rom_size, &error_abort); 306 } 307 308 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 309 unsigned int count, int unit0) 310 { 311 int i; 312 313 if (!flashtype) { 314 return; 315 } 316 317 for (i = 0; i < count; ++i) { 318 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 319 DeviceState *dev; 320 321 dev = qdev_new(flashtype); 322 if (dinfo) { 323 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 324 } 325 qdev_prop_set_uint8(dev, "cs", i); 326 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 327 } 328 } 329 330 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc) 331 { 332 DeviceState *card; 333 334 if (!dinfo) { 335 return; 336 } 337 card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD); 338 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 339 &error_fatal); 340 qdev_realize_and_unref(card, 341 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 342 &error_fatal); 343 } 344 345 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) 346 { 347 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 348 AspeedSoCState *s = bmc->soc; 349 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 350 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 351 352 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); 353 for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) { 354 if (uart == uart_chosen) { 355 continue; 356 } 357 aspeed_soc_uart_set_chr(s, uart, serial_hd(i)); 358 } 359 } 360 361 static void aspeed_machine_init(MachineState *machine) 362 { 363 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 364 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 365 AspeedSoCClass *sc; 366 int i; 367 DriveInfo *emmc0 = NULL; 368 369 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 370 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 371 object_unref(OBJECT(bmc->soc)); 372 sc = ASPEED_SOC_GET_CLASS(bmc->soc); 373 374 /* 375 * This will error out if the RAM size is not supported by the 376 * memory controller of the SoC. 377 */ 378 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size, 379 &error_fatal); 380 381 for (i = 0; i < sc->macs_num; i++) { 382 if ((amc->macs_mask & (1 << i)) && 383 !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]), 384 true, NULL)) { 385 break; /* No configs left; stop asking */ 386 } 387 } 388 389 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", amc->hw_strap1, 390 &error_abort); 391 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2, 392 &error_abort); 393 object_property_set_link(OBJECT(bmc->soc), "memory", 394 OBJECT(get_system_memory()), &error_abort); 395 object_property_set_link(OBJECT(bmc->soc), "dram", 396 OBJECT(machine->ram), &error_abort); 397 if (machine->kernel_filename) { 398 /* 399 * When booting with a -kernel command line there is no u-boot 400 * that runs to unlock the SCU. In this case set the default to 401 * be unlocked as the kernel expects 402 */ 403 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key", 404 ASPEED_SCU_PROT_KEY, &error_abort); 405 } 406 connect_serial_hds_to_uarts(bmc); 407 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 408 409 if (defaults_enabled()) { 410 aspeed_board_init_flashes(&bmc->soc->fmc, 411 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 412 amc->num_cs, 0); 413 aspeed_board_init_flashes(&bmc->soc->spi[0], 414 bmc->spi_model ? bmc->spi_model : amc->spi_model, 415 1, amc->num_cs); 416 } 417 418 if (machine->kernel_filename && sc->num_cpus > 1) { 419 /* With no u-boot we must set up a boot stub for the secondary CPU */ 420 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 421 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 422 0x80, &error_abort); 423 memory_region_add_subregion(get_system_memory(), 424 AST_SMP_MAILBOX_BASE, smpboot); 425 426 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 427 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 428 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 429 } 430 431 aspeed_board_binfo.ram_size = machine->ram_size; 432 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 433 434 if (amc->i2c_init) { 435 amc->i2c_init(bmc); 436 } 437 438 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { 439 sdhci_attach_drive(&bmc->soc->sdhci.slots[i], 440 drive_get(IF_SD, 0, i), false); 441 } 442 443 if (bmc->soc->emmc.num_slots) { 444 emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots); 445 sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true); 446 } 447 448 if (!bmc->mmio_exec) { 449 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0); 450 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL; 451 452 if (fmc0) { 453 uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot); 454 aspeed_install_boot_rom(bmc, fmc0, rom_size); 455 } else if (emmc0) { 456 aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(emmc0), 64 * KiB); 457 } 458 } 459 460 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 461 } 462 463 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 464 { 465 AspeedSoCState *soc = bmc->soc; 466 DeviceState *dev; 467 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 468 469 /* The palmetto platform expects a ds3231 RTC but a ds1338 is 470 * enough to provide basic RTC features. Alarms will be missing */ 471 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 472 473 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 474 eeprom_buf); 475 476 /* add a TMP423 temperature sensor */ 477 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 478 "tmp423", 0x4c)); 479 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 480 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 481 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 482 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 483 } 484 485 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 486 { 487 AspeedSoCState *soc = bmc->soc; 488 489 /* 490 * The quanta-q71l platform expects tmp75s which are compatible with 491 * tmp105s. 492 */ 493 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 494 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 495 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 496 497 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 498 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 499 /* TODO: Add Memory Riser i2c mux and eeproms. */ 500 501 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 502 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 503 504 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 505 506 /* i2c-7 */ 507 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 508 /* - i2c@0: pmbus@59 */ 509 /* - i2c@1: pmbus@58 */ 510 /* - i2c@2: pmbus@58 */ 511 /* - i2c@3: pmbus@59 */ 512 513 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 514 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 515 } 516 517 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 518 { 519 AspeedSoCState *soc = bmc->soc; 520 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 521 522 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 523 eeprom_buf); 524 525 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 526 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 527 TYPE_TMP105, 0x4d); 528 } 529 530 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 531 { 532 AspeedSoCState *soc = bmc->soc; 533 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 534 535 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 536 eeprom_buf); 537 538 /* LM75 is compatible with TMP105 driver */ 539 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 540 TYPE_TMP105, 0x4d); 541 } 542 543 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) 544 { 545 AspeedSoCState *soc = bmc->soc; 546 547 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); 548 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB, 549 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len); 550 /* TMP421 */ 551 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f); 552 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e); 553 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f); 554 555 } 556 557 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 558 { 559 AspeedSoCState *soc = bmc->soc; 560 561 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 562 * good enough */ 563 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 564 } 565 566 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc) 567 { 568 AspeedSoCState *soc = bmc->soc; 569 570 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB); 571 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB, 572 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len); 573 /* TMP421 */ 574 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f); 575 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f); 576 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e); 577 } 578 579 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 580 { 581 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 582 TYPE_PCA9552, addr); 583 } 584 585 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 586 { 587 AspeedSoCState *soc = bmc->soc; 588 589 /* bus 2 : */ 590 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 591 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 592 /* bus 2 : pca9546 @ 0x73 */ 593 594 /* bus 3 : pca9548 @ 0x70 */ 595 596 /* bus 4 : */ 597 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 598 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 599 eeprom4_54); 600 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 601 create_pca9552(soc, 4, 0x76); 602 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 603 create_pca9552(soc, 4, 0x77); 604 605 /* bus 6 : */ 606 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 607 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 608 /* bus 6 : pca9546 @ 0x73 */ 609 610 /* bus 8 : */ 611 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 612 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 613 eeprom8_56); 614 create_pca9552(soc, 8, 0x60); 615 create_pca9552(soc, 8, 0x61); 616 /* bus 8 : adc128d818 @ 0x1d */ 617 /* bus 8 : adc128d818 @ 0x1f */ 618 619 /* 620 * bus 13 : pca9548 @ 0x71 621 * - channel 3: 622 * - tmm421 @ 0x4c 623 * - tmp421 @ 0x4e 624 * - tmp421 @ 0x4f 625 */ 626 627 } 628 629 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 630 { 631 static const struct { 632 unsigned gpio_id; 633 LEDColor color; 634 const char *description; 635 bool gpio_polarity; 636 } pca1_leds[] = { 637 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 638 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 639 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 640 }; 641 AspeedSoCState *soc = bmc->soc; 642 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 643 DeviceState *dev; 644 LEDState *led; 645 646 /* Bus 3: TODO bmp280@77 */ 647 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 648 qdev_prop_set_string(dev, "description", "pca1"); 649 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 650 aspeed_i2c_get_bus(&soc->i2c, 3), 651 &error_fatal); 652 653 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 654 led = led_create_simple(OBJECT(bmc), 655 pca1_leds[i].gpio_polarity, 656 pca1_leds[i].color, 657 pca1_leds[i].description); 658 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 659 qdev_get_gpio_in(DEVICE(led), 0)); 660 } 661 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 662 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52); 663 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 664 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 665 666 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 667 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 668 0x4a); 669 670 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 671 * good enough */ 672 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 673 674 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 675 eeprom_buf); 676 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 677 qdev_prop_set_string(dev, "description", "pca0"); 678 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 679 aspeed_i2c_get_bus(&soc->i2c, 11), 680 &error_fatal); 681 /* Bus 11: TODO ucd90160@64 */ 682 } 683 684 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 685 { 686 AspeedSoCState *soc = bmc->soc; 687 DeviceState *dev; 688 689 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 690 "emc1413", 0x4c)); 691 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 692 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 693 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 694 695 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 696 "emc1413", 0x4c)); 697 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 698 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 699 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 700 701 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 702 "emc1413", 0x4c)); 703 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 704 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 705 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 706 707 static uint8_t eeprom_buf[2 * 1024] = { 708 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 709 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 710 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 711 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 712 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 713 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 714 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 715 }; 716 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 717 eeprom_buf); 718 } 719 720 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 721 { 722 AspeedSoCState *soc = bmc->soc; 723 I2CSlave *i2c_mux; 724 725 /* The at24c256 */ 726 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 727 728 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 729 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 730 0x48); 731 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 732 0x49); 733 734 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 735 "pca9546", 0x70); 736 /* It expects a TMP112 but a TMP105 is compatible */ 737 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 738 0x4a); 739 740 /* It expects a ds3232 but a ds1338 is good enough */ 741 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 742 743 /* It expects a pca9555 but a pca9552 is compatible */ 744 create_pca9552(soc, 8, 0x30); 745 } 746 747 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 748 { 749 AspeedSoCState *soc = bmc->soc; 750 I2CSlave *i2c_mux; 751 752 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 753 754 create_pca9552(soc, 3, 0x61); 755 756 /* The rainier expects a TMP275 but a TMP105 is compatible */ 757 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 758 0x48); 759 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 760 0x49); 761 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 762 0x4a); 763 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 764 "pca9546", 0x70); 765 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 766 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 767 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 768 create_pca9552(soc, 4, 0x60); 769 770 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 771 0x48); 772 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 773 0x49); 774 create_pca9552(soc, 5, 0x60); 775 create_pca9552(soc, 5, 0x61); 776 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 777 "pca9546", 0x70); 778 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 779 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 780 781 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 782 0x48); 783 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 784 0x4a); 785 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 786 0x4b); 787 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 788 "pca9546", 0x70); 789 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 790 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 791 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 792 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 793 794 create_pca9552(soc, 7, 0x30); 795 create_pca9552(soc, 7, 0x31); 796 create_pca9552(soc, 7, 0x32); 797 create_pca9552(soc, 7, 0x33); 798 create_pca9552(soc, 7, 0x60); 799 create_pca9552(soc, 7, 0x61); 800 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 801 /* Bus 7: TODO si7021-a20@20 */ 802 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 803 0x48); 804 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52); 805 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 806 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 807 808 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 809 0x48); 810 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 811 0x4a); 812 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 813 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len); 814 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 815 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len); 816 create_pca9552(soc, 8, 0x60); 817 create_pca9552(soc, 8, 0x61); 818 /* Bus 8: ucd90320@11 */ 819 /* Bus 8: ucd90320@b */ 820 /* Bus 8: ucd90320@c */ 821 822 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 823 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 824 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 825 826 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 827 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 828 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 829 830 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 831 0x48); 832 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 833 0x49); 834 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 835 "pca9546", 0x70); 836 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 837 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 838 create_pca9552(soc, 11, 0x60); 839 840 841 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 842 create_pca9552(soc, 13, 0x60); 843 844 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 845 create_pca9552(soc, 14, 0x60); 846 847 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 848 create_pca9552(soc, 15, 0x60); 849 } 850 851 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 852 I2CBus **channels) 853 { 854 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 855 for (int i = 0; i < 8; i++) { 856 channels[i] = pca954x_i2c_get_bus(mux, i); 857 } 858 } 859 860 #define TYPE_LM75 TYPE_TMP105 861 #define TYPE_TMP75 TYPE_TMP105 862 #define TYPE_TMP422 "tmp422" 863 864 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 865 { 866 AspeedSoCState *soc = bmc->soc; 867 I2CBus *i2c[144] = {}; 868 869 for (int i = 0; i < 16; i++) { 870 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 871 } 872 I2CBus *i2c180 = i2c[2]; 873 I2CBus *i2c480 = i2c[8]; 874 I2CBus *i2c600 = i2c[11]; 875 876 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 877 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 878 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 879 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 880 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 881 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 882 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 883 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 884 for (int i = 0; i < 8; i++) { 885 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 886 } 887 888 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 889 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 890 891 /* 892 * EEPROM 24c64 size is 64Kbits or 8 Kbytes 893 * 24c02 size is 2Kbits or 256 bytes 894 */ 895 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB); 896 at24c_eeprom_init(i2c[20], 0x50, 256); 897 at24c_eeprom_init(i2c[22], 0x52, 256); 898 899 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 900 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 901 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 902 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 903 904 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB); 905 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 906 907 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 908 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB); 909 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 910 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 911 912 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 913 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 914 915 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB); 916 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 917 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 918 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB); 919 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB); 920 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB); 921 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB); 922 923 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB); 924 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 925 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 926 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB); 927 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB); 928 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB); 929 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB); 930 at24c_eeprom_init(i2c[28], 0x50, 256); 931 932 for (int i = 0; i < 8; i++) { 933 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 934 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 935 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 936 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 937 } 938 } 939 940 #define TYPE_TMP421 "tmp421" 941 942 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 943 { 944 AspeedSoCState *soc = bmc->soc; 945 I2CBus *i2c[13] = {}; 946 for (int i = 0; i < 13; i++) { 947 if ((i == 8) || (i == 11)) { 948 continue; 949 } 950 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 951 } 952 953 /* Bus 0 - 5 all have the same config. */ 954 for (int i = 0; i < 6; i++) { 955 /* Missing model: ti,ina230 @ 0x45 */ 956 /* Missing model: mps,mp5023 @ 0x40 */ 957 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 958 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 959 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 960 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 961 /* Missing model: fsc,fusb302 @ 0x22 */ 962 } 963 964 /* Bus 6 */ 965 at24c_eeprom_init(i2c[6], 0x56, 65536); 966 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 967 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 968 969 970 /* Bus 7 */ 971 at24c_eeprom_init(i2c[7], 0x54, 65536); 972 973 /* Bus 9 */ 974 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 975 976 /* Bus 10 */ 977 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 978 /* Missing model: ti,hdc1080 @ 0x40 */ 979 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 980 981 /* Bus 12 */ 982 /* Missing model: adi,adm1278 @ 0x11 */ 983 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 984 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 985 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 986 } 987 988 static void fby35_i2c_init(AspeedMachineState *bmc) 989 { 990 AspeedSoCState *soc = bmc->soc; 991 I2CBus *i2c[16]; 992 993 for (int i = 0; i < 16; i++) { 994 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 995 } 996 997 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); 998 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); 999 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ 1000 i2c_slave_create_simple(i2c[11], "adm1272", 0x44); 1001 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); 1002 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); 1003 1004 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB); 1005 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB); 1006 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid, 1007 fby35_nic_fruid_len); 1008 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid, 1009 fby35_bb_fruid_len); 1010 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid, 1011 fby35_bmc_fruid_len); 1012 1013 /* 1014 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on 1015 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on 1016 * each. 1017 */ 1018 } 1019 1020 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) 1021 { 1022 AspeedSoCState *soc = bmc->soc; 1023 1024 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); 1025 } 1026 1027 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) 1028 { 1029 AspeedSoCState *soc = bmc->soc; 1030 I2CSlave *therm_mux, *cpuvr_mux; 1031 1032 /* Create the generic DC-SCM hardware */ 1033 qcom_dc_scm_bmc_i2c_init(bmc); 1034 1035 /* Now create the Firework specific hardware */ 1036 1037 /* I2C7 CPUVR MUX */ 1038 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 1039 "pca9546", 0x70); 1040 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72); 1041 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72); 1042 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72); 1043 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72); 1044 1045 /* I2C8 Thermal Diodes*/ 1046 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 1047 "pca9548", 0x70); 1048 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C); 1049 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C); 1050 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48); 1051 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48); 1052 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48); 1053 1054 /* I2C9 Fan Controller (MAX31785) */ 1055 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52); 1056 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54); 1057 } 1058 1059 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 1060 { 1061 return ASPEED_MACHINE(obj)->mmio_exec; 1062 } 1063 1064 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 1065 { 1066 ASPEED_MACHINE(obj)->mmio_exec = value; 1067 } 1068 1069 static void aspeed_machine_instance_init(Object *obj) 1070 { 1071 ASPEED_MACHINE(obj)->mmio_exec = false; 1072 } 1073 1074 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 1075 { 1076 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1077 return g_strdup(bmc->fmc_model); 1078 } 1079 1080 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 1081 { 1082 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1083 1084 g_free(bmc->fmc_model); 1085 bmc->fmc_model = g_strdup(value); 1086 } 1087 1088 static char *aspeed_get_spi_model(Object *obj, Error **errp) 1089 { 1090 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1091 return g_strdup(bmc->spi_model); 1092 } 1093 1094 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 1095 { 1096 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1097 1098 g_free(bmc->spi_model); 1099 bmc->spi_model = g_strdup(value); 1100 } 1101 1102 static char *aspeed_get_bmc_console(Object *obj, Error **errp) 1103 { 1104 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1105 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1106 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 1107 1108 return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen)); 1109 } 1110 1111 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp) 1112 { 1113 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1114 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1115 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1116 int val; 1117 int uart_first = aspeed_uart_first(sc); 1118 int uart_last = aspeed_uart_last(sc); 1119 1120 if (sscanf(value, "uart%u", &val) != 1) { 1121 error_setg(errp, "Bad value for \"uart\" property"); 1122 return; 1123 } 1124 1125 /* The number of UART depends on the SoC */ 1126 if (val < uart_first || val > uart_last) { 1127 error_setg(errp, "\"uart\" should be in range [%d - %d]", 1128 uart_first, uart_last); 1129 return; 1130 } 1131 bmc->uart_chosen = val + ASPEED_DEV_UART0; 1132 } 1133 1134 static void aspeed_machine_class_props_init(ObjectClass *oc) 1135 { 1136 object_class_property_add_bool(oc, "execute-in-place", 1137 aspeed_get_mmio_exec, 1138 aspeed_set_mmio_exec); 1139 object_class_property_set_description(oc, "execute-in-place", 1140 "boot directly from CE0 flash device"); 1141 1142 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console, 1143 aspeed_set_bmc_console); 1144 object_class_property_set_description(oc, "bmc-console", 1145 "Change the default UART to \"uartX\""); 1146 1147 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1148 aspeed_set_fmc_model); 1149 object_class_property_set_description(oc, "fmc-model", 1150 "Change the FMC Flash model"); 1151 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1152 aspeed_set_spi_model); 1153 object_class_property_set_description(oc, "spi-model", 1154 "Change the SPI Flash model"); 1155 } 1156 1157 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) 1158 { 1159 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc); 1160 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1161 1162 mc->default_cpus = sc->num_cpus; 1163 mc->min_cpus = sc->num_cpus; 1164 mc->max_cpus = sc->num_cpus; 1165 mc->valid_cpu_types = sc->valid_cpu_types; 1166 } 1167 1168 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 1169 { 1170 MachineClass *mc = MACHINE_CLASS(oc); 1171 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1172 1173 mc->init = aspeed_machine_init; 1174 mc->no_floppy = 1; 1175 mc->no_cdrom = 1; 1176 mc->no_parallel = 1; 1177 mc->default_ram_id = "ram"; 1178 amc->macs_mask = ASPEED_MAC0_ON; 1179 amc->uart_default = ASPEED_DEV_UART5; 1180 1181 aspeed_machine_class_props_init(oc); 1182 } 1183 1184 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 1185 { 1186 MachineClass *mc = MACHINE_CLASS(oc); 1187 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1188 1189 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1190 amc->soc_name = "ast2400-a1"; 1191 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1192 amc->fmc_model = "n25q256a"; 1193 amc->spi_model = "mx25l25635f"; 1194 amc->num_cs = 1; 1195 amc->i2c_init = palmetto_bmc_i2c_init; 1196 mc->default_ram_size = 256 * MiB; 1197 aspeed_machine_class_init_cpus_defaults(mc); 1198 }; 1199 1200 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 1201 { 1202 MachineClass *mc = MACHINE_CLASS(oc); 1203 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1204 1205 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1206 amc->soc_name = "ast2400-a1"; 1207 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1208 amc->fmc_model = "n25q256a"; 1209 amc->spi_model = "mx25l25635e"; 1210 amc->num_cs = 1; 1211 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1212 mc->default_ram_size = 128 * MiB; 1213 aspeed_machine_class_init_cpus_defaults(mc); 1214 } 1215 1216 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1217 void *data) 1218 { 1219 MachineClass *mc = MACHINE_CLASS(oc); 1220 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1221 1222 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1223 amc->soc_name = "ast2400-a1"; 1224 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1225 amc->fmc_model = "mx25l25635e"; 1226 amc->spi_model = "mx25l25635e"; 1227 amc->num_cs = 1; 1228 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1229 amc->i2c_init = palmetto_bmc_i2c_init; 1230 mc->default_ram_size = 256 * MiB; 1231 aspeed_machine_class_init_cpus_defaults(mc); 1232 } 1233 1234 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, 1235 void *data) 1236 { 1237 MachineClass *mc = MACHINE_CLASS(oc); 1238 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1239 1240 mc->desc = "Supermicro X11 SPI BMC (ARM1176)"; 1241 amc->soc_name = "ast2500-a1"; 1242 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1; 1243 amc->fmc_model = "mx25l25635e"; 1244 amc->spi_model = "mx25l25635e"; 1245 amc->num_cs = 1; 1246 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1247 amc->i2c_init = palmetto_bmc_i2c_init; 1248 mc->default_ram_size = 512 * MiB; 1249 aspeed_machine_class_init_cpus_defaults(mc); 1250 } 1251 1252 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 1253 { 1254 MachineClass *mc = MACHINE_CLASS(oc); 1255 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1256 1257 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1258 amc->soc_name = "ast2500-a1"; 1259 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1260 amc->fmc_model = "mx25l25635e"; 1261 amc->spi_model = "mx25l25635f"; 1262 amc->num_cs = 1; 1263 amc->i2c_init = ast2500_evb_i2c_init; 1264 mc->default_ram_size = 512 * MiB; 1265 aspeed_machine_class_init_cpus_defaults(mc); 1266 }; 1267 1268 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data) 1269 { 1270 MachineClass *mc = MACHINE_CLASS(oc); 1271 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1272 1273 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)"; 1274 amc->soc_name = "ast2500-a1"; 1275 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1276 amc->hw_strap2 = 0; 1277 amc->fmc_model = "n25q256a"; 1278 amc->spi_model = "mx25l25635e"; 1279 amc->num_cs = 2; 1280 amc->i2c_init = yosemitev2_bmc_i2c_init; 1281 mc->default_ram_size = 512 * MiB; 1282 aspeed_machine_class_init_cpus_defaults(mc); 1283 }; 1284 1285 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 1286 { 1287 MachineClass *mc = MACHINE_CLASS(oc); 1288 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1289 1290 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1291 amc->soc_name = "ast2500-a1"; 1292 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1293 amc->fmc_model = "n25q256a"; 1294 amc->spi_model = "mx66l1g45g"; 1295 amc->num_cs = 2; 1296 amc->i2c_init = romulus_bmc_i2c_init; 1297 mc->default_ram_size = 512 * MiB; 1298 aspeed_machine_class_init_cpus_defaults(mc); 1299 }; 1300 1301 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data) 1302 { 1303 MachineClass *mc = MACHINE_CLASS(oc); 1304 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1305 1306 mc->desc = "Facebook Tiogapass BMC (ARM1176)"; 1307 amc->soc_name = "ast2500-a1"; 1308 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1309 amc->hw_strap2 = 0; 1310 amc->fmc_model = "n25q256a"; 1311 amc->spi_model = "mx25l25635e"; 1312 amc->num_cs = 2; 1313 amc->i2c_init = tiogapass_bmc_i2c_init; 1314 mc->default_ram_size = 1 * GiB; 1315 aspeed_machine_class_init_cpus_defaults(mc); 1316 }; 1317 1318 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 1319 { 1320 MachineClass *mc = MACHINE_CLASS(oc); 1321 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1322 1323 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1324 amc->soc_name = "ast2500-a1"; 1325 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1326 amc->fmc_model = "mx66l1g45g"; 1327 amc->spi_model = "mx66l1g45g"; 1328 amc->num_cs = 2; 1329 amc->i2c_init = sonorapass_bmc_i2c_init; 1330 mc->default_ram_size = 512 * MiB; 1331 aspeed_machine_class_init_cpus_defaults(mc); 1332 }; 1333 1334 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 1335 { 1336 MachineClass *mc = MACHINE_CLASS(oc); 1337 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1338 1339 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1340 amc->soc_name = "ast2500-a1"; 1341 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1342 amc->fmc_model = "mx25l25635f"; 1343 amc->spi_model = "mx66l1g45g"; 1344 amc->num_cs = 2; 1345 amc->i2c_init = witherspoon_bmc_i2c_init; 1346 mc->default_ram_size = 512 * MiB; 1347 aspeed_machine_class_init_cpus_defaults(mc); 1348 }; 1349 1350 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 1351 { 1352 MachineClass *mc = MACHINE_CLASS(oc); 1353 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1354 1355 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1356 amc->soc_name = "ast2600-a3"; 1357 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1358 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1359 amc->fmc_model = "mx66u51235f"; 1360 amc->spi_model = "mx66u51235f"; 1361 amc->num_cs = 1; 1362 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1363 ASPEED_MAC3_ON; 1364 amc->i2c_init = ast2600_evb_i2c_init; 1365 mc->default_ram_size = 1 * GiB; 1366 aspeed_machine_class_init_cpus_defaults(mc); 1367 }; 1368 1369 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) 1370 { 1371 MachineClass *mc = MACHINE_CLASS(oc); 1372 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1373 1374 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)"; 1375 amc->soc_name = "ast2600-a3"; 1376 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; 1377 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; 1378 amc->fmc_model = "mx66l1g45g"; 1379 amc->spi_model = "mx66l1g45g"; 1380 amc->num_cs = 2; 1381 amc->macs_mask = ASPEED_MAC2_ON; 1382 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ 1383 mc->default_ram_size = 1 * GiB; 1384 aspeed_machine_class_init_cpus_defaults(mc); 1385 1386 mc->deprecation_reason = "Please use the similar 'rainier-bmc' machine"; 1387 }; 1388 1389 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 1390 { 1391 MachineClass *mc = MACHINE_CLASS(oc); 1392 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1393 1394 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1395 amc->soc_name = "ast2500-a1"; 1396 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1397 amc->fmc_model = "n25q512a"; 1398 amc->spi_model = "mx25l25635e"; 1399 amc->num_cs = 2; 1400 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1401 amc->i2c_init = g220a_bmc_i2c_init; 1402 mc->default_ram_size = 1024 * MiB; 1403 aspeed_machine_class_init_cpus_defaults(mc); 1404 }; 1405 1406 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) 1407 { 1408 MachineClass *mc = MACHINE_CLASS(oc); 1409 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1410 1411 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1412 amc->soc_name = "ast2500-a1"; 1413 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1414 amc->fmc_model = "n25q512a"; 1415 amc->spi_model = "mx25l25635e"; 1416 amc->num_cs = 2; 1417 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1418 amc->i2c_init = fp5280g2_bmc_i2c_init; 1419 mc->default_ram_size = 512 * MiB; 1420 aspeed_machine_class_init_cpus_defaults(mc); 1421 }; 1422 1423 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1424 { 1425 MachineClass *mc = MACHINE_CLASS(oc); 1426 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1427 1428 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1429 amc->soc_name = "ast2600-a3"; 1430 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1431 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1432 amc->fmc_model = "mx66l1g45g"; 1433 amc->spi_model = "mx66l1g45g"; 1434 amc->num_cs = 2; 1435 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1436 amc->i2c_init = rainier_bmc_i2c_init; 1437 mc->default_ram_size = 1 * GiB; 1438 aspeed_machine_class_init_cpus_defaults(mc); 1439 }; 1440 1441 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1442 1443 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) 1444 { 1445 MachineClass *mc = MACHINE_CLASS(oc); 1446 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1447 1448 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1449 amc->soc_name = "ast2600-a3"; 1450 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1451 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1452 amc->fmc_model = "mx66l1g45g"; 1453 amc->spi_model = "mx66l1g45g"; 1454 amc->num_cs = 2; 1455 amc->macs_mask = ASPEED_MAC3_ON; 1456 amc->i2c_init = fuji_bmc_i2c_init; 1457 amc->uart_default = ASPEED_DEV_UART1; 1458 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1459 aspeed_machine_class_init_cpus_defaults(mc); 1460 }; 1461 1462 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1463 1464 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) 1465 { 1466 MachineClass *mc = MACHINE_CLASS(oc); 1467 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1468 1469 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1470 amc->soc_name = "ast2600-a3"; 1471 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1472 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1473 amc->fmc_model = "w25q01jvq"; 1474 amc->spi_model = NULL; 1475 amc->num_cs = 2; 1476 amc->macs_mask = ASPEED_MAC2_ON; 1477 amc->i2c_init = bletchley_bmc_i2c_init; 1478 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE; 1479 aspeed_machine_class_init_cpus_defaults(mc); 1480 } 1481 1482 static void fby35_reset(MachineState *state, ShutdownCause reason) 1483 { 1484 AspeedMachineState *bmc = ASPEED_MACHINE(state); 1485 AspeedGPIOState *gpio = &bmc->soc->gpio; 1486 1487 qemu_devices_reset(reason); 1488 1489 /* Board ID: 7 (Class-1, 4 slots) */ 1490 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); 1491 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); 1492 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); 1493 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); 1494 1495 /* Slot presence pins, inverse polarity. (False means present) */ 1496 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal); 1497 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal); 1498 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal); 1499 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal); 1500 1501 /* Slot 12v power pins, normal polarity. (True means powered-on) */ 1502 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal); 1503 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal); 1504 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal); 1505 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal); 1506 } 1507 1508 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data) 1509 { 1510 MachineClass *mc = MACHINE_CLASS(oc); 1511 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1512 1513 mc->desc = "Facebook fby35 BMC (Cortex-A7)"; 1514 mc->reset = fby35_reset; 1515 amc->fmc_model = "mx66l1g45g"; 1516 amc->num_cs = 2; 1517 amc->macs_mask = ASPEED_MAC3_ON; 1518 amc->i2c_init = fby35_i2c_init; 1519 /* FIXME: Replace this macro with something more general */ 1520 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1521 aspeed_machine_class_init_cpus_defaults(mc); 1522 } 1523 1524 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) 1525 /* Main SYSCLK frequency in Hz (200MHz) */ 1526 #define SYSCLK_FRQ 200000000ULL 1527 1528 static void aspeed_minibmc_machine_init(MachineState *machine) 1529 { 1530 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 1531 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 1532 Clock *sysclk; 1533 1534 sysclk = clock_new(OBJECT(machine), "SYSCLK"); 1535 clock_set_hz(sysclk, SYSCLK_FRQ); 1536 1537 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 1538 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 1539 object_unref(OBJECT(bmc->soc)); 1540 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk); 1541 1542 object_property_set_link(OBJECT(bmc->soc), "memory", 1543 OBJECT(get_system_memory()), &error_abort); 1544 connect_serial_hds_to_uarts(bmc); 1545 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 1546 1547 aspeed_board_init_flashes(&bmc->soc->fmc, 1548 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 1549 amc->num_cs, 1550 0); 1551 1552 aspeed_board_init_flashes(&bmc->soc->spi[0], 1553 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1554 amc->num_cs, amc->num_cs); 1555 1556 aspeed_board_init_flashes(&bmc->soc->spi[1], 1557 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1558 amc->num_cs, (amc->num_cs * 2)); 1559 1560 if (amc->i2c_init) { 1561 amc->i2c_init(bmc); 1562 } 1563 1564 armv7m_load_kernel(ARM_CPU(first_cpu), 1565 machine->kernel_filename, 1566 0, 1567 AST1030_INTERNAL_FLASH_SIZE); 1568 } 1569 1570 static void ast1030_evb_i2c_init(AspeedMachineState *bmc) 1571 { 1572 AspeedSoCState *soc = bmc->soc; 1573 1574 /* U10 24C08 connects to SDA/SCL Group 1 by default */ 1575 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 1576 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); 1577 1578 /* U11 LM75 connects to SDA/SCL Group 2 by default */ 1579 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d); 1580 } 1581 1582 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, 1583 void *data) 1584 { 1585 MachineClass *mc = MACHINE_CLASS(oc); 1586 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1587 1588 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; 1589 amc->soc_name = "ast1030-a1"; 1590 amc->hw_strap1 = 0; 1591 amc->hw_strap2 = 0; 1592 mc->init = aspeed_minibmc_machine_init; 1593 amc->i2c_init = ast1030_evb_i2c_init; 1594 mc->default_ram_size = 0; 1595 amc->fmc_model = "sst25vf032b"; 1596 amc->spi_model = "sst25vf032b"; 1597 amc->num_cs = 2; 1598 amc->macs_mask = 0; 1599 aspeed_machine_class_init_cpus_defaults(mc); 1600 } 1601 1602 #ifdef TARGET_AARCH64 1603 static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data) 1604 { 1605 MachineClass *mc = MACHINE_CLASS(oc); 1606 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1607 1608 mc->desc = "Aspeed AST2700 EVB (Cortex-A35)"; 1609 amc->soc_name = "ast2700-a0"; 1610 amc->hw_strap1 = AST2700_EVB_HW_STRAP1; 1611 amc->hw_strap2 = AST2700_EVB_HW_STRAP2; 1612 amc->fmc_model = "w25q01jvq"; 1613 amc->spi_model = "w25q512jv"; 1614 amc->num_cs = 2; 1615 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; 1616 amc->uart_default = ASPEED_DEV_UART12; 1617 mc->default_ram_size = 1 * GiB; 1618 aspeed_machine_class_init_cpus_defaults(mc); 1619 } 1620 #endif 1621 1622 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, 1623 void *data) 1624 { 1625 MachineClass *mc = MACHINE_CLASS(oc); 1626 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1627 1628 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)"; 1629 amc->soc_name = "ast2600-a3"; 1630 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1631 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1632 amc->fmc_model = "n25q512a"; 1633 amc->spi_model = "n25q512a"; 1634 amc->num_cs = 2; 1635 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1636 amc->i2c_init = qcom_dc_scm_bmc_i2c_init; 1637 mc->default_ram_size = 1 * GiB; 1638 aspeed_machine_class_init_cpus_defaults(mc); 1639 }; 1640 1641 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, 1642 void *data) 1643 { 1644 MachineClass *mc = MACHINE_CLASS(oc); 1645 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1646 1647 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; 1648 amc->soc_name = "ast2600-a3"; 1649 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1650 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1651 amc->fmc_model = "n25q512a"; 1652 amc->spi_model = "n25q512a"; 1653 amc->num_cs = 2; 1654 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1655 amc->i2c_init = qcom_dc_scm_firework_i2c_init; 1656 mc->default_ram_size = 1 * GiB; 1657 aspeed_machine_class_init_cpus_defaults(mc); 1658 }; 1659 1660 static const TypeInfo aspeed_machine_types[] = { 1661 { 1662 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1663 .parent = TYPE_ASPEED_MACHINE, 1664 .class_init = aspeed_machine_palmetto_class_init, 1665 }, { 1666 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1667 .parent = TYPE_ASPEED_MACHINE, 1668 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1669 }, { 1670 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), 1671 .parent = TYPE_ASPEED_MACHINE, 1672 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, 1673 }, { 1674 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1675 .parent = TYPE_ASPEED_MACHINE, 1676 .class_init = aspeed_machine_ast2500_evb_class_init, 1677 }, { 1678 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1679 .parent = TYPE_ASPEED_MACHINE, 1680 .class_init = aspeed_machine_romulus_class_init, 1681 }, { 1682 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1683 .parent = TYPE_ASPEED_MACHINE, 1684 .class_init = aspeed_machine_sonorapass_class_init, 1685 }, { 1686 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1687 .parent = TYPE_ASPEED_MACHINE, 1688 .class_init = aspeed_machine_witherspoon_class_init, 1689 }, { 1690 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1691 .parent = TYPE_ASPEED_MACHINE, 1692 .class_init = aspeed_machine_ast2600_evb_class_init, 1693 }, { 1694 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), 1695 .parent = TYPE_ASPEED_MACHINE, 1696 .class_init = aspeed_machine_yosemitev2_class_init, 1697 }, { 1698 .name = MACHINE_TYPE_NAME("tacoma-bmc"), 1699 .parent = TYPE_ASPEED_MACHINE, 1700 .class_init = aspeed_machine_tacoma_class_init, 1701 }, { 1702 .name = MACHINE_TYPE_NAME("tiogapass-bmc"), 1703 .parent = TYPE_ASPEED_MACHINE, 1704 .class_init = aspeed_machine_tiogapass_class_init, 1705 }, { 1706 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1707 .parent = TYPE_ASPEED_MACHINE, 1708 .class_init = aspeed_machine_g220a_class_init, 1709 }, { 1710 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), 1711 .parent = TYPE_ASPEED_MACHINE, 1712 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, 1713 }, { 1714 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), 1715 .parent = TYPE_ASPEED_MACHINE, 1716 .class_init = aspeed_machine_qcom_firework_class_init, 1717 }, { 1718 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1719 .parent = TYPE_ASPEED_MACHINE, 1720 .class_init = aspeed_machine_fp5280g2_class_init, 1721 }, { 1722 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1723 .parent = TYPE_ASPEED_MACHINE, 1724 .class_init = aspeed_machine_quanta_q71l_class_init, 1725 }, { 1726 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1727 .parent = TYPE_ASPEED_MACHINE, 1728 .class_init = aspeed_machine_rainier_class_init, 1729 }, { 1730 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1731 .parent = TYPE_ASPEED_MACHINE, 1732 .class_init = aspeed_machine_fuji_class_init, 1733 }, { 1734 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 1735 .parent = TYPE_ASPEED_MACHINE, 1736 .class_init = aspeed_machine_bletchley_class_init, 1737 }, { 1738 .name = MACHINE_TYPE_NAME("fby35-bmc"), 1739 .parent = MACHINE_TYPE_NAME("ast2600-evb"), 1740 .class_init = aspeed_machine_fby35_class_init, 1741 }, { 1742 .name = MACHINE_TYPE_NAME("ast1030-evb"), 1743 .parent = TYPE_ASPEED_MACHINE, 1744 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, 1745 #ifdef TARGET_AARCH64 1746 }, { 1747 .name = MACHINE_TYPE_NAME("ast2700-evb"), 1748 .parent = TYPE_ASPEED_MACHINE, 1749 .class_init = aspeed_machine_ast2700_evb_class_init, 1750 #endif 1751 }, { 1752 .name = TYPE_ASPEED_MACHINE, 1753 .parent = TYPE_MACHINE, 1754 .instance_size = sizeof(AspeedMachineState), 1755 .instance_init = aspeed_machine_instance_init, 1756 .class_size = sizeof(AspeedMachineClass), 1757 .class_init = aspeed_machine_class_init, 1758 .abstract = true, 1759 } 1760 }; 1761 1762 DEFINE_TYPES(aspeed_machine_types) 1763