1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/arm/aspeed_eeprom.h" 18 #include "hw/block/flash.h" 19 #include "hw/i2c/i2c_mux_pca954x.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/gpio/pca9552.h" 22 #include "hw/nvram/eeprom_at24c.h" 23 #include "hw/sensor/tmp105.h" 24 #include "hw/misc/led.h" 25 #include "hw/qdev-properties.h" 26 #include "sysemu/block-backend.h" 27 #include "sysemu/reset.h" 28 #include "hw/loader.h" 29 #include "qemu/error-report.h" 30 #include "qemu/units.h" 31 #include "hw/qdev-clock.h" 32 #include "sysemu/sysemu.h" 33 34 static struct arm_boot_info aspeed_board_binfo = { 35 .board_id = -1, /* device-tree-only board */ 36 }; 37 38 struct AspeedMachineState { 39 /* Private */ 40 MachineState parent_obj; 41 /* Public */ 42 43 AspeedSoCState *soc; 44 MemoryRegion boot_rom; 45 bool mmio_exec; 46 uint32_t uart_chosen; 47 char *fmc_model; 48 char *spi_model; 49 uint32_t hw_strap1; 50 }; 51 52 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 53 #if HOST_LONG_BITS == 32 54 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB) 55 #else 56 #define ASPEED_RAM_SIZE(sz) (sz) 57 #endif 58 59 /* Palmetto hardware value: 0x120CE416 */ 60 #define PALMETTO_BMC_HW_STRAP1 ( \ 61 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 62 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 63 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 64 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 65 SCU_HW_STRAP_VGA_CLASS_CODE | \ 66 SCU_HW_STRAP_LPC_RESET_PIN | \ 67 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 68 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 69 SCU_HW_STRAP_SPI_WIDTH | \ 70 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 71 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 72 73 /* TODO: Find the actual hardware value */ 74 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 75 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 76 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 77 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 78 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 79 SCU_HW_STRAP_VGA_CLASS_CODE | \ 80 SCU_HW_STRAP_LPC_RESET_PIN | \ 81 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 82 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 83 SCU_HW_STRAP_SPI_WIDTH | \ 84 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 85 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 86 87 /* TODO: Find the actual hardware value */ 88 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ 89 AST2500_HW_STRAP1_DEFAULTS | \ 90 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 91 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 92 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 93 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 94 SCU_HW_STRAP_SPI_WIDTH | \ 95 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) 96 97 /* AST2500 evb hardware value: 0xF100C2E6 */ 98 #define AST2500_EVB_HW_STRAP1 (( \ 99 AST2500_HW_STRAP1_DEFAULTS | \ 100 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 101 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 102 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 103 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 104 SCU_HW_STRAP_MAC1_RGMII | \ 105 SCU_HW_STRAP_MAC0_RGMII) & \ 106 ~SCU_HW_STRAP_2ND_BOOT_WDT) 107 108 /* Romulus hardware value: 0xF10AD206 */ 109 #define ROMULUS_BMC_HW_STRAP1 ( \ 110 AST2500_HW_STRAP1_DEFAULTS | \ 111 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 112 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 113 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 114 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 115 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 116 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 117 118 /* Sonorapass hardware value: 0xF100D216 */ 119 #define SONORAPASS_BMC_HW_STRAP1 ( \ 120 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 121 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 122 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 123 SCU_AST2500_HW_STRAP_RESERVED28 | \ 124 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 125 SCU_HW_STRAP_VGA_CLASS_CODE | \ 126 SCU_HW_STRAP_LPC_RESET_PIN | \ 127 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 128 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 129 SCU_HW_STRAP_VGA_BIOS_ROM | \ 130 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 131 SCU_AST2500_HW_STRAP_RESERVED1) 132 133 #define G220A_BMC_HW_STRAP1 ( \ 134 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 135 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 136 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 137 SCU_AST2500_HW_STRAP_RESERVED28 | \ 138 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 139 SCU_HW_STRAP_2ND_BOOT_WDT | \ 140 SCU_HW_STRAP_VGA_CLASS_CODE | \ 141 SCU_HW_STRAP_LPC_RESET_PIN | \ 142 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 143 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 144 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 145 SCU_AST2500_HW_STRAP_RESERVED1) 146 147 /* FP5280G2 hardware value: 0XF100D286 */ 148 #define FP5280G2_BMC_HW_STRAP1 ( \ 149 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 150 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 151 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 152 SCU_AST2500_HW_STRAP_RESERVED28 | \ 153 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 154 SCU_HW_STRAP_VGA_CLASS_CODE | \ 155 SCU_HW_STRAP_LPC_RESET_PIN | \ 156 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 157 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 158 SCU_HW_STRAP_MAC1_RGMII | \ 159 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 160 SCU_AST2500_HW_STRAP_RESERVED1) 161 162 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 163 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 164 165 /* Quanta-Q71l hardware value */ 166 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 167 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 168 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 169 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 170 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 171 SCU_HW_STRAP_VGA_CLASS_CODE | \ 172 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 173 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 174 SCU_HW_STRAP_SPI_WIDTH | \ 175 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 176 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 177 178 /* AST2600 evb hardware value */ 179 #define AST2600_EVB_HW_STRAP1 0x000000C0 180 #define AST2600_EVB_HW_STRAP2 0x00000003 181 182 #ifdef TARGET_AARCH64 183 /* AST2700 evb hardware value */ 184 #define AST2700_EVB_HW_STRAP1 0x000000C0 185 #define AST2700_EVB_HW_STRAP2 0x00000003 186 #endif 187 188 /* Rainier hardware value: (QEMU prototype) */ 189 #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC) 190 #define RAINIER_BMC_HW_STRAP2 0x80000848 191 192 /* Fuji hardware value */ 193 #define FUJI_BMC_HW_STRAP1 0x00000000 194 #define FUJI_BMC_HW_STRAP2 0x00000000 195 196 /* Bletchley hardware value */ 197 /* TODO: Leave same as EVB for now. */ 198 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 199 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 200 201 /* Qualcomm DC-SCM hardware value */ 202 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 203 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 204 205 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 206 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 207 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 208 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 209 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 210 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 211 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 212 213 static void aspeed_write_smpboot(ARMCPU *cpu, 214 const struct arm_boot_info *info) 215 { 216 AddressSpace *as = arm_boot_address_space(cpu, info); 217 static const ARMInsnFixup poll_mailbox_ready[] = { 218 /* 219 * r2 = per-cpu go sign value 220 * r1 = AST_SMP_MBOX_FIELD_ENTRY 221 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 222 */ 223 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ 224 { 0xe21000ff }, /* ands r0, r0, #255 */ 225 { 0xe59f201c }, /* ldr r2, [pc, #28] */ 226 { 0xe1822000 }, /* orr r2, r2, r0 */ 227 228 { 0xe59f1018 }, /* ldr r1, [pc, #24] */ 229 { 0xe59f0018 }, /* ldr r0, [pc, #24] */ 230 231 { 0xe320f002 }, /* wfe */ 232 { 0xe5904000 }, /* ldr r4, [r0] */ 233 { 0xe1520004 }, /* cmp r2, r4 */ 234 { 0x1afffffb }, /* bne <wfe> */ 235 { 0xe591f000 }, /* ldr pc, [r1] */ 236 { AST_SMP_MBOX_GOSIGN }, 237 { AST_SMP_MBOX_FIELD_ENTRY }, 238 { AST_SMP_MBOX_FIELD_GOSIGN }, 239 { 0, FIXUP_TERMINATOR } 240 }; 241 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; 242 243 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, 244 poll_mailbox_ready, fixupcontext); 245 } 246 247 static void aspeed_reset_secondary(ARMCPU *cpu, 248 const struct arm_boot_info *info) 249 { 250 AddressSpace *as = arm_boot_address_space(cpu, info); 251 CPUState *cs = CPU(cpu); 252 253 /* info->smp_bootreg_addr */ 254 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 255 MEMTXATTRS_UNSPECIFIED, NULL); 256 cpu_set_pc(cs, info->smp_loader_start); 257 } 258 259 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size, 260 Error **errp) 261 { 262 g_autofree void *storage = NULL; 263 int64_t size; 264 265 /* 266 * The block backend size should have already been 'validated' by 267 * the creation of the m25p80 object. 268 */ 269 size = blk_getlength(blk); 270 if (size <= 0) { 271 error_setg(errp, "failed to get flash size"); 272 return; 273 } 274 275 if (rom_size > size) { 276 rom_size = size; 277 } 278 279 storage = g_malloc0(rom_size); 280 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { 281 error_setg(errp, "failed to read the initial flash content"); 282 return; 283 } 284 285 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 286 } 287 288 /* 289 * Create a ROM and copy the flash contents at the expected address 290 * (0x0). Boots faster than execute-in-place. 291 */ 292 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk, 293 uint64_t rom_size) 294 { 295 AspeedSoCState *soc = bmc->soc; 296 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc); 297 298 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size, 299 &error_abort); 300 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, 301 &bmc->boot_rom, 1); 302 write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT], 303 rom_size, &error_abort); 304 } 305 306 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 307 unsigned int count, int unit0) 308 { 309 int i; 310 311 if (!flashtype) { 312 return; 313 } 314 315 for (i = 0; i < count; ++i) { 316 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 317 DeviceState *dev; 318 319 dev = qdev_new(flashtype); 320 if (dinfo) { 321 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 322 } 323 qdev_prop_set_uint8(dev, "cs", i); 324 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 325 } 326 } 327 328 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc, 329 bool boot_emmc) 330 { 331 DeviceState *card; 332 333 if (!dinfo) { 334 return; 335 } 336 card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD); 337 338 /* 339 * Force the boot properties of the eMMC device only when the 340 * machine is strapped to boot from eMMC. Without these 341 * settings, the machine would not boot. 342 * 343 * This also allows the machine to use an eMMC device without 344 * boot areas when booting from the flash device (or -kernel) 345 * Ideally, the device and its properties should be defined on 346 * the command line. 347 */ 348 if (emmc && boot_emmc) { 349 qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB); 350 qdev_prop_set_uint8(card, "boot-config", 0x1 << 3); 351 } 352 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 353 &error_fatal); 354 qdev_realize_and_unref(card, 355 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 356 &error_fatal); 357 } 358 359 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) 360 { 361 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 362 AspeedSoCState *s = bmc->soc; 363 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 364 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 365 366 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); 367 for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) { 368 if (uart == uart_chosen) { 369 continue; 370 } 371 aspeed_soc_uart_set_chr(s, uart, serial_hd(i)); 372 } 373 } 374 375 static void aspeed_machine_init(MachineState *machine) 376 { 377 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 378 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 379 AspeedSoCClass *sc; 380 int i; 381 DriveInfo *emmc0 = NULL; 382 bool boot_emmc; 383 384 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 385 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 386 object_unref(OBJECT(bmc->soc)); 387 sc = ASPEED_SOC_GET_CLASS(bmc->soc); 388 389 /* 390 * This will error out if the RAM size is not supported by the 391 * memory controller of the SoC. 392 */ 393 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size, 394 &error_fatal); 395 396 for (i = 0; i < sc->macs_num; i++) { 397 if ((amc->macs_mask & (1 << i)) && 398 !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]), 399 true, NULL)) { 400 break; /* No configs left; stop asking */ 401 } 402 } 403 404 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", bmc->hw_strap1, 405 &error_abort); 406 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2, 407 &error_abort); 408 object_property_set_link(OBJECT(bmc->soc), "memory", 409 OBJECT(get_system_memory()), &error_abort); 410 object_property_set_link(OBJECT(bmc->soc), "dram", 411 OBJECT(machine->ram), &error_abort); 412 if (amc->sdhci_wp_inverted) { 413 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { 414 object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]), 415 "wp-inverted", true, &error_abort); 416 } 417 } 418 if (machine->kernel_filename) { 419 /* 420 * When booting with a -kernel command line there is no u-boot 421 * that runs to unlock the SCU. In this case set the default to 422 * be unlocked as the kernel expects 423 */ 424 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key", 425 ASPEED_SCU_PROT_KEY, &error_abort); 426 } 427 connect_serial_hds_to_uarts(bmc); 428 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 429 430 if (defaults_enabled()) { 431 aspeed_board_init_flashes(&bmc->soc->fmc, 432 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 433 amc->num_cs, 0); 434 aspeed_board_init_flashes(&bmc->soc->spi[0], 435 bmc->spi_model ? bmc->spi_model : amc->spi_model, 436 1, amc->num_cs); 437 } 438 439 if (machine->kernel_filename && sc->num_cpus > 1) { 440 /* With no u-boot we must set up a boot stub for the secondary CPU */ 441 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 442 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 443 0x80, &error_abort); 444 memory_region_add_subregion(get_system_memory(), 445 AST_SMP_MAILBOX_BASE, smpboot); 446 447 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 448 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 449 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 450 } 451 452 aspeed_board_binfo.ram_size = machine->ram_size; 453 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 454 455 if (amc->i2c_init) { 456 amc->i2c_init(bmc); 457 } 458 459 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { 460 sdhci_attach_drive(&bmc->soc->sdhci.slots[i], 461 drive_get(IF_SD, 0, i), false, false); 462 } 463 464 boot_emmc = sc->boot_from_emmc(bmc->soc); 465 466 if (bmc->soc->emmc.num_slots) { 467 emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots); 468 sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emmc); 469 } 470 471 if (!bmc->mmio_exec) { 472 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0); 473 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL; 474 475 if (fmc0 && !boot_emmc) { 476 uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot); 477 aspeed_install_boot_rom(bmc, fmc0, rom_size); 478 } else if (emmc0) { 479 aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(emmc0), 64 * KiB); 480 } 481 } 482 483 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 484 } 485 486 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 487 { 488 AspeedSoCState *soc = bmc->soc; 489 DeviceState *dev; 490 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 491 492 /* 493 * The palmetto platform expects a ds3231 RTC but a ds1338 is 494 * enough to provide basic RTC features. Alarms will be missing 495 */ 496 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 497 498 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 499 eeprom_buf); 500 501 /* add a TMP423 temperature sensor */ 502 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 503 "tmp423", 0x4c)); 504 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 505 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 506 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 507 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 508 } 509 510 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 511 { 512 AspeedSoCState *soc = bmc->soc; 513 514 /* 515 * The quanta-q71l platform expects tmp75s which are compatible with 516 * tmp105s. 517 */ 518 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 519 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 520 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 521 522 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 523 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 524 /* TODO: Add Memory Riser i2c mux and eeproms. */ 525 526 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 527 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 528 529 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 530 531 /* i2c-7 */ 532 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 533 /* - i2c@0: pmbus@59 */ 534 /* - i2c@1: pmbus@58 */ 535 /* - i2c@2: pmbus@58 */ 536 /* - i2c@3: pmbus@59 */ 537 538 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 539 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 540 } 541 542 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 543 { 544 AspeedSoCState *soc = bmc->soc; 545 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 546 547 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 548 eeprom_buf); 549 550 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 551 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 552 TYPE_TMP105, 0x4d); 553 } 554 555 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 556 { 557 AspeedSoCState *soc = bmc->soc; 558 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 559 560 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 561 eeprom_buf); 562 563 /* LM75 is compatible with TMP105 driver */ 564 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 565 TYPE_TMP105, 0x4d); 566 } 567 568 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) 569 { 570 AspeedSoCState *soc = bmc->soc; 571 572 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); 573 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB, 574 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len); 575 /* TMP421 */ 576 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f); 577 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e); 578 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f); 579 580 } 581 582 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 583 { 584 AspeedSoCState *soc = bmc->soc; 585 586 /* 587 * The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 588 * good enough 589 */ 590 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 591 } 592 593 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc) 594 { 595 AspeedSoCState *soc = bmc->soc; 596 597 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB); 598 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB, 599 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len); 600 /* TMP421 */ 601 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f); 602 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f); 603 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e); 604 } 605 606 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 607 { 608 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 609 TYPE_PCA9552, addr); 610 } 611 612 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 613 { 614 AspeedSoCState *soc = bmc->soc; 615 616 /* bus 2 : */ 617 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 618 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 619 /* bus 2 : pca9546 @ 0x73 */ 620 621 /* bus 3 : pca9548 @ 0x70 */ 622 623 /* bus 4 : */ 624 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 625 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 626 eeprom4_54); 627 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 628 create_pca9552(soc, 4, 0x76); 629 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 630 create_pca9552(soc, 4, 0x77); 631 632 /* bus 6 : */ 633 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 634 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 635 /* bus 6 : pca9546 @ 0x73 */ 636 637 /* bus 8 : */ 638 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 639 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 640 eeprom8_56); 641 create_pca9552(soc, 8, 0x60); 642 create_pca9552(soc, 8, 0x61); 643 /* bus 8 : adc128d818 @ 0x1d */ 644 /* bus 8 : adc128d818 @ 0x1f */ 645 646 /* 647 * bus 13 : pca9548 @ 0x71 648 * - channel 3: 649 * - tmm421 @ 0x4c 650 * - tmp421 @ 0x4e 651 * - tmp421 @ 0x4f 652 */ 653 654 } 655 656 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 657 { 658 static const struct { 659 unsigned gpio_id; 660 LEDColor color; 661 const char *description; 662 bool gpio_polarity; 663 } pca1_leds[] = { 664 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 665 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 666 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 667 }; 668 AspeedSoCState *soc = bmc->soc; 669 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 670 DeviceState *dev; 671 LEDState *led; 672 673 /* Bus 3: TODO bmp280@77 */ 674 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 675 qdev_prop_set_string(dev, "description", "pca1"); 676 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 677 aspeed_i2c_get_bus(&soc->i2c, 3), 678 &error_fatal); 679 680 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 681 led = led_create_simple(OBJECT(bmc), 682 pca1_leds[i].gpio_polarity, 683 pca1_leds[i].color, 684 pca1_leds[i].description); 685 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 686 qdev_get_gpio_in(DEVICE(led), 0)); 687 } 688 689 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 690 0x68); 691 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 692 0x69); 693 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 694 695 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52); 696 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 697 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 698 699 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 700 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 701 0x4a); 702 703 /* 704 * The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 705 * good enough 706 */ 707 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 708 709 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 710 eeprom_buf); 711 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 712 qdev_prop_set_string(dev, "description", "pca0"); 713 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 714 aspeed_i2c_get_bus(&soc->i2c, 11), 715 &error_fatal); 716 /* Bus 11: TODO ucd90160@64 */ 717 } 718 719 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 720 { 721 AspeedSoCState *soc = bmc->soc; 722 DeviceState *dev; 723 724 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 725 "emc1413", 0x4c)); 726 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 727 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 728 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 729 730 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 731 "emc1413", 0x4c)); 732 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 733 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 734 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 735 736 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 737 "emc1413", 0x4c)); 738 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 739 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 740 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 741 742 static uint8_t eeprom_buf[2 * 1024] = { 743 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 744 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 745 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 746 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 747 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 748 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 749 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 750 }; 751 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 752 eeprom_buf); 753 } 754 755 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 756 { 757 AspeedSoCState *soc = bmc->soc; 758 I2CSlave *i2c_mux; 759 760 /* The at24c256 */ 761 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 762 763 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 764 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 765 0x48); 766 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 767 0x49); 768 769 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 770 "pca9546", 0x70); 771 /* It expects a TMP112 but a TMP105 is compatible */ 772 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 773 0x4a); 774 775 /* It expects a ds3232 but a ds1338 is good enough */ 776 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 777 778 /* It expects a pca9555 but a pca9552 is compatible */ 779 create_pca9552(soc, 8, 0x30); 780 } 781 782 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 783 { 784 AspeedSoCState *soc = bmc->soc; 785 I2CSlave *i2c_mux; 786 787 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 788 789 create_pca9552(soc, 3, 0x61); 790 791 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 792 0x68); 793 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 794 0x69); 795 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 796 0x6a); 797 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "ibm-cffps", 798 0x6b); 799 800 /* The rainier expects a TMP275 but a TMP105 is compatible */ 801 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 802 0x48); 803 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 804 0x49); 805 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 806 0x4a); 807 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 808 "pca9546", 0x70); 809 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 810 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 811 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 812 create_pca9552(soc, 4, 0x60); 813 814 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 815 0x48); 816 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 817 0x49); 818 create_pca9552(soc, 5, 0x60); 819 create_pca9552(soc, 5, 0x61); 820 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 821 "pca9546", 0x70); 822 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 823 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 824 825 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 826 0x48); 827 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 828 0x4a); 829 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 830 0x4b); 831 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 832 "pca9546", 0x70); 833 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 834 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 835 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 836 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 837 838 create_pca9552(soc, 7, 0x30); 839 create_pca9552(soc, 7, 0x31); 840 create_pca9552(soc, 7, 0x32); 841 create_pca9552(soc, 7, 0x33); 842 create_pca9552(soc, 7, 0x60); 843 create_pca9552(soc, 7, 0x61); 844 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 845 /* Bus 7: TODO si7021-a20@20 */ 846 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 847 0x48); 848 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52); 849 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 850 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 851 852 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 853 0x48); 854 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 855 0x4a); 856 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 857 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len); 858 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 859 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len); 860 create_pca9552(soc, 8, 0x60); 861 create_pca9552(soc, 8, 0x61); 862 /* Bus 8: ucd90320@11 */ 863 /* Bus 8: ucd90320@b */ 864 /* Bus 8: ucd90320@c */ 865 866 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 867 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 868 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 869 870 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 871 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 872 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 873 874 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 875 0x48); 876 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 877 0x49); 878 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 879 "pca9546", 0x70); 880 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 881 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 882 create_pca9552(soc, 11, 0x60); 883 884 885 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 886 create_pca9552(soc, 13, 0x60); 887 888 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 889 create_pca9552(soc, 14, 0x60); 890 891 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 892 create_pca9552(soc, 15, 0x60); 893 } 894 895 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 896 I2CBus **channels) 897 { 898 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 899 for (int i = 0; i < 8; i++) { 900 channels[i] = pca954x_i2c_get_bus(mux, i); 901 } 902 } 903 904 #define TYPE_LM75 TYPE_TMP105 905 #define TYPE_TMP75 TYPE_TMP105 906 #define TYPE_TMP422 "tmp422" 907 908 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 909 { 910 AspeedSoCState *soc = bmc->soc; 911 I2CBus *i2c[144] = {}; 912 913 for (int i = 0; i < 16; i++) { 914 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 915 } 916 I2CBus *i2c180 = i2c[2]; 917 I2CBus *i2c480 = i2c[8]; 918 I2CBus *i2c600 = i2c[11]; 919 920 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 921 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 922 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 923 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 924 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 925 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 926 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 927 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 928 for (int i = 0; i < 8; i++) { 929 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 930 } 931 932 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 933 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 934 935 /* 936 * EEPROM 24c64 size is 64Kbits or 8 Kbytes 937 * 24c02 size is 2Kbits or 256 bytes 938 */ 939 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB); 940 at24c_eeprom_init(i2c[20], 0x50, 256); 941 at24c_eeprom_init(i2c[22], 0x52, 256); 942 943 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 944 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 945 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 946 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 947 948 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB); 949 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 950 951 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 952 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB); 953 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 954 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 955 956 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 957 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 958 959 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB); 960 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 961 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 962 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB); 963 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB); 964 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB); 965 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB); 966 967 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB); 968 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 969 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 970 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB); 971 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB); 972 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB); 973 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB); 974 at24c_eeprom_init(i2c[28], 0x50, 256); 975 976 for (int i = 0; i < 8; i++) { 977 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 978 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 979 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 980 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 981 } 982 } 983 984 #define TYPE_TMP421 "tmp421" 985 986 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 987 { 988 AspeedSoCState *soc = bmc->soc; 989 I2CBus *i2c[13] = {}; 990 for (int i = 0; i < 13; i++) { 991 if ((i == 8) || (i == 11)) { 992 continue; 993 } 994 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 995 } 996 997 /* Bus 0 - 5 all have the same config. */ 998 for (int i = 0; i < 6; i++) { 999 /* Missing model: ti,ina230 @ 0x45 */ 1000 /* Missing model: mps,mp5023 @ 0x40 */ 1001 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 1002 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 1003 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 1004 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 1005 /* Missing model: fsc,fusb302 @ 0x22 */ 1006 } 1007 1008 /* Bus 6 */ 1009 at24c_eeprom_init(i2c[6], 0x56, 65536); 1010 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 1011 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 1012 1013 1014 /* Bus 7 */ 1015 at24c_eeprom_init(i2c[7], 0x54, 65536); 1016 1017 /* Bus 9 */ 1018 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 1019 1020 /* Bus 10 */ 1021 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 1022 /* Missing model: ti,hdc1080 @ 0x40 */ 1023 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 1024 1025 /* Bus 12 */ 1026 /* Missing model: adi,adm1278 @ 0x11 */ 1027 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 1028 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 1029 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 1030 } 1031 1032 static void fby35_i2c_init(AspeedMachineState *bmc) 1033 { 1034 AspeedSoCState *soc = bmc->soc; 1035 I2CBus *i2c[16]; 1036 1037 for (int i = 0; i < 16; i++) { 1038 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1039 } 1040 1041 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); 1042 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); 1043 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ 1044 i2c_slave_create_simple(i2c[11], "adm1272", 0x44); 1045 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); 1046 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); 1047 1048 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB); 1049 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB); 1050 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid, 1051 fby35_nic_fruid_len); 1052 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid, 1053 fby35_bb_fruid_len); 1054 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid, 1055 fby35_bmc_fruid_len); 1056 1057 /* 1058 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on 1059 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on 1060 * each. 1061 */ 1062 } 1063 1064 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) 1065 { 1066 AspeedSoCState *soc = bmc->soc; 1067 1068 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); 1069 } 1070 1071 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) 1072 { 1073 AspeedSoCState *soc = bmc->soc; 1074 I2CSlave *therm_mux, *cpuvr_mux; 1075 1076 /* Create the generic DC-SCM hardware */ 1077 qcom_dc_scm_bmc_i2c_init(bmc); 1078 1079 /* Now create the Firework specific hardware */ 1080 1081 /* I2C7 CPUVR MUX */ 1082 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 1083 "pca9546", 0x70); 1084 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72); 1085 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72); 1086 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72); 1087 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72); 1088 1089 /* I2C8 Thermal Diodes*/ 1090 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 1091 "pca9548", 0x70); 1092 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C); 1093 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C); 1094 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48); 1095 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48); 1096 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48); 1097 1098 /* I2C9 Fan Controller (MAX31785) */ 1099 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52); 1100 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54); 1101 } 1102 1103 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 1104 { 1105 return ASPEED_MACHINE(obj)->mmio_exec; 1106 } 1107 1108 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 1109 { 1110 ASPEED_MACHINE(obj)->mmio_exec = value; 1111 } 1112 1113 static void aspeed_machine_instance_init(Object *obj) 1114 { 1115 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj); 1116 1117 ASPEED_MACHINE(obj)->mmio_exec = false; 1118 ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1; 1119 } 1120 1121 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 1122 { 1123 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1124 return g_strdup(bmc->fmc_model); 1125 } 1126 1127 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 1128 { 1129 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1130 1131 g_free(bmc->fmc_model); 1132 bmc->fmc_model = g_strdup(value); 1133 } 1134 1135 static char *aspeed_get_spi_model(Object *obj, Error **errp) 1136 { 1137 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1138 return g_strdup(bmc->spi_model); 1139 } 1140 1141 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 1142 { 1143 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1144 1145 g_free(bmc->spi_model); 1146 bmc->spi_model = g_strdup(value); 1147 } 1148 1149 static char *aspeed_get_bmc_console(Object *obj, Error **errp) 1150 { 1151 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1152 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1153 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 1154 1155 return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen)); 1156 } 1157 1158 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp) 1159 { 1160 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1161 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1162 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1163 int val; 1164 int uart_first = aspeed_uart_first(sc); 1165 int uart_last = aspeed_uart_last(sc); 1166 1167 if (sscanf(value, "uart%u", &val) != 1) { 1168 error_setg(errp, "Bad value for \"uart\" property"); 1169 return; 1170 } 1171 1172 /* The number of UART depends on the SoC */ 1173 if (val < uart_first || val > uart_last) { 1174 error_setg(errp, "\"uart\" should be in range [%d - %d]", 1175 uart_first, uart_last); 1176 return; 1177 } 1178 bmc->uart_chosen = val + ASPEED_DEV_UART0; 1179 } 1180 1181 static void aspeed_machine_class_props_init(ObjectClass *oc) 1182 { 1183 object_class_property_add_bool(oc, "execute-in-place", 1184 aspeed_get_mmio_exec, 1185 aspeed_set_mmio_exec); 1186 object_class_property_set_description(oc, "execute-in-place", 1187 "boot directly from CE0 flash device"); 1188 1189 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console, 1190 aspeed_set_bmc_console); 1191 object_class_property_set_description(oc, "bmc-console", 1192 "Change the default UART to \"uartX\""); 1193 1194 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1195 aspeed_set_fmc_model); 1196 object_class_property_set_description(oc, "fmc-model", 1197 "Change the FMC Flash model"); 1198 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1199 aspeed_set_spi_model); 1200 object_class_property_set_description(oc, "spi-model", 1201 "Change the SPI Flash model"); 1202 } 1203 1204 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) 1205 { 1206 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc); 1207 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1208 1209 mc->default_cpus = sc->num_cpus; 1210 mc->min_cpus = sc->num_cpus; 1211 mc->max_cpus = sc->num_cpus; 1212 mc->valid_cpu_types = sc->valid_cpu_types; 1213 } 1214 1215 static bool aspeed_machine_ast2600_get_boot_from_emmc(Object *obj, Error **errp) 1216 { 1217 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1218 1219 return !!(bmc->hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); 1220 } 1221 1222 static void aspeed_machine_ast2600_set_boot_from_emmc(Object *obj, bool value, 1223 Error **errp) 1224 { 1225 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1226 1227 if (value) { 1228 bmc->hw_strap1 |= SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 1229 } else { 1230 bmc->hw_strap1 &= ~SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 1231 } 1232 } 1233 1234 static void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc) 1235 { 1236 object_class_property_add_bool(oc, "boot-emmc", 1237 aspeed_machine_ast2600_get_boot_from_emmc, 1238 aspeed_machine_ast2600_set_boot_from_emmc); 1239 object_class_property_set_description(oc, "boot-emmc", 1240 "Set or unset boot from EMMC"); 1241 } 1242 1243 static void aspeed_machine_class_init(ObjectClass *oc, void *data) 1244 { 1245 MachineClass *mc = MACHINE_CLASS(oc); 1246 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1247 1248 mc->init = aspeed_machine_init; 1249 mc->no_floppy = 1; 1250 mc->no_cdrom = 1; 1251 mc->no_parallel = 1; 1252 mc->default_ram_id = "ram"; 1253 amc->macs_mask = ASPEED_MAC0_ON; 1254 amc->uart_default = ASPEED_DEV_UART5; 1255 1256 aspeed_machine_class_props_init(oc); 1257 } 1258 1259 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) 1260 { 1261 MachineClass *mc = MACHINE_CLASS(oc); 1262 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1263 1264 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1265 amc->soc_name = "ast2400-a1"; 1266 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1267 amc->fmc_model = "n25q256a"; 1268 amc->spi_model = "mx25l25635f"; 1269 amc->num_cs = 1; 1270 amc->i2c_init = palmetto_bmc_i2c_init; 1271 mc->default_ram_size = 256 * MiB; 1272 aspeed_machine_class_init_cpus_defaults(mc); 1273 }; 1274 1275 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) 1276 { 1277 MachineClass *mc = MACHINE_CLASS(oc); 1278 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1279 1280 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1281 amc->soc_name = "ast2400-a1"; 1282 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1283 amc->fmc_model = "n25q256a"; 1284 amc->spi_model = "mx25l25635e"; 1285 amc->num_cs = 1; 1286 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1287 mc->default_ram_size = 128 * MiB; 1288 aspeed_machine_class_init_cpus_defaults(mc); 1289 } 1290 1291 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1292 void *data) 1293 { 1294 MachineClass *mc = MACHINE_CLASS(oc); 1295 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1296 1297 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1298 amc->soc_name = "ast2400-a1"; 1299 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1300 amc->fmc_model = "mx25l25635e"; 1301 amc->spi_model = "mx25l25635e"; 1302 amc->num_cs = 1; 1303 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1304 amc->i2c_init = palmetto_bmc_i2c_init; 1305 mc->default_ram_size = 256 * MiB; 1306 aspeed_machine_class_init_cpus_defaults(mc); 1307 } 1308 1309 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, 1310 void *data) 1311 { 1312 MachineClass *mc = MACHINE_CLASS(oc); 1313 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1314 1315 mc->desc = "Supermicro X11 SPI BMC (ARM1176)"; 1316 amc->soc_name = "ast2500-a1"; 1317 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1; 1318 amc->fmc_model = "mx25l25635e"; 1319 amc->spi_model = "mx25l25635e"; 1320 amc->num_cs = 1; 1321 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1322 amc->i2c_init = palmetto_bmc_i2c_init; 1323 mc->default_ram_size = 512 * MiB; 1324 aspeed_machine_class_init_cpus_defaults(mc); 1325 } 1326 1327 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) 1328 { 1329 MachineClass *mc = MACHINE_CLASS(oc); 1330 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1331 1332 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1333 amc->soc_name = "ast2500-a1"; 1334 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1335 amc->fmc_model = "mx25l25635e"; 1336 amc->spi_model = "mx25l25635f"; 1337 amc->num_cs = 1; 1338 amc->i2c_init = ast2500_evb_i2c_init; 1339 mc->default_ram_size = 512 * MiB; 1340 aspeed_machine_class_init_cpus_defaults(mc); 1341 }; 1342 1343 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data) 1344 { 1345 MachineClass *mc = MACHINE_CLASS(oc); 1346 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1347 1348 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)"; 1349 amc->soc_name = "ast2500-a1"; 1350 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1351 amc->hw_strap2 = 0; 1352 amc->fmc_model = "n25q256a"; 1353 amc->spi_model = "mx25l25635e"; 1354 amc->num_cs = 2; 1355 amc->i2c_init = yosemitev2_bmc_i2c_init; 1356 mc->default_ram_size = 512 * MiB; 1357 aspeed_machine_class_init_cpus_defaults(mc); 1358 }; 1359 1360 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) 1361 { 1362 MachineClass *mc = MACHINE_CLASS(oc); 1363 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1364 1365 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1366 amc->soc_name = "ast2500-a1"; 1367 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1368 amc->fmc_model = "n25q256a"; 1369 amc->spi_model = "mx66l1g45g"; 1370 amc->num_cs = 2; 1371 amc->i2c_init = romulus_bmc_i2c_init; 1372 mc->default_ram_size = 512 * MiB; 1373 aspeed_machine_class_init_cpus_defaults(mc); 1374 }; 1375 1376 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data) 1377 { 1378 MachineClass *mc = MACHINE_CLASS(oc); 1379 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1380 1381 mc->desc = "Facebook Tiogapass BMC (ARM1176)"; 1382 amc->soc_name = "ast2500-a1"; 1383 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1384 amc->hw_strap2 = 0; 1385 amc->fmc_model = "n25q256a"; 1386 amc->spi_model = "mx25l25635e"; 1387 amc->num_cs = 2; 1388 amc->i2c_init = tiogapass_bmc_i2c_init; 1389 mc->default_ram_size = 1 * GiB; 1390 aspeed_machine_class_init_cpus_defaults(mc); 1391 }; 1392 1393 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) 1394 { 1395 MachineClass *mc = MACHINE_CLASS(oc); 1396 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1397 1398 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1399 amc->soc_name = "ast2500-a1"; 1400 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1401 amc->fmc_model = "mx66l1g45g"; 1402 amc->spi_model = "mx66l1g45g"; 1403 amc->num_cs = 2; 1404 amc->i2c_init = sonorapass_bmc_i2c_init; 1405 mc->default_ram_size = 512 * MiB; 1406 aspeed_machine_class_init_cpus_defaults(mc); 1407 }; 1408 1409 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) 1410 { 1411 MachineClass *mc = MACHINE_CLASS(oc); 1412 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1413 1414 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1415 amc->soc_name = "ast2500-a1"; 1416 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1417 amc->fmc_model = "mx25l25635f"; 1418 amc->spi_model = "mx66l1g45g"; 1419 amc->num_cs = 2; 1420 amc->i2c_init = witherspoon_bmc_i2c_init; 1421 mc->default_ram_size = 512 * MiB; 1422 aspeed_machine_class_init_cpus_defaults(mc); 1423 }; 1424 1425 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) 1426 { 1427 MachineClass *mc = MACHINE_CLASS(oc); 1428 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1429 1430 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1431 amc->soc_name = "ast2600-a3"; 1432 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1433 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1434 amc->fmc_model = "mx66u51235f"; 1435 amc->spi_model = "mx66u51235f"; 1436 amc->num_cs = 1; 1437 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1438 ASPEED_MAC3_ON; 1439 amc->sdhci_wp_inverted = true; 1440 amc->i2c_init = ast2600_evb_i2c_init; 1441 mc->default_ram_size = 1 * GiB; 1442 aspeed_machine_class_init_cpus_defaults(mc); 1443 aspeed_machine_ast2600_class_emmc_init(oc); 1444 }; 1445 1446 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) 1447 { 1448 MachineClass *mc = MACHINE_CLASS(oc); 1449 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1450 1451 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1452 amc->soc_name = "ast2500-a1"; 1453 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1454 amc->fmc_model = "n25q512a"; 1455 amc->spi_model = "mx25l25635e"; 1456 amc->num_cs = 2; 1457 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1458 amc->i2c_init = g220a_bmc_i2c_init; 1459 mc->default_ram_size = 1024 * MiB; 1460 aspeed_machine_class_init_cpus_defaults(mc); 1461 }; 1462 1463 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) 1464 { 1465 MachineClass *mc = MACHINE_CLASS(oc); 1466 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1467 1468 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1469 amc->soc_name = "ast2500-a1"; 1470 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1471 amc->fmc_model = "n25q512a"; 1472 amc->spi_model = "mx25l25635e"; 1473 amc->num_cs = 2; 1474 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1475 amc->i2c_init = fp5280g2_bmc_i2c_init; 1476 mc->default_ram_size = 512 * MiB; 1477 aspeed_machine_class_init_cpus_defaults(mc); 1478 }; 1479 1480 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) 1481 { 1482 MachineClass *mc = MACHINE_CLASS(oc); 1483 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1484 1485 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1486 amc->soc_name = "ast2600-a3"; 1487 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1488 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1489 amc->fmc_model = "mx66l1g45g"; 1490 amc->spi_model = "mx66l1g45g"; 1491 amc->num_cs = 2; 1492 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1493 amc->i2c_init = rainier_bmc_i2c_init; 1494 mc->default_ram_size = 1 * GiB; 1495 aspeed_machine_class_init_cpus_defaults(mc); 1496 aspeed_machine_ast2600_class_emmc_init(oc); 1497 }; 1498 1499 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1500 1501 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) 1502 { 1503 MachineClass *mc = MACHINE_CLASS(oc); 1504 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1505 1506 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1507 amc->soc_name = "ast2600-a3"; 1508 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1509 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1510 amc->fmc_model = "mx66l1g45g"; 1511 amc->spi_model = "mx66l1g45g"; 1512 amc->num_cs = 2; 1513 amc->macs_mask = ASPEED_MAC3_ON; 1514 amc->i2c_init = fuji_bmc_i2c_init; 1515 amc->uart_default = ASPEED_DEV_UART1; 1516 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1517 aspeed_machine_class_init_cpus_defaults(mc); 1518 }; 1519 1520 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1521 1522 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) 1523 { 1524 MachineClass *mc = MACHINE_CLASS(oc); 1525 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1526 1527 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1528 amc->soc_name = "ast2600-a3"; 1529 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1530 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1531 amc->fmc_model = "w25q01jvq"; 1532 amc->spi_model = NULL; 1533 amc->num_cs = 2; 1534 amc->macs_mask = ASPEED_MAC2_ON; 1535 amc->i2c_init = bletchley_bmc_i2c_init; 1536 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE; 1537 aspeed_machine_class_init_cpus_defaults(mc); 1538 } 1539 1540 static void fby35_reset(MachineState *state, ResetType type) 1541 { 1542 AspeedMachineState *bmc = ASPEED_MACHINE(state); 1543 AspeedGPIOState *gpio = &bmc->soc->gpio; 1544 1545 qemu_devices_reset(type); 1546 1547 /* Board ID: 7 (Class-1, 4 slots) */ 1548 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); 1549 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); 1550 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); 1551 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); 1552 1553 /* Slot presence pins, inverse polarity. (False means present) */ 1554 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal); 1555 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal); 1556 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal); 1557 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal); 1558 1559 /* Slot 12v power pins, normal polarity. (True means powered-on) */ 1560 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal); 1561 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal); 1562 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal); 1563 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal); 1564 } 1565 1566 static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data) 1567 { 1568 MachineClass *mc = MACHINE_CLASS(oc); 1569 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1570 1571 mc->desc = "Facebook fby35 BMC (Cortex-A7)"; 1572 mc->reset = fby35_reset; 1573 amc->fmc_model = "mx66l1g45g"; 1574 amc->num_cs = 2; 1575 amc->macs_mask = ASPEED_MAC3_ON; 1576 amc->i2c_init = fby35_i2c_init; 1577 /* FIXME: Replace this macro with something more general */ 1578 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1579 aspeed_machine_class_init_cpus_defaults(mc); 1580 } 1581 1582 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) 1583 /* Main SYSCLK frequency in Hz (200MHz) */ 1584 #define SYSCLK_FRQ 200000000ULL 1585 1586 static void aspeed_minibmc_machine_init(MachineState *machine) 1587 { 1588 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 1589 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 1590 Clock *sysclk; 1591 1592 sysclk = clock_new(OBJECT(machine), "SYSCLK"); 1593 clock_set_hz(sysclk, SYSCLK_FRQ); 1594 1595 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 1596 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 1597 object_unref(OBJECT(bmc->soc)); 1598 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk); 1599 1600 object_property_set_link(OBJECT(bmc->soc), "memory", 1601 OBJECT(get_system_memory()), &error_abort); 1602 connect_serial_hds_to_uarts(bmc); 1603 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 1604 1605 if (defaults_enabled()) { 1606 aspeed_board_init_flashes(&bmc->soc->fmc, 1607 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 1608 amc->num_cs, 1609 0); 1610 1611 aspeed_board_init_flashes(&bmc->soc->spi[0], 1612 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1613 amc->num_cs, amc->num_cs); 1614 1615 aspeed_board_init_flashes(&bmc->soc->spi[1], 1616 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1617 amc->num_cs, (amc->num_cs * 2)); 1618 } 1619 1620 if (amc->i2c_init) { 1621 amc->i2c_init(bmc); 1622 } 1623 1624 armv7m_load_kernel(ARM_CPU(first_cpu), 1625 machine->kernel_filename, 1626 0, 1627 AST1030_INTERNAL_FLASH_SIZE); 1628 } 1629 1630 static void ast1030_evb_i2c_init(AspeedMachineState *bmc) 1631 { 1632 AspeedSoCState *soc = bmc->soc; 1633 1634 /* U10 24C08 connects to SDA/SCL Group 1 by default */ 1635 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 1636 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); 1637 1638 /* U11 LM75 connects to SDA/SCL Group 2 by default */ 1639 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d); 1640 } 1641 1642 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, 1643 void *data) 1644 { 1645 MachineClass *mc = MACHINE_CLASS(oc); 1646 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1647 1648 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; 1649 amc->soc_name = "ast1030-a1"; 1650 amc->hw_strap1 = 0; 1651 amc->hw_strap2 = 0; 1652 mc->init = aspeed_minibmc_machine_init; 1653 amc->i2c_init = ast1030_evb_i2c_init; 1654 mc->default_ram_size = 0; 1655 amc->fmc_model = "w25q80bl"; 1656 amc->spi_model = "w25q256"; 1657 amc->num_cs = 2; 1658 amc->macs_mask = 0; 1659 aspeed_machine_class_init_cpus_defaults(mc); 1660 } 1661 1662 #ifdef TARGET_AARCH64 1663 static void ast2700_evb_i2c_init(AspeedMachineState *bmc) 1664 { 1665 AspeedSoCState *soc = bmc->soc; 1666 1667 /* LM75 is compatible with TMP105 driver */ 1668 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), 1669 TYPE_TMP105, 0x4d); 1670 } 1671 1672 static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data) 1673 { 1674 MachineClass *mc = MACHINE_CLASS(oc); 1675 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1676 1677 mc->desc = "Aspeed AST2700 EVB (Cortex-A35)"; 1678 amc->soc_name = "ast2700-a0"; 1679 amc->hw_strap1 = AST2700_EVB_HW_STRAP1; 1680 amc->hw_strap2 = AST2700_EVB_HW_STRAP2; 1681 amc->fmc_model = "w25q01jvq"; 1682 amc->spi_model = "w25q512jv"; 1683 amc->num_cs = 2; 1684 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; 1685 amc->uart_default = ASPEED_DEV_UART12; 1686 amc->i2c_init = ast2700_evb_i2c_init; 1687 mc->default_ram_size = 1 * GiB; 1688 aspeed_machine_class_init_cpus_defaults(mc); 1689 } 1690 #endif 1691 1692 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, 1693 void *data) 1694 { 1695 MachineClass *mc = MACHINE_CLASS(oc); 1696 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1697 1698 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)"; 1699 amc->soc_name = "ast2600-a3"; 1700 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1701 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1702 amc->fmc_model = "n25q512a"; 1703 amc->spi_model = "n25q512a"; 1704 amc->num_cs = 2; 1705 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1706 amc->i2c_init = qcom_dc_scm_bmc_i2c_init; 1707 mc->default_ram_size = 1 * GiB; 1708 aspeed_machine_class_init_cpus_defaults(mc); 1709 }; 1710 1711 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, 1712 void *data) 1713 { 1714 MachineClass *mc = MACHINE_CLASS(oc); 1715 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1716 1717 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; 1718 amc->soc_name = "ast2600-a3"; 1719 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1720 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1721 amc->fmc_model = "n25q512a"; 1722 amc->spi_model = "n25q512a"; 1723 amc->num_cs = 2; 1724 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1725 amc->i2c_init = qcom_dc_scm_firework_i2c_init; 1726 mc->default_ram_size = 1 * GiB; 1727 aspeed_machine_class_init_cpus_defaults(mc); 1728 }; 1729 1730 static const TypeInfo aspeed_machine_types[] = { 1731 { 1732 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1733 .parent = TYPE_ASPEED_MACHINE, 1734 .class_init = aspeed_machine_palmetto_class_init, 1735 }, { 1736 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1737 .parent = TYPE_ASPEED_MACHINE, 1738 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1739 }, { 1740 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), 1741 .parent = TYPE_ASPEED_MACHINE, 1742 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, 1743 }, { 1744 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1745 .parent = TYPE_ASPEED_MACHINE, 1746 .class_init = aspeed_machine_ast2500_evb_class_init, 1747 }, { 1748 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1749 .parent = TYPE_ASPEED_MACHINE, 1750 .class_init = aspeed_machine_romulus_class_init, 1751 }, { 1752 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1753 .parent = TYPE_ASPEED_MACHINE, 1754 .class_init = aspeed_machine_sonorapass_class_init, 1755 }, { 1756 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1757 .parent = TYPE_ASPEED_MACHINE, 1758 .class_init = aspeed_machine_witherspoon_class_init, 1759 }, { 1760 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1761 .parent = TYPE_ASPEED_MACHINE, 1762 .class_init = aspeed_machine_ast2600_evb_class_init, 1763 }, { 1764 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), 1765 .parent = TYPE_ASPEED_MACHINE, 1766 .class_init = aspeed_machine_yosemitev2_class_init, 1767 }, { 1768 .name = MACHINE_TYPE_NAME("tiogapass-bmc"), 1769 .parent = TYPE_ASPEED_MACHINE, 1770 .class_init = aspeed_machine_tiogapass_class_init, 1771 }, { 1772 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1773 .parent = TYPE_ASPEED_MACHINE, 1774 .class_init = aspeed_machine_g220a_class_init, 1775 }, { 1776 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), 1777 .parent = TYPE_ASPEED_MACHINE, 1778 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, 1779 }, { 1780 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), 1781 .parent = TYPE_ASPEED_MACHINE, 1782 .class_init = aspeed_machine_qcom_firework_class_init, 1783 }, { 1784 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1785 .parent = TYPE_ASPEED_MACHINE, 1786 .class_init = aspeed_machine_fp5280g2_class_init, 1787 }, { 1788 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1789 .parent = TYPE_ASPEED_MACHINE, 1790 .class_init = aspeed_machine_quanta_q71l_class_init, 1791 }, { 1792 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1793 .parent = TYPE_ASPEED_MACHINE, 1794 .class_init = aspeed_machine_rainier_class_init, 1795 }, { 1796 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1797 .parent = TYPE_ASPEED_MACHINE, 1798 .class_init = aspeed_machine_fuji_class_init, 1799 }, { 1800 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 1801 .parent = TYPE_ASPEED_MACHINE, 1802 .class_init = aspeed_machine_bletchley_class_init, 1803 }, { 1804 .name = MACHINE_TYPE_NAME("fby35-bmc"), 1805 .parent = MACHINE_TYPE_NAME("ast2600-evb"), 1806 .class_init = aspeed_machine_fby35_class_init, 1807 }, { 1808 .name = MACHINE_TYPE_NAME("ast1030-evb"), 1809 .parent = TYPE_ASPEED_MACHINE, 1810 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, 1811 #ifdef TARGET_AARCH64 1812 }, { 1813 .name = MACHINE_TYPE_NAME("ast2700-evb"), 1814 .parent = TYPE_ASPEED_MACHINE, 1815 .class_init = aspeed_machine_ast2700_evb_class_init, 1816 #endif 1817 }, { 1818 .name = TYPE_ASPEED_MACHINE, 1819 .parent = TYPE_MACHINE, 1820 .instance_size = sizeof(AspeedMachineState), 1821 .instance_init = aspeed_machine_instance_init, 1822 .class_size = sizeof(AspeedMachineClass), 1823 .class_init = aspeed_machine_class_init, 1824 .abstract = true, 1825 } 1826 }; 1827 1828 DEFINE_TYPES(aspeed_machine_types) 1829