1 /* 2 * Arm SSE (Subsystems for Embedded): IoTKit 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/log.h" 14 #include "qemu/module.h" 15 #include "qemu/bitops.h" 16 #include "qapi/error.h" 17 #include "trace.h" 18 #include "hw/sysbus.h" 19 #include "migration/vmstate.h" 20 #include "hw/registerfields.h" 21 #include "hw/arm/armsse.h" 22 #include "hw/arm/boot.h" 23 #include "hw/irq.h" 24 25 /* Format of the System Information block SYS_CONFIG register */ 26 typedef enum SysConfigFormat { 27 IoTKitFormat, 28 SSE200Format, 29 } SysConfigFormat; 30 31 struct ARMSSEInfo { 32 const char *name; 33 int sram_banks; 34 int num_cpus; 35 uint32_t sys_version; 36 uint32_t cpuwait_rst; 37 SysConfigFormat sys_config_format; 38 bool has_mhus; 39 bool has_ppus; 40 bool has_cachectrl; 41 bool has_cpusecctrl; 42 bool has_cpuid; 43 Property *props; 44 }; 45 46 static Property iotkit_properties[] = { 47 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 48 MemoryRegion *), 49 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 50 DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), 51 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 52 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 53 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), 54 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), 55 DEFINE_PROP_END_OF_LIST() 56 }; 57 58 static Property armsse_properties[] = { 59 DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, 60 MemoryRegion *), 61 DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), 62 DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), 63 DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), 64 DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), 65 DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), 66 DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), 67 DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true), 68 DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true), 69 DEFINE_PROP_END_OF_LIST() 70 }; 71 72 static const ARMSSEInfo armsse_variants[] = { 73 { 74 .name = TYPE_IOTKIT, 75 .sram_banks = 1, 76 .num_cpus = 1, 77 .sys_version = 0x41743, 78 .cpuwait_rst = 0, 79 .sys_config_format = IoTKitFormat, 80 .has_mhus = false, 81 .has_ppus = false, 82 .has_cachectrl = false, 83 .has_cpusecctrl = false, 84 .has_cpuid = false, 85 .props = iotkit_properties, 86 }, 87 { 88 .name = TYPE_SSE200, 89 .sram_banks = 4, 90 .num_cpus = 2, 91 .sys_version = 0x22041743, 92 .cpuwait_rst = 2, 93 .sys_config_format = SSE200Format, 94 .has_mhus = true, 95 .has_ppus = true, 96 .has_cachectrl = true, 97 .has_cpusecctrl = true, 98 .has_cpuid = true, 99 .props = armsse_properties, 100 }, 101 }; 102 103 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) 104 { 105 /* Return the SYS_CONFIG value for this SSE */ 106 uint32_t sys_config; 107 108 switch (info->sys_config_format) { 109 case IoTKitFormat: 110 sys_config = 0; 111 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 112 sys_config = deposit32(sys_config, 4, 4, s->sram_addr_width - 12); 113 break; 114 case SSE200Format: 115 sys_config = 0; 116 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); 117 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); 118 sys_config = deposit32(sys_config, 24, 4, 2); 119 if (info->num_cpus > 1) { 120 sys_config = deposit32(sys_config, 10, 1, 1); 121 sys_config = deposit32(sys_config, 20, 4, info->sram_banks - 1); 122 sys_config = deposit32(sys_config, 28, 4, 2); 123 } 124 break; 125 default: 126 g_assert_not_reached(); 127 } 128 return sys_config; 129 } 130 131 /* Clock frequency in HZ of the 32KHz "slow clock" */ 132 #define S32KCLK (32 * 1000) 133 134 /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ 135 static bool irq_is_common[32] = { 136 [0 ... 5] = true, 137 /* 6, 7: per-CPU MHU interrupts */ 138 [8 ... 12] = true, 139 /* 13: per-CPU icache interrupt */ 140 /* 14: reserved */ 141 [15 ... 20] = true, 142 /* 21: reserved */ 143 [22 ... 26] = true, 144 /* 27: reserved */ 145 /* 28, 29: per-CPU CTI interrupts */ 146 /* 30, 31: reserved */ 147 }; 148 149 /* 150 * Create an alias region in @container of @size bytes starting at @base 151 * which mirrors the memory starting at @orig. 152 */ 153 static void make_alias(ARMSSE *s, MemoryRegion *mr, MemoryRegion *container, 154 const char *name, hwaddr base, hwaddr size, hwaddr orig) 155 { 156 memory_region_init_alias(mr, NULL, name, container, orig, size); 157 /* The alias is even lower priority than unimplemented_device regions */ 158 memory_region_add_subregion_overlap(container, base, mr, -1500); 159 } 160 161 static void irq_status_forwarder(void *opaque, int n, int level) 162 { 163 qemu_irq destirq = opaque; 164 165 qemu_set_irq(destirq, level); 166 } 167 168 static void nsccfg_handler(void *opaque, int n, int level) 169 { 170 ARMSSE *s = ARMSSE(opaque); 171 172 s->nsccfg = level; 173 } 174 175 static void armsse_forward_ppc(ARMSSE *s, const char *ppcname, int ppcnum) 176 { 177 /* Each of the 4 AHB and 4 APB PPCs that might be present in a 178 * system using the ARMSSE has a collection of control lines which 179 * are provided by the security controller and which we want to 180 * expose as control lines on the ARMSSE device itself, so the 181 * code using the ARMSSE can wire them up to the PPCs. 182 */ 183 SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum]; 184 DeviceState *armssedev = DEVICE(s); 185 DeviceState *dev_secctl = DEVICE(&s->secctl); 186 DeviceState *dev_splitter = DEVICE(splitter); 187 char *name; 188 189 name = g_strdup_printf("%s_nonsec", ppcname); 190 qdev_pass_gpios(dev_secctl, armssedev, name); 191 g_free(name); 192 name = g_strdup_printf("%s_ap", ppcname); 193 qdev_pass_gpios(dev_secctl, armssedev, name); 194 g_free(name); 195 name = g_strdup_printf("%s_irq_enable", ppcname); 196 qdev_pass_gpios(dev_secctl, armssedev, name); 197 g_free(name); 198 name = g_strdup_printf("%s_irq_clear", ppcname); 199 qdev_pass_gpios(dev_secctl, armssedev, name); 200 g_free(name); 201 202 /* irq_status is a little more tricky, because we need to 203 * split it so we can send it both to the security controller 204 * and to our OR gate for the NVIC interrupt line. 205 * Connect up the splitter's outputs, and create a GPIO input 206 * which will pass the line state to the input splitter. 207 */ 208 name = g_strdup_printf("%s_irq_status", ppcname); 209 qdev_connect_gpio_out(dev_splitter, 0, 210 qdev_get_gpio_in_named(dev_secctl, 211 name, 0)); 212 qdev_connect_gpio_out(dev_splitter, 1, 213 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppcnum)); 214 s->irq_status_in[ppcnum] = qdev_get_gpio_in(dev_splitter, 0); 215 qdev_init_gpio_in_named_with_opaque(armssedev, irq_status_forwarder, 216 s->irq_status_in[ppcnum], name, 1); 217 g_free(name); 218 } 219 220 static void armsse_forward_sec_resp_cfg(ARMSSE *s) 221 { 222 /* Forward the 3rd output from the splitter device as a 223 * named GPIO output of the armsse object. 224 */ 225 DeviceState *dev = DEVICE(s); 226 DeviceState *dev_splitter = DEVICE(&s->sec_resp_splitter); 227 228 qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); 229 s->sec_resp_cfg_in = qemu_allocate_irq(irq_status_forwarder, 230 s->sec_resp_cfg, 1); 231 qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); 232 } 233 234 static void armsse_init(Object *obj) 235 { 236 ARMSSE *s = ARMSSE(obj); 237 ARMSSEClass *asc = ARMSSE_GET_CLASS(obj); 238 const ARMSSEInfo *info = asc->info; 239 int i; 240 241 assert(info->sram_banks <= MAX_SRAM_BANKS); 242 assert(info->num_cpus <= SSE_MAX_CPUS); 243 244 memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); 245 246 for (i = 0; i < info->num_cpus; i++) { 247 /* 248 * We put each CPU in its own cluster as they are logically 249 * distinct and may be configured differently. 250 */ 251 char *name; 252 253 name = g_strdup_printf("cluster%d", i); 254 object_initialize_child(obj, name, &s->cluster[i], TYPE_CPU_CLUSTER); 255 qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i); 256 g_free(name); 257 258 name = g_strdup_printf("armv7m%d", i); 259 sysbus_init_child_obj(OBJECT(&s->cluster[i]), name, 260 &s->armv7m[i], sizeof(s->armv7m[i]), 261 TYPE_ARMV7M); 262 qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", 263 ARM_CPU_TYPE_NAME("cortex-m33")); 264 g_free(name); 265 name = g_strdup_printf("arm-sse-cpu-container%d", i); 266 memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX); 267 g_free(name); 268 if (i > 0) { 269 name = g_strdup_printf("arm-sse-container-alias%d", i); 270 memory_region_init_alias(&s->container_alias[i - 1], obj, 271 name, &s->container, 0, UINT64_MAX); 272 g_free(name); 273 } 274 } 275 276 sysbus_init_child_obj(obj, "secctl", &s->secctl, sizeof(s->secctl), 277 TYPE_IOTKIT_SECCTL); 278 sysbus_init_child_obj(obj, "apb-ppc0", &s->apb_ppc0, sizeof(s->apb_ppc0), 279 TYPE_TZ_PPC); 280 sysbus_init_child_obj(obj, "apb-ppc1", &s->apb_ppc1, sizeof(s->apb_ppc1), 281 TYPE_TZ_PPC); 282 for (i = 0; i < info->sram_banks; i++) { 283 char *name = g_strdup_printf("mpc%d", i); 284 sysbus_init_child_obj(obj, name, &s->mpc[i], 285 sizeof(s->mpc[i]), TYPE_TZ_MPC); 286 g_free(name); 287 } 288 object_initialize_child(obj, "mpc-irq-orgate", &s->mpc_irq_orgate, 289 TYPE_OR_IRQ); 290 291 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 292 char *name = g_strdup_printf("mpc-irq-splitter-%d", i); 293 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 294 295 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 296 g_free(name); 297 } 298 sysbus_init_child_obj(obj, "timer0", &s->timer0, sizeof(s->timer0), 299 TYPE_CMSDK_APB_TIMER); 300 sysbus_init_child_obj(obj, "timer1", &s->timer1, sizeof(s->timer1), 301 TYPE_CMSDK_APB_TIMER); 302 sysbus_init_child_obj(obj, "s32ktimer", &s->s32ktimer, sizeof(s->s32ktimer), 303 TYPE_CMSDK_APB_TIMER); 304 sysbus_init_child_obj(obj, "dualtimer", &s->dualtimer, sizeof(s->dualtimer), 305 TYPE_CMSDK_APB_DUALTIMER); 306 sysbus_init_child_obj(obj, "s32kwatchdog", &s->s32kwatchdog, 307 sizeof(s->s32kwatchdog), TYPE_CMSDK_APB_WATCHDOG); 308 sysbus_init_child_obj(obj, "nswatchdog", &s->nswatchdog, 309 sizeof(s->nswatchdog), TYPE_CMSDK_APB_WATCHDOG); 310 sysbus_init_child_obj(obj, "swatchdog", &s->swatchdog, 311 sizeof(s->swatchdog), TYPE_CMSDK_APB_WATCHDOG); 312 sysbus_init_child_obj(obj, "armsse-sysctl", &s->sysctl, 313 sizeof(s->sysctl), TYPE_IOTKIT_SYSCTL); 314 sysbus_init_child_obj(obj, "armsse-sysinfo", &s->sysinfo, 315 sizeof(s->sysinfo), TYPE_IOTKIT_SYSINFO); 316 if (info->has_mhus) { 317 sysbus_init_child_obj(obj, "mhu0", &s->mhu[0], sizeof(s->mhu[0]), 318 TYPE_ARMSSE_MHU); 319 sysbus_init_child_obj(obj, "mhu1", &s->mhu[1], sizeof(s->mhu[1]), 320 TYPE_ARMSSE_MHU); 321 } 322 if (info->has_ppus) { 323 for (i = 0; i < info->num_cpus; i++) { 324 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 325 int ppuidx = CPU0CORE_PPU + i; 326 327 sysbus_init_child_obj(obj, name, &s->ppu[ppuidx], 328 sizeof(s->ppu[ppuidx]), 329 TYPE_UNIMPLEMENTED_DEVICE); 330 g_free(name); 331 } 332 sysbus_init_child_obj(obj, "DBG_PPU", &s->ppu[DBG_PPU], 333 sizeof(s->ppu[DBG_PPU]), 334 TYPE_UNIMPLEMENTED_DEVICE); 335 for (i = 0; i < info->sram_banks; i++) { 336 char *name = g_strdup_printf("RAM%d_PPU", i); 337 int ppuidx = RAM0_PPU + i; 338 339 sysbus_init_child_obj(obj, name, &s->ppu[ppuidx], 340 sizeof(s->ppu[ppuidx]), 341 TYPE_UNIMPLEMENTED_DEVICE); 342 g_free(name); 343 } 344 } 345 if (info->has_cachectrl) { 346 for (i = 0; i < info->num_cpus; i++) { 347 char *name = g_strdup_printf("cachectrl%d", i); 348 349 sysbus_init_child_obj(obj, name, &s->cachectrl[i], 350 sizeof(s->cachectrl[i]), 351 TYPE_UNIMPLEMENTED_DEVICE); 352 g_free(name); 353 } 354 } 355 if (info->has_cpusecctrl) { 356 for (i = 0; i < info->num_cpus; i++) { 357 char *name = g_strdup_printf("cpusecctrl%d", i); 358 359 sysbus_init_child_obj(obj, name, &s->cpusecctrl[i], 360 sizeof(s->cpusecctrl[i]), 361 TYPE_UNIMPLEMENTED_DEVICE); 362 g_free(name); 363 } 364 } 365 if (info->has_cpuid) { 366 for (i = 0; i < info->num_cpus; i++) { 367 char *name = g_strdup_printf("cpuid%d", i); 368 369 sysbus_init_child_obj(obj, name, &s->cpuid[i], 370 sizeof(s->cpuid[i]), 371 TYPE_ARMSSE_CPUID); 372 g_free(name); 373 } 374 } 375 object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, TYPE_OR_IRQ); 376 object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate, 377 TYPE_OR_IRQ); 378 object_initialize_child(obj, "sec-resp-splitter", &s->sec_resp_splitter, 379 TYPE_SPLIT_IRQ); 380 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 381 char *name = g_strdup_printf("ppc-irq-splitter-%d", i); 382 SplitIRQ *splitter = &s->ppc_irq_splitter[i]; 383 384 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 385 g_free(name); 386 } 387 if (info->num_cpus > 1) { 388 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 389 if (irq_is_common[i]) { 390 char *name = g_strdup_printf("cpu-irq-splitter%d", i); 391 SplitIRQ *splitter = &s->cpu_irq_splitter[i]; 392 393 object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); 394 g_free(name); 395 } 396 } 397 } 398 } 399 400 static void armsse_exp_irq(void *opaque, int n, int level) 401 { 402 qemu_irq *irqarray = opaque; 403 404 qemu_set_irq(irqarray[n], level); 405 } 406 407 static void armsse_mpcexp_status(void *opaque, int n, int level) 408 { 409 ARMSSE *s = ARMSSE(opaque); 410 qemu_set_irq(s->mpcexp_status_in[n], level); 411 } 412 413 static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int irqno) 414 { 415 /* 416 * Return a qemu_irq which can be used to signal IRQ n to 417 * all CPUs in the SSE. 418 */ 419 ARMSSEClass *asc = ARMSSE_GET_CLASS(s); 420 const ARMSSEInfo *info = asc->info; 421 422 assert(irq_is_common[irqno]); 423 424 if (info->num_cpus == 1) { 425 /* Only one CPU -- just connect directly to it */ 426 return qdev_get_gpio_in(DEVICE(&s->armv7m[0]), irqno); 427 } else { 428 /* Connect to the splitter which feeds all CPUs */ 429 return qdev_get_gpio_in(DEVICE(&s->cpu_irq_splitter[irqno]), 0); 430 } 431 } 432 433 static void map_ppu(ARMSSE *s, int ppuidx, const char *name, hwaddr addr) 434 { 435 /* Map a PPU unimplemented device stub */ 436 DeviceState *dev = DEVICE(&s->ppu[ppuidx]); 437 438 qdev_prop_set_string(dev, "name", name); 439 qdev_prop_set_uint64(dev, "size", 0x1000); 440 qdev_init_nofail(dev); 441 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ppu[ppuidx]), 0, addr); 442 } 443 444 static void armsse_realize(DeviceState *dev, Error **errp) 445 { 446 ARMSSE *s = ARMSSE(dev); 447 ARMSSEClass *asc = ARMSSE_GET_CLASS(dev); 448 const ARMSSEInfo *info = asc->info; 449 int i; 450 MemoryRegion *mr; 451 Error *err = NULL; 452 SysBusDevice *sbd_apb_ppc0; 453 SysBusDevice *sbd_secctl; 454 DeviceState *dev_apb_ppc0; 455 DeviceState *dev_apb_ppc1; 456 DeviceState *dev_secctl; 457 DeviceState *dev_splitter; 458 uint32_t addr_width_max; 459 460 if (!s->board_memory) { 461 error_setg(errp, "memory property was not set"); 462 return; 463 } 464 465 if (!s->mainclk_frq) { 466 error_setg(errp, "MAINCLK property was not set"); 467 return; 468 } 469 470 /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */ 471 assert(is_power_of_2(info->sram_banks)); 472 addr_width_max = 24 - ctz32(info->sram_banks); 473 if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) { 474 error_setg(errp, "SRAM_ADDR_WIDTH must be between 1 and %d", 475 addr_width_max); 476 return; 477 } 478 479 /* Handling of which devices should be available only to secure 480 * code is usually done differently for M profile than for A profile. 481 * Instead of putting some devices only into the secure address space, 482 * devices exist in both address spaces but with hard-wired security 483 * permissions that will cause the CPU to fault for non-secure accesses. 484 * 485 * The ARMSSE has an IDAU (Implementation Defined Access Unit), 486 * which specifies hard-wired security permissions for different 487 * areas of the physical address space. For the ARMSSE IDAU, the 488 * top 4 bits of the physical address are the IDAU region ID, and 489 * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS 490 * region, otherwise it is an S region. 491 * 492 * The various devices and RAMs are generally all mapped twice, 493 * once into a region that the IDAU defines as secure and once 494 * into a non-secure region. They sit behind either a Memory 495 * Protection Controller (for RAM) or a Peripheral Protection 496 * Controller (for devices), which allow a more fine grained 497 * configuration of whether non-secure accesses are permitted. 498 * 499 * (The other place that guest software can configure security 500 * permissions is in the architected SAU (Security Attribution 501 * Unit), which is entirely inside the CPU. The IDAU can upgrade 502 * the security attributes for a region to more restrictive than 503 * the SAU specifies, but cannot downgrade them.) 504 * 505 * 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff 506 * 0x20000000..0x2007ffff 32KB FPGA block RAM 507 * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff 508 * 0x40000000..0x4000ffff base peripheral region 1 509 * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE) 510 * 0x40020000..0x4002ffff system control element peripherals 511 * 0x40080000..0x400fffff base peripheral region 2 512 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff 513 */ 514 515 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -2); 516 517 for (i = 0; i < info->num_cpus; i++) { 518 DeviceState *cpudev = DEVICE(&s->armv7m[i]); 519 Object *cpuobj = OBJECT(&s->armv7m[i]); 520 int j; 521 char *gpioname; 522 523 qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32); 524 /* 525 * In real hardware the initial Secure VTOR is set from the INITSVTOR* 526 * registers in the IoT Kit System Control Register block. In QEMU 527 * we set the initial value here, and also the reset value of the 528 * sysctl register, from this object's QOM init-svtor property. 529 * If the guest changes the INITSVTOR* registers at runtime then the 530 * code in iotkit-sysctl.c will update the CPU init-svtor property 531 * (which will then take effect on the next CPU warm-reset). 532 * 533 * Note that typically a board using the SSE-200 will have a system 534 * control processor whose boot firmware initializes the INITSVTOR* 535 * registers before powering up the CPUs. QEMU doesn't emulate 536 * the control processor, so instead we behave in the way that the 537 * firmware does: the initial value should be set by the board code 538 * (using the init-svtor property on the ARMSSE object) to match 539 * whatever its firmware does. 540 */ 541 qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor); 542 /* 543 * CPUs start powered down if the corresponding bit in the CPUWAIT 544 * register is 1. In real hardware the CPUWAIT register reset value is 545 * a configurable property of the SSE-200 (via the CPUWAIT0_RST and 546 * CPUWAIT1_RST parameters), but since all the boards we care about 547 * start CPU0 and leave CPU1 powered off, we hard-code that in 548 * info->cpuwait_rst for now. We can add QOM properties for this 549 * later if necessary. 550 */ 551 if (extract32(info->cpuwait_rst, i, 1)) { 552 object_property_set_bool(cpuobj, true, "start-powered-off", &err); 553 if (err) { 554 error_propagate(errp, err); 555 return; 556 } 557 } 558 if (!s->cpu_fpu[i]) { 559 object_property_set_bool(cpuobj, false, "vfp", &err); 560 if (err) { 561 error_propagate(errp, err); 562 return; 563 } 564 } 565 if (!s->cpu_dsp[i]) { 566 object_property_set_bool(cpuobj, false, "dsp", &err); 567 if (err) { 568 error_propagate(errp, err); 569 return; 570 } 571 } 572 573 if (i > 0) { 574 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 575 &s->container_alias[i - 1], -1); 576 } else { 577 memory_region_add_subregion_overlap(&s->cpu_container[i], 0, 578 &s->container, -1); 579 } 580 object_property_set_link(cpuobj, OBJECT(&s->cpu_container[i]), 581 "memory", &err); 582 if (err) { 583 error_propagate(errp, err); 584 return; 585 } 586 object_property_set_link(cpuobj, OBJECT(s), "idau", &err); 587 if (err) { 588 error_propagate(errp, err); 589 return; 590 } 591 object_property_set_bool(cpuobj, true, "realized", &err); 592 if (err) { 593 error_propagate(errp, err); 594 return; 595 } 596 /* 597 * The cluster must be realized after the armv7m container, as 598 * the container's CPU object is only created on realize, and the 599 * CPU must exist and have been parented into the cluster before 600 * the cluster is realized. 601 */ 602 object_property_set_bool(OBJECT(&s->cluster[i]), 603 true, "realized", &err); 604 if (err) { 605 error_propagate(errp, err); 606 return; 607 } 608 609 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */ 610 s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq); 611 for (j = 0; j < s->exp_numirq; j++) { 612 s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + 32); 613 } 614 if (i == 0) { 615 gpioname = g_strdup("EXP_IRQ"); 616 } else { 617 gpioname = g_strdup_printf("EXP_CPU%d_IRQ", i); 618 } 619 qdev_init_gpio_in_named_with_opaque(dev, armsse_exp_irq, 620 s->exp_irqs[i], 621 gpioname, s->exp_numirq); 622 g_free(gpioname); 623 } 624 625 /* Wire up the splitters that connect common IRQs to all CPUs */ 626 if (info->num_cpus > 1) { 627 for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { 628 if (irq_is_common[i]) { 629 Object *splitter = OBJECT(&s->cpu_irq_splitter[i]); 630 DeviceState *devs = DEVICE(splitter); 631 int cpunum; 632 633 object_property_set_int(splitter, info->num_cpus, 634 "num-lines", &err); 635 if (err) { 636 error_propagate(errp, err); 637 return; 638 } 639 object_property_set_bool(splitter, true, "realized", &err); 640 if (err) { 641 error_propagate(errp, err); 642 return; 643 } 644 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 645 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 646 647 qdev_connect_gpio_out(devs, cpunum, 648 qdev_get_gpio_in(cpudev, i)); 649 } 650 } 651 } 652 } 653 654 /* Set up the big aliases first */ 655 make_alias(s, &s->alias1, &s->container, "alias 1", 656 0x10000000, 0x10000000, 0x00000000); 657 make_alias(s, &s->alias2, &s->container, 658 "alias 2", 0x30000000, 0x10000000, 0x20000000); 659 /* The 0x50000000..0x5fffffff region is not a pure alias: it has 660 * a few extra devices that only appear there (generally the 661 * control interfaces for the protection controllers). 662 * We implement this by mapping those devices over the top of this 663 * alias MR at a higher priority. Some of the devices in this range 664 * are per-CPU, so we must put this alias in the per-cpu containers. 665 */ 666 for (i = 0; i < info->num_cpus; i++) { 667 make_alias(s, &s->alias3[i], &s->cpu_container[i], 668 "alias 3", 0x50000000, 0x10000000, 0x40000000); 669 } 670 671 /* Security controller */ 672 object_property_set_bool(OBJECT(&s->secctl), true, "realized", &err); 673 if (err) { 674 error_propagate(errp, err); 675 return; 676 } 677 sbd_secctl = SYS_BUS_DEVICE(&s->secctl); 678 dev_secctl = DEVICE(&s->secctl); 679 sysbus_mmio_map(sbd_secctl, 0, 0x50080000); 680 sysbus_mmio_map(sbd_secctl, 1, 0x40080000); 681 682 s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1); 683 qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); 684 685 /* The sec_resp_cfg output from the security controller must be split into 686 * multiple lines, one for each of the PPCs within the ARMSSE and one 687 * that will be an output from the ARMSSE to the system. 688 */ 689 object_property_set_int(OBJECT(&s->sec_resp_splitter), 3, 690 "num-lines", &err); 691 if (err) { 692 error_propagate(errp, err); 693 return; 694 } 695 object_property_set_bool(OBJECT(&s->sec_resp_splitter), true, 696 "realized", &err); 697 if (err) { 698 error_propagate(errp, err); 699 return; 700 } 701 dev_splitter = DEVICE(&s->sec_resp_splitter); 702 qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, 703 qdev_get_gpio_in(dev_splitter, 0)); 704 705 /* Each SRAM bank lives behind its own Memory Protection Controller */ 706 for (i = 0; i < info->sram_banks; i++) { 707 char *ramname = g_strdup_printf("armsse.sram%d", i); 708 SysBusDevice *sbd_mpc; 709 uint32_t sram_bank_size = 1 << s->sram_addr_width; 710 711 memory_region_init_ram(&s->sram[i], NULL, ramname, 712 sram_bank_size, &err); 713 g_free(ramname); 714 if (err) { 715 error_propagate(errp, err); 716 return; 717 } 718 object_property_set_link(OBJECT(&s->mpc[i]), OBJECT(&s->sram[i]), 719 "downstream", &err); 720 if (err) { 721 error_propagate(errp, err); 722 return; 723 } 724 object_property_set_bool(OBJECT(&s->mpc[i]), true, "realized", &err); 725 if (err) { 726 error_propagate(errp, err); 727 return; 728 } 729 /* Map the upstream end of the MPC into the right place... */ 730 sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]); 731 memory_region_add_subregion(&s->container, 732 0x20000000 + i * sram_bank_size, 733 sysbus_mmio_get_region(sbd_mpc, 1)); 734 /* ...and its register interface */ 735 memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, 736 sysbus_mmio_get_region(sbd_mpc, 0)); 737 } 738 739 /* We must OR together lines from the MPC splitters to go to the NVIC */ 740 object_property_set_int(OBJECT(&s->mpc_irq_orgate), 741 IOTS_NUM_EXP_MPC + info->sram_banks, 742 "num-lines", &err); 743 if (err) { 744 error_propagate(errp, err); 745 return; 746 } 747 object_property_set_bool(OBJECT(&s->mpc_irq_orgate), true, 748 "realized", &err); 749 if (err) { 750 error_propagate(errp, err); 751 return; 752 } 753 qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0, 754 armsse_get_common_irq_in(s, 9)); 755 756 /* Devices behind APB PPC0: 757 * 0x40000000: timer0 758 * 0x40001000: timer1 759 * 0x40002000: dual timer 760 * 0x40003000: MHU0 (SSE-200 only) 761 * 0x40004000: MHU1 (SSE-200 only) 762 * We must configure and realize each downstream device and connect 763 * it to the appropriate PPC port; then we can realize the PPC and 764 * map its upstream ends to the right place in the container. 765 */ 766 qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq); 767 object_property_set_bool(OBJECT(&s->timer0), true, "realized", &err); 768 if (err) { 769 error_propagate(errp, err); 770 return; 771 } 772 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, 773 armsse_get_common_irq_in(s, 3)); 774 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); 775 object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[0]", &err); 776 if (err) { 777 error_propagate(errp, err); 778 return; 779 } 780 781 qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq); 782 object_property_set_bool(OBJECT(&s->timer1), true, "realized", &err); 783 if (err) { 784 error_propagate(errp, err); 785 return; 786 } 787 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, 788 armsse_get_common_irq_in(s, 4)); 789 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); 790 object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[1]", &err); 791 if (err) { 792 error_propagate(errp, err); 793 return; 794 } 795 796 797 qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq); 798 object_property_set_bool(OBJECT(&s->dualtimer), true, "realized", &err); 799 if (err) { 800 error_propagate(errp, err); 801 return; 802 } 803 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dualtimer), 0, 804 armsse_get_common_irq_in(s, 5)); 805 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dualtimer), 0); 806 object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[2]", &err); 807 if (err) { 808 error_propagate(errp, err); 809 return; 810 } 811 812 if (info->has_mhus) { 813 /* 814 * An SSE-200 with only one CPU should have only one MHU created, 815 * with the region where the second MHU usually is being RAZ/WI. 816 * We don't implement that SSE-200 config; if we want to support 817 * it then this code needs to be enhanced to handle creating the 818 * RAZ/WI region instead of the second MHU. 819 */ 820 assert(info->num_cpus == ARRAY_SIZE(s->mhu)); 821 822 for (i = 0; i < ARRAY_SIZE(s->mhu); i++) { 823 char *port; 824 int cpunum; 825 SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]); 826 827 object_property_set_bool(OBJECT(&s->mhu[i]), true, 828 "realized", &err); 829 if (err) { 830 error_propagate(errp, err); 831 return; 832 } 833 port = g_strdup_printf("port[%d]", i + 3); 834 mr = sysbus_mmio_get_region(mhu_sbd, 0); 835 object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), 836 port, &err); 837 g_free(port); 838 if (err) { 839 error_propagate(errp, err); 840 return; 841 } 842 843 /* 844 * Each MHU has an irq line for each CPU: 845 * MHU 0 irq line 0 -> CPU 0 IRQ 6 846 * MHU 0 irq line 1 -> CPU 1 IRQ 6 847 * MHU 1 irq line 0 -> CPU 0 IRQ 7 848 * MHU 1 irq line 1 -> CPU 1 IRQ 7 849 */ 850 for (cpunum = 0; cpunum < info->num_cpus; cpunum++) { 851 DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]); 852 853 sysbus_connect_irq(mhu_sbd, cpunum, 854 qdev_get_gpio_in(cpudev, 6 + i)); 855 } 856 } 857 } 858 859 object_property_set_bool(OBJECT(&s->apb_ppc0), true, "realized", &err); 860 if (err) { 861 error_propagate(errp, err); 862 return; 863 } 864 865 sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc0); 866 dev_apb_ppc0 = DEVICE(&s->apb_ppc0); 867 868 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 0); 869 memory_region_add_subregion(&s->container, 0x40000000, mr); 870 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 1); 871 memory_region_add_subregion(&s->container, 0x40001000, mr); 872 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 2); 873 memory_region_add_subregion(&s->container, 0x40002000, mr); 874 if (info->has_mhus) { 875 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 3); 876 memory_region_add_subregion(&s->container, 0x40003000, mr); 877 mr = sysbus_mmio_get_region(sbd_apb_ppc0, 4); 878 memory_region_add_subregion(&s->container, 0x40004000, mr); 879 } 880 for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { 881 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, 882 qdev_get_gpio_in_named(dev_apb_ppc0, 883 "cfg_nonsec", i)); 884 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i, 885 qdev_get_gpio_in_named(dev_apb_ppc0, 886 "cfg_ap", i)); 887 } 888 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0, 889 qdev_get_gpio_in_named(dev_apb_ppc0, 890 "irq_enable", 0)); 891 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0, 892 qdev_get_gpio_in_named(dev_apb_ppc0, 893 "irq_clear", 0)); 894 qdev_connect_gpio_out(dev_splitter, 0, 895 qdev_get_gpio_in_named(dev_apb_ppc0, 896 "cfg_sec_resp", 0)); 897 898 /* All the PPC irq lines (from the 2 internal PPCs and the 8 external 899 * ones) are sent individually to the security controller, and also 900 * ORed together to give a single combined PPC interrupt to the NVIC. 901 */ 902 object_property_set_int(OBJECT(&s->ppc_irq_orgate), 903 NUM_PPCS, "num-lines", &err); 904 if (err) { 905 error_propagate(errp, err); 906 return; 907 } 908 object_property_set_bool(OBJECT(&s->ppc_irq_orgate), true, 909 "realized", &err); 910 if (err) { 911 error_propagate(errp, err); 912 return; 913 } 914 qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, 915 armsse_get_common_irq_in(s, 10)); 916 917 /* 918 * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias): 919 * private per-CPU region (all these devices are SSE-200 only): 920 * 0x50010000: L1 icache control registers 921 * 0x50011000: CPUSECCTRL (CPU local security control registers) 922 * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block 923 */ 924 if (info->has_cachectrl) { 925 for (i = 0; i < info->num_cpus; i++) { 926 char *name = g_strdup_printf("cachectrl%d", i); 927 MemoryRegion *mr; 928 929 qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name); 930 g_free(name); 931 qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000); 932 object_property_set_bool(OBJECT(&s->cachectrl[i]), true, 933 "realized", &err); 934 if (err) { 935 error_propagate(errp, err); 936 return; 937 } 938 939 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0); 940 memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr); 941 } 942 } 943 if (info->has_cpusecctrl) { 944 for (i = 0; i < info->num_cpus; i++) { 945 char *name = g_strdup_printf("CPUSECCTRL%d", i); 946 MemoryRegion *mr; 947 948 qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name); 949 g_free(name); 950 qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000); 951 object_property_set_bool(OBJECT(&s->cpusecctrl[i]), true, 952 "realized", &err); 953 if (err) { 954 error_propagate(errp, err); 955 return; 956 } 957 958 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]), 0); 959 memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr); 960 } 961 } 962 if (info->has_cpuid) { 963 for (i = 0; i < info->num_cpus; i++) { 964 MemoryRegion *mr; 965 966 qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i); 967 object_property_set_bool(OBJECT(&s->cpuid[i]), true, 968 "realized", &err); 969 if (err) { 970 error_propagate(errp, err); 971 return; 972 } 973 974 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0); 975 memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr); 976 } 977 } 978 979 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */ 980 /* Devices behind APB PPC1: 981 * 0x4002f000: S32K timer 982 */ 983 qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK); 984 object_property_set_bool(OBJECT(&s->s32ktimer), true, "realized", &err); 985 if (err) { 986 error_propagate(errp, err); 987 return; 988 } 989 sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32ktimer), 0, 990 armsse_get_common_irq_in(s, 2)); 991 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); 992 object_property_set_link(OBJECT(&s->apb_ppc1), OBJECT(mr), "port[0]", &err); 993 if (err) { 994 error_propagate(errp, err); 995 return; 996 } 997 998 object_property_set_bool(OBJECT(&s->apb_ppc1), true, "realized", &err); 999 if (err) { 1000 error_propagate(errp, err); 1001 return; 1002 } 1003 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->apb_ppc1), 0); 1004 memory_region_add_subregion(&s->container, 0x4002f000, mr); 1005 1006 dev_apb_ppc1 = DEVICE(&s->apb_ppc1); 1007 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0, 1008 qdev_get_gpio_in_named(dev_apb_ppc1, 1009 "cfg_nonsec", 0)); 1010 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0, 1011 qdev_get_gpio_in_named(dev_apb_ppc1, 1012 "cfg_ap", 0)); 1013 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0, 1014 qdev_get_gpio_in_named(dev_apb_ppc1, 1015 "irq_enable", 0)); 1016 qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0, 1017 qdev_get_gpio_in_named(dev_apb_ppc1, 1018 "irq_clear", 0)); 1019 qdev_connect_gpio_out(dev_splitter, 1, 1020 qdev_get_gpio_in_named(dev_apb_ppc1, 1021 "cfg_sec_resp", 0)); 1022 1023 object_property_set_int(OBJECT(&s->sysinfo), info->sys_version, 1024 "SYS_VERSION", &err); 1025 if (err) { 1026 error_propagate(errp, err); 1027 return; 1028 } 1029 object_property_set_int(OBJECT(&s->sysinfo), 1030 armsse_sys_config_value(s, info), 1031 "SYS_CONFIG", &err); 1032 if (err) { 1033 error_propagate(errp, err); 1034 return; 1035 } 1036 object_property_set_bool(OBJECT(&s->sysinfo), true, "realized", &err); 1037 if (err) { 1038 error_propagate(errp, err); 1039 return; 1040 } 1041 /* System information registers */ 1042 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000); 1043 /* System control registers */ 1044 object_property_set_int(OBJECT(&s->sysctl), info->sys_version, 1045 "SYS_VERSION", &err); 1046 object_property_set_int(OBJECT(&s->sysctl), info->cpuwait_rst, 1047 "CPUWAIT_RST", &err); 1048 object_property_set_int(OBJECT(&s->sysctl), s->init_svtor, 1049 "INITSVTOR0_RST", &err); 1050 object_property_set_int(OBJECT(&s->sysctl), s->init_svtor, 1051 "INITSVTOR1_RST", &err); 1052 object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err); 1053 if (err) { 1054 error_propagate(errp, err); 1055 return; 1056 } 1057 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctl), 0, 0x50021000); 1058 1059 if (info->has_ppus) { 1060 /* CPUnCORE_PPU for each CPU */ 1061 for (i = 0; i < info->num_cpus; i++) { 1062 char *name = g_strdup_printf("CPU%dCORE_PPU", i); 1063 1064 map_ppu(s, CPU0CORE_PPU + i, name, 0x50023000 + i * 0x2000); 1065 /* 1066 * We don't support CPU debug so don't create the 1067 * CPU0DEBUG_PPU at 0x50024000 and 0x50026000. 1068 */ 1069 g_free(name); 1070 } 1071 map_ppu(s, DBG_PPU, "DBG_PPU", 0x50029000); 1072 1073 for (i = 0; i < info->sram_banks; i++) { 1074 char *name = g_strdup_printf("RAM%d_PPU", i); 1075 1076 map_ppu(s, RAM0_PPU + i, name, 0x5002a000 + i * 0x1000); 1077 g_free(name); 1078 } 1079 } 1080 1081 /* This OR gate wires together outputs from the secure watchdogs to NMI */ 1082 object_property_set_int(OBJECT(&s->nmi_orgate), 2, "num-lines", &err); 1083 if (err) { 1084 error_propagate(errp, err); 1085 return; 1086 } 1087 object_property_set_bool(OBJECT(&s->nmi_orgate), true, "realized", &err); 1088 if (err) { 1089 error_propagate(errp, err); 1090 return; 1091 } 1092 qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, 1093 qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0)); 1094 1095 qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK); 1096 object_property_set_bool(OBJECT(&s->s32kwatchdog), true, "realized", &err); 1097 if (err) { 1098 error_propagate(errp, err); 1099 return; 1100 } 1101 sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 1102 qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 0)); 1103 sysbus_mmio_map(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 0x5002e000); 1104 1105 /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ 1106 1107 qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq); 1108 object_property_set_bool(OBJECT(&s->nswatchdog), true, "realized", &err); 1109 if (err) { 1110 error_propagate(errp, err); 1111 return; 1112 } 1113 sysbus_connect_irq(SYS_BUS_DEVICE(&s->nswatchdog), 0, 1114 armsse_get_common_irq_in(s, 1)); 1115 sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); 1116 1117 qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq); 1118 object_property_set_bool(OBJECT(&s->swatchdog), true, "realized", &err); 1119 if (err) { 1120 error_propagate(errp, err); 1121 return; 1122 } 1123 sysbus_connect_irq(SYS_BUS_DEVICE(&s->swatchdog), 0, 1124 qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 1)); 1125 sysbus_mmio_map(SYS_BUS_DEVICE(&s->swatchdog), 0, 0x50081000); 1126 1127 for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { 1128 Object *splitter = OBJECT(&s->ppc_irq_splitter[i]); 1129 1130 object_property_set_int(splitter, 2, "num-lines", &err); 1131 if (err) { 1132 error_propagate(errp, err); 1133 return; 1134 } 1135 object_property_set_bool(splitter, true, "realized", &err); 1136 if (err) { 1137 error_propagate(errp, err); 1138 return; 1139 } 1140 } 1141 1142 for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { 1143 char *ppcname = g_strdup_printf("ahb_ppcexp%d", i); 1144 1145 armsse_forward_ppc(s, ppcname, i); 1146 g_free(ppcname); 1147 } 1148 1149 for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) { 1150 char *ppcname = g_strdup_printf("apb_ppcexp%d", i); 1151 1152 armsse_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); 1153 g_free(ppcname); 1154 } 1155 1156 for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) { 1157 /* Wire up IRQ splitter for internal PPCs */ 1158 DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]); 1159 char *gpioname = g_strdup_printf("apb_ppc%d_irq_status", 1160 i - NUM_EXTERNAL_PPCS); 1161 TZPPC *ppc = (i == NUM_EXTERNAL_PPCS) ? &s->apb_ppc0 : &s->apb_ppc1; 1162 1163 qdev_connect_gpio_out(devs, 0, 1164 qdev_get_gpio_in_named(dev_secctl, gpioname, 0)); 1165 qdev_connect_gpio_out(devs, 1, 1166 qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i)); 1167 qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0, 1168 qdev_get_gpio_in(devs, 0)); 1169 g_free(gpioname); 1170 } 1171 1172 /* Wire up the splitters for the MPC IRQs */ 1173 for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { 1174 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 1175 DeviceState *dev_splitter = DEVICE(splitter); 1176 1177 object_property_set_int(OBJECT(splitter), 2, "num-lines", &err); 1178 if (err) { 1179 error_propagate(errp, err); 1180 return; 1181 } 1182 object_property_set_bool(OBJECT(splitter), true, "realized", &err); 1183 if (err) { 1184 error_propagate(errp, err); 1185 return; 1186 } 1187 1188 if (i < IOTS_NUM_EXP_MPC) { 1189 /* Splitter input is from GPIO input line */ 1190 s->mpcexp_status_in[i] = qdev_get_gpio_in(dev_splitter, 0); 1191 qdev_connect_gpio_out(dev_splitter, 0, 1192 qdev_get_gpio_in_named(dev_secctl, 1193 "mpcexp_status", i)); 1194 } else { 1195 /* Splitter input is from our own MPC */ 1196 qdev_connect_gpio_out_named(DEVICE(&s->mpc[i - IOTS_NUM_EXP_MPC]), 1197 "irq", 0, 1198 qdev_get_gpio_in(dev_splitter, 0)); 1199 qdev_connect_gpio_out(dev_splitter, 0, 1200 qdev_get_gpio_in_named(dev_secctl, 1201 "mpc_status", 0)); 1202 } 1203 1204 qdev_connect_gpio_out(dev_splitter, 1, 1205 qdev_get_gpio_in(DEVICE(&s->mpc_irq_orgate), i)); 1206 } 1207 /* Create GPIO inputs which will pass the line state for our 1208 * mpcexp_irq inputs to the correct splitter devices. 1209 */ 1210 qdev_init_gpio_in_named(dev, armsse_mpcexp_status, "mpcexp_status", 1211 IOTS_NUM_EXP_MPC); 1212 1213 armsse_forward_sec_resp_cfg(s); 1214 1215 /* Forward the MSC related signals */ 1216 qdev_pass_gpios(dev_secctl, dev, "mscexp_status"); 1217 qdev_pass_gpios(dev_secctl, dev, "mscexp_clear"); 1218 qdev_pass_gpios(dev_secctl, dev, "mscexp_ns"); 1219 qdev_connect_gpio_out_named(dev_secctl, "msc_irq", 0, 1220 armsse_get_common_irq_in(s, 11)); 1221 1222 /* 1223 * Expose our container region to the board model; this corresponds 1224 * to the AHB Slave Expansion ports which allow bus master devices 1225 * (eg DMA controllers) in the board model to make transactions into 1226 * devices in the ARMSSE. 1227 */ 1228 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); 1229 1230 system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq; 1231 } 1232 1233 static void armsse_idau_check(IDAUInterface *ii, uint32_t address, 1234 int *iregion, bool *exempt, bool *ns, bool *nsc) 1235 { 1236 /* 1237 * For ARMSSE systems the IDAU responses are simple logical functions 1238 * of the address bits. The NSC attribute is guest-adjustable via the 1239 * NSCCFG register in the security controller. 1240 */ 1241 ARMSSE *s = ARMSSE(ii); 1242 int region = extract32(address, 28, 4); 1243 1244 *ns = !(region & 1); 1245 *nsc = (region == 1 && (s->nsccfg & 1)) || (region == 3 && (s->nsccfg & 2)); 1246 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ 1247 *exempt = (address & 0xeff00000) == 0xe0000000; 1248 *iregion = region; 1249 } 1250 1251 static const VMStateDescription armsse_vmstate = { 1252 .name = "iotkit", 1253 .version_id = 1, 1254 .minimum_version_id = 1, 1255 .fields = (VMStateField[]) { 1256 VMSTATE_UINT32(nsccfg, ARMSSE), 1257 VMSTATE_END_OF_LIST() 1258 } 1259 }; 1260 1261 static void armsse_reset(DeviceState *dev) 1262 { 1263 ARMSSE *s = ARMSSE(dev); 1264 1265 s->nsccfg = 0; 1266 } 1267 1268 static void armsse_class_init(ObjectClass *klass, void *data) 1269 { 1270 DeviceClass *dc = DEVICE_CLASS(klass); 1271 IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass); 1272 ARMSSEClass *asc = ARMSSE_CLASS(klass); 1273 const ARMSSEInfo *info = data; 1274 1275 dc->realize = armsse_realize; 1276 dc->vmsd = &armsse_vmstate; 1277 device_class_set_props(dc, info->props); 1278 dc->reset = armsse_reset; 1279 iic->check = armsse_idau_check; 1280 asc->info = info; 1281 } 1282 1283 static const TypeInfo armsse_info = { 1284 .name = TYPE_ARMSSE, 1285 .parent = TYPE_SYS_BUS_DEVICE, 1286 .instance_size = sizeof(ARMSSE), 1287 .instance_init = armsse_init, 1288 .abstract = true, 1289 .interfaces = (InterfaceInfo[]) { 1290 { TYPE_IDAU_INTERFACE }, 1291 { } 1292 } 1293 }; 1294 1295 static void armsse_register_types(void) 1296 { 1297 int i; 1298 1299 type_register_static(&armsse_info); 1300 1301 for (i = 0; i < ARRAY_SIZE(armsse_variants); i++) { 1302 TypeInfo ti = { 1303 .name = armsse_variants[i].name, 1304 .parent = TYPE_ARMSSE, 1305 .class_init = armsse_class_init, 1306 .class_data = (void *)&armsse_variants[i], 1307 }; 1308 type_register(&ti); 1309 } 1310 } 1311 1312 type_init(armsse_register_types); 1313