1 /* 2 * Allwinner H3 System on Chip emulation 3 * 4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "exec/address-spaces.h" 22 #include "qapi/error.h" 23 #include "qemu/error-report.h" 24 #include "qemu/module.h" 25 #include "qemu/units.h" 26 #include "hw/qdev-core.h" 27 #include "cpu.h" 28 #include "hw/sysbus.h" 29 #include "hw/char/serial.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/usb/hcd-ehci.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/arm/allwinner-h3.h" 34 35 /* Memory map */ 36 const hwaddr allwinner_h3_memmap[] = { 37 [AW_H3_SRAM_A1] = 0x00000000, 38 [AW_H3_SRAM_A2] = 0x00044000, 39 [AW_H3_SRAM_C] = 0x00010000, 40 [AW_H3_SYSCTRL] = 0x01c00000, 41 [AW_H3_MMC0] = 0x01c0f000, 42 [AW_H3_SID] = 0x01c14000, 43 [AW_H3_EHCI0] = 0x01c1a000, 44 [AW_H3_OHCI0] = 0x01c1a400, 45 [AW_H3_EHCI1] = 0x01c1b000, 46 [AW_H3_OHCI1] = 0x01c1b400, 47 [AW_H3_EHCI2] = 0x01c1c000, 48 [AW_H3_OHCI2] = 0x01c1c400, 49 [AW_H3_EHCI3] = 0x01c1d000, 50 [AW_H3_OHCI3] = 0x01c1d400, 51 [AW_H3_CCU] = 0x01c20000, 52 [AW_H3_PIT] = 0x01c20c00, 53 [AW_H3_UART0] = 0x01c28000, 54 [AW_H3_UART1] = 0x01c28400, 55 [AW_H3_UART2] = 0x01c28800, 56 [AW_H3_UART3] = 0x01c28c00, 57 [AW_H3_EMAC] = 0x01c30000, 58 [AW_H3_GIC_DIST] = 0x01c81000, 59 [AW_H3_GIC_CPU] = 0x01c82000, 60 [AW_H3_GIC_HYP] = 0x01c84000, 61 [AW_H3_GIC_VCPU] = 0x01c86000, 62 [AW_H3_CPUCFG] = 0x01f01c00, 63 [AW_H3_SDRAM] = 0x40000000 64 }; 65 66 /* List of unimplemented devices */ 67 struct AwH3Unimplemented { 68 const char *device_name; 69 hwaddr base; 70 hwaddr size; 71 } unimplemented[] = { 72 { "d-engine", 0x01000000, 4 * MiB }, 73 { "d-inter", 0x01400000, 128 * KiB }, 74 { "dma", 0x01c02000, 4 * KiB }, 75 { "nfdc", 0x01c03000, 4 * KiB }, 76 { "ts", 0x01c06000, 4 * KiB }, 77 { "keymem", 0x01c0b000, 4 * KiB }, 78 { "lcd0", 0x01c0c000, 4 * KiB }, 79 { "lcd1", 0x01c0d000, 4 * KiB }, 80 { "ve", 0x01c0e000, 4 * KiB }, 81 { "mmc1", 0x01c10000, 4 * KiB }, 82 { "mmc2", 0x01c11000, 4 * KiB }, 83 { "crypto", 0x01c15000, 4 * KiB }, 84 { "msgbox", 0x01c17000, 4 * KiB }, 85 { "spinlock", 0x01c18000, 4 * KiB }, 86 { "usb0-otg", 0x01c19000, 4 * KiB }, 87 { "usb0-phy", 0x01c1a000, 4 * KiB }, 88 { "usb1-phy", 0x01c1b000, 4 * KiB }, 89 { "usb2-phy", 0x01c1c000, 4 * KiB }, 90 { "usb3-phy", 0x01c1d000, 4 * KiB }, 91 { "smc", 0x01c1e000, 4 * KiB }, 92 { "pio", 0x01c20800, 1 * KiB }, 93 { "owa", 0x01c21000, 1 * KiB }, 94 { "pwm", 0x01c21400, 1 * KiB }, 95 { "keyadc", 0x01c21800, 1 * KiB }, 96 { "pcm0", 0x01c22000, 1 * KiB }, 97 { "pcm1", 0x01c22400, 1 * KiB }, 98 { "pcm2", 0x01c22800, 1 * KiB }, 99 { "audio", 0x01c22c00, 2 * KiB }, 100 { "smta", 0x01c23400, 1 * KiB }, 101 { "ths", 0x01c25000, 1 * KiB }, 102 { "uart0", 0x01c28000, 1 * KiB }, 103 { "uart1", 0x01c28400, 1 * KiB }, 104 { "uart2", 0x01c28800, 1 * KiB }, 105 { "uart3", 0x01c28c00, 1 * KiB }, 106 { "twi0", 0x01c2ac00, 1 * KiB }, 107 { "twi1", 0x01c2b000, 1 * KiB }, 108 { "twi2", 0x01c2b400, 1 * KiB }, 109 { "scr", 0x01c2c400, 1 * KiB }, 110 { "gpu", 0x01c40000, 64 * KiB }, 111 { "hstmr", 0x01c60000, 4 * KiB }, 112 { "dramcom", 0x01c62000, 4 * KiB }, 113 { "dramctl0", 0x01c63000, 4 * KiB }, 114 { "dramphy0", 0x01c65000, 4 * KiB }, 115 { "spi0", 0x01c68000, 4 * KiB }, 116 { "spi1", 0x01c69000, 4 * KiB }, 117 { "csi", 0x01cb0000, 320 * KiB }, 118 { "tve", 0x01e00000, 64 * KiB }, 119 { "hdmi", 0x01ee0000, 128 * KiB }, 120 { "rtc", 0x01f00000, 1 * KiB }, 121 { "r_timer", 0x01f00800, 1 * KiB }, 122 { "r_intc", 0x01f00c00, 1 * KiB }, 123 { "r_wdog", 0x01f01000, 1 * KiB }, 124 { "r_prcm", 0x01f01400, 1 * KiB }, 125 { "r_twd", 0x01f01800, 1 * KiB }, 126 { "r_cir-rx", 0x01f02000, 1 * KiB }, 127 { "r_twi", 0x01f02400, 1 * KiB }, 128 { "r_uart", 0x01f02800, 1 * KiB }, 129 { "r_pio", 0x01f02c00, 1 * KiB }, 130 { "r_pwm", 0x01f03800, 1 * KiB }, 131 { "core-dbg", 0x3f500000, 128 * KiB }, 132 { "tsgen-ro", 0x3f506000, 4 * KiB }, 133 { "tsgen-ctl", 0x3f507000, 4 * KiB }, 134 { "ddr-mem", 0x40000000, 2 * GiB }, 135 { "n-brom", 0xffff0000, 32 * KiB }, 136 { "s-brom", 0xffff0000, 64 * KiB } 137 }; 138 139 /* Per Processor Interrupts */ 140 enum { 141 AW_H3_GIC_PPI_MAINT = 9, 142 AW_H3_GIC_PPI_HYPTIMER = 10, 143 AW_H3_GIC_PPI_VIRTTIMER = 11, 144 AW_H3_GIC_PPI_SECTIMER = 13, 145 AW_H3_GIC_PPI_PHYSTIMER = 14 146 }; 147 148 /* Shared Processor Interrupts */ 149 enum { 150 AW_H3_GIC_SPI_UART0 = 0, 151 AW_H3_GIC_SPI_UART1 = 1, 152 AW_H3_GIC_SPI_UART2 = 2, 153 AW_H3_GIC_SPI_UART3 = 3, 154 AW_H3_GIC_SPI_TIMER0 = 18, 155 AW_H3_GIC_SPI_TIMER1 = 19, 156 AW_H3_GIC_SPI_MMC0 = 60, 157 AW_H3_GIC_SPI_EHCI0 = 72, 158 AW_H3_GIC_SPI_OHCI0 = 73, 159 AW_H3_GIC_SPI_EHCI1 = 74, 160 AW_H3_GIC_SPI_OHCI1 = 75, 161 AW_H3_GIC_SPI_EHCI2 = 76, 162 AW_H3_GIC_SPI_OHCI2 = 77, 163 AW_H3_GIC_SPI_EHCI3 = 78, 164 AW_H3_GIC_SPI_OHCI3 = 79, 165 AW_H3_GIC_SPI_EMAC = 82 166 }; 167 168 /* Allwinner H3 general constants */ 169 enum { 170 AW_H3_GIC_NUM_SPI = 128 171 }; 172 173 static void allwinner_h3_init(Object *obj) 174 { 175 AwH3State *s = AW_H3(obj); 176 177 s->memmap = allwinner_h3_memmap; 178 179 for (int i = 0; i < AW_H3_NUM_CPUS; i++) { 180 object_initialize_child(obj, "cpu[*]", &s->cpus[i], sizeof(s->cpus[i]), 181 ARM_CPU_TYPE_NAME("cortex-a7"), 182 &error_abort, NULL); 183 } 184 185 sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), 186 TYPE_ARM_GIC); 187 188 sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer), 189 TYPE_AW_A10_PIT); 190 object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer), 191 "clk0-freq", &error_abort); 192 object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer), 193 "clk1-freq", &error_abort); 194 195 sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu), 196 TYPE_AW_H3_CCU); 197 198 sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl), 199 TYPE_AW_H3_SYSCTRL); 200 201 sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg), 202 TYPE_AW_CPUCFG); 203 204 sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid), 205 TYPE_AW_SID); 206 object_property_add_alias(obj, "identifier", OBJECT(&s->sid), 207 "identifier", &error_abort); 208 209 sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0), 210 TYPE_AW_SDHOST_SUN5I); 211 212 sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), 213 TYPE_AW_SUN8I_EMAC); 214 } 215 216 static void allwinner_h3_realize(DeviceState *dev, Error **errp) 217 { 218 AwH3State *s = AW_H3(dev); 219 unsigned i; 220 221 /* CPUs */ 222 for (i = 0; i < AW_H3_NUM_CPUS; i++) { 223 224 /* Provide Power State Coordination Interface */ 225 qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit", 226 QEMU_PSCI_CONDUIT_HVC); 227 228 /* Disable secondary CPUs */ 229 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off", 230 i > 0); 231 232 /* All exception levels required */ 233 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true); 234 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true); 235 236 /* Mark realized */ 237 qdev_init_nofail(DEVICE(&s->cpus[i])); 238 } 239 240 /* Generic Interrupt Controller */ 241 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI + 242 GIC_INTERNAL); 243 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); 244 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS); 245 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false); 246 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true); 247 qdev_init_nofail(DEVICE(&s->gic)); 248 249 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]); 250 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]); 251 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_GIC_HYP]); 252 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_GIC_VCPU]); 253 254 /* 255 * Wire the outputs from each CPU's generic timer and the GICv3 256 * maintenance interrupt signal to the appropriate GIC PPI inputs, 257 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. 258 */ 259 for (i = 0; i < AW_H3_NUM_CPUS; i++) { 260 DeviceState *cpudev = DEVICE(&s->cpus[i]); 261 int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS; 262 int irq; 263 /* 264 * Mapping from the output timer irq lines from the CPU to the 265 * GIC PPI inputs used for this board. 266 */ 267 const int timer_irq[] = { 268 [GTIMER_PHYS] = AW_H3_GIC_PPI_PHYSTIMER, 269 [GTIMER_VIRT] = AW_H3_GIC_PPI_VIRTTIMER, 270 [GTIMER_HYP] = AW_H3_GIC_PPI_HYPTIMER, 271 [GTIMER_SEC] = AW_H3_GIC_PPI_SECTIMER, 272 }; 273 274 /* Connect CPU timer outputs to GIC PPI inputs */ 275 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { 276 qdev_connect_gpio_out(cpudev, irq, 277 qdev_get_gpio_in(DEVICE(&s->gic), 278 ppibase + timer_irq[irq])); 279 } 280 281 /* Connect GIC outputs to CPU interrupt inputs */ 282 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, 283 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); 284 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS, 285 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); 286 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_H3_NUM_CPUS), 287 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); 288 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_H3_NUM_CPUS), 289 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); 290 291 /* GIC maintenance signal */ 292 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS), 293 qdev_get_gpio_in(DEVICE(&s->gic), 294 ppibase + AW_H3_GIC_PPI_MAINT)); 295 } 296 297 /* Timer */ 298 qdev_init_nofail(DEVICE(&s->timer)); 299 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]); 300 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0, 301 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0)); 302 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1, 303 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1)); 304 305 /* SRAM */ 306 memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1", 307 64 * KiB, &error_abort); 308 memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2", 309 32 * KiB, &error_abort); 310 memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C", 311 44 * KiB, &error_abort); 312 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A1], 313 &s->sram_a1); 314 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A2], 315 &s->sram_a2); 316 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C], 317 &s->sram_c); 318 319 /* Clock Control Unit */ 320 qdev_init_nofail(DEVICE(&s->ccu)); 321 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]); 322 323 /* System Control */ 324 qdev_init_nofail(DEVICE(&s->sysctrl)); 325 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]); 326 327 /* CPU Configuration */ 328 qdev_init_nofail(DEVICE(&s->cpucfg)); 329 sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]); 330 331 /* Security Identifier */ 332 qdev_init_nofail(DEVICE(&s->sid)); 333 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]); 334 335 /* SD/MMC */ 336 qdev_init_nofail(DEVICE(&s->mmc0)); 337 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]); 338 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, 339 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0)); 340 341 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0), 342 "sd-bus", &error_abort); 343 344 /* EMAC */ 345 if (nd_table[0].used) { 346 qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC); 347 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); 348 } 349 qdev_init_nofail(DEVICE(&s->emac)); 350 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]); 351 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0, 352 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC)); 353 354 /* Universal Serial Bus */ 355 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0], 356 qdev_get_gpio_in(DEVICE(&s->gic), 357 AW_H3_GIC_SPI_EHCI0)); 358 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1], 359 qdev_get_gpio_in(DEVICE(&s->gic), 360 AW_H3_GIC_SPI_EHCI1)); 361 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2], 362 qdev_get_gpio_in(DEVICE(&s->gic), 363 AW_H3_GIC_SPI_EHCI2)); 364 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3], 365 qdev_get_gpio_in(DEVICE(&s->gic), 366 AW_H3_GIC_SPI_EHCI3)); 367 368 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0], 369 qdev_get_gpio_in(DEVICE(&s->gic), 370 AW_H3_GIC_SPI_OHCI0)); 371 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1], 372 qdev_get_gpio_in(DEVICE(&s->gic), 373 AW_H3_GIC_SPI_OHCI1)); 374 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2], 375 qdev_get_gpio_in(DEVICE(&s->gic), 376 AW_H3_GIC_SPI_OHCI2)); 377 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3], 378 qdev_get_gpio_in(DEVICE(&s->gic), 379 AW_H3_GIC_SPI_OHCI3)); 380 381 /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */ 382 serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2, 383 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0), 384 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); 385 /* UART1 */ 386 serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART1], 2, 387 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1), 388 115200, serial_hd(1), DEVICE_NATIVE_ENDIAN); 389 /* UART2 */ 390 serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART2], 2, 391 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2), 392 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN); 393 /* UART3 */ 394 serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2, 395 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3), 396 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN); 397 398 /* Unimplemented devices */ 399 for (i = 0; i < ARRAY_SIZE(unimplemented); i++) { 400 create_unimplemented_device(unimplemented[i].device_name, 401 unimplemented[i].base, 402 unimplemented[i].size); 403 } 404 } 405 406 static void allwinner_h3_class_init(ObjectClass *oc, void *data) 407 { 408 DeviceClass *dc = DEVICE_CLASS(oc); 409 410 dc->realize = allwinner_h3_realize; 411 /* Reason: uses serial_hd() in realize function */ 412 dc->user_creatable = false; 413 } 414 415 static const TypeInfo allwinner_h3_type_info = { 416 .name = TYPE_AW_H3, 417 .parent = TYPE_DEVICE, 418 .instance_size = sizeof(AwH3State), 419 .instance_init = allwinner_h3_init, 420 .class_init = allwinner_h3_class_init, 421 }; 422 423 static void allwinner_h3_register_types(void) 424 { 425 type_register_static(&allwinner_h3_type_info); 426 } 427 428 type_init(allwinner_h3_register_types) 429