1 /* 2 * Allwinner A10 SoC emulation 3 * 4 * Copyright (C) 2013 Li Guang 5 * Written by Li Guang <lig.fnst@cn.fujitsu.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qapi/error.h" 20 #include "qemu/module.h" 21 #include "hw/sysbus.h" 22 #include "hw/arm/allwinner-a10.h" 23 #include "hw/misc/unimp.h" 24 #include "sysemu/sysemu.h" 25 #include "hw/boards.h" 26 #include "hw/usb/hcd-ohci.h" 27 28 #define AW_A10_DRAMC_BASE 0x01c01000 29 #define AW_A10_MMC0_BASE 0x01c0f000 30 #define AW_A10_CCM_BASE 0x01c20000 31 #define AW_A10_PIC_REG_BASE 0x01c20400 32 #define AW_A10_PIT_REG_BASE 0x01c20c00 33 #define AW_A10_UART0_REG_BASE 0x01c28000 34 #define AW_A10_EMAC_BASE 0x01c0b000 35 #define AW_A10_EHCI_BASE 0x01c14000 36 #define AW_A10_OHCI_BASE 0x01c14400 37 #define AW_A10_SATA_BASE 0x01c18000 38 #define AW_A10_RTC_BASE 0x01c20d00 39 #define AW_A10_I2C0_BASE 0x01c2ac00 40 41 static void aw_a10_init(Object *obj) 42 { 43 AwA10State *s = AW_A10(obj); 44 45 object_initialize_child(obj, "cpu", &s->cpu, 46 ARM_CPU_TYPE_NAME("cortex-a8")); 47 48 object_initialize_child(obj, "intc", &s->intc, TYPE_AW_A10_PIC); 49 50 object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT); 51 52 object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM); 53 54 object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_A10_DRAMC); 55 56 object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC); 57 58 object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI); 59 60 object_initialize_child(obj, "i2c0", &s->i2c0, TYPE_AW_I2C); 61 62 if (machine_usb(current_machine)) { 63 int i; 64 65 for (i = 0; i < AW_A10_NUM_USB; i++) { 66 object_initialize_child(obj, "ehci[*]", &s->ehci[i], 67 TYPE_PLATFORM_EHCI); 68 object_initialize_child(obj, "ohci[*]", &s->ohci[i], 69 TYPE_SYSBUS_OHCI); 70 } 71 } 72 73 object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN4I); 74 75 object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN4I); 76 } 77 78 static void aw_a10_realize(DeviceState *dev, Error **errp) 79 { 80 AwA10State *s = AW_A10(dev); 81 SysBusDevice *sysbusdev; 82 83 if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) { 84 return; 85 } 86 87 if (!sysbus_realize(SYS_BUS_DEVICE(&s->intc), errp)) { 88 return; 89 } 90 sysbusdev = SYS_BUS_DEVICE(&s->intc); 91 sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE); 92 sysbus_connect_irq(sysbusdev, 0, 93 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); 94 sysbus_connect_irq(sysbusdev, 1, 95 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); 96 qdev_pass_gpios(DEVICE(&s->intc), dev, NULL); 97 98 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) { 99 return; 100 } 101 sysbusdev = SYS_BUS_DEVICE(&s->timer); 102 sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE); 103 sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 22)); 104 sysbus_connect_irq(sysbusdev, 1, qdev_get_gpio_in(dev, 23)); 105 sysbus_connect_irq(sysbusdev, 2, qdev_get_gpio_in(dev, 24)); 106 sysbus_connect_irq(sysbusdev, 3, qdev_get_gpio_in(dev, 25)); 107 sysbus_connect_irq(sysbusdev, 4, qdev_get_gpio_in(dev, 67)); 108 sysbus_connect_irq(sysbusdev, 5, qdev_get_gpio_in(dev, 68)); 109 110 memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB, 111 &error_fatal); 112 memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a); 113 create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB); 114 115 /* Clock Control Module */ 116 sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal); 117 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE); 118 119 /* DRAM Control Module */ 120 sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal); 121 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, AW_A10_DRAMC_BASE); 122 123 /* FIXME use qdev NIC properties instead of nd_table[] */ 124 if (nd_table[0].used) { 125 qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC); 126 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); 127 } 128 if (!sysbus_realize(SYS_BUS_DEVICE(&s->emac), errp)) { 129 return; 130 } 131 sysbusdev = SYS_BUS_DEVICE(&s->emac); 132 sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE); 133 sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(dev, 55)); 134 135 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) { 136 return; 137 } 138 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE); 139 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, qdev_get_gpio_in(dev, 56)); 140 141 /* FIXME use a qdev chardev prop instead of serial_hd() */ 142 serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, 143 qdev_get_gpio_in(dev, 1), 144 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); 145 146 if (machine_usb(current_machine)) { 147 int i; 148 149 for (i = 0; i < AW_A10_NUM_USB; i++) { 150 g_autofree char *bus = g_strdup_printf("usb-bus.%d", i); 151 152 object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", 153 true, &error_fatal); 154 sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal); 155 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, 156 AW_A10_EHCI_BASE + i * 0x8000); 157 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, 158 qdev_get_gpio_in(dev, 39 + i)); 159 160 object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus, 161 &error_fatal); 162 sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal); 163 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0, 164 AW_A10_OHCI_BASE + i * 0x8000); 165 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0, 166 qdev_get_gpio_in(dev, 64 + i)); 167 } 168 } 169 170 /* SD/MMC */ 171 object_property_set_link(OBJECT(&s->mmc0), "dma-memory", 172 OBJECT(get_system_memory()), &error_fatal); 173 sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal); 174 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE); 175 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32)); 176 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0), 177 "sd-bus"); 178 179 /* RTC */ 180 sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal); 181 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10); 182 183 /* I2C */ 184 sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal); 185 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, AW_A10_I2C0_BASE); 186 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, qdev_get_gpio_in(dev, 7)); 187 } 188 189 static void aw_a10_class_init(ObjectClass *oc, void *data) 190 { 191 DeviceClass *dc = DEVICE_CLASS(oc); 192 193 dc->realize = aw_a10_realize; 194 /* Reason: Uses serial_hds and nd_table in realize function */ 195 dc->user_creatable = false; 196 } 197 198 static const TypeInfo aw_a10_type_info = { 199 .name = TYPE_AW_A10, 200 .parent = TYPE_DEVICE, 201 .instance_size = sizeof(AwA10State), 202 .instance_init = aw_a10_init, 203 .class_init = aw_a10_class_init, 204 }; 205 206 static void aw_a10_register_types(void) 207 { 208 type_register_static(&aw_a10_type_info); 209 } 210 211 type_init(aw_a10_register_types) 212