1d1f711d4SAlistair Francis /* 2d1f711d4SAlistair Francis * STM32F2XX ADC 3d1f711d4SAlistair Francis * 4d1f711d4SAlistair Francis * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5d1f711d4SAlistair Francis * 6d1f711d4SAlistair Francis * Permission is hereby granted, free of charge, to any person obtaining a copy 7d1f711d4SAlistair Francis * of this software and associated documentation files (the "Software"), to deal 8d1f711d4SAlistair Francis * in the Software without restriction, including without limitation the rights 9d1f711d4SAlistair Francis * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10d1f711d4SAlistair Francis * copies of the Software, and to permit persons to whom the Software is 11d1f711d4SAlistair Francis * furnished to do so, subject to the following conditions: 12d1f711d4SAlistair Francis * 13d1f711d4SAlistair Francis * The above copyright notice and this permission notice shall be included in 14d1f711d4SAlistair Francis * all copies or substantial portions of the Software. 15d1f711d4SAlistair Francis * 16d1f711d4SAlistair Francis * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17d1f711d4SAlistair Francis * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18d1f711d4SAlistair Francis * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19d1f711d4SAlistair Francis * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20d1f711d4SAlistair Francis * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21d1f711d4SAlistair Francis * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22d1f711d4SAlistair Francis * THE SOFTWARE. 23d1f711d4SAlistair Francis */ 24d1f711d4SAlistair Francis 25d1f711d4SAlistair Francis #include "qemu/osdep.h" 26d1f711d4SAlistair Francis #include "hw/sysbus.h" 27*d6454270SMarkus Armbruster #include "migration/vmstate.h" 28d1f711d4SAlistair Francis #include "hw/hw.h" 29d1f711d4SAlistair Francis #include "qemu/log.h" 300b8fa32fSMarkus Armbruster #include "qemu/module.h" 31d1f711d4SAlistair Francis #include "hw/adc/stm32f2xx_adc.h" 32d1f711d4SAlistair Francis 33d1f711d4SAlistair Francis #ifndef STM_ADC_ERR_DEBUG 34d1f711d4SAlistair Francis #define STM_ADC_ERR_DEBUG 0 35d1f711d4SAlistair Francis #endif 36d1f711d4SAlistair Francis 37d1f711d4SAlistair Francis #define DB_PRINT_L(lvl, fmt, args...) do { \ 38d1f711d4SAlistair Francis if (STM_ADC_ERR_DEBUG >= lvl) { \ 39d1f711d4SAlistair Francis qemu_log("%s: " fmt, __func__, ## args); \ 40d1f711d4SAlistair Francis } \ 412562755eSEric Blake } while (0) 42d1f711d4SAlistair Francis 43d1f711d4SAlistair Francis #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 44d1f711d4SAlistair Francis 45d1f711d4SAlistair Francis static void stm32f2xx_adc_reset(DeviceState *dev) 46d1f711d4SAlistair Francis { 47d1f711d4SAlistair Francis STM32F2XXADCState *s = STM32F2XX_ADC(dev); 48d1f711d4SAlistair Francis 49d1f711d4SAlistair Francis s->adc_sr = 0x00000000; 50d1f711d4SAlistair Francis s->adc_cr1 = 0x00000000; 51d1f711d4SAlistair Francis s->adc_cr2 = 0x00000000; 52d1f711d4SAlistair Francis s->adc_smpr1 = 0x00000000; 53d1f711d4SAlistair Francis s->adc_smpr2 = 0x00000000; 54d1f711d4SAlistair Francis s->adc_jofr[0] = 0x00000000; 55d1f711d4SAlistair Francis s->adc_jofr[1] = 0x00000000; 56d1f711d4SAlistair Francis s->adc_jofr[2] = 0x00000000; 57d1f711d4SAlistair Francis s->adc_jofr[3] = 0x00000000; 58d1f711d4SAlistair Francis s->adc_htr = 0x00000FFF; 59d1f711d4SAlistair Francis s->adc_ltr = 0x00000000; 60d1f711d4SAlistair Francis s->adc_sqr1 = 0x00000000; 61d1f711d4SAlistair Francis s->adc_sqr2 = 0x00000000; 62d1f711d4SAlistair Francis s->adc_sqr3 = 0x00000000; 63d1f711d4SAlistair Francis s->adc_jsqr = 0x00000000; 64d1f711d4SAlistair Francis s->adc_jdr[0] = 0x00000000; 65d1f711d4SAlistair Francis s->adc_jdr[1] = 0x00000000; 66d1f711d4SAlistair Francis s->adc_jdr[2] = 0x00000000; 67d1f711d4SAlistair Francis s->adc_jdr[3] = 0x00000000; 68d1f711d4SAlistair Francis s->adc_dr = 0x00000000; 69d1f711d4SAlistair Francis } 70d1f711d4SAlistair Francis 71d1f711d4SAlistair Francis static uint32_t stm32f2xx_adc_generate_value(STM32F2XXADCState *s) 72d1f711d4SAlistair Francis { 73d1f711d4SAlistair Francis /* Attempts to fake some ADC values */ 74d1f711d4SAlistair Francis s->adc_dr = s->adc_dr + 7; 75d1f711d4SAlistair Francis 76d1f711d4SAlistair Francis switch ((s->adc_cr1 & ADC_CR1_RES) >> 24) { 77d1f711d4SAlistair Francis case 0: 78d1f711d4SAlistair Francis /* 12-bit */ 79d1f711d4SAlistair Francis s->adc_dr &= 0xFFF; 80d1f711d4SAlistair Francis break; 81d1f711d4SAlistair Francis case 1: 82d1f711d4SAlistair Francis /* 10-bit */ 83d1f711d4SAlistair Francis s->adc_dr &= 0x3FF; 84d1f711d4SAlistair Francis break; 85d1f711d4SAlistair Francis case 2: 86d1f711d4SAlistair Francis /* 8-bit */ 87d1f711d4SAlistair Francis s->adc_dr &= 0xFF; 88d1f711d4SAlistair Francis break; 89d1f711d4SAlistair Francis default: 90d1f711d4SAlistair Francis /* 6-bit */ 91d1f711d4SAlistair Francis s->adc_dr &= 0x3F; 92d1f711d4SAlistair Francis } 93d1f711d4SAlistair Francis 94d1f711d4SAlistair Francis if (s->adc_cr2 & ADC_CR2_ALIGN) { 95d1f711d4SAlistair Francis return (s->adc_dr << 1) & 0xFFF0; 96d1f711d4SAlistair Francis } else { 97d1f711d4SAlistair Francis return s->adc_dr; 98d1f711d4SAlistair Francis } 99d1f711d4SAlistair Francis } 100d1f711d4SAlistair Francis 101d1f711d4SAlistair Francis static uint64_t stm32f2xx_adc_read(void *opaque, hwaddr addr, 102d1f711d4SAlistair Francis unsigned int size) 103d1f711d4SAlistair Francis { 104d1f711d4SAlistair Francis STM32F2XXADCState *s = opaque; 105d1f711d4SAlistair Francis 106d1f711d4SAlistair Francis DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr); 107d1f711d4SAlistair Francis 108d1f711d4SAlistair Francis if (addr >= ADC_COMMON_ADDRESS) { 109d1f711d4SAlistair Francis qemu_log_mask(LOG_UNIMP, 110d1f711d4SAlistair Francis "%s: ADC Common Register Unsupported\n", __func__); 111d1f711d4SAlistair Francis } 112d1f711d4SAlistair Francis 113d1f711d4SAlistair Francis switch (addr) { 114d1f711d4SAlistair Francis case ADC_SR: 115d1f711d4SAlistair Francis return s->adc_sr; 116d1f711d4SAlistair Francis case ADC_CR1: 117d1f711d4SAlistair Francis return s->adc_cr1; 118d1f711d4SAlistair Francis case ADC_CR2: 119d1f711d4SAlistair Francis return s->adc_cr2 & 0xFFFFFFF; 120d1f711d4SAlistair Francis case ADC_SMPR1: 121d1f711d4SAlistair Francis return s->adc_smpr1; 122d1f711d4SAlistair Francis case ADC_SMPR2: 123d1f711d4SAlistair Francis return s->adc_smpr2; 124d1f711d4SAlistair Francis case ADC_JOFR1: 125d1f711d4SAlistair Francis case ADC_JOFR2: 126d1f711d4SAlistair Francis case ADC_JOFR3: 127d1f711d4SAlistair Francis case ADC_JOFR4: 128d1f711d4SAlistair Francis qemu_log_mask(LOG_UNIMP, "%s: " \ 129d1f711d4SAlistair Francis "Injection ADC is not implemented, the registers are " \ 130d1f711d4SAlistair Francis "included for compatibility\n", __func__); 131d1f711d4SAlistair Francis return s->adc_jofr[(addr - ADC_JOFR1) / 4]; 132d1f711d4SAlistair Francis case ADC_HTR: 133d1f711d4SAlistair Francis return s->adc_htr; 134d1f711d4SAlistair Francis case ADC_LTR: 135d1f711d4SAlistair Francis return s->adc_ltr; 136d1f711d4SAlistair Francis case ADC_SQR1: 137d1f711d4SAlistair Francis return s->adc_sqr1; 138d1f711d4SAlistair Francis case ADC_SQR2: 139d1f711d4SAlistair Francis return s->adc_sqr2; 140d1f711d4SAlistair Francis case ADC_SQR3: 141d1f711d4SAlistair Francis return s->adc_sqr3; 142d1f711d4SAlistair Francis case ADC_JSQR: 143d1f711d4SAlistair Francis qemu_log_mask(LOG_UNIMP, "%s: " \ 144d1f711d4SAlistair Francis "Injection ADC is not implemented, the registers are " \ 145d1f711d4SAlistair Francis "included for compatibility\n", __func__); 146d1f711d4SAlistair Francis return s->adc_jsqr; 147d1f711d4SAlistair Francis case ADC_JDR1: 148d1f711d4SAlistair Francis case ADC_JDR2: 149d1f711d4SAlistair Francis case ADC_JDR3: 150d1f711d4SAlistair Francis case ADC_JDR4: 151d1f711d4SAlistair Francis qemu_log_mask(LOG_UNIMP, "%s: " \ 152d1f711d4SAlistair Francis "Injection ADC is not implemented, the registers are " \ 153d1f711d4SAlistair Francis "included for compatibility\n", __func__); 154d1f711d4SAlistair Francis return s->adc_jdr[(addr - ADC_JDR1) / 4] - 155d1f711d4SAlistair Francis s->adc_jofr[(addr - ADC_JDR1) / 4]; 156d1f711d4SAlistair Francis case ADC_DR: 157d1f711d4SAlistair Francis if ((s->adc_cr2 & ADC_CR2_ADON) && (s->adc_cr2 & ADC_CR2_SWSTART)) { 158d1f711d4SAlistair Francis s->adc_cr2 ^= ADC_CR2_SWSTART; 159d1f711d4SAlistair Francis return stm32f2xx_adc_generate_value(s); 160d1f711d4SAlistair Francis } else { 161d1f711d4SAlistair Francis return 0; 162d1f711d4SAlistair Francis } 163d1f711d4SAlistair Francis default: 164d1f711d4SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, 165d1f711d4SAlistair Francis "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr); 166d1f711d4SAlistair Francis } 167d1f711d4SAlistair Francis 168d1f711d4SAlistair Francis return 0; 169d1f711d4SAlistair Francis } 170d1f711d4SAlistair Francis 171d1f711d4SAlistair Francis static void stm32f2xx_adc_write(void *opaque, hwaddr addr, 172d1f711d4SAlistair Francis uint64_t val64, unsigned int size) 173d1f711d4SAlistair Francis { 174d1f711d4SAlistair Francis STM32F2XXADCState *s = opaque; 175d1f711d4SAlistair Francis uint32_t value = (uint32_t) val64; 176d1f711d4SAlistair Francis 177d1f711d4SAlistair Francis DB_PRINT("Address: 0x%" HWADDR_PRIx ", Value: 0x%x\n", 178d1f711d4SAlistair Francis addr, value); 179d1f711d4SAlistair Francis 180d1f711d4SAlistair Francis if (addr >= 0x100) { 181d1f711d4SAlistair Francis qemu_log_mask(LOG_UNIMP, 182d1f711d4SAlistair Francis "%s: ADC Common Register Unsupported\n", __func__); 183d1f711d4SAlistair Francis } 184d1f711d4SAlistair Francis 185d1f711d4SAlistair Francis switch (addr) { 186d1f711d4SAlistair Francis case ADC_SR: 187d1f711d4SAlistair Francis s->adc_sr &= (value & 0x3F); 188d1f711d4SAlistair Francis break; 189d1f711d4SAlistair Francis case ADC_CR1: 190d1f711d4SAlistair Francis s->adc_cr1 = value; 191d1f711d4SAlistair Francis break; 192d1f711d4SAlistair Francis case ADC_CR2: 193d1f711d4SAlistair Francis s->adc_cr2 = value; 194d1f711d4SAlistair Francis break; 195d1f711d4SAlistair Francis case ADC_SMPR1: 196d1f711d4SAlistair Francis s->adc_smpr1 = value; 197d1f711d4SAlistair Francis break; 198d1f711d4SAlistair Francis case ADC_SMPR2: 199d1f711d4SAlistair Francis s->adc_smpr2 = value; 200d1f711d4SAlistair Francis break; 201d1f711d4SAlistair Francis case ADC_JOFR1: 202d1f711d4SAlistair Francis case ADC_JOFR2: 203d1f711d4SAlistair Francis case ADC_JOFR3: 204d1f711d4SAlistair Francis case ADC_JOFR4: 205d1f711d4SAlistair Francis s->adc_jofr[(addr - ADC_JOFR1) / 4] = (value & 0xFFF); 206d1f711d4SAlistair Francis qemu_log_mask(LOG_UNIMP, "%s: " \ 207d1f711d4SAlistair Francis "Injection ADC is not implemented, the registers are " \ 208d1f711d4SAlistair Francis "included for compatibility\n", __func__); 209d1f711d4SAlistair Francis break; 210d1f711d4SAlistair Francis case ADC_HTR: 211d1f711d4SAlistair Francis s->adc_htr = value; 212d1f711d4SAlistair Francis break; 213d1f711d4SAlistair Francis case ADC_LTR: 214d1f711d4SAlistair Francis s->adc_ltr = value; 215d1f711d4SAlistair Francis break; 216d1f711d4SAlistair Francis case ADC_SQR1: 217d1f711d4SAlistair Francis s->adc_sqr1 = value; 218d1f711d4SAlistair Francis break; 219d1f711d4SAlistair Francis case ADC_SQR2: 220d1f711d4SAlistair Francis s->adc_sqr2 = value; 221d1f711d4SAlistair Francis break; 222d1f711d4SAlistair Francis case ADC_SQR3: 223d1f711d4SAlistair Francis s->adc_sqr3 = value; 224d1f711d4SAlistair Francis break; 225d1f711d4SAlistair Francis case ADC_JSQR: 226d1f711d4SAlistair Francis s->adc_jsqr = value; 227d1f711d4SAlistair Francis qemu_log_mask(LOG_UNIMP, "%s: " \ 228d1f711d4SAlistair Francis "Injection ADC is not implemented, the registers are " \ 229d1f711d4SAlistair Francis "included for compatibility\n", __func__); 230d1f711d4SAlistair Francis break; 231d1f711d4SAlistair Francis case ADC_JDR1: 232d1f711d4SAlistair Francis case ADC_JDR2: 233d1f711d4SAlistair Francis case ADC_JDR3: 234d1f711d4SAlistair Francis case ADC_JDR4: 235d1f711d4SAlistair Francis s->adc_jdr[(addr - ADC_JDR1) / 4] = value; 236d1f711d4SAlistair Francis qemu_log_mask(LOG_UNIMP, "%s: " \ 237d1f711d4SAlistair Francis "Injection ADC is not implemented, the registers are " \ 238d1f711d4SAlistair Francis "included for compatibility\n", __func__); 239d1f711d4SAlistair Francis break; 240d1f711d4SAlistair Francis default: 241d1f711d4SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, 242d1f711d4SAlistair Francis "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr); 243d1f711d4SAlistair Francis } 244d1f711d4SAlistair Francis } 245d1f711d4SAlistair Francis 246d1f711d4SAlistair Francis static const MemoryRegionOps stm32f2xx_adc_ops = { 247d1f711d4SAlistair Francis .read = stm32f2xx_adc_read, 248d1f711d4SAlistair Francis .write = stm32f2xx_adc_write, 249d1f711d4SAlistair Francis .endianness = DEVICE_NATIVE_ENDIAN, 250d1f711d4SAlistair Francis }; 251d1f711d4SAlistair Francis 252d1f711d4SAlistair Francis static const VMStateDescription vmstate_stm32f2xx_adc = { 253d1f711d4SAlistair Francis .name = TYPE_STM32F2XX_ADC, 254d1f711d4SAlistair Francis .version_id = 1, 255d1f711d4SAlistair Francis .minimum_version_id = 1, 256d1f711d4SAlistair Francis .fields = (VMStateField[]) { 257d1f711d4SAlistair Francis VMSTATE_UINT32(adc_sr, STM32F2XXADCState), 258d1f711d4SAlistair Francis VMSTATE_UINT32(adc_cr1, STM32F2XXADCState), 259d1f711d4SAlistair Francis VMSTATE_UINT32(adc_cr2, STM32F2XXADCState), 260d1f711d4SAlistair Francis VMSTATE_UINT32(adc_smpr1, STM32F2XXADCState), 261d1f711d4SAlistair Francis VMSTATE_UINT32(adc_smpr2, STM32F2XXADCState), 262d1f711d4SAlistair Francis VMSTATE_UINT32_ARRAY(adc_jofr, STM32F2XXADCState, 4), 263d1f711d4SAlistair Francis VMSTATE_UINT32(adc_htr, STM32F2XXADCState), 264d1f711d4SAlistair Francis VMSTATE_UINT32(adc_ltr, STM32F2XXADCState), 265d1f711d4SAlistair Francis VMSTATE_UINT32(adc_sqr1, STM32F2XXADCState), 266d1f711d4SAlistair Francis VMSTATE_UINT32(adc_sqr2, STM32F2XXADCState), 267d1f711d4SAlistair Francis VMSTATE_UINT32(adc_sqr3, STM32F2XXADCState), 268d1f711d4SAlistair Francis VMSTATE_UINT32(adc_jsqr, STM32F2XXADCState), 269d1f711d4SAlistair Francis VMSTATE_UINT32_ARRAY(adc_jdr, STM32F2XXADCState, 4), 270d1f711d4SAlistair Francis VMSTATE_UINT32(adc_dr, STM32F2XXADCState), 271d1f711d4SAlistair Francis VMSTATE_END_OF_LIST() 272d1f711d4SAlistair Francis } 273d1f711d4SAlistair Francis }; 274d1f711d4SAlistair Francis 275d1f711d4SAlistair Francis static void stm32f2xx_adc_init(Object *obj) 276d1f711d4SAlistair Francis { 277d1f711d4SAlistair Francis STM32F2XXADCState *s = STM32F2XX_ADC(obj); 278d1f711d4SAlistair Francis 279d1f711d4SAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 280d1f711d4SAlistair Francis 281d1f711d4SAlistair Francis memory_region_init_io(&s->mmio, obj, &stm32f2xx_adc_ops, s, 282d1f711d4SAlistair Francis TYPE_STM32F2XX_ADC, 0xFF); 283d1f711d4SAlistair Francis sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 284d1f711d4SAlistair Francis } 285d1f711d4SAlistair Francis 286d1f711d4SAlistair Francis static void stm32f2xx_adc_class_init(ObjectClass *klass, void *data) 287d1f711d4SAlistair Francis { 288d1f711d4SAlistair Francis DeviceClass *dc = DEVICE_CLASS(klass); 289d1f711d4SAlistair Francis 290d1f711d4SAlistair Francis dc->reset = stm32f2xx_adc_reset; 291d1f711d4SAlistair Francis dc->vmsd = &vmstate_stm32f2xx_adc; 292d1f711d4SAlistair Francis } 293d1f711d4SAlistair Francis 294d1f711d4SAlistair Francis static const TypeInfo stm32f2xx_adc_info = { 295d1f711d4SAlistair Francis .name = TYPE_STM32F2XX_ADC, 296d1f711d4SAlistair Francis .parent = TYPE_SYS_BUS_DEVICE, 297d1f711d4SAlistair Francis .instance_size = sizeof(STM32F2XXADCState), 298d1f711d4SAlistair Francis .instance_init = stm32f2xx_adc_init, 299d1f711d4SAlistair Francis .class_init = stm32f2xx_adc_class_init, 300d1f711d4SAlistair Francis }; 301d1f711d4SAlistair Francis 302d1f711d4SAlistair Francis static void stm32f2xx_adc_register_types(void) 303d1f711d4SAlistair Francis { 304d1f711d4SAlistair Francis type_register_static(&stm32f2xx_adc_info); 305d1f711d4SAlistair Francis } 306d1f711d4SAlistair Francis 307d1f711d4SAlistair Francis type_init(stm32f2xx_adc_register_types) 308