1 /* 2 * ACPI implementation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2.1 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 * 18 * Contributions after 2012-01-13 are licensed under the terms of the 19 * GNU GPL, version 2 or (at your option) any later version. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "hw/irq.h" 24 #include "hw/isa/apm.h" 25 #include "hw/i2c/pm_smbus.h" 26 #include "hw/pci/pci.h" 27 #include "hw/qdev-properties.h" 28 #include "hw/acpi/acpi.h" 29 #include "hw/acpi/pcihp.h" 30 #include "hw/acpi/piix4.h" 31 #include "sysemu/runstate.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/xen.h" 34 #include "qapi/error.h" 35 #include "qemu/range.h" 36 #include "hw/acpi/cpu_hotplug.h" 37 #include "hw/acpi/cpu.h" 38 #include "hw/hotplug.h" 39 #include "hw/mem/pc-dimm.h" 40 #include "hw/mem/nvdimm.h" 41 #include "hw/acpi/memory_hotplug.h" 42 #include "hw/acpi/acpi_dev_interface.h" 43 #include "migration/vmstate.h" 44 #include "hw/core/cpu.h" 45 #include "trace.h" 46 #include "qom/object.h" 47 48 #define GPE_BASE 0xafe0 49 #define GPE_LEN 4 50 51 #define ACPI_PCIHP_ADDR_PIIX4 0xae00 52 53 struct pci_status { 54 uint32_t up; /* deprecated, maintained for migration compatibility */ 55 uint32_t down; 56 }; 57 58 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 59 PCIBus *bus, PIIX4PMState *s); 60 61 #define ACPI_ENABLE 0xf1 62 #define ACPI_DISABLE 0xf0 63 64 static void pm_tmr_timer(ACPIREGS *ar) 65 { 66 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); 67 acpi_update_sci(&s->ar, s->irq); 68 } 69 70 static void apm_ctrl_changed(uint32_t val, void *arg) 71 { 72 PIIX4PMState *s = arg; 73 PCIDevice *d = PCI_DEVICE(s); 74 75 /* ACPI specs 3.0, 4.7.2.5 */ 76 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); 77 if (val == ACPI_ENABLE || val == ACPI_DISABLE) { 78 return; 79 } 80 81 if (d->config[0x5b] & (1 << 1)) { 82 if (s->smi_irq) { 83 qemu_irq_raise(s->smi_irq); 84 } 85 } 86 } 87 88 static void pm_io_space_update(PIIX4PMState *s) 89 { 90 PCIDevice *d = PCI_DEVICE(s); 91 92 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); 93 s->io_base &= 0xffc0; 94 95 memory_region_transaction_begin(); 96 memory_region_set_enabled(&s->io, d->config[0x80] & 1); 97 memory_region_set_address(&s->io, s->io_base); 98 memory_region_transaction_commit(); 99 } 100 101 static void smbus_io_space_update(PIIX4PMState *s) 102 { 103 PCIDevice *d = PCI_DEVICE(s); 104 105 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); 106 s->smb_io_base &= 0xffc0; 107 108 memory_region_transaction_begin(); 109 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1); 110 memory_region_set_address(&s->smb.io, s->smb_io_base); 111 memory_region_transaction_commit(); 112 } 113 114 static void pm_write_config(PCIDevice *d, 115 uint32_t address, uint32_t val, int len) 116 { 117 pci_default_write_config(d, address, val, len); 118 if (range_covers_byte(address, len, 0x80) || 119 ranges_overlap(address, len, 0x40, 4)) { 120 pm_io_space_update((PIIX4PMState *)d); 121 } 122 if (range_covers_byte(address, len, 0xd2) || 123 ranges_overlap(address, len, 0x90, 4)) { 124 smbus_io_space_update((PIIX4PMState *)d); 125 } 126 } 127 128 static int vmstate_acpi_post_load(void *opaque, int version_id) 129 { 130 PIIX4PMState *s = opaque; 131 132 pm_io_space_update(s); 133 smbus_io_space_update(s); 134 return 0; 135 } 136 137 #define VMSTATE_GPE_ARRAY(_field, _state) \ 138 { \ 139 .name = (stringify(_field)), \ 140 .version_id = 0, \ 141 .info = &vmstate_info_uint16, \ 142 .size = sizeof(uint16_t), \ 143 .flags = VMS_SINGLE | VMS_POINTER, \ 144 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ 145 } 146 147 static const VMStateDescription vmstate_gpe = { 148 .name = "gpe", 149 .version_id = 1, 150 .minimum_version_id = 1, 151 .fields = (VMStateField[]) { 152 VMSTATE_GPE_ARRAY(sts, ACPIGPE), 153 VMSTATE_GPE_ARRAY(en, ACPIGPE), 154 VMSTATE_END_OF_LIST() 155 } 156 }; 157 158 static const VMStateDescription vmstate_pci_status = { 159 .name = "pci_status", 160 .version_id = 1, 161 .minimum_version_id = 1, 162 .fields = (VMStateField[]) { 163 VMSTATE_UINT32(up, struct AcpiPciHpPciStatus), 164 VMSTATE_UINT32(down, struct AcpiPciHpPciStatus), 165 VMSTATE_END_OF_LIST() 166 } 167 }; 168 169 static bool vmstate_test_use_acpi_hotplug_bridge(void *opaque, int version_id) 170 { 171 PIIX4PMState *s = opaque; 172 return s->acpi_pci_hotplug.use_acpi_hotplug_bridge; 173 } 174 175 static bool vmstate_test_no_use_acpi_hotplug_bridge(void *opaque, 176 int version_id) 177 { 178 PIIX4PMState *s = opaque; 179 return !s->acpi_pci_hotplug.use_acpi_hotplug_bridge; 180 } 181 182 static bool vmstate_test_use_memhp(void *opaque) 183 { 184 PIIX4PMState *s = opaque; 185 return s->acpi_memory_hotplug.is_enabled; 186 } 187 188 static const VMStateDescription vmstate_memhp_state = { 189 .name = "piix4_pm/memhp", 190 .version_id = 1, 191 .minimum_version_id = 1, 192 .needed = vmstate_test_use_memhp, 193 .fields = (VMStateField[]) { 194 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState), 195 VMSTATE_END_OF_LIST() 196 } 197 }; 198 199 static bool vmstate_test_use_cpuhp(void *opaque) 200 { 201 PIIX4PMState *s = opaque; 202 return !s->cpu_hotplug_legacy; 203 } 204 205 static int vmstate_cpuhp_pre_load(void *opaque) 206 { 207 Object *obj = OBJECT(opaque); 208 object_property_set_bool(obj, "cpu-hotplug-legacy", false, &error_abort); 209 return 0; 210 } 211 212 static const VMStateDescription vmstate_cpuhp_state = { 213 .name = "piix4_pm/cpuhp", 214 .version_id = 1, 215 .minimum_version_id = 1, 216 .needed = vmstate_test_use_cpuhp, 217 .pre_load = vmstate_cpuhp_pre_load, 218 .fields = (VMStateField[]) { 219 VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState), 220 VMSTATE_END_OF_LIST() 221 } 222 }; 223 224 static bool piix4_vmstate_need_smbus(void *opaque, int version_id) 225 { 226 return pm_smbus_vmstate_needed(); 227 } 228 229 /* 230 * This is a fudge to turn off the acpi_index field, 231 * whose test was always broken on piix4 with 6.2 and older machine types. 232 */ 233 static bool vmstate_test_migrate_acpi_index(void *opaque, int version_id) 234 { 235 PIIX4PMState *s = PIIX4_PM(opaque); 236 return s->acpi_pci_hotplug.use_acpi_hotplug_bridge && 237 !s->not_migrate_acpi_index; 238 } 239 240 /* qemu-kvm 1.2 uses version 3 but advertised as 2 241 * To support incoming qemu-kvm 1.2 migration, change version_id 242 * and minimum_version_id to 2 below (which breaks migration from 243 * qemu 1.2). 244 * 245 */ 246 static const VMStateDescription vmstate_acpi = { 247 .name = "piix4_pm", 248 .version_id = 3, 249 .minimum_version_id = 3, 250 .post_load = vmstate_acpi_post_load, 251 .fields = (VMStateField[]) { 252 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState), 253 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState), 254 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState), 255 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState), 256 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), 257 VMSTATE_STRUCT_TEST(smb, PIIX4PMState, piix4_vmstate_need_smbus, 3, 258 pmsmb_vmstate, PMSMBus), 259 VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState), 260 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState), 261 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE), 262 VMSTATE_STRUCT_TEST( 263 acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 264 PIIX4PMState, 265 vmstate_test_no_use_acpi_hotplug_bridge, 266 2, vmstate_pci_status, 267 struct AcpiPciHpPciStatus), 268 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState, 269 vmstate_test_use_acpi_hotplug_bridge, 270 vmstate_test_migrate_acpi_index), 271 VMSTATE_END_OF_LIST() 272 }, 273 .subsections = (const VMStateDescription*[]) { 274 &vmstate_memhp_state, 275 &vmstate_cpuhp_state, 276 NULL 277 } 278 }; 279 280 static void piix4_pm_reset(DeviceState *dev) 281 { 282 PIIX4PMState *s = PIIX4_PM(dev); 283 PCIDevice *d = PCI_DEVICE(s); 284 uint8_t *pci_conf = d->config; 285 286 pci_conf[0x58] = 0; 287 pci_conf[0x59] = 0; 288 pci_conf[0x5a] = 0; 289 pci_conf[0x5b] = 0; 290 291 pci_conf[0x40] = 0x01; /* PM io base read only bit */ 292 pci_conf[0x80] = 0; 293 294 if (!s->smm_enabled) { 295 /* Mark SMM as already inited (until KVM supports SMM). */ 296 pci_conf[0x5B] = 0x02; 297 } 298 299 acpi_pm1_evt_reset(&s->ar); 300 acpi_pm1_cnt_reset(&s->ar); 301 acpi_pm_tmr_reset(&s->ar); 302 acpi_gpe_reset(&s->ar); 303 acpi_update_sci(&s->ar, s->irq); 304 305 pm_io_space_update(s); 306 if (s->acpi_pci_hotplug.use_acpi_hotplug_bridge || 307 s->acpi_pci_hotplug.use_acpi_root_pci_hotplug) { 308 acpi_pcihp_reset(&s->acpi_pci_hotplug); 309 } 310 } 311 312 static void piix4_pm_powerdown_req(Notifier *n, void *opaque) 313 { 314 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier); 315 316 assert(s != NULL); 317 acpi_pm1_evt_power_down(&s->ar); 318 } 319 320 static void piix4_device_pre_plug_cb(HotplugHandler *hotplug_dev, 321 DeviceState *dev, Error **errp) 322 { 323 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 324 325 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 326 acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp); 327 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 328 if (!s->acpi_memory_hotplug.is_enabled) { 329 error_setg(errp, 330 "memory hotplug is not enabled: %s.memory-hotplug-support " 331 "is not set", object_get_typename(OBJECT(s))); 332 } 333 } else if ( 334 !object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 335 error_setg(errp, "acpi: device pre plug request for not supported" 336 " device type: %s", object_get_typename(OBJECT(dev))); 337 } 338 } 339 340 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev, 341 DeviceState *dev, Error **errp) 342 { 343 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 344 345 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 346 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 347 nvdimm_acpi_plug_cb(hotplug_dev, dev); 348 } else { 349 acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug, 350 dev, errp); 351 } 352 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 353 acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp); 354 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 355 if (s->cpu_hotplug_legacy) { 356 legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp); 357 } else { 358 acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp); 359 } 360 } else { 361 g_assert_not_reached(); 362 } 363 } 364 365 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev, 366 DeviceState *dev, Error **errp) 367 { 368 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 369 370 if (s->acpi_memory_hotplug.is_enabled && 371 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 372 acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug, 373 dev, errp); 374 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 375 acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug, 376 dev, errp); 377 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && 378 !s->cpu_hotplug_legacy) { 379 acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp); 380 } else { 381 error_setg(errp, "acpi: device unplug request for not supported device" 382 " type: %s", object_get_typename(OBJECT(dev))); 383 } 384 } 385 386 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev, 387 DeviceState *dev, Error **errp) 388 { 389 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 390 391 if (s->acpi_memory_hotplug.is_enabled && 392 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 393 acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp); 394 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 395 acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, 396 errp); 397 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && 398 !s->cpu_hotplug_legacy) { 399 acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp); 400 } else { 401 error_setg(errp, "acpi: device unplug for not supported device" 402 " type: %s", object_get_typename(OBJECT(dev))); 403 } 404 } 405 406 static bool piix4_is_hotpluggable_bus(HotplugHandler *hotplug_dev, 407 BusState *bus) 408 { 409 PIIX4PMState *s = PIIX4_PM(hotplug_dev); 410 return acpi_pcihp_is_hotpluggbale_bus(&s->acpi_pci_hotplug, bus); 411 } 412 413 static void piix4_pm_machine_ready(Notifier *n, void *opaque) 414 { 415 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready); 416 PCIDevice *d = PCI_DEVICE(s); 417 MemoryRegion *io_as = pci_address_space_io(d); 418 uint8_t *pci_conf; 419 420 pci_conf = d->config; 421 pci_conf[0x5f] = 0x10 | 422 (memory_region_present(io_as, 0x378) ? 0x80 : 0); 423 pci_conf[0x63] = 0x60; 424 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) | 425 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0); 426 } 427 428 static void piix4_pm_add_properties(PIIX4PMState *s) 429 { 430 static const uint8_t acpi_enable_cmd = ACPI_ENABLE; 431 static const uint8_t acpi_disable_cmd = ACPI_DISABLE; 432 static const uint32_t gpe0_blk = GPE_BASE; 433 static const uint32_t gpe0_blk_len = GPE_LEN; 434 static const uint16_t sci_int = 9; 435 436 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD, 437 &acpi_enable_cmd, OBJ_PROP_FLAG_READ); 438 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD, 439 &acpi_disable_cmd, OBJ_PROP_FLAG_READ); 440 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK, 441 &gpe0_blk, OBJ_PROP_FLAG_READ); 442 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN, 443 &gpe0_blk_len, OBJ_PROP_FLAG_READ); 444 object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT, 445 &sci_int, OBJ_PROP_FLAG_READ); 446 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE, 447 &s->io_base, OBJ_PROP_FLAG_READ); 448 } 449 450 static void piix4_pm_realize(PCIDevice *dev, Error **errp) 451 { 452 PIIX4PMState *s = PIIX4_PM(dev); 453 uint8_t *pci_conf; 454 455 pci_conf = dev->config; 456 pci_conf[0x06] = 0x80; 457 pci_conf[0x07] = 0x02; 458 pci_conf[0x09] = 0x00; 459 pci_conf[0x3d] = 0x01; // interrupt pin 1 460 461 /* APM */ 462 apm_init(dev, &s->apm, apm_ctrl_changed, s); 463 464 if (!s->smm_enabled) { 465 /* Mark SMM as already inited to prevent SMM from running. KVM does not 466 * support SMM mode. */ 467 pci_conf[0x5B] = 0x02; 468 } 469 470 /* XXX: which specification is used ? The i82731AB has different 471 mappings */ 472 pci_conf[0x90] = s->smb_io_base | 1; 473 pci_conf[0x91] = s->smb_io_base >> 8; 474 pci_conf[0xd2] = 0x09; 475 pm_smbus_init(DEVICE(dev), &s->smb, true); 476 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); 477 memory_region_add_subregion(pci_address_space_io(dev), 478 s->smb_io_base, &s->smb.io); 479 480 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64); 481 memory_region_set_enabled(&s->io, false); 482 memory_region_add_subregion(pci_address_space_io(dev), 483 0, &s->io); 484 485 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 486 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 487 acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val, 488 !s->smm_compat && !s->smm_enabled); 489 acpi_gpe_init(&s->ar, GPE_LEN); 490 491 s->powerdown_notifier.notify = piix4_pm_powerdown_req; 492 qemu_register_powerdown_notifier(&s->powerdown_notifier); 493 494 s->machine_ready.notify = piix4_pm_machine_ready; 495 qemu_add_machine_init_done_notifier(&s->machine_ready); 496 497 if (xen_enabled()) { 498 s->acpi_pci_hotplug.use_acpi_hotplug_bridge = false; 499 } 500 501 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), 502 pci_get_bus(dev), s); 503 504 piix4_pm_add_properties(s); 505 } 506 507 static void piix4_pm_init(Object *obj) 508 { 509 PIIX4PMState *s = PIIX4_PM(obj); 510 511 qdev_init_gpio_out(DEVICE(obj), &s->irq, 1); 512 qdev_init_gpio_out_named(DEVICE(obj), &s->smi_irq, "smi-irq", 1); 513 } 514 515 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) 516 { 517 PIIX4PMState *s = opaque; 518 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); 519 520 trace_piix4_gpe_readb(addr, width, val); 521 return val; 522 } 523 524 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, 525 unsigned width) 526 { 527 PIIX4PMState *s = opaque; 528 529 trace_piix4_gpe_writeb(addr, width, val); 530 acpi_gpe_ioport_writeb(&s->ar, addr, val); 531 acpi_update_sci(&s->ar, s->irq); 532 } 533 534 static const MemoryRegionOps piix4_gpe_ops = { 535 .read = gpe_readb, 536 .write = gpe_writeb, 537 .valid.min_access_size = 1, 538 .valid.max_access_size = 4, 539 .impl.min_access_size = 1, 540 .impl.max_access_size = 1, 541 .endianness = DEVICE_LITTLE_ENDIAN, 542 }; 543 544 545 static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp) 546 { 547 PIIX4PMState *s = PIIX4_PM(obj); 548 549 return s->cpu_hotplug_legacy; 550 } 551 552 static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp) 553 { 554 PIIX4PMState *s = PIIX4_PM(obj); 555 556 assert(!value); 557 if (s->cpu_hotplug_legacy && value == false) { 558 acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state, 559 PIIX4_CPU_HOTPLUG_IO_BASE); 560 } 561 s->cpu_hotplug_legacy = value; 562 } 563 564 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, 565 PCIBus *bus, PIIX4PMState *s) 566 { 567 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s, 568 "acpi-gpe0", GPE_LEN); 569 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); 570 571 if (s->acpi_pci_hotplug.use_acpi_hotplug_bridge || 572 s->acpi_pci_hotplug.use_acpi_root_pci_hotplug) { 573 acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, 574 ACPI_PCIHP_ADDR_PIIX4); 575 qbus_set_hotplug_handler(BUS(pci_get_bus(PCI_DEVICE(s))), OBJECT(s)); 576 } 577 578 s->cpu_hotplug_legacy = true; 579 object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy", 580 piix4_get_cpu_hotplug_legacy, 581 piix4_set_cpu_hotplug_legacy); 582 legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu, 583 PIIX4_CPU_HOTPLUG_IO_BASE); 584 585 if (s->acpi_memory_hotplug.is_enabled) { 586 acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug, 587 ACPI_MEMORY_HOTPLUG_BASE); 588 } 589 } 590 591 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list) 592 { 593 PIIX4PMState *s = PIIX4_PM(adev); 594 595 acpi_memory_ospm_status(&s->acpi_memory_hotplug, list); 596 if (!s->cpu_hotplug_legacy) { 597 acpi_cpu_ospm_status(&s->cpuhp_state, list); 598 } 599 } 600 601 static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) 602 { 603 PIIX4PMState *s = PIIX4_PM(adev); 604 605 acpi_send_gpe_event(&s->ar, s->irq, ev); 606 } 607 608 static Property piix4_pm_properties[] = { 609 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0), 610 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), 611 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), 612 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), 613 DEFINE_PROP_BOOL(ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, PIIX4PMState, 614 acpi_pci_hotplug.use_acpi_hotplug_bridge, true), 615 DEFINE_PROP_BOOL(ACPI_PM_PROP_ACPI_PCI_ROOTHP, PIIX4PMState, 616 acpi_pci_hotplug.use_acpi_root_pci_hotplug, true), 617 DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, 618 acpi_memory_hotplug.is_enabled, true), 619 DEFINE_PROP_BOOL("smm-compat", PIIX4PMState, smm_compat, false), 620 DEFINE_PROP_BOOL("smm-enabled", PIIX4PMState, smm_enabled, false), 621 DEFINE_PROP_BOOL("x-not-migrate-acpi-index", PIIX4PMState, 622 not_migrate_acpi_index, false), 623 DEFINE_PROP_END_OF_LIST(), 624 }; 625 626 static void piix4_pm_class_init(ObjectClass *klass, void *data) 627 { 628 DeviceClass *dc = DEVICE_CLASS(klass); 629 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 630 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 631 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 632 633 k->realize = piix4_pm_realize; 634 k->config_write = pm_write_config; 635 k->vendor_id = PCI_VENDOR_ID_INTEL; 636 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3; 637 k->revision = 0x03; 638 k->class_id = PCI_CLASS_BRIDGE_OTHER; 639 dc->reset = piix4_pm_reset; 640 dc->desc = "PM"; 641 dc->vmsd = &vmstate_acpi; 642 device_class_set_props(dc, piix4_pm_properties); 643 /* 644 * Reason: part of PIIX4 southbridge, needs to be wired up, 645 * e.g. by mips_malta_init() 646 */ 647 dc->user_creatable = false; 648 dc->hotpluggable = false; 649 hc->pre_plug = piix4_device_pre_plug_cb; 650 hc->plug = piix4_device_plug_cb; 651 hc->unplug_request = piix4_device_unplug_request_cb; 652 hc->unplug = piix4_device_unplug_cb; 653 hc->is_hotpluggable_bus = piix4_is_hotpluggable_bus; 654 adevc->ospm_status = piix4_ospm_status; 655 adevc->send_event = piix4_send_gpe; 656 } 657 658 static const TypeInfo piix4_pm_info = { 659 .name = TYPE_PIIX4_PM, 660 .parent = TYPE_PCI_DEVICE, 661 .instance_init = piix4_pm_init, 662 .instance_size = sizeof(PIIX4PMState), 663 .class_init = piix4_pm_class_init, 664 .interfaces = (InterfaceInfo[]) { 665 { TYPE_HOTPLUG_HANDLER }, 666 { TYPE_ACPI_DEVICE_IF }, 667 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 668 { } 669 } 670 }; 671 672 static void piix4_pm_register_types(void) 673 { 674 type_register_static(&piix4_pm_info); 675 } 676 677 type_init(piix4_pm_register_types) 678