xref: /openbmc/qemu/gdb-xml/aarch64-fpu.xml (revision 3dc7e2a3fedafc2f951bd62300b342c84e3606f8)
1*6a669427SPeter Maydell<?xml version="1.0"?>
2*6a669427SPeter Maydell<!-- Copyright (C) 2009-2012 Free Software Foundation, Inc.
3*6a669427SPeter Maydell     Contributed by ARM Ltd.
4*6a669427SPeter Maydell
5*6a669427SPeter Maydell     Copying and distribution of this file, with or without modification,
6*6a669427SPeter Maydell     are permitted in any medium without royalty provided the copyright
7*6a669427SPeter Maydell     notice and this notice are preserved.  -->
8*6a669427SPeter Maydell
9*6a669427SPeter Maydell<!DOCTYPE feature SYSTEM "gdb-target.dtd">
10*6a669427SPeter Maydell<feature name="org.gnu.gdb.aarch64.fpu">
11*6a669427SPeter Maydell  <vector id="v2d" type="ieee_double" count="2"/>
12*6a669427SPeter Maydell  <vector id="v2u" type="uint64" count="2"/>
13*6a669427SPeter Maydell  <vector id="v2i" type="int64" count="2"/>
14*6a669427SPeter Maydell  <vector id="v4f" type="ieee_single" count="4"/>
15*6a669427SPeter Maydell  <vector id="v4u" type="uint32" count="4"/>
16*6a669427SPeter Maydell  <vector id="v4i" type="int32" count="4"/>
17*6a669427SPeter Maydell  <vector id="v8u" type="uint16" count="8"/>
18*6a669427SPeter Maydell  <vector id="v8i" type="int16" count="8"/>
19*6a669427SPeter Maydell  <vector id="v16u" type="uint8" count="16"/>
20*6a669427SPeter Maydell  <vector id="v16i" type="int8" count="16"/>
21*6a669427SPeter Maydell  <vector id="v1u" type="uint128" count="1"/>
22*6a669427SPeter Maydell  <vector id="v1i" type="int128" count="1"/>
23*6a669427SPeter Maydell  <union id="vnd">
24*6a669427SPeter Maydell    <field name="f" type="v2d"/>
25*6a669427SPeter Maydell    <field name="u" type="v2u"/>
26*6a669427SPeter Maydell    <field name="s" type="v2i"/>
27*6a669427SPeter Maydell  </union>
28*6a669427SPeter Maydell  <union id="vns">
29*6a669427SPeter Maydell    <field name="f" type="v4f"/>
30*6a669427SPeter Maydell    <field name="u" type="v4u"/>
31*6a669427SPeter Maydell    <field name="s" type="v4i"/>
32*6a669427SPeter Maydell  </union>
33*6a669427SPeter Maydell  <union id="vnh">
34*6a669427SPeter Maydell    <field name="u" type="v8u"/>
35*6a669427SPeter Maydell    <field name="s" type="v8i"/>
36*6a669427SPeter Maydell  </union>
37*6a669427SPeter Maydell  <union id="vnb">
38*6a669427SPeter Maydell    <field name="u" type="v16u"/>
39*6a669427SPeter Maydell    <field name="s" type="v16i"/>
40*6a669427SPeter Maydell  </union>
41*6a669427SPeter Maydell  <union id="vnq">
42*6a669427SPeter Maydell    <field name="u" type="v1u"/>
43*6a669427SPeter Maydell    <field name="s" type="v1i"/>
44*6a669427SPeter Maydell  </union>
45*6a669427SPeter Maydell  <union id="aarch64v">
46*6a669427SPeter Maydell    <field name="d" type="vnd"/>
47*6a669427SPeter Maydell    <field name="s" type="vns"/>
48*6a669427SPeter Maydell    <field name="h" type="vnh"/>
49*6a669427SPeter Maydell    <field name="b" type="vnb"/>
50*6a669427SPeter Maydell    <field name="q" type="vnq"/>
51*6a669427SPeter Maydell  </union>
52*6a669427SPeter Maydell  <reg name="v0" bitsize="128" type="aarch64v" regnum="34"/>
53*6a669427SPeter Maydell  <reg name="v1" bitsize="128" type="aarch64v" />
54*6a669427SPeter Maydell  <reg name="v2" bitsize="128" type="aarch64v" />
55*6a669427SPeter Maydell  <reg name="v3" bitsize="128" type="aarch64v" />
56*6a669427SPeter Maydell  <reg name="v4" bitsize="128" type="aarch64v" />
57*6a669427SPeter Maydell  <reg name="v5" bitsize="128" type="aarch64v" />
58*6a669427SPeter Maydell  <reg name="v6" bitsize="128" type="aarch64v" />
59*6a669427SPeter Maydell  <reg name="v7" bitsize="128" type="aarch64v" />
60*6a669427SPeter Maydell  <reg name="v8" bitsize="128" type="aarch64v" />
61*6a669427SPeter Maydell  <reg name="v9" bitsize="128" type="aarch64v" />
62*6a669427SPeter Maydell  <reg name="v10" bitsize="128" type="aarch64v"/>
63*6a669427SPeter Maydell  <reg name="v11" bitsize="128" type="aarch64v"/>
64*6a669427SPeter Maydell  <reg name="v12" bitsize="128" type="aarch64v"/>
65*6a669427SPeter Maydell  <reg name="v13" bitsize="128" type="aarch64v"/>
66*6a669427SPeter Maydell  <reg name="v14" bitsize="128" type="aarch64v"/>
67*6a669427SPeter Maydell  <reg name="v15" bitsize="128" type="aarch64v"/>
68*6a669427SPeter Maydell  <reg name="v16" bitsize="128" type="aarch64v"/>
69*6a669427SPeter Maydell  <reg name="v17" bitsize="128" type="aarch64v"/>
70*6a669427SPeter Maydell  <reg name="v18" bitsize="128" type="aarch64v"/>
71*6a669427SPeter Maydell  <reg name="v19" bitsize="128" type="aarch64v"/>
72*6a669427SPeter Maydell  <reg name="v20" bitsize="128" type="aarch64v"/>
73*6a669427SPeter Maydell  <reg name="v21" bitsize="128" type="aarch64v"/>
74*6a669427SPeter Maydell  <reg name="v22" bitsize="128" type="aarch64v"/>
75*6a669427SPeter Maydell  <reg name="v23" bitsize="128" type="aarch64v"/>
76*6a669427SPeter Maydell  <reg name="v24" bitsize="128" type="aarch64v"/>
77*6a669427SPeter Maydell  <reg name="v25" bitsize="128" type="aarch64v"/>
78*6a669427SPeter Maydell  <reg name="v26" bitsize="128" type="aarch64v"/>
79*6a669427SPeter Maydell  <reg name="v27" bitsize="128" type="aarch64v"/>
80*6a669427SPeter Maydell  <reg name="v28" bitsize="128" type="aarch64v"/>
81*6a669427SPeter Maydell  <reg name="v29" bitsize="128" type="aarch64v"/>
82*6a669427SPeter Maydell  <reg name="v30" bitsize="128" type="aarch64v"/>
83*6a669427SPeter Maydell  <reg name="v31" bitsize="128" type="aarch64v"/>
84*6a669427SPeter Maydell  <reg name="fpsr" bitsize="32"/>
85*6a669427SPeter Maydell  <reg name="fpcr" bitsize="32"/>
86*6a669427SPeter Maydell</feature>
87