1*b14df228SStafford HorneCPU Features 2*b14df228SStafford Horne============ 3*b14df228SStafford Horne 4*b14df228SStafford HorneThe QEMU emulation of the OpenRISC architecture provides following built in 5*b14df228SStafford Hornefeatures. 6*b14df228SStafford Horne 7*b14df228SStafford Horne- Shadow GPRs 8*b14df228SStafford Horne- MMU TLB with 128 entries, 1 way 9*b14df228SStafford Horne- Power Management (PM) 10*b14df228SStafford Horne- Programmable Interrupt Controller (PIC) 11*b14df228SStafford Horne- Tick Timer 12*b14df228SStafford Horne 13*b14df228SStafford HorneThese features are on by default and the presence can be confirmed by checking 14*b14df228SStafford Hornethe contents of the Unit Presence Register (``UPR``) and CPU Configuration 15*b14df228SStafford HorneRegister (``CPUCFGR``). 16