xref: /openbmc/qemu/accel/tcg/tcg-all.c (revision 1583a389885346208217e8170395624b3aa90480)
1 /*
2  * QEMU System Emulator, accelerator interfaces
3  *
4  * Copyright (c) 2003-2008 Fabrice Bellard
5  * Copyright (c) 2014 Red Hat Inc.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy
8  * of this software and associated documentation files (the "Software"), to deal
9  * in the Software without restriction, including without limitation the rights
10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11  * copies of the Software, and to permit persons to whom the Software is
12  * furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in
15  * all copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23  * THE SOFTWARE.
24  */
25 
26 #include "qemu/osdep.h"
27 #include "qemu-common.h"
28 #include "sysemu/tcg.h"
29 #include "sysemu/cpu-timers.h"
30 #include "tcg/tcg.h"
31 #include "qapi/error.h"
32 #include "qemu/error-report.h"
33 #include "hw/boards.h"
34 #include "qapi/qapi-builtin-visit.h"
35 #include "tcg-cpus.h"
36 
37 struct TCGState {
38     AccelState parent_obj;
39 
40     bool mttcg_enabled;
41     unsigned long tb_size;
42 };
43 typedef struct TCGState TCGState;
44 
45 #define TYPE_TCG_ACCEL ACCEL_CLASS_NAME("tcg")
46 
47 DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE,
48                          TYPE_TCG_ACCEL)
49 
50 /* mask must never be zero, except for A20 change call */
51 static void tcg_handle_interrupt(CPUState *cpu, int mask)
52 {
53     int old_mask;
54     g_assert(qemu_mutex_iothread_locked());
55 
56     old_mask = cpu->interrupt_request;
57     cpu->interrupt_request |= mask;
58 
59     /*
60      * If called from iothread context, wake the target cpu in
61      * case its halted.
62      */
63     if (!qemu_cpu_is_self(cpu)) {
64         qemu_cpu_kick(cpu);
65     } else {
66         qatomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1);
67         if (icount_enabled() &&
68             !cpu->can_do_io
69             && (mask & ~old_mask) != 0) {
70             cpu_abort(cpu, "Raised interrupt while not in I/O function");
71         }
72     }
73 }
74 
75 /*
76  * We default to false if we know other options have been enabled
77  * which are currently incompatible with MTTCG. Otherwise when each
78  * guest (target) has been updated to support:
79  *   - atomic instructions
80  *   - memory ordering primitives (barriers)
81  * they can set the appropriate CONFIG flags in ${target}-softmmu.mak
82  *
83  * Once a guest architecture has been converted to the new primitives
84  * there are two remaining limitations to check.
85  *
86  * - The guest can't be oversized (e.g. 64 bit guest on 32 bit host)
87  * - The host must have a stronger memory order than the guest
88  *
89  * It may be possible in future to support strong guests on weak hosts
90  * but that will require tagging all load/stores in a guest with their
91  * implicit memory order requirements which would likely slow things
92  * down a lot.
93  */
94 
95 static bool check_tcg_memory_orders_compatible(void)
96 {
97 #if defined(TCG_GUEST_DEFAULT_MO) && defined(TCG_TARGET_DEFAULT_MO)
98     return (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO) == 0;
99 #else
100     return false;
101 #endif
102 }
103 
104 static bool default_mttcg_enabled(void)
105 {
106     if (icount_enabled() || TCG_OVERSIZED_GUEST) {
107         return false;
108     } else {
109 #ifdef TARGET_SUPPORTS_MTTCG
110         return check_tcg_memory_orders_compatible();
111 #else
112         return false;
113 #endif
114     }
115 }
116 
117 static void tcg_accel_instance_init(Object *obj)
118 {
119     TCGState *s = TCG_STATE(obj);
120 
121     s->mttcg_enabled = default_mttcg_enabled();
122 }
123 
124 bool mttcg_enabled;
125 
126 static int tcg_init(MachineState *ms)
127 {
128     TCGState *s = TCG_STATE(current_accel());
129 
130     tcg_exec_init(s->tb_size * 1024 * 1024);
131     cpu_interrupt_handler = tcg_handle_interrupt;
132     mttcg_enabled = s->mttcg_enabled;
133     cpus_register_accel(&tcg_cpus);
134 
135     return 0;
136 }
137 
138 static char *tcg_get_thread(Object *obj, Error **errp)
139 {
140     TCGState *s = TCG_STATE(obj);
141 
142     return g_strdup(s->mttcg_enabled ? "multi" : "single");
143 }
144 
145 static void tcg_set_thread(Object *obj, const char *value, Error **errp)
146 {
147     TCGState *s = TCG_STATE(obj);
148 
149     if (strcmp(value, "multi") == 0) {
150         if (TCG_OVERSIZED_GUEST) {
151             error_setg(errp, "No MTTCG when guest word size > hosts");
152         } else if (icount_enabled()) {
153             error_setg(errp, "No MTTCG when icount is enabled");
154         } else {
155 #ifndef TARGET_SUPPORTS_MTTCG
156             warn_report("Guest not yet converted to MTTCG - "
157                         "you may get unexpected results");
158 #endif
159             if (!check_tcg_memory_orders_compatible()) {
160                 warn_report("Guest expects a stronger memory ordering "
161                             "than the host provides");
162                 error_printf("This may cause strange/hard to debug errors\n");
163             }
164             s->mttcg_enabled = true;
165         }
166     } else if (strcmp(value, "single") == 0) {
167         s->mttcg_enabled = false;
168     } else {
169         error_setg(errp, "Invalid 'thread' setting %s", value);
170     }
171 }
172 
173 static void tcg_get_tb_size(Object *obj, Visitor *v,
174                             const char *name, void *opaque,
175                             Error **errp)
176 {
177     TCGState *s = TCG_STATE(obj);
178     uint32_t value = s->tb_size;
179 
180     visit_type_uint32(v, name, &value, errp);
181 }
182 
183 static void tcg_set_tb_size(Object *obj, Visitor *v,
184                             const char *name, void *opaque,
185                             Error **errp)
186 {
187     TCGState *s = TCG_STATE(obj);
188     uint32_t value;
189 
190     if (!visit_type_uint32(v, name, &value, errp)) {
191         return;
192     }
193 
194     s->tb_size = value;
195 }
196 
197 static void tcg_accel_class_init(ObjectClass *oc, void *data)
198 {
199     AccelClass *ac = ACCEL_CLASS(oc);
200     ac->name = "tcg";
201     ac->init_machine = tcg_init;
202     ac->allowed = &tcg_allowed;
203 
204     object_class_property_add_str(oc, "thread",
205                                   tcg_get_thread,
206                                   tcg_set_thread);
207 
208     object_class_property_add(oc, "tb-size", "int",
209         tcg_get_tb_size, tcg_set_tb_size,
210         NULL, NULL);
211     object_class_property_set_description(oc, "tb-size",
212         "TCG translation block cache size");
213 
214 }
215 
216 static const TypeInfo tcg_accel_type = {
217     .name = TYPE_TCG_ACCEL,
218     .parent = TYPE_ACCEL,
219     .instance_init = tcg_accel_instance_init,
220     .class_init = tcg_accel_class_init,
221     .instance_size = sizeof(TCGState),
222 };
223 
224 static void register_accel_types(void)
225 {
226     type_register_static(&tcg_accel_type);
227 }
228 
229 type_init(register_accel_types);
230