1 /* 2 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of version 2 of the GNU General Public License as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 11 * General Public License for more details. 12 */ 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 #include <linux/platform_device.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/workqueue.h> 17 #include <linux/libnvdimm.h> 18 #include <linux/vmalloc.h> 19 #include <linux/device.h> 20 #include <linux/module.h> 21 #include <linux/mutex.h> 22 #include <linux/ndctl.h> 23 #include <linux/sizes.h> 24 #include <linux/list.h> 25 #include <linux/slab.h> 26 #include <nd-core.h> 27 #include <nfit.h> 28 #include <nd.h> 29 #include "nfit_test.h" 30 #include "../watermark.h" 31 32 #include <asm/mcsafe_test.h> 33 34 /* 35 * Generate an NFIT table to describe the following topology: 36 * 37 * BUS0: Interleaved PMEM regions, and aliasing with BLK regions 38 * 39 * (a) (b) DIMM BLK-REGION 40 * +----------+--------------+----------+---------+ 41 * +------+ | blk2.0 | pm0.0 | blk2.1 | pm1.0 | 0 region2 42 * | imc0 +--+- - - - - region0 - - - -+----------+ + 43 * +--+---+ | blk3.0 | pm0.0 | blk3.1 | pm1.0 | 1 region3 44 * | +----------+--------------v----------v v 45 * +--+---+ | | 46 * | cpu0 | region1 47 * +--+---+ | | 48 * | +-------------------------^----------^ ^ 49 * +--+---+ | blk4.0 | pm1.0 | 2 region4 50 * | imc1 +--+-------------------------+----------+ + 51 * +------+ | blk5.0 | pm1.0 | 3 region5 52 * +-------------------------+----------+-+-------+ 53 * 54 * +--+---+ 55 * | cpu1 | 56 * +--+---+ (Hotplug DIMM) 57 * | +----------------------------------------------+ 58 * +--+---+ | blk6.0/pm7.0 | 4 region6/7 59 * | imc0 +--+----------------------------------------------+ 60 * +------+ 61 * 62 * 63 * *) In this layout we have four dimms and two memory controllers in one 64 * socket. Each unique interface (BLK or PMEM) to DPA space 65 * is identified by a region device with a dynamically assigned id. 66 * 67 * *) The first portion of dimm0 and dimm1 are interleaved as REGION0. 68 * A single PMEM namespace "pm0.0" is created using half of the 69 * REGION0 SPA-range. REGION0 spans dimm0 and dimm1. PMEM namespace 70 * allocate from from the bottom of a region. The unallocated 71 * portion of REGION0 aliases with REGION2 and REGION3. That 72 * unallacted capacity is reclaimed as BLK namespaces ("blk2.0" and 73 * "blk3.0") starting at the base of each DIMM to offset (a) in those 74 * DIMMs. "pm0.0", "blk2.0" and "blk3.0" are free-form readable 75 * names that can be assigned to a namespace. 76 * 77 * *) In the last portion of dimm0 and dimm1 we have an interleaved 78 * SPA range, REGION1, that spans those two dimms as well as dimm2 79 * and dimm3. Some of REGION1 allocated to a PMEM namespace named 80 * "pm1.0" the rest is reclaimed in 4 BLK namespaces (for each 81 * dimm in the interleave set), "blk2.1", "blk3.1", "blk4.0", and 82 * "blk5.0". 83 * 84 * *) The portion of dimm2 and dimm3 that do not participate in the 85 * REGION1 interleaved SPA range (i.e. the DPA address below offset 86 * (b) are also included in the "blk4.0" and "blk5.0" namespaces. 87 * Note, that BLK namespaces need not be contiguous in DPA-space, and 88 * can consume aliased capacity from multiple interleave sets. 89 * 90 * BUS1: Legacy NVDIMM (single contiguous range) 91 * 92 * region2 93 * +---------------------+ 94 * |---------------------| 95 * || pm2.0 || 96 * |---------------------| 97 * +---------------------+ 98 * 99 * *) A NFIT-table may describe a simple system-physical-address range 100 * with no BLK aliasing. This type of region may optionally 101 * reference an NVDIMM. 102 */ 103 enum { 104 NUM_PM = 3, 105 NUM_DCR = 5, 106 NUM_HINTS = 8, 107 NUM_BDW = NUM_DCR, 108 NUM_SPA = NUM_PM + NUM_DCR + NUM_BDW, 109 NUM_MEM = NUM_DCR + NUM_BDW + 2 /* spa0 iset */ 110 + 4 /* spa1 iset */ + 1 /* spa11 iset */, 111 DIMM_SIZE = SZ_32M, 112 LABEL_SIZE = SZ_128K, 113 SPA_VCD_SIZE = SZ_4M, 114 SPA0_SIZE = DIMM_SIZE, 115 SPA1_SIZE = DIMM_SIZE*2, 116 SPA2_SIZE = DIMM_SIZE, 117 BDW_SIZE = 64 << 8, 118 DCR_SIZE = 12, 119 NUM_NFITS = 2, /* permit testing multiple NFITs per system */ 120 }; 121 122 struct nfit_test_dcr { 123 __le64 bdw_addr; 124 __le32 bdw_status; 125 __u8 aperature[BDW_SIZE]; 126 }; 127 128 #define NFIT_DIMM_HANDLE(node, socket, imc, chan, dimm) \ 129 (((node & 0xfff) << 16) | ((socket & 0xf) << 12) \ 130 | ((imc & 0xf) << 8) | ((chan & 0xf) << 4) | (dimm & 0xf)) 131 132 static u32 handle[] = { 133 [0] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 0), 134 [1] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 1), 135 [2] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 0), 136 [3] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 1), 137 [4] = NFIT_DIMM_HANDLE(0, 1, 0, 0, 0), 138 [5] = NFIT_DIMM_HANDLE(1, 0, 0, 0, 0), 139 [6] = NFIT_DIMM_HANDLE(1, 0, 0, 0, 1), 140 }; 141 142 static unsigned long dimm_fail_cmd_flags[NUM_DCR]; 143 static int dimm_fail_cmd_code[NUM_DCR]; 144 145 struct nfit_test_fw { 146 enum intel_fw_update_state state; 147 u32 context; 148 u64 version; 149 u32 size_received; 150 u64 end_time; 151 }; 152 153 struct nfit_test { 154 struct acpi_nfit_desc acpi_desc; 155 struct platform_device pdev; 156 struct list_head resources; 157 void *nfit_buf; 158 dma_addr_t nfit_dma; 159 size_t nfit_size; 160 size_t nfit_filled; 161 int dcr_idx; 162 int num_dcr; 163 int num_pm; 164 void **dimm; 165 dma_addr_t *dimm_dma; 166 void **flush; 167 dma_addr_t *flush_dma; 168 void **label; 169 dma_addr_t *label_dma; 170 void **spa_set; 171 dma_addr_t *spa_set_dma; 172 struct nfit_test_dcr **dcr; 173 dma_addr_t *dcr_dma; 174 int (*alloc)(struct nfit_test *t); 175 void (*setup)(struct nfit_test *t); 176 int setup_hotplug; 177 union acpi_object **_fit; 178 dma_addr_t _fit_dma; 179 struct ars_state { 180 struct nd_cmd_ars_status *ars_status; 181 unsigned long deadline; 182 spinlock_t lock; 183 } ars_state; 184 struct device *dimm_dev[NUM_DCR]; 185 struct nd_intel_smart *smart; 186 struct nd_intel_smart_threshold *smart_threshold; 187 struct badrange badrange; 188 struct work_struct work; 189 struct nfit_test_fw *fw; 190 }; 191 192 static struct workqueue_struct *nfit_wq; 193 194 static struct nfit_test *to_nfit_test(struct device *dev) 195 { 196 struct platform_device *pdev = to_platform_device(dev); 197 198 return container_of(pdev, struct nfit_test, pdev); 199 } 200 201 static int nd_intel_test_get_fw_info(struct nfit_test *t, 202 struct nd_intel_fw_info *nd_cmd, unsigned int buf_len, 203 int idx) 204 { 205 struct device *dev = &t->pdev.dev; 206 struct nfit_test_fw *fw = &t->fw[idx]; 207 208 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p, buf_len: %u, idx: %d\n", 209 __func__, t, nd_cmd, buf_len, idx); 210 211 if (buf_len < sizeof(*nd_cmd)) 212 return -EINVAL; 213 214 nd_cmd->status = 0; 215 nd_cmd->storage_size = INTEL_FW_STORAGE_SIZE; 216 nd_cmd->max_send_len = INTEL_FW_MAX_SEND_LEN; 217 nd_cmd->query_interval = INTEL_FW_QUERY_INTERVAL; 218 nd_cmd->max_query_time = INTEL_FW_QUERY_MAX_TIME; 219 nd_cmd->update_cap = 0; 220 nd_cmd->fis_version = INTEL_FW_FIS_VERSION; 221 nd_cmd->run_version = 0; 222 nd_cmd->updated_version = fw->version; 223 224 return 0; 225 } 226 227 static int nd_intel_test_start_update(struct nfit_test *t, 228 struct nd_intel_fw_start *nd_cmd, unsigned int buf_len, 229 int idx) 230 { 231 struct device *dev = &t->pdev.dev; 232 struct nfit_test_fw *fw = &t->fw[idx]; 233 234 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n", 235 __func__, t, nd_cmd, buf_len, idx); 236 237 if (buf_len < sizeof(*nd_cmd)) 238 return -EINVAL; 239 240 if (fw->state != FW_STATE_NEW) { 241 /* extended status, FW update in progress */ 242 nd_cmd->status = 0x10007; 243 return 0; 244 } 245 246 fw->state = FW_STATE_IN_PROGRESS; 247 fw->context++; 248 fw->size_received = 0; 249 nd_cmd->status = 0; 250 nd_cmd->context = fw->context; 251 252 dev_dbg(dev, "%s: context issued: %#x\n", __func__, nd_cmd->context); 253 254 return 0; 255 } 256 257 static int nd_intel_test_send_data(struct nfit_test *t, 258 struct nd_intel_fw_send_data *nd_cmd, unsigned int buf_len, 259 int idx) 260 { 261 struct device *dev = &t->pdev.dev; 262 struct nfit_test_fw *fw = &t->fw[idx]; 263 u32 *status = (u32 *)&nd_cmd->data[nd_cmd->length]; 264 265 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n", 266 __func__, t, nd_cmd, buf_len, idx); 267 268 if (buf_len < sizeof(*nd_cmd)) 269 return -EINVAL; 270 271 272 dev_dbg(dev, "%s: cmd->status: %#x\n", __func__, *status); 273 dev_dbg(dev, "%s: cmd->data[0]: %#x\n", __func__, nd_cmd->data[0]); 274 dev_dbg(dev, "%s: cmd->data[%u]: %#x\n", __func__, nd_cmd->length-1, 275 nd_cmd->data[nd_cmd->length-1]); 276 277 if (fw->state != FW_STATE_IN_PROGRESS) { 278 dev_dbg(dev, "%s: not in IN_PROGRESS state\n", __func__); 279 *status = 0x5; 280 return 0; 281 } 282 283 if (nd_cmd->context != fw->context) { 284 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n", 285 __func__, nd_cmd->context, fw->context); 286 *status = 0x10007; 287 return 0; 288 } 289 290 /* 291 * check offset + len > size of fw storage 292 * check length is > max send length 293 */ 294 if (nd_cmd->offset + nd_cmd->length > INTEL_FW_STORAGE_SIZE || 295 nd_cmd->length > INTEL_FW_MAX_SEND_LEN) { 296 *status = 0x3; 297 dev_dbg(dev, "%s: buffer boundary violation\n", __func__); 298 return 0; 299 } 300 301 fw->size_received += nd_cmd->length; 302 dev_dbg(dev, "%s: copying %u bytes, %u bytes so far\n", 303 __func__, nd_cmd->length, fw->size_received); 304 *status = 0; 305 return 0; 306 } 307 308 static int nd_intel_test_finish_fw(struct nfit_test *t, 309 struct nd_intel_fw_finish_update *nd_cmd, 310 unsigned int buf_len, int idx) 311 { 312 struct device *dev = &t->pdev.dev; 313 struct nfit_test_fw *fw = &t->fw[idx]; 314 315 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n", 316 __func__, t, nd_cmd, buf_len, idx); 317 318 if (fw->state == FW_STATE_UPDATED) { 319 /* update already done, need cold boot */ 320 nd_cmd->status = 0x20007; 321 return 0; 322 } 323 324 dev_dbg(dev, "%s: context: %#x ctrl_flags: %#x\n", 325 __func__, nd_cmd->context, nd_cmd->ctrl_flags); 326 327 switch (nd_cmd->ctrl_flags) { 328 case 0: /* finish */ 329 if (nd_cmd->context != fw->context) { 330 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n", 331 __func__, nd_cmd->context, 332 fw->context); 333 nd_cmd->status = 0x10007; 334 return 0; 335 } 336 nd_cmd->status = 0; 337 fw->state = FW_STATE_VERIFY; 338 /* set 1 second of time for firmware "update" */ 339 fw->end_time = jiffies + HZ; 340 break; 341 342 case 1: /* abort */ 343 fw->size_received = 0; 344 /* successfully aborted status */ 345 nd_cmd->status = 0x40007; 346 fw->state = FW_STATE_NEW; 347 dev_dbg(dev, "%s: abort successful\n", __func__); 348 break; 349 350 default: /* bad control flag */ 351 dev_warn(dev, "%s: unknown control flag: %#x\n", 352 __func__, nd_cmd->ctrl_flags); 353 return -EINVAL; 354 } 355 356 return 0; 357 } 358 359 static int nd_intel_test_finish_query(struct nfit_test *t, 360 struct nd_intel_fw_finish_query *nd_cmd, 361 unsigned int buf_len, int idx) 362 { 363 struct device *dev = &t->pdev.dev; 364 struct nfit_test_fw *fw = &t->fw[idx]; 365 366 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n", 367 __func__, t, nd_cmd, buf_len, idx); 368 369 if (buf_len < sizeof(*nd_cmd)) 370 return -EINVAL; 371 372 if (nd_cmd->context != fw->context) { 373 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n", 374 __func__, nd_cmd->context, fw->context); 375 nd_cmd->status = 0x10007; 376 return 0; 377 } 378 379 dev_dbg(dev, "%s context: %#x\n", __func__, nd_cmd->context); 380 381 switch (fw->state) { 382 case FW_STATE_NEW: 383 nd_cmd->updated_fw_rev = 0; 384 nd_cmd->status = 0; 385 dev_dbg(dev, "%s: new state\n", __func__); 386 break; 387 388 case FW_STATE_IN_PROGRESS: 389 /* sequencing error */ 390 nd_cmd->status = 0x40007; 391 nd_cmd->updated_fw_rev = 0; 392 dev_dbg(dev, "%s: sequence error\n", __func__); 393 break; 394 395 case FW_STATE_VERIFY: 396 if (time_is_after_jiffies64(fw->end_time)) { 397 nd_cmd->updated_fw_rev = 0; 398 nd_cmd->status = 0x20007; 399 dev_dbg(dev, "%s: still verifying\n", __func__); 400 break; 401 } 402 403 dev_dbg(dev, "%s: transition out verify\n", __func__); 404 fw->state = FW_STATE_UPDATED; 405 /* we are going to fall through if it's "done" */ 406 case FW_STATE_UPDATED: 407 nd_cmd->status = 0; 408 /* bogus test version */ 409 fw->version = nd_cmd->updated_fw_rev = 410 INTEL_FW_FAKE_VERSION; 411 dev_dbg(dev, "%s: updated\n", __func__); 412 break; 413 414 default: /* we should never get here */ 415 return -EINVAL; 416 } 417 418 return 0; 419 } 420 421 static int nfit_test_cmd_get_config_size(struct nd_cmd_get_config_size *nd_cmd, 422 unsigned int buf_len) 423 { 424 if (buf_len < sizeof(*nd_cmd)) 425 return -EINVAL; 426 427 nd_cmd->status = 0; 428 nd_cmd->config_size = LABEL_SIZE; 429 nd_cmd->max_xfer = SZ_4K; 430 431 return 0; 432 } 433 434 static int nfit_test_cmd_get_config_data(struct nd_cmd_get_config_data_hdr 435 *nd_cmd, unsigned int buf_len, void *label) 436 { 437 unsigned int len, offset = nd_cmd->in_offset; 438 int rc; 439 440 if (buf_len < sizeof(*nd_cmd)) 441 return -EINVAL; 442 if (offset >= LABEL_SIZE) 443 return -EINVAL; 444 if (nd_cmd->in_length + sizeof(*nd_cmd) > buf_len) 445 return -EINVAL; 446 447 nd_cmd->status = 0; 448 len = min(nd_cmd->in_length, LABEL_SIZE - offset); 449 memcpy(nd_cmd->out_buf, label + offset, len); 450 rc = buf_len - sizeof(*nd_cmd) - len; 451 452 return rc; 453 } 454 455 static int nfit_test_cmd_set_config_data(struct nd_cmd_set_config_hdr *nd_cmd, 456 unsigned int buf_len, void *label) 457 { 458 unsigned int len, offset = nd_cmd->in_offset; 459 u32 *status; 460 int rc; 461 462 if (buf_len < sizeof(*nd_cmd)) 463 return -EINVAL; 464 if (offset >= LABEL_SIZE) 465 return -EINVAL; 466 if (nd_cmd->in_length + sizeof(*nd_cmd) + 4 > buf_len) 467 return -EINVAL; 468 469 status = (void *)nd_cmd + nd_cmd->in_length + sizeof(*nd_cmd); 470 *status = 0; 471 len = min(nd_cmd->in_length, LABEL_SIZE - offset); 472 memcpy(label + offset, nd_cmd->in_buf, len); 473 rc = buf_len - sizeof(*nd_cmd) - (len + 4); 474 475 return rc; 476 } 477 478 #define NFIT_TEST_CLEAR_ERR_UNIT 256 479 480 static int nfit_test_cmd_ars_cap(struct nd_cmd_ars_cap *nd_cmd, 481 unsigned int buf_len) 482 { 483 int ars_recs; 484 485 if (buf_len < sizeof(*nd_cmd)) 486 return -EINVAL; 487 488 /* for testing, only store up to n records that fit within 4k */ 489 ars_recs = SZ_4K / sizeof(struct nd_ars_record); 490 491 nd_cmd->max_ars_out = sizeof(struct nd_cmd_ars_status) 492 + ars_recs * sizeof(struct nd_ars_record); 493 nd_cmd->status = (ND_ARS_PERSISTENT | ND_ARS_VOLATILE) << 16; 494 nd_cmd->clear_err_unit = NFIT_TEST_CLEAR_ERR_UNIT; 495 496 return 0; 497 } 498 499 static void post_ars_status(struct ars_state *ars_state, 500 struct badrange *badrange, u64 addr, u64 len) 501 { 502 struct nd_cmd_ars_status *ars_status; 503 struct nd_ars_record *ars_record; 504 struct badrange_entry *be; 505 u64 end = addr + len - 1; 506 int i = 0; 507 508 ars_state->deadline = jiffies + 1*HZ; 509 ars_status = ars_state->ars_status; 510 ars_status->status = 0; 511 ars_status->address = addr; 512 ars_status->length = len; 513 ars_status->type = ND_ARS_PERSISTENT; 514 515 spin_lock(&badrange->lock); 516 list_for_each_entry(be, &badrange->list, list) { 517 u64 be_end = be->start + be->length - 1; 518 u64 rstart, rend; 519 520 /* skip entries outside the range */ 521 if (be_end < addr || be->start > end) 522 continue; 523 524 rstart = (be->start < addr) ? addr : be->start; 525 rend = (be_end < end) ? be_end : end; 526 ars_record = &ars_status->records[i]; 527 ars_record->handle = 0; 528 ars_record->err_address = rstart; 529 ars_record->length = rend - rstart + 1; 530 i++; 531 } 532 spin_unlock(&badrange->lock); 533 ars_status->num_records = i; 534 ars_status->out_length = sizeof(struct nd_cmd_ars_status) 535 + i * sizeof(struct nd_ars_record); 536 } 537 538 static int nfit_test_cmd_ars_start(struct nfit_test *t, 539 struct ars_state *ars_state, 540 struct nd_cmd_ars_start *ars_start, unsigned int buf_len, 541 int *cmd_rc) 542 { 543 if (buf_len < sizeof(*ars_start)) 544 return -EINVAL; 545 546 spin_lock(&ars_state->lock); 547 if (time_before(jiffies, ars_state->deadline)) { 548 ars_start->status = NFIT_ARS_START_BUSY; 549 *cmd_rc = -EBUSY; 550 } else { 551 ars_start->status = 0; 552 ars_start->scrub_time = 1; 553 post_ars_status(ars_state, &t->badrange, ars_start->address, 554 ars_start->length); 555 *cmd_rc = 0; 556 } 557 spin_unlock(&ars_state->lock); 558 559 return 0; 560 } 561 562 static int nfit_test_cmd_ars_status(struct ars_state *ars_state, 563 struct nd_cmd_ars_status *ars_status, unsigned int buf_len, 564 int *cmd_rc) 565 { 566 if (buf_len < ars_state->ars_status->out_length) 567 return -EINVAL; 568 569 spin_lock(&ars_state->lock); 570 if (time_before(jiffies, ars_state->deadline)) { 571 memset(ars_status, 0, buf_len); 572 ars_status->status = NFIT_ARS_STATUS_BUSY; 573 ars_status->out_length = sizeof(*ars_status); 574 *cmd_rc = -EBUSY; 575 } else { 576 memcpy(ars_status, ars_state->ars_status, 577 ars_state->ars_status->out_length); 578 *cmd_rc = 0; 579 } 580 spin_unlock(&ars_state->lock); 581 return 0; 582 } 583 584 static int nfit_test_cmd_clear_error(struct nfit_test *t, 585 struct nd_cmd_clear_error *clear_err, 586 unsigned int buf_len, int *cmd_rc) 587 { 588 const u64 mask = NFIT_TEST_CLEAR_ERR_UNIT - 1; 589 if (buf_len < sizeof(*clear_err)) 590 return -EINVAL; 591 592 if ((clear_err->address & mask) || (clear_err->length & mask)) 593 return -EINVAL; 594 595 badrange_forget(&t->badrange, clear_err->address, clear_err->length); 596 clear_err->status = 0; 597 clear_err->cleared = clear_err->length; 598 *cmd_rc = 0; 599 return 0; 600 } 601 602 struct region_search_spa { 603 u64 addr; 604 struct nd_region *region; 605 }; 606 607 static int is_region_device(struct device *dev) 608 { 609 return !strncmp(dev->kobj.name, "region", 6); 610 } 611 612 static int nfit_test_search_region_spa(struct device *dev, void *data) 613 { 614 struct region_search_spa *ctx = data; 615 struct nd_region *nd_region; 616 resource_size_t ndr_end; 617 618 if (!is_region_device(dev)) 619 return 0; 620 621 nd_region = to_nd_region(dev); 622 ndr_end = nd_region->ndr_start + nd_region->ndr_size; 623 624 if (ctx->addr >= nd_region->ndr_start && ctx->addr < ndr_end) { 625 ctx->region = nd_region; 626 return 1; 627 } 628 629 return 0; 630 } 631 632 static int nfit_test_search_spa(struct nvdimm_bus *bus, 633 struct nd_cmd_translate_spa *spa) 634 { 635 int ret; 636 struct nd_region *nd_region = NULL; 637 struct nvdimm *nvdimm = NULL; 638 struct nd_mapping *nd_mapping = NULL; 639 struct region_search_spa ctx = { 640 .addr = spa->spa, 641 .region = NULL, 642 }; 643 u64 dpa; 644 645 ret = device_for_each_child(&bus->dev, &ctx, 646 nfit_test_search_region_spa); 647 648 if (!ret) 649 return -ENODEV; 650 651 nd_region = ctx.region; 652 653 dpa = ctx.addr - nd_region->ndr_start; 654 655 /* 656 * last dimm is selected for test 657 */ 658 nd_mapping = &nd_region->mapping[nd_region->ndr_mappings - 1]; 659 nvdimm = nd_mapping->nvdimm; 660 661 spa->devices[0].nfit_device_handle = handle[nvdimm->id]; 662 spa->num_nvdimms = 1; 663 spa->devices[0].dpa = dpa; 664 665 return 0; 666 } 667 668 static int nfit_test_cmd_translate_spa(struct nvdimm_bus *bus, 669 struct nd_cmd_translate_spa *spa, unsigned int buf_len) 670 { 671 if (buf_len < spa->translate_length) 672 return -EINVAL; 673 674 if (nfit_test_search_spa(bus, spa) < 0 || !spa->num_nvdimms) 675 spa->status = 2; 676 677 return 0; 678 } 679 680 static int nfit_test_cmd_smart(struct nd_intel_smart *smart, unsigned int buf_len, 681 struct nd_intel_smart *smart_data) 682 { 683 if (buf_len < sizeof(*smart)) 684 return -EINVAL; 685 memcpy(smart, smart_data, sizeof(*smart)); 686 return 0; 687 } 688 689 static int nfit_test_cmd_smart_threshold( 690 struct nd_intel_smart_threshold *out, 691 unsigned int buf_len, 692 struct nd_intel_smart_threshold *smart_t) 693 { 694 if (buf_len < sizeof(*smart_t)) 695 return -EINVAL; 696 memcpy(out, smart_t, sizeof(*smart_t)); 697 return 0; 698 } 699 700 static void smart_notify(struct device *bus_dev, 701 struct device *dimm_dev, struct nd_intel_smart *smart, 702 struct nd_intel_smart_threshold *thresh) 703 { 704 dev_dbg(dimm_dev, "%s: alarm: %#x spares: %d (%d) mtemp: %d (%d) ctemp: %d (%d)\n", 705 __func__, thresh->alarm_control, thresh->spares, 706 smart->spares, thresh->media_temperature, 707 smart->media_temperature, thresh->ctrl_temperature, 708 smart->ctrl_temperature); 709 if (((thresh->alarm_control & ND_INTEL_SMART_SPARE_TRIP) 710 && smart->spares 711 <= thresh->spares) 712 || ((thresh->alarm_control & ND_INTEL_SMART_TEMP_TRIP) 713 && smart->media_temperature 714 >= thresh->media_temperature) 715 || ((thresh->alarm_control & ND_INTEL_SMART_CTEMP_TRIP) 716 && smart->ctrl_temperature 717 >= thresh->ctrl_temperature) 718 || (smart->health != ND_INTEL_SMART_NON_CRITICAL_HEALTH) 719 || (smart->shutdown_state != 0)) { 720 device_lock(bus_dev); 721 __acpi_nvdimm_notify(dimm_dev, 0x81); 722 device_unlock(bus_dev); 723 } 724 } 725 726 static int nfit_test_cmd_smart_set_threshold( 727 struct nd_intel_smart_set_threshold *in, 728 unsigned int buf_len, 729 struct nd_intel_smart_threshold *thresh, 730 struct nd_intel_smart *smart, 731 struct device *bus_dev, struct device *dimm_dev) 732 { 733 unsigned int size; 734 735 size = sizeof(*in) - 4; 736 if (buf_len < size) 737 return -EINVAL; 738 memcpy(thresh->data, in, size); 739 in->status = 0; 740 smart_notify(bus_dev, dimm_dev, smart, thresh); 741 742 return 0; 743 } 744 745 static int nfit_test_cmd_smart_inject( 746 struct nd_intel_smart_inject *inj, 747 unsigned int buf_len, 748 struct nd_intel_smart_threshold *thresh, 749 struct nd_intel_smart *smart, 750 struct device *bus_dev, struct device *dimm_dev) 751 { 752 if (buf_len != sizeof(*inj)) 753 return -EINVAL; 754 755 if (inj->mtemp_enable) 756 smart->media_temperature = inj->media_temperature; 757 if (inj->spare_enable) 758 smart->spares = inj->spares; 759 if (inj->fatal_enable) 760 smart->health = ND_INTEL_SMART_FATAL_HEALTH; 761 if (inj->unsafe_shutdown_enable) { 762 smart->shutdown_state = 1; 763 smart->shutdown_count++; 764 } 765 inj->status = 0; 766 smart_notify(bus_dev, dimm_dev, smart, thresh); 767 768 return 0; 769 } 770 771 static void uc_error_notify(struct work_struct *work) 772 { 773 struct nfit_test *t = container_of(work, typeof(*t), work); 774 775 __acpi_nfit_notify(&t->pdev.dev, t, NFIT_NOTIFY_UC_MEMORY_ERROR); 776 } 777 778 static int nfit_test_cmd_ars_error_inject(struct nfit_test *t, 779 struct nd_cmd_ars_err_inj *err_inj, unsigned int buf_len) 780 { 781 int rc; 782 783 if (buf_len != sizeof(*err_inj)) { 784 rc = -EINVAL; 785 goto err; 786 } 787 788 if (err_inj->err_inj_spa_range_length <= 0) { 789 rc = -EINVAL; 790 goto err; 791 } 792 793 rc = badrange_add(&t->badrange, err_inj->err_inj_spa_range_base, 794 err_inj->err_inj_spa_range_length); 795 if (rc < 0) 796 goto err; 797 798 if (err_inj->err_inj_options & (1 << ND_ARS_ERR_INJ_OPT_NOTIFY)) 799 queue_work(nfit_wq, &t->work); 800 801 err_inj->status = 0; 802 return 0; 803 804 err: 805 err_inj->status = NFIT_ARS_INJECT_INVALID; 806 return rc; 807 } 808 809 static int nfit_test_cmd_ars_inject_clear(struct nfit_test *t, 810 struct nd_cmd_ars_err_inj_clr *err_clr, unsigned int buf_len) 811 { 812 int rc; 813 814 if (buf_len != sizeof(*err_clr)) { 815 rc = -EINVAL; 816 goto err; 817 } 818 819 if (err_clr->err_inj_clr_spa_range_length <= 0) { 820 rc = -EINVAL; 821 goto err; 822 } 823 824 badrange_forget(&t->badrange, err_clr->err_inj_clr_spa_range_base, 825 err_clr->err_inj_clr_spa_range_length); 826 827 err_clr->status = 0; 828 return 0; 829 830 err: 831 err_clr->status = NFIT_ARS_INJECT_INVALID; 832 return rc; 833 } 834 835 static int nfit_test_cmd_ars_inject_status(struct nfit_test *t, 836 struct nd_cmd_ars_err_inj_stat *err_stat, 837 unsigned int buf_len) 838 { 839 struct badrange_entry *be; 840 int max = SZ_4K / sizeof(struct nd_error_stat_query_record); 841 int i = 0; 842 843 err_stat->status = 0; 844 spin_lock(&t->badrange.lock); 845 list_for_each_entry(be, &t->badrange.list, list) { 846 err_stat->record[i].err_inj_stat_spa_range_base = be->start; 847 err_stat->record[i].err_inj_stat_spa_range_length = be->length; 848 i++; 849 if (i > max) 850 break; 851 } 852 spin_unlock(&t->badrange.lock); 853 err_stat->inj_err_rec_count = i; 854 855 return 0; 856 } 857 858 static int nd_intel_test_cmd_set_lss_status(struct nfit_test *t, 859 struct nd_intel_lss *nd_cmd, unsigned int buf_len) 860 { 861 struct device *dev = &t->pdev.dev; 862 863 if (buf_len < sizeof(*nd_cmd)) 864 return -EINVAL; 865 866 switch (nd_cmd->enable) { 867 case 0: 868 nd_cmd->status = 0; 869 dev_dbg(dev, "%s: Latch System Shutdown Status disabled\n", 870 __func__); 871 break; 872 case 1: 873 nd_cmd->status = 0; 874 dev_dbg(dev, "%s: Latch System Shutdown Status enabled\n", 875 __func__); 876 break; 877 default: 878 dev_warn(dev, "Unknown enable value: %#x\n", nd_cmd->enable); 879 nd_cmd->status = 0x3; 880 break; 881 } 882 883 884 return 0; 885 } 886 887 static int override_return_code(int dimm, unsigned int func, int rc) 888 { 889 if ((1 << func) & dimm_fail_cmd_flags[dimm]) { 890 if (dimm_fail_cmd_code[dimm]) 891 return dimm_fail_cmd_code[dimm]; 892 return -EIO; 893 } 894 return rc; 895 } 896 897 static int get_dimm(struct nfit_mem *nfit_mem, unsigned int func) 898 { 899 int i; 900 901 /* lookup per-dimm data */ 902 for (i = 0; i < ARRAY_SIZE(handle); i++) 903 if (__to_nfit_memdev(nfit_mem)->device_handle == handle[i]) 904 break; 905 if (i >= ARRAY_SIZE(handle)) 906 return -ENXIO; 907 return i; 908 } 909 910 static int nfit_test_ctl(struct nvdimm_bus_descriptor *nd_desc, 911 struct nvdimm *nvdimm, unsigned int cmd, void *buf, 912 unsigned int buf_len, int *cmd_rc) 913 { 914 struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc); 915 struct nfit_test *t = container_of(acpi_desc, typeof(*t), acpi_desc); 916 unsigned int func = cmd; 917 int i, rc = 0, __cmd_rc; 918 919 if (!cmd_rc) 920 cmd_rc = &__cmd_rc; 921 *cmd_rc = 0; 922 923 if (nvdimm) { 924 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); 925 unsigned long cmd_mask = nvdimm_cmd_mask(nvdimm); 926 927 if (!nfit_mem) 928 return -ENOTTY; 929 930 if (cmd == ND_CMD_CALL) { 931 struct nd_cmd_pkg *call_pkg = buf; 932 933 buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out; 934 buf = (void *) call_pkg->nd_payload; 935 func = call_pkg->nd_command; 936 if (call_pkg->nd_family != nfit_mem->family) 937 return -ENOTTY; 938 939 i = get_dimm(nfit_mem, func); 940 if (i < 0) 941 return i; 942 943 switch (func) { 944 case ND_INTEL_ENABLE_LSS_STATUS: 945 rc = nd_intel_test_cmd_set_lss_status(t, 946 buf, buf_len); 947 break; 948 case ND_INTEL_FW_GET_INFO: 949 rc = nd_intel_test_get_fw_info(t, buf, 950 buf_len, i - t->dcr_idx); 951 break; 952 case ND_INTEL_FW_START_UPDATE: 953 rc = nd_intel_test_start_update(t, buf, 954 buf_len, i - t->dcr_idx); 955 break; 956 case ND_INTEL_FW_SEND_DATA: 957 rc = nd_intel_test_send_data(t, buf, 958 buf_len, i - t->dcr_idx); 959 break; 960 case ND_INTEL_FW_FINISH_UPDATE: 961 rc = nd_intel_test_finish_fw(t, buf, 962 buf_len, i - t->dcr_idx); 963 break; 964 case ND_INTEL_FW_FINISH_QUERY: 965 rc = nd_intel_test_finish_query(t, buf, 966 buf_len, i - t->dcr_idx); 967 break; 968 case ND_INTEL_SMART: 969 rc = nfit_test_cmd_smart(buf, buf_len, 970 &t->smart[i - t->dcr_idx]); 971 break; 972 case ND_INTEL_SMART_THRESHOLD: 973 rc = nfit_test_cmd_smart_threshold(buf, 974 buf_len, 975 &t->smart_threshold[i - 976 t->dcr_idx]); 977 break; 978 case ND_INTEL_SMART_SET_THRESHOLD: 979 rc = nfit_test_cmd_smart_set_threshold(buf, 980 buf_len, 981 &t->smart_threshold[i - 982 t->dcr_idx], 983 &t->smart[i - t->dcr_idx], 984 &t->pdev.dev, t->dimm_dev[i]); 985 break; 986 case ND_INTEL_SMART_INJECT: 987 rc = nfit_test_cmd_smart_inject(buf, 988 buf_len, 989 &t->smart_threshold[i - 990 t->dcr_idx], 991 &t->smart[i - t->dcr_idx], 992 &t->pdev.dev, t->dimm_dev[i]); 993 break; 994 default: 995 return -ENOTTY; 996 } 997 return override_return_code(i, func, rc); 998 } 999 1000 if (!test_bit(cmd, &cmd_mask) 1001 || !test_bit(func, &nfit_mem->dsm_mask)) 1002 return -ENOTTY; 1003 1004 i = get_dimm(nfit_mem, func); 1005 if (i < 0) 1006 return i; 1007 1008 switch (func) { 1009 case ND_CMD_GET_CONFIG_SIZE: 1010 rc = nfit_test_cmd_get_config_size(buf, buf_len); 1011 break; 1012 case ND_CMD_GET_CONFIG_DATA: 1013 rc = nfit_test_cmd_get_config_data(buf, buf_len, 1014 t->label[i - t->dcr_idx]); 1015 break; 1016 case ND_CMD_SET_CONFIG_DATA: 1017 rc = nfit_test_cmd_set_config_data(buf, buf_len, 1018 t->label[i - t->dcr_idx]); 1019 break; 1020 default: 1021 return -ENOTTY; 1022 } 1023 return override_return_code(i, func, rc); 1024 } else { 1025 struct ars_state *ars_state = &t->ars_state; 1026 struct nd_cmd_pkg *call_pkg = buf; 1027 1028 if (!nd_desc) 1029 return -ENOTTY; 1030 1031 if (cmd == ND_CMD_CALL) { 1032 func = call_pkg->nd_command; 1033 1034 buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out; 1035 buf = (void *) call_pkg->nd_payload; 1036 1037 switch (func) { 1038 case NFIT_CMD_TRANSLATE_SPA: 1039 rc = nfit_test_cmd_translate_spa( 1040 acpi_desc->nvdimm_bus, buf, buf_len); 1041 return rc; 1042 case NFIT_CMD_ARS_INJECT_SET: 1043 rc = nfit_test_cmd_ars_error_inject(t, buf, 1044 buf_len); 1045 return rc; 1046 case NFIT_CMD_ARS_INJECT_CLEAR: 1047 rc = nfit_test_cmd_ars_inject_clear(t, buf, 1048 buf_len); 1049 return rc; 1050 case NFIT_CMD_ARS_INJECT_GET: 1051 rc = nfit_test_cmd_ars_inject_status(t, buf, 1052 buf_len); 1053 return rc; 1054 default: 1055 return -ENOTTY; 1056 } 1057 } 1058 1059 if (!nd_desc || !test_bit(cmd, &nd_desc->cmd_mask)) 1060 return -ENOTTY; 1061 1062 switch (func) { 1063 case ND_CMD_ARS_CAP: 1064 rc = nfit_test_cmd_ars_cap(buf, buf_len); 1065 break; 1066 case ND_CMD_ARS_START: 1067 rc = nfit_test_cmd_ars_start(t, ars_state, buf, 1068 buf_len, cmd_rc); 1069 break; 1070 case ND_CMD_ARS_STATUS: 1071 rc = nfit_test_cmd_ars_status(ars_state, buf, buf_len, 1072 cmd_rc); 1073 break; 1074 case ND_CMD_CLEAR_ERROR: 1075 rc = nfit_test_cmd_clear_error(t, buf, buf_len, cmd_rc); 1076 break; 1077 default: 1078 return -ENOTTY; 1079 } 1080 } 1081 1082 return rc; 1083 } 1084 1085 static DEFINE_SPINLOCK(nfit_test_lock); 1086 static struct nfit_test *instances[NUM_NFITS]; 1087 1088 static void release_nfit_res(void *data) 1089 { 1090 struct nfit_test_resource *nfit_res = data; 1091 1092 spin_lock(&nfit_test_lock); 1093 list_del(&nfit_res->list); 1094 spin_unlock(&nfit_test_lock); 1095 1096 vfree(nfit_res->buf); 1097 kfree(nfit_res); 1098 } 1099 1100 static void *__test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma, 1101 void *buf) 1102 { 1103 struct device *dev = &t->pdev.dev; 1104 struct nfit_test_resource *nfit_res = kzalloc(sizeof(*nfit_res), 1105 GFP_KERNEL); 1106 int rc; 1107 1108 if (!buf || !nfit_res) 1109 goto err; 1110 rc = devm_add_action(dev, release_nfit_res, nfit_res); 1111 if (rc) 1112 goto err; 1113 INIT_LIST_HEAD(&nfit_res->list); 1114 memset(buf, 0, size); 1115 nfit_res->dev = dev; 1116 nfit_res->buf = buf; 1117 nfit_res->res.start = *dma; 1118 nfit_res->res.end = *dma + size - 1; 1119 nfit_res->res.name = "NFIT"; 1120 spin_lock_init(&nfit_res->lock); 1121 INIT_LIST_HEAD(&nfit_res->requests); 1122 spin_lock(&nfit_test_lock); 1123 list_add(&nfit_res->list, &t->resources); 1124 spin_unlock(&nfit_test_lock); 1125 1126 return nfit_res->buf; 1127 err: 1128 if (buf) 1129 vfree(buf); 1130 kfree(nfit_res); 1131 return NULL; 1132 } 1133 1134 static void *test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma) 1135 { 1136 void *buf = vmalloc(size); 1137 1138 *dma = (unsigned long) buf; 1139 return __test_alloc(t, size, dma, buf); 1140 } 1141 1142 static struct nfit_test_resource *nfit_test_lookup(resource_size_t addr) 1143 { 1144 int i; 1145 1146 for (i = 0; i < ARRAY_SIZE(instances); i++) { 1147 struct nfit_test_resource *n, *nfit_res = NULL; 1148 struct nfit_test *t = instances[i]; 1149 1150 if (!t) 1151 continue; 1152 spin_lock(&nfit_test_lock); 1153 list_for_each_entry(n, &t->resources, list) { 1154 if (addr >= n->res.start && (addr < n->res.start 1155 + resource_size(&n->res))) { 1156 nfit_res = n; 1157 break; 1158 } else if (addr >= (unsigned long) n->buf 1159 && (addr < (unsigned long) n->buf 1160 + resource_size(&n->res))) { 1161 nfit_res = n; 1162 break; 1163 } 1164 } 1165 spin_unlock(&nfit_test_lock); 1166 if (nfit_res) 1167 return nfit_res; 1168 } 1169 1170 return NULL; 1171 } 1172 1173 static int ars_state_init(struct device *dev, struct ars_state *ars_state) 1174 { 1175 /* for testing, only store up to n records that fit within 4k */ 1176 ars_state->ars_status = devm_kzalloc(dev, 1177 sizeof(struct nd_cmd_ars_status) + SZ_4K, GFP_KERNEL); 1178 if (!ars_state->ars_status) 1179 return -ENOMEM; 1180 spin_lock_init(&ars_state->lock); 1181 return 0; 1182 } 1183 1184 static void put_dimms(void *data) 1185 { 1186 struct nfit_test *t = data; 1187 int i; 1188 1189 for (i = 0; i < t->num_dcr; i++) 1190 if (t->dimm_dev[i]) 1191 device_unregister(t->dimm_dev[i]); 1192 } 1193 1194 static struct class *nfit_test_dimm; 1195 1196 static int dimm_name_to_id(struct device *dev) 1197 { 1198 int dimm; 1199 1200 if (sscanf(dev_name(dev), "test_dimm%d", &dimm) != 1) 1201 return -ENXIO; 1202 return dimm; 1203 } 1204 1205 static ssize_t handle_show(struct device *dev, struct device_attribute *attr, 1206 char *buf) 1207 { 1208 int dimm = dimm_name_to_id(dev); 1209 1210 if (dimm < 0) 1211 return dimm; 1212 1213 return sprintf(buf, "%#x\n", handle[dimm]); 1214 } 1215 DEVICE_ATTR_RO(handle); 1216 1217 static ssize_t fail_cmd_show(struct device *dev, struct device_attribute *attr, 1218 char *buf) 1219 { 1220 int dimm = dimm_name_to_id(dev); 1221 1222 if (dimm < 0) 1223 return dimm; 1224 1225 return sprintf(buf, "%#lx\n", dimm_fail_cmd_flags[dimm]); 1226 } 1227 1228 static ssize_t fail_cmd_store(struct device *dev, struct device_attribute *attr, 1229 const char *buf, size_t size) 1230 { 1231 int dimm = dimm_name_to_id(dev); 1232 unsigned long val; 1233 ssize_t rc; 1234 1235 if (dimm < 0) 1236 return dimm; 1237 1238 rc = kstrtol(buf, 0, &val); 1239 if (rc) 1240 return rc; 1241 1242 dimm_fail_cmd_flags[dimm] = val; 1243 return size; 1244 } 1245 static DEVICE_ATTR_RW(fail_cmd); 1246 1247 static ssize_t fail_cmd_code_show(struct device *dev, struct device_attribute *attr, 1248 char *buf) 1249 { 1250 int dimm = dimm_name_to_id(dev); 1251 1252 if (dimm < 0) 1253 return dimm; 1254 1255 return sprintf(buf, "%d\n", dimm_fail_cmd_code[dimm]); 1256 } 1257 1258 static ssize_t fail_cmd_code_store(struct device *dev, struct device_attribute *attr, 1259 const char *buf, size_t size) 1260 { 1261 int dimm = dimm_name_to_id(dev); 1262 unsigned long val; 1263 ssize_t rc; 1264 1265 if (dimm < 0) 1266 return dimm; 1267 1268 rc = kstrtol(buf, 0, &val); 1269 if (rc) 1270 return rc; 1271 1272 dimm_fail_cmd_code[dimm] = val; 1273 return size; 1274 } 1275 static DEVICE_ATTR_RW(fail_cmd_code); 1276 1277 static struct attribute *nfit_test_dimm_attributes[] = { 1278 &dev_attr_fail_cmd.attr, 1279 &dev_attr_fail_cmd_code.attr, 1280 &dev_attr_handle.attr, 1281 NULL, 1282 }; 1283 1284 static struct attribute_group nfit_test_dimm_attribute_group = { 1285 .attrs = nfit_test_dimm_attributes, 1286 }; 1287 1288 static const struct attribute_group *nfit_test_dimm_attribute_groups[] = { 1289 &nfit_test_dimm_attribute_group, 1290 NULL, 1291 }; 1292 1293 static int nfit_test_dimm_init(struct nfit_test *t) 1294 { 1295 int i; 1296 1297 if (devm_add_action_or_reset(&t->pdev.dev, put_dimms, t)) 1298 return -ENOMEM; 1299 for (i = 0; i < t->num_dcr; i++) { 1300 t->dimm_dev[i] = device_create_with_groups(nfit_test_dimm, 1301 &t->pdev.dev, 0, NULL, 1302 nfit_test_dimm_attribute_groups, 1303 "test_dimm%d", i + t->dcr_idx); 1304 if (!t->dimm_dev[i]) 1305 return -ENOMEM; 1306 } 1307 return 0; 1308 } 1309 1310 static void smart_init(struct nfit_test *t) 1311 { 1312 int i; 1313 const struct nd_intel_smart_threshold smart_t_data = { 1314 .alarm_control = ND_INTEL_SMART_SPARE_TRIP 1315 | ND_INTEL_SMART_TEMP_TRIP, 1316 .media_temperature = 40 * 16, 1317 .ctrl_temperature = 30 * 16, 1318 .spares = 5, 1319 }; 1320 const struct nd_intel_smart smart_data = { 1321 .flags = ND_INTEL_SMART_HEALTH_VALID 1322 | ND_INTEL_SMART_SPARES_VALID 1323 | ND_INTEL_SMART_ALARM_VALID 1324 | ND_INTEL_SMART_USED_VALID 1325 | ND_INTEL_SMART_SHUTDOWN_VALID 1326 | ND_INTEL_SMART_MTEMP_VALID, 1327 .health = ND_INTEL_SMART_NON_CRITICAL_HEALTH, 1328 .media_temperature = 23 * 16, 1329 .ctrl_temperature = 25 * 16, 1330 .pmic_temperature = 40 * 16, 1331 .spares = 75, 1332 .alarm_flags = ND_INTEL_SMART_SPARE_TRIP 1333 | ND_INTEL_SMART_TEMP_TRIP, 1334 .ait_status = 1, 1335 .life_used = 5, 1336 .shutdown_state = 0, 1337 .vendor_size = 0, 1338 .shutdown_count = 100, 1339 }; 1340 1341 for (i = 0; i < t->num_dcr; i++) { 1342 memcpy(&t->smart[i], &smart_data, sizeof(smart_data)); 1343 memcpy(&t->smart_threshold[i], &smart_t_data, 1344 sizeof(smart_t_data)); 1345 } 1346 } 1347 1348 static int nfit_test0_alloc(struct nfit_test *t) 1349 { 1350 size_t nfit_size = sizeof(struct acpi_nfit_system_address) * NUM_SPA 1351 + sizeof(struct acpi_nfit_memory_map) * NUM_MEM 1352 + sizeof(struct acpi_nfit_control_region) * NUM_DCR 1353 + offsetof(struct acpi_nfit_control_region, 1354 window_size) * NUM_DCR 1355 + sizeof(struct acpi_nfit_data_region) * NUM_BDW 1356 + (sizeof(struct acpi_nfit_flush_address) 1357 + sizeof(u64) * NUM_HINTS) * NUM_DCR 1358 + sizeof(struct acpi_nfit_capabilities); 1359 int i; 1360 1361 t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma); 1362 if (!t->nfit_buf) 1363 return -ENOMEM; 1364 t->nfit_size = nfit_size; 1365 1366 t->spa_set[0] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[0]); 1367 if (!t->spa_set[0]) 1368 return -ENOMEM; 1369 1370 t->spa_set[1] = test_alloc(t, SPA1_SIZE, &t->spa_set_dma[1]); 1371 if (!t->spa_set[1]) 1372 return -ENOMEM; 1373 1374 t->spa_set[2] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[2]); 1375 if (!t->spa_set[2]) 1376 return -ENOMEM; 1377 1378 for (i = 0; i < t->num_dcr; i++) { 1379 t->dimm[i] = test_alloc(t, DIMM_SIZE, &t->dimm_dma[i]); 1380 if (!t->dimm[i]) 1381 return -ENOMEM; 1382 1383 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]); 1384 if (!t->label[i]) 1385 return -ENOMEM; 1386 sprintf(t->label[i], "label%d", i); 1387 1388 t->flush[i] = test_alloc(t, max(PAGE_SIZE, 1389 sizeof(u64) * NUM_HINTS), 1390 &t->flush_dma[i]); 1391 if (!t->flush[i]) 1392 return -ENOMEM; 1393 } 1394 1395 for (i = 0; i < t->num_dcr; i++) { 1396 t->dcr[i] = test_alloc(t, LABEL_SIZE, &t->dcr_dma[i]); 1397 if (!t->dcr[i]) 1398 return -ENOMEM; 1399 } 1400 1401 t->_fit = test_alloc(t, sizeof(union acpi_object **), &t->_fit_dma); 1402 if (!t->_fit) 1403 return -ENOMEM; 1404 1405 if (nfit_test_dimm_init(t)) 1406 return -ENOMEM; 1407 smart_init(t); 1408 return ars_state_init(&t->pdev.dev, &t->ars_state); 1409 } 1410 1411 static int nfit_test1_alloc(struct nfit_test *t) 1412 { 1413 size_t nfit_size = sizeof(struct acpi_nfit_system_address) * 2 1414 + sizeof(struct acpi_nfit_memory_map) * 2 1415 + offsetof(struct acpi_nfit_control_region, window_size) * 2; 1416 int i; 1417 1418 t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma); 1419 if (!t->nfit_buf) 1420 return -ENOMEM; 1421 t->nfit_size = nfit_size; 1422 1423 t->spa_set[0] = test_alloc(t, SPA2_SIZE, &t->spa_set_dma[0]); 1424 if (!t->spa_set[0]) 1425 return -ENOMEM; 1426 1427 for (i = 0; i < t->num_dcr; i++) { 1428 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]); 1429 if (!t->label[i]) 1430 return -ENOMEM; 1431 sprintf(t->label[i], "label%d", i); 1432 } 1433 1434 t->spa_set[1] = test_alloc(t, SPA_VCD_SIZE, &t->spa_set_dma[1]); 1435 if (!t->spa_set[1]) 1436 return -ENOMEM; 1437 1438 if (nfit_test_dimm_init(t)) 1439 return -ENOMEM; 1440 smart_init(t); 1441 return ars_state_init(&t->pdev.dev, &t->ars_state); 1442 } 1443 1444 static void dcr_common_init(struct acpi_nfit_control_region *dcr) 1445 { 1446 dcr->vendor_id = 0xabcd; 1447 dcr->device_id = 0; 1448 dcr->revision_id = 1; 1449 dcr->valid_fields = 1; 1450 dcr->manufacturing_location = 0xa; 1451 dcr->manufacturing_date = cpu_to_be16(2016); 1452 } 1453 1454 static void nfit_test0_setup(struct nfit_test *t) 1455 { 1456 const int flush_hint_size = sizeof(struct acpi_nfit_flush_address) 1457 + (sizeof(u64) * NUM_HINTS); 1458 struct acpi_nfit_desc *acpi_desc; 1459 struct acpi_nfit_memory_map *memdev; 1460 void *nfit_buf = t->nfit_buf; 1461 struct acpi_nfit_system_address *spa; 1462 struct acpi_nfit_control_region *dcr; 1463 struct acpi_nfit_data_region *bdw; 1464 struct acpi_nfit_flush_address *flush; 1465 struct acpi_nfit_capabilities *pcap; 1466 unsigned int offset = 0, i; 1467 1468 /* 1469 * spa0 (interleave first half of dimm0 and dimm1, note storage 1470 * does not actually alias the related block-data-window 1471 * regions) 1472 */ 1473 spa = nfit_buf; 1474 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1475 spa->header.length = sizeof(*spa); 1476 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16); 1477 spa->range_index = 0+1; 1478 spa->address = t->spa_set_dma[0]; 1479 spa->length = SPA0_SIZE; 1480 offset += spa->header.length; 1481 1482 /* 1483 * spa1 (interleave last half of the 4 DIMMS, note storage 1484 * does not actually alias the related block-data-window 1485 * regions) 1486 */ 1487 spa = nfit_buf + offset; 1488 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1489 spa->header.length = sizeof(*spa); 1490 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16); 1491 spa->range_index = 1+1; 1492 spa->address = t->spa_set_dma[1]; 1493 spa->length = SPA1_SIZE; 1494 offset += spa->header.length; 1495 1496 /* spa2 (dcr0) dimm0 */ 1497 spa = nfit_buf + offset; 1498 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1499 spa->header.length = sizeof(*spa); 1500 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16); 1501 spa->range_index = 2+1; 1502 spa->address = t->dcr_dma[0]; 1503 spa->length = DCR_SIZE; 1504 offset += spa->header.length; 1505 1506 /* spa3 (dcr1) dimm1 */ 1507 spa = nfit_buf + offset; 1508 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1509 spa->header.length = sizeof(*spa); 1510 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16); 1511 spa->range_index = 3+1; 1512 spa->address = t->dcr_dma[1]; 1513 spa->length = DCR_SIZE; 1514 offset += spa->header.length; 1515 1516 /* spa4 (dcr2) dimm2 */ 1517 spa = nfit_buf + offset; 1518 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1519 spa->header.length = sizeof(*spa); 1520 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16); 1521 spa->range_index = 4+1; 1522 spa->address = t->dcr_dma[2]; 1523 spa->length = DCR_SIZE; 1524 offset += spa->header.length; 1525 1526 /* spa5 (dcr3) dimm3 */ 1527 spa = nfit_buf + offset; 1528 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1529 spa->header.length = sizeof(*spa); 1530 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16); 1531 spa->range_index = 5+1; 1532 spa->address = t->dcr_dma[3]; 1533 spa->length = DCR_SIZE; 1534 offset += spa->header.length; 1535 1536 /* spa6 (bdw for dcr0) dimm0 */ 1537 spa = nfit_buf + offset; 1538 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1539 spa->header.length = sizeof(*spa); 1540 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16); 1541 spa->range_index = 6+1; 1542 spa->address = t->dimm_dma[0]; 1543 spa->length = DIMM_SIZE; 1544 offset += spa->header.length; 1545 1546 /* spa7 (bdw for dcr1) dimm1 */ 1547 spa = nfit_buf + offset; 1548 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1549 spa->header.length = sizeof(*spa); 1550 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16); 1551 spa->range_index = 7+1; 1552 spa->address = t->dimm_dma[1]; 1553 spa->length = DIMM_SIZE; 1554 offset += spa->header.length; 1555 1556 /* spa8 (bdw for dcr2) dimm2 */ 1557 spa = nfit_buf + offset; 1558 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1559 spa->header.length = sizeof(*spa); 1560 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16); 1561 spa->range_index = 8+1; 1562 spa->address = t->dimm_dma[2]; 1563 spa->length = DIMM_SIZE; 1564 offset += spa->header.length; 1565 1566 /* spa9 (bdw for dcr3) dimm3 */ 1567 spa = nfit_buf + offset; 1568 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 1569 spa->header.length = sizeof(*spa); 1570 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16); 1571 spa->range_index = 9+1; 1572 spa->address = t->dimm_dma[3]; 1573 spa->length = DIMM_SIZE; 1574 offset += spa->header.length; 1575 1576 /* mem-region0 (spa0, dimm0) */ 1577 memdev = nfit_buf + offset; 1578 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1579 memdev->header.length = sizeof(*memdev); 1580 memdev->device_handle = handle[0]; 1581 memdev->physical_id = 0; 1582 memdev->region_id = 0; 1583 memdev->range_index = 0+1; 1584 memdev->region_index = 4+1; 1585 memdev->region_size = SPA0_SIZE/2; 1586 memdev->region_offset = 1; 1587 memdev->address = 0; 1588 memdev->interleave_index = 0; 1589 memdev->interleave_ways = 2; 1590 offset += memdev->header.length; 1591 1592 /* mem-region1 (spa0, dimm1) */ 1593 memdev = nfit_buf + offset; 1594 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1595 memdev->header.length = sizeof(*memdev); 1596 memdev->device_handle = handle[1]; 1597 memdev->physical_id = 1; 1598 memdev->region_id = 0; 1599 memdev->range_index = 0+1; 1600 memdev->region_index = 5+1; 1601 memdev->region_size = SPA0_SIZE/2; 1602 memdev->region_offset = (1 << 8); 1603 memdev->address = 0; 1604 memdev->interleave_index = 0; 1605 memdev->interleave_ways = 2; 1606 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED; 1607 offset += memdev->header.length; 1608 1609 /* mem-region2 (spa1, dimm0) */ 1610 memdev = nfit_buf + offset; 1611 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1612 memdev->header.length = sizeof(*memdev); 1613 memdev->device_handle = handle[0]; 1614 memdev->physical_id = 0; 1615 memdev->region_id = 1; 1616 memdev->range_index = 1+1; 1617 memdev->region_index = 4+1; 1618 memdev->region_size = SPA1_SIZE/4; 1619 memdev->region_offset = (1 << 16); 1620 memdev->address = SPA0_SIZE/2; 1621 memdev->interleave_index = 0; 1622 memdev->interleave_ways = 4; 1623 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED; 1624 offset += memdev->header.length; 1625 1626 /* mem-region3 (spa1, dimm1) */ 1627 memdev = nfit_buf + offset; 1628 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1629 memdev->header.length = sizeof(*memdev); 1630 memdev->device_handle = handle[1]; 1631 memdev->physical_id = 1; 1632 memdev->region_id = 1; 1633 memdev->range_index = 1+1; 1634 memdev->region_index = 5+1; 1635 memdev->region_size = SPA1_SIZE/4; 1636 memdev->region_offset = (1 << 24); 1637 memdev->address = SPA0_SIZE/2; 1638 memdev->interleave_index = 0; 1639 memdev->interleave_ways = 4; 1640 offset += memdev->header.length; 1641 1642 /* mem-region4 (spa1, dimm2) */ 1643 memdev = nfit_buf + offset; 1644 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1645 memdev->header.length = sizeof(*memdev); 1646 memdev->device_handle = handle[2]; 1647 memdev->physical_id = 2; 1648 memdev->region_id = 0; 1649 memdev->range_index = 1+1; 1650 memdev->region_index = 6+1; 1651 memdev->region_size = SPA1_SIZE/4; 1652 memdev->region_offset = (1ULL << 32); 1653 memdev->address = SPA0_SIZE/2; 1654 memdev->interleave_index = 0; 1655 memdev->interleave_ways = 4; 1656 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED; 1657 offset += memdev->header.length; 1658 1659 /* mem-region5 (spa1, dimm3) */ 1660 memdev = nfit_buf + offset; 1661 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1662 memdev->header.length = sizeof(*memdev); 1663 memdev->device_handle = handle[3]; 1664 memdev->physical_id = 3; 1665 memdev->region_id = 0; 1666 memdev->range_index = 1+1; 1667 memdev->region_index = 7+1; 1668 memdev->region_size = SPA1_SIZE/4; 1669 memdev->region_offset = (1ULL << 40); 1670 memdev->address = SPA0_SIZE/2; 1671 memdev->interleave_index = 0; 1672 memdev->interleave_ways = 4; 1673 offset += memdev->header.length; 1674 1675 /* mem-region6 (spa/dcr0, dimm0) */ 1676 memdev = nfit_buf + offset; 1677 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1678 memdev->header.length = sizeof(*memdev); 1679 memdev->device_handle = handle[0]; 1680 memdev->physical_id = 0; 1681 memdev->region_id = 0; 1682 memdev->range_index = 2+1; 1683 memdev->region_index = 0+1; 1684 memdev->region_size = 0; 1685 memdev->region_offset = 0; 1686 memdev->address = 0; 1687 memdev->interleave_index = 0; 1688 memdev->interleave_ways = 1; 1689 offset += memdev->header.length; 1690 1691 /* mem-region7 (spa/dcr1, dimm1) */ 1692 memdev = nfit_buf + offset; 1693 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1694 memdev->header.length = sizeof(*memdev); 1695 memdev->device_handle = handle[1]; 1696 memdev->physical_id = 1; 1697 memdev->region_id = 0; 1698 memdev->range_index = 3+1; 1699 memdev->region_index = 1+1; 1700 memdev->region_size = 0; 1701 memdev->region_offset = 0; 1702 memdev->address = 0; 1703 memdev->interleave_index = 0; 1704 memdev->interleave_ways = 1; 1705 offset += memdev->header.length; 1706 1707 /* mem-region8 (spa/dcr2, dimm2) */ 1708 memdev = nfit_buf + offset; 1709 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1710 memdev->header.length = sizeof(*memdev); 1711 memdev->device_handle = handle[2]; 1712 memdev->physical_id = 2; 1713 memdev->region_id = 0; 1714 memdev->range_index = 4+1; 1715 memdev->region_index = 2+1; 1716 memdev->region_size = 0; 1717 memdev->region_offset = 0; 1718 memdev->address = 0; 1719 memdev->interleave_index = 0; 1720 memdev->interleave_ways = 1; 1721 offset += memdev->header.length; 1722 1723 /* mem-region9 (spa/dcr3, dimm3) */ 1724 memdev = nfit_buf + offset; 1725 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1726 memdev->header.length = sizeof(*memdev); 1727 memdev->device_handle = handle[3]; 1728 memdev->physical_id = 3; 1729 memdev->region_id = 0; 1730 memdev->range_index = 5+1; 1731 memdev->region_index = 3+1; 1732 memdev->region_size = 0; 1733 memdev->region_offset = 0; 1734 memdev->address = 0; 1735 memdev->interleave_index = 0; 1736 memdev->interleave_ways = 1; 1737 offset += memdev->header.length; 1738 1739 /* mem-region10 (spa/bdw0, dimm0) */ 1740 memdev = nfit_buf + offset; 1741 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1742 memdev->header.length = sizeof(*memdev); 1743 memdev->device_handle = handle[0]; 1744 memdev->physical_id = 0; 1745 memdev->region_id = 0; 1746 memdev->range_index = 6+1; 1747 memdev->region_index = 0+1; 1748 memdev->region_size = 0; 1749 memdev->region_offset = 0; 1750 memdev->address = 0; 1751 memdev->interleave_index = 0; 1752 memdev->interleave_ways = 1; 1753 offset += memdev->header.length; 1754 1755 /* mem-region11 (spa/bdw1, dimm1) */ 1756 memdev = nfit_buf + offset; 1757 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1758 memdev->header.length = sizeof(*memdev); 1759 memdev->device_handle = handle[1]; 1760 memdev->physical_id = 1; 1761 memdev->region_id = 0; 1762 memdev->range_index = 7+1; 1763 memdev->region_index = 1+1; 1764 memdev->region_size = 0; 1765 memdev->region_offset = 0; 1766 memdev->address = 0; 1767 memdev->interleave_index = 0; 1768 memdev->interleave_ways = 1; 1769 offset += memdev->header.length; 1770 1771 /* mem-region12 (spa/bdw2, dimm2) */ 1772 memdev = nfit_buf + offset; 1773 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1774 memdev->header.length = sizeof(*memdev); 1775 memdev->device_handle = handle[2]; 1776 memdev->physical_id = 2; 1777 memdev->region_id = 0; 1778 memdev->range_index = 8+1; 1779 memdev->region_index = 2+1; 1780 memdev->region_size = 0; 1781 memdev->region_offset = 0; 1782 memdev->address = 0; 1783 memdev->interleave_index = 0; 1784 memdev->interleave_ways = 1; 1785 offset += memdev->header.length; 1786 1787 /* mem-region13 (spa/dcr3, dimm3) */ 1788 memdev = nfit_buf + offset; 1789 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 1790 memdev->header.length = sizeof(*memdev); 1791 memdev->device_handle = handle[3]; 1792 memdev->physical_id = 3; 1793 memdev->region_id = 0; 1794 memdev->range_index = 9+1; 1795 memdev->region_index = 3+1; 1796 memdev->region_size = 0; 1797 memdev->region_offset = 0; 1798 memdev->address = 0; 1799 memdev->interleave_index = 0; 1800 memdev->interleave_ways = 1; 1801 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED; 1802 offset += memdev->header.length; 1803 1804 /* dcr-descriptor0: blk */ 1805 dcr = nfit_buf + offset; 1806 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1807 dcr->header.length = sizeof(*dcr); 1808 dcr->region_index = 0+1; 1809 dcr_common_init(dcr); 1810 dcr->serial_number = ~handle[0]; 1811 dcr->code = NFIT_FIC_BLK; 1812 dcr->windows = 1; 1813 dcr->window_size = DCR_SIZE; 1814 dcr->command_offset = 0; 1815 dcr->command_size = 8; 1816 dcr->status_offset = 8; 1817 dcr->status_size = 4; 1818 offset += dcr->header.length; 1819 1820 /* dcr-descriptor1: blk */ 1821 dcr = nfit_buf + offset; 1822 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1823 dcr->header.length = sizeof(*dcr); 1824 dcr->region_index = 1+1; 1825 dcr_common_init(dcr); 1826 dcr->serial_number = ~handle[1]; 1827 dcr->code = NFIT_FIC_BLK; 1828 dcr->windows = 1; 1829 dcr->window_size = DCR_SIZE; 1830 dcr->command_offset = 0; 1831 dcr->command_size = 8; 1832 dcr->status_offset = 8; 1833 dcr->status_size = 4; 1834 offset += dcr->header.length; 1835 1836 /* dcr-descriptor2: blk */ 1837 dcr = nfit_buf + offset; 1838 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1839 dcr->header.length = sizeof(*dcr); 1840 dcr->region_index = 2+1; 1841 dcr_common_init(dcr); 1842 dcr->serial_number = ~handle[2]; 1843 dcr->code = NFIT_FIC_BLK; 1844 dcr->windows = 1; 1845 dcr->window_size = DCR_SIZE; 1846 dcr->command_offset = 0; 1847 dcr->command_size = 8; 1848 dcr->status_offset = 8; 1849 dcr->status_size = 4; 1850 offset += dcr->header.length; 1851 1852 /* dcr-descriptor3: blk */ 1853 dcr = nfit_buf + offset; 1854 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1855 dcr->header.length = sizeof(*dcr); 1856 dcr->region_index = 3+1; 1857 dcr_common_init(dcr); 1858 dcr->serial_number = ~handle[3]; 1859 dcr->code = NFIT_FIC_BLK; 1860 dcr->windows = 1; 1861 dcr->window_size = DCR_SIZE; 1862 dcr->command_offset = 0; 1863 dcr->command_size = 8; 1864 dcr->status_offset = 8; 1865 dcr->status_size = 4; 1866 offset += dcr->header.length; 1867 1868 /* dcr-descriptor0: pmem */ 1869 dcr = nfit_buf + offset; 1870 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1871 dcr->header.length = offsetof(struct acpi_nfit_control_region, 1872 window_size); 1873 dcr->region_index = 4+1; 1874 dcr_common_init(dcr); 1875 dcr->serial_number = ~handle[0]; 1876 dcr->code = NFIT_FIC_BYTEN; 1877 dcr->windows = 0; 1878 offset += dcr->header.length; 1879 1880 /* dcr-descriptor1: pmem */ 1881 dcr = nfit_buf + offset; 1882 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1883 dcr->header.length = offsetof(struct acpi_nfit_control_region, 1884 window_size); 1885 dcr->region_index = 5+1; 1886 dcr_common_init(dcr); 1887 dcr->serial_number = ~handle[1]; 1888 dcr->code = NFIT_FIC_BYTEN; 1889 dcr->windows = 0; 1890 offset += dcr->header.length; 1891 1892 /* dcr-descriptor2: pmem */ 1893 dcr = nfit_buf + offset; 1894 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1895 dcr->header.length = offsetof(struct acpi_nfit_control_region, 1896 window_size); 1897 dcr->region_index = 6+1; 1898 dcr_common_init(dcr); 1899 dcr->serial_number = ~handle[2]; 1900 dcr->code = NFIT_FIC_BYTEN; 1901 dcr->windows = 0; 1902 offset += dcr->header.length; 1903 1904 /* dcr-descriptor3: pmem */ 1905 dcr = nfit_buf + offset; 1906 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 1907 dcr->header.length = offsetof(struct acpi_nfit_control_region, 1908 window_size); 1909 dcr->region_index = 7+1; 1910 dcr_common_init(dcr); 1911 dcr->serial_number = ~handle[3]; 1912 dcr->code = NFIT_FIC_BYTEN; 1913 dcr->windows = 0; 1914 offset += dcr->header.length; 1915 1916 /* bdw0 (spa/dcr0, dimm0) */ 1917 bdw = nfit_buf + offset; 1918 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION; 1919 bdw->header.length = sizeof(*bdw); 1920 bdw->region_index = 0+1; 1921 bdw->windows = 1; 1922 bdw->offset = 0; 1923 bdw->size = BDW_SIZE; 1924 bdw->capacity = DIMM_SIZE; 1925 bdw->start_address = 0; 1926 offset += bdw->header.length; 1927 1928 /* bdw1 (spa/dcr1, dimm1) */ 1929 bdw = nfit_buf + offset; 1930 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION; 1931 bdw->header.length = sizeof(*bdw); 1932 bdw->region_index = 1+1; 1933 bdw->windows = 1; 1934 bdw->offset = 0; 1935 bdw->size = BDW_SIZE; 1936 bdw->capacity = DIMM_SIZE; 1937 bdw->start_address = 0; 1938 offset += bdw->header.length; 1939 1940 /* bdw2 (spa/dcr2, dimm2) */ 1941 bdw = nfit_buf + offset; 1942 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION; 1943 bdw->header.length = sizeof(*bdw); 1944 bdw->region_index = 2+1; 1945 bdw->windows = 1; 1946 bdw->offset = 0; 1947 bdw->size = BDW_SIZE; 1948 bdw->capacity = DIMM_SIZE; 1949 bdw->start_address = 0; 1950 offset += bdw->header.length; 1951 1952 /* bdw3 (spa/dcr3, dimm3) */ 1953 bdw = nfit_buf + offset; 1954 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION; 1955 bdw->header.length = sizeof(*bdw); 1956 bdw->region_index = 3+1; 1957 bdw->windows = 1; 1958 bdw->offset = 0; 1959 bdw->size = BDW_SIZE; 1960 bdw->capacity = DIMM_SIZE; 1961 bdw->start_address = 0; 1962 offset += bdw->header.length; 1963 1964 /* flush0 (dimm0) */ 1965 flush = nfit_buf + offset; 1966 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; 1967 flush->header.length = flush_hint_size; 1968 flush->device_handle = handle[0]; 1969 flush->hint_count = NUM_HINTS; 1970 for (i = 0; i < NUM_HINTS; i++) 1971 flush->hint_address[i] = t->flush_dma[0] + i * sizeof(u64); 1972 offset += flush->header.length; 1973 1974 /* flush1 (dimm1) */ 1975 flush = nfit_buf + offset; 1976 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; 1977 flush->header.length = flush_hint_size; 1978 flush->device_handle = handle[1]; 1979 flush->hint_count = NUM_HINTS; 1980 for (i = 0; i < NUM_HINTS; i++) 1981 flush->hint_address[i] = t->flush_dma[1] + i * sizeof(u64); 1982 offset += flush->header.length; 1983 1984 /* flush2 (dimm2) */ 1985 flush = nfit_buf + offset; 1986 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; 1987 flush->header.length = flush_hint_size; 1988 flush->device_handle = handle[2]; 1989 flush->hint_count = NUM_HINTS; 1990 for (i = 0; i < NUM_HINTS; i++) 1991 flush->hint_address[i] = t->flush_dma[2] + i * sizeof(u64); 1992 offset += flush->header.length; 1993 1994 /* flush3 (dimm3) */ 1995 flush = nfit_buf + offset; 1996 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; 1997 flush->header.length = flush_hint_size; 1998 flush->device_handle = handle[3]; 1999 flush->hint_count = NUM_HINTS; 2000 for (i = 0; i < NUM_HINTS; i++) 2001 flush->hint_address[i] = t->flush_dma[3] + i * sizeof(u64); 2002 offset += flush->header.length; 2003 2004 /* platform capabilities */ 2005 pcap = nfit_buf + offset; 2006 pcap->header.type = ACPI_NFIT_TYPE_CAPABILITIES; 2007 pcap->header.length = sizeof(*pcap); 2008 pcap->highest_capability = 1; 2009 pcap->capabilities = ACPI_NFIT_CAPABILITY_MEM_FLUSH; 2010 offset += pcap->header.length; 2011 2012 if (t->setup_hotplug) { 2013 /* dcr-descriptor4: blk */ 2014 dcr = nfit_buf + offset; 2015 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2016 dcr->header.length = sizeof(*dcr); 2017 dcr->region_index = 8+1; 2018 dcr_common_init(dcr); 2019 dcr->serial_number = ~handle[4]; 2020 dcr->code = NFIT_FIC_BLK; 2021 dcr->windows = 1; 2022 dcr->window_size = DCR_SIZE; 2023 dcr->command_offset = 0; 2024 dcr->command_size = 8; 2025 dcr->status_offset = 8; 2026 dcr->status_size = 4; 2027 offset += dcr->header.length; 2028 2029 /* dcr-descriptor4: pmem */ 2030 dcr = nfit_buf + offset; 2031 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2032 dcr->header.length = offsetof(struct acpi_nfit_control_region, 2033 window_size); 2034 dcr->region_index = 9+1; 2035 dcr_common_init(dcr); 2036 dcr->serial_number = ~handle[4]; 2037 dcr->code = NFIT_FIC_BYTEN; 2038 dcr->windows = 0; 2039 offset += dcr->header.length; 2040 2041 /* bdw4 (spa/dcr4, dimm4) */ 2042 bdw = nfit_buf + offset; 2043 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION; 2044 bdw->header.length = sizeof(*bdw); 2045 bdw->region_index = 8+1; 2046 bdw->windows = 1; 2047 bdw->offset = 0; 2048 bdw->size = BDW_SIZE; 2049 bdw->capacity = DIMM_SIZE; 2050 bdw->start_address = 0; 2051 offset += bdw->header.length; 2052 2053 /* spa10 (dcr4) dimm4 */ 2054 spa = nfit_buf + offset; 2055 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 2056 spa->header.length = sizeof(*spa); 2057 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16); 2058 spa->range_index = 10+1; 2059 spa->address = t->dcr_dma[4]; 2060 spa->length = DCR_SIZE; 2061 offset += spa->header.length; 2062 2063 /* 2064 * spa11 (single-dimm interleave for hotplug, note storage 2065 * does not actually alias the related block-data-window 2066 * regions) 2067 */ 2068 spa = nfit_buf + offset; 2069 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 2070 spa->header.length = sizeof(*spa); 2071 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16); 2072 spa->range_index = 11+1; 2073 spa->address = t->spa_set_dma[2]; 2074 spa->length = SPA0_SIZE; 2075 offset += spa->header.length; 2076 2077 /* spa12 (bdw for dcr4) dimm4 */ 2078 spa = nfit_buf + offset; 2079 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 2080 spa->header.length = sizeof(*spa); 2081 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16); 2082 spa->range_index = 12+1; 2083 spa->address = t->dimm_dma[4]; 2084 spa->length = DIMM_SIZE; 2085 offset += spa->header.length; 2086 2087 /* mem-region14 (spa/dcr4, dimm4) */ 2088 memdev = nfit_buf + offset; 2089 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2090 memdev->header.length = sizeof(*memdev); 2091 memdev->device_handle = handle[4]; 2092 memdev->physical_id = 4; 2093 memdev->region_id = 0; 2094 memdev->range_index = 10+1; 2095 memdev->region_index = 8+1; 2096 memdev->region_size = 0; 2097 memdev->region_offset = 0; 2098 memdev->address = 0; 2099 memdev->interleave_index = 0; 2100 memdev->interleave_ways = 1; 2101 offset += memdev->header.length; 2102 2103 /* mem-region15 (spa11, dimm4) */ 2104 memdev = nfit_buf + offset; 2105 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2106 memdev->header.length = sizeof(*memdev); 2107 memdev->device_handle = handle[4]; 2108 memdev->physical_id = 4; 2109 memdev->region_id = 0; 2110 memdev->range_index = 11+1; 2111 memdev->region_index = 9+1; 2112 memdev->region_size = SPA0_SIZE; 2113 memdev->region_offset = (1ULL << 48); 2114 memdev->address = 0; 2115 memdev->interleave_index = 0; 2116 memdev->interleave_ways = 1; 2117 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED; 2118 offset += memdev->header.length; 2119 2120 /* mem-region16 (spa/bdw4, dimm4) */ 2121 memdev = nfit_buf + offset; 2122 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2123 memdev->header.length = sizeof(*memdev); 2124 memdev->device_handle = handle[4]; 2125 memdev->physical_id = 4; 2126 memdev->region_id = 0; 2127 memdev->range_index = 12+1; 2128 memdev->region_index = 8+1; 2129 memdev->region_size = 0; 2130 memdev->region_offset = 0; 2131 memdev->address = 0; 2132 memdev->interleave_index = 0; 2133 memdev->interleave_ways = 1; 2134 offset += memdev->header.length; 2135 2136 /* flush3 (dimm4) */ 2137 flush = nfit_buf + offset; 2138 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; 2139 flush->header.length = flush_hint_size; 2140 flush->device_handle = handle[4]; 2141 flush->hint_count = NUM_HINTS; 2142 for (i = 0; i < NUM_HINTS; i++) 2143 flush->hint_address[i] = t->flush_dma[4] 2144 + i * sizeof(u64); 2145 offset += flush->header.length; 2146 2147 /* sanity check to make sure we've filled the buffer */ 2148 WARN_ON(offset != t->nfit_size); 2149 } 2150 2151 t->nfit_filled = offset; 2152 2153 post_ars_status(&t->ars_state, &t->badrange, t->spa_set_dma[0], 2154 SPA0_SIZE); 2155 2156 acpi_desc = &t->acpi_desc; 2157 set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en); 2158 set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en); 2159 set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en); 2160 set_bit(ND_INTEL_SMART, &acpi_desc->dimm_cmd_force_en); 2161 set_bit(ND_INTEL_SMART_THRESHOLD, &acpi_desc->dimm_cmd_force_en); 2162 set_bit(ND_INTEL_SMART_SET_THRESHOLD, &acpi_desc->dimm_cmd_force_en); 2163 set_bit(ND_INTEL_SMART_INJECT, &acpi_desc->dimm_cmd_force_en); 2164 set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en); 2165 set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en); 2166 set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en); 2167 set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en); 2168 set_bit(ND_CMD_CALL, &acpi_desc->bus_cmd_force_en); 2169 set_bit(NFIT_CMD_TRANSLATE_SPA, &acpi_desc->bus_nfit_cmd_force_en); 2170 set_bit(NFIT_CMD_ARS_INJECT_SET, &acpi_desc->bus_nfit_cmd_force_en); 2171 set_bit(NFIT_CMD_ARS_INJECT_CLEAR, &acpi_desc->bus_nfit_cmd_force_en); 2172 set_bit(NFIT_CMD_ARS_INJECT_GET, &acpi_desc->bus_nfit_cmd_force_en); 2173 set_bit(ND_INTEL_FW_GET_INFO, &acpi_desc->dimm_cmd_force_en); 2174 set_bit(ND_INTEL_FW_START_UPDATE, &acpi_desc->dimm_cmd_force_en); 2175 set_bit(ND_INTEL_FW_SEND_DATA, &acpi_desc->dimm_cmd_force_en); 2176 set_bit(ND_INTEL_FW_FINISH_UPDATE, &acpi_desc->dimm_cmd_force_en); 2177 set_bit(ND_INTEL_FW_FINISH_QUERY, &acpi_desc->dimm_cmd_force_en); 2178 set_bit(ND_INTEL_ENABLE_LSS_STATUS, &acpi_desc->dimm_cmd_force_en); 2179 } 2180 2181 static void nfit_test1_setup(struct nfit_test *t) 2182 { 2183 size_t offset; 2184 void *nfit_buf = t->nfit_buf; 2185 struct acpi_nfit_memory_map *memdev; 2186 struct acpi_nfit_control_region *dcr; 2187 struct acpi_nfit_system_address *spa; 2188 struct acpi_nfit_desc *acpi_desc; 2189 2190 offset = 0; 2191 /* spa0 (flat range with no bdw aliasing) */ 2192 spa = nfit_buf + offset; 2193 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 2194 spa->header.length = sizeof(*spa); 2195 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16); 2196 spa->range_index = 0+1; 2197 spa->address = t->spa_set_dma[0]; 2198 spa->length = SPA2_SIZE; 2199 offset += spa->header.length; 2200 2201 /* virtual cd region */ 2202 spa = nfit_buf + offset; 2203 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS; 2204 spa->header.length = sizeof(*spa); 2205 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_VCD), 16); 2206 spa->range_index = 0; 2207 spa->address = t->spa_set_dma[1]; 2208 spa->length = SPA_VCD_SIZE; 2209 offset += spa->header.length; 2210 2211 /* mem-region0 (spa0, dimm0) */ 2212 memdev = nfit_buf + offset; 2213 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2214 memdev->header.length = sizeof(*memdev); 2215 memdev->device_handle = handle[5]; 2216 memdev->physical_id = 0; 2217 memdev->region_id = 0; 2218 memdev->range_index = 0+1; 2219 memdev->region_index = 0+1; 2220 memdev->region_size = SPA2_SIZE; 2221 memdev->region_offset = 0; 2222 memdev->address = 0; 2223 memdev->interleave_index = 0; 2224 memdev->interleave_ways = 1; 2225 memdev->flags = ACPI_NFIT_MEM_SAVE_FAILED | ACPI_NFIT_MEM_RESTORE_FAILED 2226 | ACPI_NFIT_MEM_FLUSH_FAILED | ACPI_NFIT_MEM_HEALTH_OBSERVED 2227 | ACPI_NFIT_MEM_NOT_ARMED; 2228 offset += memdev->header.length; 2229 2230 /* dcr-descriptor0 */ 2231 dcr = nfit_buf + offset; 2232 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2233 dcr->header.length = offsetof(struct acpi_nfit_control_region, 2234 window_size); 2235 dcr->region_index = 0+1; 2236 dcr_common_init(dcr); 2237 dcr->serial_number = ~handle[5]; 2238 dcr->code = NFIT_FIC_BYTE; 2239 dcr->windows = 0; 2240 offset += dcr->header.length; 2241 2242 memdev = nfit_buf + offset; 2243 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP; 2244 memdev->header.length = sizeof(*memdev); 2245 memdev->device_handle = handle[6]; 2246 memdev->physical_id = 0; 2247 memdev->region_id = 0; 2248 memdev->range_index = 0; 2249 memdev->region_index = 0+2; 2250 memdev->region_size = SPA2_SIZE; 2251 memdev->region_offset = 0; 2252 memdev->address = 0; 2253 memdev->interleave_index = 0; 2254 memdev->interleave_ways = 1; 2255 memdev->flags = ACPI_NFIT_MEM_MAP_FAILED; 2256 offset += memdev->header.length; 2257 2258 /* dcr-descriptor1 */ 2259 dcr = nfit_buf + offset; 2260 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; 2261 dcr->header.length = offsetof(struct acpi_nfit_control_region, 2262 window_size); 2263 dcr->region_index = 0+2; 2264 dcr_common_init(dcr); 2265 dcr->serial_number = ~handle[6]; 2266 dcr->code = NFIT_FIC_BYTE; 2267 dcr->windows = 0; 2268 offset += dcr->header.length; 2269 2270 /* sanity check to make sure we've filled the buffer */ 2271 WARN_ON(offset != t->nfit_size); 2272 2273 t->nfit_filled = offset; 2274 2275 post_ars_status(&t->ars_state, &t->badrange, t->spa_set_dma[0], 2276 SPA2_SIZE); 2277 2278 acpi_desc = &t->acpi_desc; 2279 set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en); 2280 set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en); 2281 set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en); 2282 set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en); 2283 set_bit(ND_INTEL_ENABLE_LSS_STATUS, &acpi_desc->dimm_cmd_force_en); 2284 set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en); 2285 set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en); 2286 set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en); 2287 } 2288 2289 static int nfit_test_blk_do_io(struct nd_blk_region *ndbr, resource_size_t dpa, 2290 void *iobuf, u64 len, int rw) 2291 { 2292 struct nfit_blk *nfit_blk = ndbr->blk_provider_data; 2293 struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW]; 2294 struct nd_region *nd_region = &ndbr->nd_region; 2295 unsigned int lane; 2296 2297 lane = nd_region_acquire_lane(nd_region); 2298 if (rw) 2299 memcpy(mmio->addr.base + dpa, iobuf, len); 2300 else { 2301 memcpy(iobuf, mmio->addr.base + dpa, len); 2302 2303 /* give us some some coverage of the arch_invalidate_pmem() API */ 2304 arch_invalidate_pmem(mmio->addr.base + dpa, len); 2305 } 2306 nd_region_release_lane(nd_region, lane); 2307 2308 return 0; 2309 } 2310 2311 static unsigned long nfit_ctl_handle; 2312 2313 union acpi_object *result; 2314 2315 static union acpi_object *nfit_test_evaluate_dsm(acpi_handle handle, 2316 const guid_t *guid, u64 rev, u64 func, union acpi_object *argv4) 2317 { 2318 if (handle != &nfit_ctl_handle) 2319 return ERR_PTR(-ENXIO); 2320 2321 return result; 2322 } 2323 2324 static int setup_result(void *buf, size_t size) 2325 { 2326 result = kmalloc(sizeof(union acpi_object) + size, GFP_KERNEL); 2327 if (!result) 2328 return -ENOMEM; 2329 result->package.type = ACPI_TYPE_BUFFER, 2330 result->buffer.pointer = (void *) (result + 1); 2331 result->buffer.length = size; 2332 memcpy(result->buffer.pointer, buf, size); 2333 memset(buf, 0, size); 2334 return 0; 2335 } 2336 2337 static int nfit_ctl_test(struct device *dev) 2338 { 2339 int rc, cmd_rc; 2340 struct nvdimm *nvdimm; 2341 struct acpi_device *adev; 2342 struct nfit_mem *nfit_mem; 2343 struct nd_ars_record *record; 2344 struct acpi_nfit_desc *acpi_desc; 2345 const u64 test_val = 0x0123456789abcdefULL; 2346 unsigned long mask, cmd_size, offset; 2347 union { 2348 struct nd_cmd_get_config_size cfg_size; 2349 struct nd_cmd_clear_error clear_err; 2350 struct nd_cmd_ars_status ars_stat; 2351 struct nd_cmd_ars_cap ars_cap; 2352 char buf[sizeof(struct nd_cmd_ars_status) 2353 + sizeof(struct nd_ars_record)]; 2354 } cmds; 2355 2356 adev = devm_kzalloc(dev, sizeof(*adev), GFP_KERNEL); 2357 if (!adev) 2358 return -ENOMEM; 2359 *adev = (struct acpi_device) { 2360 .handle = &nfit_ctl_handle, 2361 .dev = { 2362 .init_name = "test-adev", 2363 }, 2364 }; 2365 2366 acpi_desc = devm_kzalloc(dev, sizeof(*acpi_desc), GFP_KERNEL); 2367 if (!acpi_desc) 2368 return -ENOMEM; 2369 *acpi_desc = (struct acpi_nfit_desc) { 2370 .nd_desc = { 2371 .cmd_mask = 1UL << ND_CMD_ARS_CAP 2372 | 1UL << ND_CMD_ARS_START 2373 | 1UL << ND_CMD_ARS_STATUS 2374 | 1UL << ND_CMD_CLEAR_ERROR 2375 | 1UL << ND_CMD_CALL, 2376 .module = THIS_MODULE, 2377 .provider_name = "ACPI.NFIT", 2378 .ndctl = acpi_nfit_ctl, 2379 .bus_dsm_mask = 1UL << NFIT_CMD_TRANSLATE_SPA 2380 | 1UL << NFIT_CMD_ARS_INJECT_SET 2381 | 1UL << NFIT_CMD_ARS_INJECT_CLEAR 2382 | 1UL << NFIT_CMD_ARS_INJECT_GET, 2383 }, 2384 .dev = &adev->dev, 2385 }; 2386 2387 nfit_mem = devm_kzalloc(dev, sizeof(*nfit_mem), GFP_KERNEL); 2388 if (!nfit_mem) 2389 return -ENOMEM; 2390 2391 mask = 1UL << ND_CMD_SMART | 1UL << ND_CMD_SMART_THRESHOLD 2392 | 1UL << ND_CMD_DIMM_FLAGS | 1UL << ND_CMD_GET_CONFIG_SIZE 2393 | 1UL << ND_CMD_GET_CONFIG_DATA | 1UL << ND_CMD_SET_CONFIG_DATA 2394 | 1UL << ND_CMD_VENDOR; 2395 *nfit_mem = (struct nfit_mem) { 2396 .adev = adev, 2397 .family = NVDIMM_FAMILY_INTEL, 2398 .dsm_mask = mask, 2399 }; 2400 2401 nvdimm = devm_kzalloc(dev, sizeof(*nvdimm), GFP_KERNEL); 2402 if (!nvdimm) 2403 return -ENOMEM; 2404 *nvdimm = (struct nvdimm) { 2405 .provider_data = nfit_mem, 2406 .cmd_mask = mask, 2407 .dev = { 2408 .init_name = "test-dimm", 2409 }, 2410 }; 2411 2412 2413 /* basic checkout of a typical 'get config size' command */ 2414 cmd_size = sizeof(cmds.cfg_size); 2415 cmds.cfg_size = (struct nd_cmd_get_config_size) { 2416 .status = 0, 2417 .config_size = SZ_128K, 2418 .max_xfer = SZ_4K, 2419 }; 2420 rc = setup_result(cmds.buf, cmd_size); 2421 if (rc) 2422 return rc; 2423 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, nvdimm, ND_CMD_GET_CONFIG_SIZE, 2424 cmds.buf, cmd_size, &cmd_rc); 2425 2426 if (rc < 0 || cmd_rc || cmds.cfg_size.status != 0 2427 || cmds.cfg_size.config_size != SZ_128K 2428 || cmds.cfg_size.max_xfer != SZ_4K) { 2429 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2430 __func__, __LINE__, rc, cmd_rc); 2431 return -EIO; 2432 } 2433 2434 2435 /* test ars_status with zero output */ 2436 cmd_size = offsetof(struct nd_cmd_ars_status, address); 2437 cmds.ars_stat = (struct nd_cmd_ars_status) { 2438 .out_length = 0, 2439 }; 2440 rc = setup_result(cmds.buf, cmd_size); 2441 if (rc) 2442 return rc; 2443 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS, 2444 cmds.buf, cmd_size, &cmd_rc); 2445 2446 if (rc < 0 || cmd_rc) { 2447 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2448 __func__, __LINE__, rc, cmd_rc); 2449 return -EIO; 2450 } 2451 2452 2453 /* test ars_cap with benign extended status */ 2454 cmd_size = sizeof(cmds.ars_cap); 2455 cmds.ars_cap = (struct nd_cmd_ars_cap) { 2456 .status = ND_ARS_PERSISTENT << 16, 2457 }; 2458 offset = offsetof(struct nd_cmd_ars_cap, status); 2459 rc = setup_result(cmds.buf + offset, cmd_size - offset); 2460 if (rc) 2461 return rc; 2462 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_CAP, 2463 cmds.buf, cmd_size, &cmd_rc); 2464 2465 if (rc < 0 || cmd_rc) { 2466 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2467 __func__, __LINE__, rc, cmd_rc); 2468 return -EIO; 2469 } 2470 2471 2472 /* test ars_status with 'status' trimmed from 'out_length' */ 2473 cmd_size = sizeof(cmds.ars_stat) + sizeof(struct nd_ars_record); 2474 cmds.ars_stat = (struct nd_cmd_ars_status) { 2475 .out_length = cmd_size - 4, 2476 }; 2477 record = &cmds.ars_stat.records[0]; 2478 *record = (struct nd_ars_record) { 2479 .length = test_val, 2480 }; 2481 rc = setup_result(cmds.buf, cmd_size); 2482 if (rc) 2483 return rc; 2484 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS, 2485 cmds.buf, cmd_size, &cmd_rc); 2486 2487 if (rc < 0 || cmd_rc || record->length != test_val) { 2488 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2489 __func__, __LINE__, rc, cmd_rc); 2490 return -EIO; 2491 } 2492 2493 2494 /* test ars_status with 'Output (Size)' including 'status' */ 2495 cmd_size = sizeof(cmds.ars_stat) + sizeof(struct nd_ars_record); 2496 cmds.ars_stat = (struct nd_cmd_ars_status) { 2497 .out_length = cmd_size, 2498 }; 2499 record = &cmds.ars_stat.records[0]; 2500 *record = (struct nd_ars_record) { 2501 .length = test_val, 2502 }; 2503 rc = setup_result(cmds.buf, cmd_size); 2504 if (rc) 2505 return rc; 2506 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS, 2507 cmds.buf, cmd_size, &cmd_rc); 2508 2509 if (rc < 0 || cmd_rc || record->length != test_val) { 2510 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2511 __func__, __LINE__, rc, cmd_rc); 2512 return -EIO; 2513 } 2514 2515 2516 /* test extended status for get_config_size results in failure */ 2517 cmd_size = sizeof(cmds.cfg_size); 2518 cmds.cfg_size = (struct nd_cmd_get_config_size) { 2519 .status = 1 << 16, 2520 }; 2521 rc = setup_result(cmds.buf, cmd_size); 2522 if (rc) 2523 return rc; 2524 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, nvdimm, ND_CMD_GET_CONFIG_SIZE, 2525 cmds.buf, cmd_size, &cmd_rc); 2526 2527 if (rc < 0 || cmd_rc >= 0) { 2528 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2529 __func__, __LINE__, rc, cmd_rc); 2530 return -EIO; 2531 } 2532 2533 /* test clear error */ 2534 cmd_size = sizeof(cmds.clear_err); 2535 cmds.clear_err = (struct nd_cmd_clear_error) { 2536 .length = 512, 2537 .cleared = 512, 2538 }; 2539 rc = setup_result(cmds.buf, cmd_size); 2540 if (rc) 2541 return rc; 2542 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_CLEAR_ERROR, 2543 cmds.buf, cmd_size, &cmd_rc); 2544 if (rc < 0 || cmd_rc) { 2545 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n", 2546 __func__, __LINE__, rc, cmd_rc); 2547 return -EIO; 2548 } 2549 2550 return 0; 2551 } 2552 2553 static int nfit_test_probe(struct platform_device *pdev) 2554 { 2555 struct nvdimm_bus_descriptor *nd_desc; 2556 struct acpi_nfit_desc *acpi_desc; 2557 struct device *dev = &pdev->dev; 2558 struct nfit_test *nfit_test; 2559 struct nfit_mem *nfit_mem; 2560 union acpi_object *obj; 2561 int rc; 2562 2563 if (strcmp(dev_name(&pdev->dev), "nfit_test.0") == 0) { 2564 rc = nfit_ctl_test(&pdev->dev); 2565 if (rc) 2566 return rc; 2567 } 2568 2569 nfit_test = to_nfit_test(&pdev->dev); 2570 2571 /* common alloc */ 2572 if (nfit_test->num_dcr) { 2573 int num = nfit_test->num_dcr; 2574 2575 nfit_test->dimm = devm_kcalloc(dev, num, sizeof(void *), 2576 GFP_KERNEL); 2577 nfit_test->dimm_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t), 2578 GFP_KERNEL); 2579 nfit_test->flush = devm_kcalloc(dev, num, sizeof(void *), 2580 GFP_KERNEL); 2581 nfit_test->flush_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t), 2582 GFP_KERNEL); 2583 nfit_test->label = devm_kcalloc(dev, num, sizeof(void *), 2584 GFP_KERNEL); 2585 nfit_test->label_dma = devm_kcalloc(dev, num, 2586 sizeof(dma_addr_t), GFP_KERNEL); 2587 nfit_test->dcr = devm_kcalloc(dev, num, 2588 sizeof(struct nfit_test_dcr *), GFP_KERNEL); 2589 nfit_test->dcr_dma = devm_kcalloc(dev, num, 2590 sizeof(dma_addr_t), GFP_KERNEL); 2591 nfit_test->smart = devm_kcalloc(dev, num, 2592 sizeof(struct nd_intel_smart), GFP_KERNEL); 2593 nfit_test->smart_threshold = devm_kcalloc(dev, num, 2594 sizeof(struct nd_intel_smart_threshold), 2595 GFP_KERNEL); 2596 nfit_test->fw = devm_kcalloc(dev, num, 2597 sizeof(struct nfit_test_fw), GFP_KERNEL); 2598 if (nfit_test->dimm && nfit_test->dimm_dma && nfit_test->label 2599 && nfit_test->label_dma && nfit_test->dcr 2600 && nfit_test->dcr_dma && nfit_test->flush 2601 && nfit_test->flush_dma 2602 && nfit_test->fw) 2603 /* pass */; 2604 else 2605 return -ENOMEM; 2606 } 2607 2608 if (nfit_test->num_pm) { 2609 int num = nfit_test->num_pm; 2610 2611 nfit_test->spa_set = devm_kcalloc(dev, num, sizeof(void *), 2612 GFP_KERNEL); 2613 nfit_test->spa_set_dma = devm_kcalloc(dev, num, 2614 sizeof(dma_addr_t), GFP_KERNEL); 2615 if (nfit_test->spa_set && nfit_test->spa_set_dma) 2616 /* pass */; 2617 else 2618 return -ENOMEM; 2619 } 2620 2621 /* per-nfit specific alloc */ 2622 if (nfit_test->alloc(nfit_test)) 2623 return -ENOMEM; 2624 2625 nfit_test->setup(nfit_test); 2626 acpi_desc = &nfit_test->acpi_desc; 2627 acpi_nfit_desc_init(acpi_desc, &pdev->dev); 2628 acpi_desc->blk_do_io = nfit_test_blk_do_io; 2629 nd_desc = &acpi_desc->nd_desc; 2630 nd_desc->provider_name = NULL; 2631 nd_desc->module = THIS_MODULE; 2632 nd_desc->ndctl = nfit_test_ctl; 2633 2634 rc = acpi_nfit_init(acpi_desc, nfit_test->nfit_buf, 2635 nfit_test->nfit_filled); 2636 if (rc) 2637 return rc; 2638 2639 rc = devm_add_action_or_reset(&pdev->dev, acpi_nfit_shutdown, acpi_desc); 2640 if (rc) 2641 return rc; 2642 2643 if (nfit_test->setup != nfit_test0_setup) 2644 return 0; 2645 2646 nfit_test->setup_hotplug = 1; 2647 nfit_test->setup(nfit_test); 2648 2649 obj = kzalloc(sizeof(*obj), GFP_KERNEL); 2650 if (!obj) 2651 return -ENOMEM; 2652 obj->type = ACPI_TYPE_BUFFER; 2653 obj->buffer.length = nfit_test->nfit_size; 2654 obj->buffer.pointer = nfit_test->nfit_buf; 2655 *(nfit_test->_fit) = obj; 2656 __acpi_nfit_notify(&pdev->dev, nfit_test, 0x80); 2657 2658 /* associate dimm devices with nfit_mem data for notification testing */ 2659 mutex_lock(&acpi_desc->init_mutex); 2660 list_for_each_entry(nfit_mem, &acpi_desc->dimms, list) { 2661 u32 nfit_handle = __to_nfit_memdev(nfit_mem)->device_handle; 2662 int i; 2663 2664 for (i = 0; i < NUM_DCR; i++) 2665 if (nfit_handle == handle[i]) 2666 dev_set_drvdata(nfit_test->dimm_dev[i], 2667 nfit_mem); 2668 } 2669 mutex_unlock(&acpi_desc->init_mutex); 2670 2671 return 0; 2672 } 2673 2674 static int nfit_test_remove(struct platform_device *pdev) 2675 { 2676 return 0; 2677 } 2678 2679 static void nfit_test_release(struct device *dev) 2680 { 2681 struct nfit_test *nfit_test = to_nfit_test(dev); 2682 2683 kfree(nfit_test); 2684 } 2685 2686 static const struct platform_device_id nfit_test_id[] = { 2687 { KBUILD_MODNAME }, 2688 { }, 2689 }; 2690 2691 static struct platform_driver nfit_test_driver = { 2692 .probe = nfit_test_probe, 2693 .remove = nfit_test_remove, 2694 .driver = { 2695 .name = KBUILD_MODNAME, 2696 }, 2697 .id_table = nfit_test_id, 2698 }; 2699 2700 static char mcsafe_buf[PAGE_SIZE] __attribute__((__aligned__(PAGE_SIZE))); 2701 2702 enum INJECT { 2703 INJECT_NONE, 2704 INJECT_SRC, 2705 INJECT_DST, 2706 }; 2707 2708 static void mcsafe_test_init(char *dst, char *src, size_t size) 2709 { 2710 size_t i; 2711 2712 memset(dst, 0xff, size); 2713 for (i = 0; i < size; i++) 2714 src[i] = (char) i; 2715 } 2716 2717 static bool mcsafe_test_validate(unsigned char *dst, unsigned char *src, 2718 size_t size, unsigned long rem) 2719 { 2720 size_t i; 2721 2722 for (i = 0; i < size - rem; i++) 2723 if (dst[i] != (unsigned char) i) { 2724 pr_info_once("%s:%d: offset: %zd got: %#x expect: %#x\n", 2725 __func__, __LINE__, i, dst[i], 2726 (unsigned char) i); 2727 return false; 2728 } 2729 for (i = size - rem; i < size; i++) 2730 if (dst[i] != 0xffU) { 2731 pr_info_once("%s:%d: offset: %zd got: %#x expect: 0xff\n", 2732 __func__, __LINE__, i, dst[i]); 2733 return false; 2734 } 2735 return true; 2736 } 2737 2738 void mcsafe_test(void) 2739 { 2740 char *inject_desc[] = { "none", "source", "destination" }; 2741 enum INJECT inj; 2742 2743 if (IS_ENABLED(CONFIG_MCSAFE_TEST)) { 2744 pr_info("%s: run...\n", __func__); 2745 } else { 2746 pr_info("%s: disabled, skip.\n", __func__); 2747 return; 2748 } 2749 2750 for (inj = INJECT_NONE; inj <= INJECT_DST; inj++) { 2751 int i; 2752 2753 pr_info("%s: inject: %s\n", __func__, inject_desc[inj]); 2754 for (i = 0; i < 512; i++) { 2755 unsigned long expect, rem; 2756 void *src, *dst; 2757 bool valid; 2758 2759 switch (inj) { 2760 case INJECT_NONE: 2761 mcsafe_inject_src(NULL); 2762 mcsafe_inject_dst(NULL); 2763 dst = &mcsafe_buf[2048]; 2764 src = &mcsafe_buf[1024 - i]; 2765 expect = 0; 2766 break; 2767 case INJECT_SRC: 2768 mcsafe_inject_src(&mcsafe_buf[1024]); 2769 mcsafe_inject_dst(NULL); 2770 dst = &mcsafe_buf[2048]; 2771 src = &mcsafe_buf[1024 - i]; 2772 expect = 512 - i; 2773 break; 2774 case INJECT_DST: 2775 mcsafe_inject_src(NULL); 2776 mcsafe_inject_dst(&mcsafe_buf[2048]); 2777 dst = &mcsafe_buf[2048 - i]; 2778 src = &mcsafe_buf[1024]; 2779 expect = 512 - i; 2780 break; 2781 } 2782 2783 mcsafe_test_init(dst, src, 512); 2784 rem = __memcpy_mcsafe(dst, src, 512); 2785 valid = mcsafe_test_validate(dst, src, 512, expect); 2786 if (rem == expect && valid) 2787 continue; 2788 pr_info("%s: copy(%#lx, %#lx, %d) off: %d rem: %ld %s expect: %ld\n", 2789 __func__, 2790 ((unsigned long) dst) & ~PAGE_MASK, 2791 ((unsigned long ) src) & ~PAGE_MASK, 2792 512, i, rem, valid ? "valid" : "bad", 2793 expect); 2794 } 2795 } 2796 2797 mcsafe_inject_src(NULL); 2798 mcsafe_inject_dst(NULL); 2799 } 2800 2801 static __init int nfit_test_init(void) 2802 { 2803 int rc, i; 2804 2805 pmem_test(); 2806 libnvdimm_test(); 2807 acpi_nfit_test(); 2808 device_dax_test(); 2809 mcsafe_test(); 2810 2811 nfit_test_setup(nfit_test_lookup, nfit_test_evaluate_dsm); 2812 2813 nfit_wq = create_singlethread_workqueue("nfit"); 2814 if (!nfit_wq) 2815 return -ENOMEM; 2816 2817 nfit_test_dimm = class_create(THIS_MODULE, "nfit_test_dimm"); 2818 if (IS_ERR(nfit_test_dimm)) { 2819 rc = PTR_ERR(nfit_test_dimm); 2820 goto err_register; 2821 } 2822 2823 for (i = 0; i < NUM_NFITS; i++) { 2824 struct nfit_test *nfit_test; 2825 struct platform_device *pdev; 2826 2827 nfit_test = kzalloc(sizeof(*nfit_test), GFP_KERNEL); 2828 if (!nfit_test) { 2829 rc = -ENOMEM; 2830 goto err_register; 2831 } 2832 INIT_LIST_HEAD(&nfit_test->resources); 2833 badrange_init(&nfit_test->badrange); 2834 switch (i) { 2835 case 0: 2836 nfit_test->num_pm = NUM_PM; 2837 nfit_test->dcr_idx = 0; 2838 nfit_test->num_dcr = NUM_DCR; 2839 nfit_test->alloc = nfit_test0_alloc; 2840 nfit_test->setup = nfit_test0_setup; 2841 break; 2842 case 1: 2843 nfit_test->num_pm = 2; 2844 nfit_test->dcr_idx = NUM_DCR; 2845 nfit_test->num_dcr = 2; 2846 nfit_test->alloc = nfit_test1_alloc; 2847 nfit_test->setup = nfit_test1_setup; 2848 break; 2849 default: 2850 rc = -EINVAL; 2851 goto err_register; 2852 } 2853 pdev = &nfit_test->pdev; 2854 pdev->name = KBUILD_MODNAME; 2855 pdev->id = i; 2856 pdev->dev.release = nfit_test_release; 2857 rc = platform_device_register(pdev); 2858 if (rc) { 2859 put_device(&pdev->dev); 2860 goto err_register; 2861 } 2862 get_device(&pdev->dev); 2863 2864 rc = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2865 if (rc) 2866 goto err_register; 2867 2868 instances[i] = nfit_test; 2869 INIT_WORK(&nfit_test->work, uc_error_notify); 2870 } 2871 2872 rc = platform_driver_register(&nfit_test_driver); 2873 if (rc) 2874 goto err_register; 2875 return 0; 2876 2877 err_register: 2878 destroy_workqueue(nfit_wq); 2879 for (i = 0; i < NUM_NFITS; i++) 2880 if (instances[i]) 2881 platform_device_unregister(&instances[i]->pdev); 2882 nfit_test_teardown(); 2883 for (i = 0; i < NUM_NFITS; i++) 2884 if (instances[i]) 2885 put_device(&instances[i]->pdev.dev); 2886 2887 return rc; 2888 } 2889 2890 static __exit void nfit_test_exit(void) 2891 { 2892 int i; 2893 2894 flush_workqueue(nfit_wq); 2895 destroy_workqueue(nfit_wq); 2896 for (i = 0; i < NUM_NFITS; i++) 2897 platform_device_unregister(&instances[i]->pdev); 2898 platform_driver_unregister(&nfit_test_driver); 2899 nfit_test_teardown(); 2900 2901 for (i = 0; i < NUM_NFITS; i++) 2902 put_device(&instances[i]->pdev.dev); 2903 class_destroy(nfit_test_dimm); 2904 } 2905 2906 module_init(nfit_test_init); 2907 module_exit(nfit_test_exit); 2908 MODULE_LICENSE("GPL v2"); 2909 MODULE_AUTHOR("Intel Corporation"); 2910