1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * turbostat -- show CPU frequency and C-state residency 4 * on modern Intel and AMD processors. 5 * 6 * Copyright (c) 2013 Intel Corporation. 7 * Len Brown <len.brown@intel.com> 8 */ 9 10 #define _GNU_SOURCE 11 #include MSRHEADER 12 #include INTEL_FAMILY_HEADER 13 #include <stdarg.h> 14 #include <stdio.h> 15 #include <err.h> 16 #include <unistd.h> 17 #include <sys/types.h> 18 #include <sys/wait.h> 19 #include <sys/stat.h> 20 #include <sys/select.h> 21 #include <sys/resource.h> 22 #include <fcntl.h> 23 #include <signal.h> 24 #include <sys/time.h> 25 #include <stdlib.h> 26 #include <getopt.h> 27 #include <dirent.h> 28 #include <string.h> 29 #include <ctype.h> 30 #include <sched.h> 31 #include <time.h> 32 #include <cpuid.h> 33 #include <sys/capability.h> 34 #include <errno.h> 35 #include <math.h> 36 #include <linux/perf_event.h> 37 #include <asm/unistd.h> 38 39 char *proc_stat = "/proc/stat"; 40 FILE *outf; 41 int *fd_percpu; 42 int *fd_instr_count_percpu; 43 struct timeval interval_tv = {5, 0}; 44 struct timespec interval_ts = {5, 0}; 45 unsigned int num_iterations; 46 unsigned int debug; 47 unsigned int quiet; 48 unsigned int shown; 49 unsigned int sums_need_wide_columns; 50 unsigned int rapl_joules; 51 unsigned int summary_only; 52 unsigned int list_header_only; 53 unsigned int dump_only; 54 unsigned int do_snb_cstates; 55 unsigned int do_knl_cstates; 56 unsigned int do_slm_cstates; 57 unsigned int use_c1_residency_msr; 58 unsigned int has_aperf; 59 unsigned int has_epb; 60 unsigned int do_irtl_snb; 61 unsigned int do_irtl_hsw; 62 unsigned int units = 1000000; /* MHz etc */ 63 unsigned int genuine_intel; 64 unsigned int authentic_amd; 65 unsigned int hygon_genuine; 66 unsigned int max_level, max_extended_level; 67 unsigned int has_invariant_tsc; 68 unsigned int do_nhm_platform_info; 69 unsigned int no_MSR_MISC_PWR_MGMT; 70 unsigned int aperf_mperf_multiplier = 1; 71 double bclk; 72 double base_hz; 73 unsigned int has_base_hz; 74 double tsc_tweak = 1.0; 75 unsigned int show_pkg_only; 76 unsigned int show_core_only; 77 char *output_buffer, *outp; 78 unsigned int do_rapl; 79 unsigned int do_dts; 80 unsigned int do_ptm; 81 unsigned int do_ipc; 82 unsigned long long gfx_cur_rc6_ms; 83 unsigned long long cpuidle_cur_cpu_lpi_us; 84 unsigned long long cpuidle_cur_sys_lpi_us; 85 unsigned int gfx_cur_mhz; 86 unsigned int gfx_act_mhz; 87 unsigned int tcc_activation_temp; 88 unsigned int tcc_activation_temp_override; 89 double rapl_power_units, rapl_time_units; 90 double rapl_dram_energy_units, rapl_energy_units; 91 double rapl_joule_counter_range; 92 unsigned int do_core_perf_limit_reasons; 93 unsigned int has_automatic_cstate_conversion; 94 unsigned int do_gfx_perf_limit_reasons; 95 unsigned int do_ring_perf_limit_reasons; 96 unsigned int crystal_hz; 97 unsigned long long tsc_hz; 98 int base_cpu; 99 double discover_bclk(unsigned int family, unsigned int model); 100 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ 101 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ 102 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ 103 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ 104 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ 105 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ 106 unsigned int has_misc_feature_control; 107 unsigned int first_counter_read = 1; 108 int ignore_stdin; 109 110 #define RAPL_PKG (1 << 0) 111 /* 0x610 MSR_PKG_POWER_LIMIT */ 112 /* 0x611 MSR_PKG_ENERGY_STATUS */ 113 #define RAPL_PKG_PERF_STATUS (1 << 1) 114 /* 0x613 MSR_PKG_PERF_STATUS */ 115 #define RAPL_PKG_POWER_INFO (1 << 2) 116 /* 0x614 MSR_PKG_POWER_INFO */ 117 118 #define RAPL_DRAM (1 << 3) 119 /* 0x618 MSR_DRAM_POWER_LIMIT */ 120 /* 0x619 MSR_DRAM_ENERGY_STATUS */ 121 #define RAPL_DRAM_PERF_STATUS (1 << 4) 122 /* 0x61b MSR_DRAM_PERF_STATUS */ 123 #define RAPL_DRAM_POWER_INFO (1 << 5) 124 /* 0x61c MSR_DRAM_POWER_INFO */ 125 126 #define RAPL_CORES_POWER_LIMIT (1 << 6) 127 /* 0x638 MSR_PP0_POWER_LIMIT */ 128 #define RAPL_CORE_POLICY (1 << 7) 129 /* 0x63a MSR_PP0_POLICY */ 130 131 #define RAPL_GFX (1 << 8) 132 /* 0x640 MSR_PP1_POWER_LIMIT */ 133 /* 0x641 MSR_PP1_ENERGY_STATUS */ 134 /* 0x642 MSR_PP1_POLICY */ 135 136 #define RAPL_CORES_ENERGY_STATUS (1 << 9) 137 /* 0x639 MSR_PP0_ENERGY_STATUS */ 138 #define RAPL_PER_CORE_ENERGY (1 << 10) 139 /* Indicates cores energy collection is per-core, 140 * not per-package. */ 141 #define RAPL_AMD_F17H (1 << 11) 142 /* 0xc0010299 MSR_RAPL_PWR_UNIT */ 143 /* 0xc001029a MSR_CORE_ENERGY_STAT */ 144 /* 0xc001029b MSR_PKG_ENERGY_STAT */ 145 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT) 146 #define TJMAX_DEFAULT 100 147 148 /* MSRs that are not yet in the kernel-provided header. */ 149 #define MSR_RAPL_PWR_UNIT 0xc0010299 150 #define MSR_CORE_ENERGY_STAT 0xc001029a 151 #define MSR_PKG_ENERGY_STAT 0xc001029b 152 153 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 154 155 /* 156 * buffer size used by sscanf() for added column names 157 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters 158 */ 159 #define NAME_BYTES 20 160 #define PATH_BYTES 128 161 162 int backwards_count; 163 char *progname; 164 165 #define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */ 166 cpu_set_t *cpu_present_set, *cpu_affinity_set, *cpu_subset; 167 size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size; 168 #define MAX_ADDED_COUNTERS 8 169 #define MAX_ADDED_THREAD_COUNTERS 24 170 #define BITMASK_SIZE 32 171 172 struct thread_data { 173 struct timeval tv_begin; 174 struct timeval tv_end; 175 struct timeval tv_delta; 176 unsigned long long tsc; 177 unsigned long long aperf; 178 unsigned long long mperf; 179 unsigned long long c1; 180 unsigned long long instr_count; 181 unsigned long long irq_count; 182 unsigned int smi_count; 183 unsigned int cpu_id; 184 unsigned int apic_id; 185 unsigned int x2apic_id; 186 unsigned int flags; 187 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2 188 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 189 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS]; 190 } *thread_even, *thread_odd; 191 192 struct core_data { 193 unsigned long long c3; 194 unsigned long long c6; 195 unsigned long long c7; 196 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */ 197 unsigned int core_temp_c; 198 unsigned int core_energy; /* MSR_CORE_ENERGY_STAT */ 199 unsigned int core_id; 200 unsigned long long counter[MAX_ADDED_COUNTERS]; 201 } *core_even, *core_odd; 202 203 struct pkg_data { 204 unsigned long long pc2; 205 unsigned long long pc3; 206 unsigned long long pc6; 207 unsigned long long pc7; 208 unsigned long long pc8; 209 unsigned long long pc9; 210 unsigned long long pc10; 211 unsigned long long cpu_lpi; 212 unsigned long long sys_lpi; 213 unsigned long long pkg_wtd_core_c0; 214 unsigned long long pkg_any_core_c0; 215 unsigned long long pkg_any_gfxe_c0; 216 unsigned long long pkg_both_core_gfxe_c0; 217 long long gfx_rc6_ms; 218 unsigned int gfx_mhz; 219 unsigned int gfx_act_mhz; 220 unsigned int package_id; 221 unsigned long long energy_pkg; /* MSR_PKG_ENERGY_STATUS */ 222 unsigned long long energy_dram; /* MSR_DRAM_ENERGY_STATUS */ 223 unsigned long long energy_cores; /* MSR_PP0_ENERGY_STATUS */ 224 unsigned long long energy_gfx; /* MSR_PP1_ENERGY_STATUS */ 225 unsigned long long rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ 226 unsigned long long rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ 227 unsigned int pkg_temp_c; 228 unsigned long long counter[MAX_ADDED_COUNTERS]; 229 } *package_even, *package_odd; 230 231 #define ODD_COUNTERS thread_odd, core_odd, package_odd 232 #define EVEN_COUNTERS thread_even, core_even, package_even 233 234 #define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \ 235 ((thread_base) + \ 236 ((pkg_no) * \ 237 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \ 238 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \ 239 ((core_no) * topo.threads_per_core) + \ 240 (thread_no)) 241 242 #define GET_CORE(core_base, core_no, node_no, pkg_no) \ 243 ((core_base) + \ 244 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \ 245 ((node_no) * topo.cores_per_node) + \ 246 (core_no)) 247 248 249 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) 250 251 enum counter_scope {SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE}; 252 enum counter_type {COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC}; 253 enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT}; 254 255 struct msr_counter { 256 unsigned int msr_num; 257 char name[NAME_BYTES]; 258 char path[PATH_BYTES]; 259 unsigned int width; 260 enum counter_type type; 261 enum counter_format format; 262 struct msr_counter *next; 263 unsigned int flags; 264 #define FLAGS_HIDE (1 << 0) 265 #define FLAGS_SHOW (1 << 1) 266 #define SYSFS_PERCPU (1 << 1) 267 }; 268 269 /* 270 * The accumulated sum of MSR is defined as a monotonic 271 * increasing MSR, it will be accumulated periodically, 272 * despite its register's bit width. 273 */ 274 enum { 275 IDX_PKG_ENERGY, 276 IDX_DRAM_ENERGY, 277 IDX_PP0_ENERGY, 278 IDX_PP1_ENERGY, 279 IDX_PKG_PERF, 280 IDX_DRAM_PERF, 281 IDX_COUNT, 282 }; 283 284 int get_msr_sum(int cpu, off_t offset, unsigned long long *msr); 285 286 struct msr_sum_array { 287 /* get_msr_sum() = sum + (get_msr() - last) */ 288 struct { 289 /*The accumulated MSR value is updated by the timer*/ 290 unsigned long long sum; 291 /*The MSR footprint recorded in last timer*/ 292 unsigned long long last; 293 } entries[IDX_COUNT]; 294 }; 295 296 /* The percpu MSR sum array.*/ 297 struct msr_sum_array *per_cpu_msr_sum; 298 299 int idx_to_offset(int idx) 300 { 301 int offset; 302 303 switch (idx) { 304 case IDX_PKG_ENERGY: 305 offset = MSR_PKG_ENERGY_STATUS; 306 break; 307 case IDX_DRAM_ENERGY: 308 offset = MSR_DRAM_ENERGY_STATUS; 309 break; 310 case IDX_PP0_ENERGY: 311 offset = MSR_PP0_ENERGY_STATUS; 312 break; 313 case IDX_PP1_ENERGY: 314 offset = MSR_PP1_ENERGY_STATUS; 315 break; 316 case IDX_PKG_PERF: 317 offset = MSR_PKG_PERF_STATUS; 318 break; 319 case IDX_DRAM_PERF: 320 offset = MSR_DRAM_PERF_STATUS; 321 break; 322 default: 323 offset = -1; 324 } 325 return offset; 326 } 327 328 int offset_to_idx(int offset) 329 { 330 int idx; 331 332 switch (offset) { 333 case MSR_PKG_ENERGY_STATUS: 334 idx = IDX_PKG_ENERGY; 335 break; 336 case MSR_DRAM_ENERGY_STATUS: 337 idx = IDX_DRAM_ENERGY; 338 break; 339 case MSR_PP0_ENERGY_STATUS: 340 idx = IDX_PP0_ENERGY; 341 break; 342 case MSR_PP1_ENERGY_STATUS: 343 idx = IDX_PP1_ENERGY; 344 break; 345 case MSR_PKG_PERF_STATUS: 346 idx = IDX_PKG_PERF; 347 break; 348 case MSR_DRAM_PERF_STATUS: 349 idx = IDX_DRAM_PERF; 350 break; 351 default: 352 idx = -1; 353 } 354 return idx; 355 } 356 357 int idx_valid(int idx) 358 { 359 switch (idx) { 360 case IDX_PKG_ENERGY: 361 return do_rapl & RAPL_PKG; 362 case IDX_DRAM_ENERGY: 363 return do_rapl & RAPL_DRAM; 364 case IDX_PP0_ENERGY: 365 return do_rapl & RAPL_CORES_ENERGY_STATUS; 366 case IDX_PP1_ENERGY: 367 return do_rapl & RAPL_GFX; 368 case IDX_PKG_PERF: 369 return do_rapl & RAPL_PKG_PERF_STATUS; 370 case IDX_DRAM_PERF: 371 return do_rapl & RAPL_DRAM_PERF_STATUS; 372 default: 373 return 0; 374 } 375 } 376 struct sys_counters { 377 unsigned int added_thread_counters; 378 unsigned int added_core_counters; 379 unsigned int added_package_counters; 380 struct msr_counter *tp; 381 struct msr_counter *cp; 382 struct msr_counter *pp; 383 } sys; 384 385 struct system_summary { 386 struct thread_data threads; 387 struct core_data cores; 388 struct pkg_data packages; 389 } average; 390 391 struct cpu_topology { 392 int physical_package_id; 393 int die_id; 394 int logical_cpu_id; 395 int physical_node_id; 396 int logical_node_id; /* 0-based count within the package */ 397 int physical_core_id; 398 int thread_id; 399 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */ 400 } *cpus; 401 402 struct topo_params { 403 int num_packages; 404 int num_die; 405 int num_cpus; 406 int num_cores; 407 int max_cpu_num; 408 int max_node_num; 409 int nodes_per_pkg; 410 int cores_per_node; 411 int threads_per_core; 412 } topo; 413 414 struct timeval tv_even, tv_odd, tv_delta; 415 416 int *irq_column_2_cpu; /* /proc/interrupts column numbers */ 417 int *irqs_per_cpu; /* indexed by cpu_num */ 418 419 void setup_all_buffers(void); 420 421 char *sys_lpi_file; 422 char *sys_lpi_file_sysfs = "/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us"; 423 char *sys_lpi_file_debugfs = "/sys/kernel/debug/pmc_core/slp_s0_residency_usec"; 424 425 int cpu_is_not_present(int cpu) 426 { 427 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); 428 } 429 /* 430 * run func(thread, core, package) in topology order 431 * skip non-present cpus 432 */ 433 434 int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *), 435 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) 436 { 437 int retval, pkg_no, core_no, thread_no, node_no; 438 439 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 440 for (node_no = 0; node_no < topo.nodes_per_pkg; node_no++) { 441 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) { 442 for (thread_no = 0; thread_no < 443 topo.threads_per_core; ++thread_no) { 444 struct thread_data *t; 445 struct core_data *c; 446 struct pkg_data *p; 447 448 t = GET_THREAD(thread_base, thread_no, 449 core_no, node_no, 450 pkg_no); 451 452 if (cpu_is_not_present(t->cpu_id)) 453 continue; 454 455 c = GET_CORE(core_base, core_no, 456 node_no, pkg_no); 457 p = GET_PKG(pkg_base, pkg_no); 458 459 retval = func(t, c, p); 460 if (retval) 461 return retval; 462 } 463 } 464 } 465 } 466 return 0; 467 } 468 469 int cpu_migrate(int cpu) 470 { 471 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 472 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); 473 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) 474 return -1; 475 else 476 return 0; 477 } 478 int get_msr_fd(int cpu) 479 { 480 char pathname[32]; 481 int fd; 482 483 fd = fd_percpu[cpu]; 484 485 if (fd) 486 return fd; 487 488 sprintf(pathname, "/dev/cpu/%d/msr", cpu); 489 fd = open(pathname, O_RDONLY); 490 if (fd < 0) 491 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); 492 493 fd_percpu[cpu] = fd; 494 495 return fd; 496 } 497 498 static long perf_event_open(struct perf_event_attr *hw_event, pid_t pid, int cpu, int group_fd, unsigned long flags) 499 { 500 return syscall(__NR_perf_event_open, hw_event, pid, cpu, group_fd, flags); 501 } 502 503 static int perf_instr_count_open(int cpu_num) 504 { 505 struct perf_event_attr pea; 506 int fd; 507 508 memset(&pea, 0, sizeof(struct perf_event_attr)); 509 pea.type = PERF_TYPE_HARDWARE; 510 pea.size = sizeof(struct perf_event_attr); 511 pea.config = PERF_COUNT_HW_INSTRUCTIONS; 512 513 /* counter for cpu_num, including user + kernel and all processes */ 514 fd = perf_event_open(&pea, -1, cpu_num, -1, 0); 515 if (fd == -1) 516 err(-1, "cpu%d: perf instruction counter\n", cpu_num); 517 518 return fd; 519 } 520 521 int get_instr_count_fd(int cpu) 522 { 523 if (fd_instr_count_percpu[cpu]) 524 return fd_instr_count_percpu[cpu]; 525 526 fd_instr_count_percpu[cpu] = perf_instr_count_open(cpu); 527 528 return fd_instr_count_percpu[cpu]; 529 } 530 531 int get_msr(int cpu, off_t offset, unsigned long long *msr) 532 { 533 ssize_t retval; 534 535 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); 536 537 if (retval != sizeof *msr) 538 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset); 539 540 return 0; 541 } 542 543 /* 544 * This list matches the column headers, except 545 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time 546 * 2. Core and CPU are moved to the end, we can't have strings that contain them 547 * matching on them for --show and --hide. 548 */ 549 struct msr_counter bic[] = { 550 { 0x0, "usec" }, 551 { 0x0, "Time_Of_Day_Seconds" }, 552 { 0x0, "Package" }, 553 { 0x0, "Node" }, 554 { 0x0, "Avg_MHz" }, 555 { 0x0, "Busy%" }, 556 { 0x0, "Bzy_MHz" }, 557 { 0x0, "TSC_MHz" }, 558 { 0x0, "IRQ" }, 559 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL}, 560 { 0x0, "sysfs" }, 561 { 0x0, "CPU%c1" }, 562 { 0x0, "CPU%c3" }, 563 { 0x0, "CPU%c6" }, 564 { 0x0, "CPU%c7" }, 565 { 0x0, "ThreadC" }, 566 { 0x0, "CoreTmp" }, 567 { 0x0, "CoreCnt" }, 568 { 0x0, "PkgTmp" }, 569 { 0x0, "GFX%rc6" }, 570 { 0x0, "GFXMHz" }, 571 { 0x0, "Pkg%pc2" }, 572 { 0x0, "Pkg%pc3" }, 573 { 0x0, "Pkg%pc6" }, 574 { 0x0, "Pkg%pc7" }, 575 { 0x0, "Pkg%pc8" }, 576 { 0x0, "Pkg%pc9" }, 577 { 0x0, "Pk%pc10" }, 578 { 0x0, "CPU%LPI" }, 579 { 0x0, "SYS%LPI" }, 580 { 0x0, "PkgWatt" }, 581 { 0x0, "CorWatt" }, 582 { 0x0, "GFXWatt" }, 583 { 0x0, "PkgCnt" }, 584 { 0x0, "RAMWatt" }, 585 { 0x0, "PKG_%" }, 586 { 0x0, "RAM_%" }, 587 { 0x0, "Pkg_J" }, 588 { 0x0, "Cor_J" }, 589 { 0x0, "GFX_J" }, 590 { 0x0, "RAM_J" }, 591 { 0x0, "Mod%c6" }, 592 { 0x0, "Totl%C0" }, 593 { 0x0, "Any%C0" }, 594 { 0x0, "GFX%C0" }, 595 { 0x0, "CPUGFX%" }, 596 { 0x0, "Core" }, 597 { 0x0, "CPU" }, 598 { 0x0, "APIC" }, 599 { 0x0, "X2APIC" }, 600 { 0x0, "Die" }, 601 { 0x0, "GFXAMHz" }, 602 { 0x0, "IPC" }, 603 }; 604 605 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter)) 606 #define BIC_USEC (1ULL << 0) 607 #define BIC_TOD (1ULL << 1) 608 #define BIC_Package (1ULL << 2) 609 #define BIC_Node (1ULL << 3) 610 #define BIC_Avg_MHz (1ULL << 4) 611 #define BIC_Busy (1ULL << 5) 612 #define BIC_Bzy_MHz (1ULL << 6) 613 #define BIC_TSC_MHz (1ULL << 7) 614 #define BIC_IRQ (1ULL << 8) 615 #define BIC_SMI (1ULL << 9) 616 #define BIC_sysfs (1ULL << 10) 617 #define BIC_CPU_c1 (1ULL << 11) 618 #define BIC_CPU_c3 (1ULL << 12) 619 #define BIC_CPU_c6 (1ULL << 13) 620 #define BIC_CPU_c7 (1ULL << 14) 621 #define BIC_ThreadC (1ULL << 15) 622 #define BIC_CoreTmp (1ULL << 16) 623 #define BIC_CoreCnt (1ULL << 17) 624 #define BIC_PkgTmp (1ULL << 18) 625 #define BIC_GFX_rc6 (1ULL << 19) 626 #define BIC_GFXMHz (1ULL << 20) 627 #define BIC_Pkgpc2 (1ULL << 21) 628 #define BIC_Pkgpc3 (1ULL << 22) 629 #define BIC_Pkgpc6 (1ULL << 23) 630 #define BIC_Pkgpc7 (1ULL << 24) 631 #define BIC_Pkgpc8 (1ULL << 25) 632 #define BIC_Pkgpc9 (1ULL << 26) 633 #define BIC_Pkgpc10 (1ULL << 27) 634 #define BIC_CPU_LPI (1ULL << 28) 635 #define BIC_SYS_LPI (1ULL << 29) 636 #define BIC_PkgWatt (1ULL << 30) 637 #define BIC_CorWatt (1ULL << 31) 638 #define BIC_GFXWatt (1ULL << 32) 639 #define BIC_PkgCnt (1ULL << 33) 640 #define BIC_RAMWatt (1ULL << 34) 641 #define BIC_PKG__ (1ULL << 35) 642 #define BIC_RAM__ (1ULL << 36) 643 #define BIC_Pkg_J (1ULL << 37) 644 #define BIC_Cor_J (1ULL << 38) 645 #define BIC_GFX_J (1ULL << 39) 646 #define BIC_RAM_J (1ULL << 40) 647 #define BIC_Mod_c6 (1ULL << 41) 648 #define BIC_Totl_c0 (1ULL << 42) 649 #define BIC_Any_c0 (1ULL << 43) 650 #define BIC_GFX_c0 (1ULL << 44) 651 #define BIC_CPUGFX (1ULL << 45) 652 #define BIC_Core (1ULL << 46) 653 #define BIC_CPU (1ULL << 47) 654 #define BIC_APIC (1ULL << 48) 655 #define BIC_X2APIC (1ULL << 49) 656 #define BIC_Die (1ULL << 50) 657 #define BIC_GFXACTMHz (1ULL << 51) 658 #define BIC_IPC (1ULL << 52) 659 660 #define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC) 661 662 unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT); 663 unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC; 664 665 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME) 666 #define DO_BIC_READ(COUNTER_NAME) (bic_present & COUNTER_NAME) 667 #define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME) 668 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT) 669 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT) 670 #define BIC_IS_ENABLED(COUNTER_BIT) (bic_enabled & COUNTER_BIT) 671 672 673 #define MAX_DEFERRED 16 674 char *deferred_skip_names[MAX_DEFERRED]; 675 int deferred_skip_index; 676 677 /* 678 * HIDE_LIST - hide this list of counters, show the rest [default] 679 * SHOW_LIST - show this list of counters, hide the rest 680 */ 681 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST; 682 683 void help(void) 684 { 685 fprintf(outf, 686 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" 687 "\n" 688 "Turbostat forks the specified COMMAND and prints statistics\n" 689 "when COMMAND completes.\n" 690 "If no COMMAND is specified, turbostat wakes every 5-seconds\n" 691 "to print statistics, until interrupted.\n" 692 " -a, --add add a counter\n" 693 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n" 694 " -c, --cpu cpu-set limit output to summary plus cpu-set:\n" 695 " {core | package | j,k,l..m,n-p }\n" 696 " -d, --debug displays usec, Time_Of_Day_Seconds and more debugging\n" 697 " -D, --Dump displays the raw counter values\n" 698 " -e, --enable [all | column]\n" 699 " shows all or the specified disabled column\n" 700 " -H, --hide [column|column,column,...]\n" 701 " hide the specified column(s)\n" 702 " -i, --interval sec.subsec\n" 703 " Override default 5-second measurement interval\n" 704 " -J, --Joules displays energy in Joules instead of Watts\n" 705 " -l, --list list column headers only\n" 706 " -n, --num_iterations num\n" 707 " number of the measurement iterations\n" 708 " -o, --out file\n" 709 " create or truncate \"file\" for all output\n" 710 " -q, --quiet skip decoding system configuration header\n" 711 " -s, --show [column|column,column,...]\n" 712 " show only the specified column(s)\n" 713 " -S, --Summary\n" 714 " limits output to 1-line system summary per interval\n" 715 " -T, --TCC temperature\n" 716 " sets the Thermal Control Circuit temperature in\n" 717 " degrees Celsius\n" 718 " -h, --help print this help message\n" 719 " -v, --version print version information\n" 720 "\n" 721 "For more help, run \"man turbostat\"\n"); 722 } 723 724 /* 725 * bic_lookup 726 * for all the strings in comma separate name_list, 727 * set the approprate bit in return value. 728 */ 729 unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode) 730 { 731 int i; 732 unsigned long long retval = 0; 733 734 while (name_list) { 735 char *comma; 736 737 comma = strchr(name_list, ','); 738 739 if (comma) 740 *comma = '\0'; 741 742 if (!strcmp(name_list, "all")) 743 return ~0; 744 745 for (i = 0; i < MAX_BIC; ++i) { 746 if (!strcmp(name_list, bic[i].name)) { 747 retval |= (1ULL << i); 748 break; 749 } 750 } 751 if (i == MAX_BIC) { 752 if (mode == SHOW_LIST) { 753 fprintf(stderr, "Invalid counter name: %s\n", name_list); 754 exit(-1); 755 } 756 deferred_skip_names[deferred_skip_index++] = name_list; 757 if (debug) 758 fprintf(stderr, "deferred \"%s\"\n", name_list); 759 if (deferred_skip_index >= MAX_DEFERRED) { 760 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n", 761 MAX_DEFERRED, name_list); 762 help(); 763 exit(1); 764 } 765 } 766 767 name_list = comma; 768 if (name_list) 769 name_list++; 770 771 } 772 return retval; 773 } 774 775 776 void print_header(char *delim) 777 { 778 struct msr_counter *mp; 779 int printed = 0; 780 781 if (DO_BIC(BIC_USEC)) 782 outp += sprintf(outp, "%susec", (printed++ ? delim : "")); 783 if (DO_BIC(BIC_TOD)) 784 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : "")); 785 if (DO_BIC(BIC_Package)) 786 outp += sprintf(outp, "%sPackage", (printed++ ? delim : "")); 787 if (DO_BIC(BIC_Die)) 788 outp += sprintf(outp, "%sDie", (printed++ ? delim : "")); 789 if (DO_BIC(BIC_Node)) 790 outp += sprintf(outp, "%sNode", (printed++ ? delim : "")); 791 if (DO_BIC(BIC_Core)) 792 outp += sprintf(outp, "%sCore", (printed++ ? delim : "")); 793 if (DO_BIC(BIC_CPU)) 794 outp += sprintf(outp, "%sCPU", (printed++ ? delim : "")); 795 if (DO_BIC(BIC_APIC)) 796 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : "")); 797 if (DO_BIC(BIC_X2APIC)) 798 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : "")); 799 if (DO_BIC(BIC_Avg_MHz)) 800 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : "")); 801 if (DO_BIC(BIC_Busy)) 802 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : "")); 803 if (DO_BIC(BIC_Bzy_MHz)) 804 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : "")); 805 if (DO_BIC(BIC_TSC_MHz)) 806 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : "")); 807 808 if (DO_BIC(BIC_IPC)) 809 outp += sprintf(outp, "%sIPC", (printed++ ? delim : "")); 810 811 if (DO_BIC(BIC_IRQ)) { 812 if (sums_need_wide_columns) 813 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : "")); 814 else 815 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : "")); 816 } 817 818 if (DO_BIC(BIC_SMI)) 819 outp += sprintf(outp, "%sSMI", (printed++ ? delim : "")); 820 821 for (mp = sys.tp; mp; mp = mp->next) { 822 823 if (mp->format == FORMAT_RAW) { 824 if (mp->width == 64) 825 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name); 826 else 827 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name); 828 } else { 829 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 830 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name); 831 else 832 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name); 833 } 834 } 835 836 if (DO_BIC(BIC_CPU_c1)) 837 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : "")); 838 if (DO_BIC(BIC_CPU_c3)) 839 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : "")); 840 if (DO_BIC(BIC_CPU_c6)) 841 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : "")); 842 if (DO_BIC(BIC_CPU_c7)) 843 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : "")); 844 845 if (DO_BIC(BIC_Mod_c6)) 846 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : "")); 847 848 if (DO_BIC(BIC_CoreTmp)) 849 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : "")); 850 851 if (do_rapl && !rapl_joules) { 852 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY)) 853 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 854 } else if (do_rapl && rapl_joules) { 855 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY)) 856 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 857 } 858 859 for (mp = sys.cp; mp; mp = mp->next) { 860 if (mp->format == FORMAT_RAW) { 861 if (mp->width == 64) 862 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 863 else 864 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 865 } else { 866 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 867 outp += sprintf(outp, "%s%8s", delim, mp->name); 868 else 869 outp += sprintf(outp, "%s%s", delim, mp->name); 870 } 871 } 872 873 if (DO_BIC(BIC_PkgTmp)) 874 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : "")); 875 876 if (DO_BIC(BIC_GFX_rc6)) 877 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : "")); 878 879 if (DO_BIC(BIC_GFXMHz)) 880 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : "")); 881 882 if (DO_BIC(BIC_GFXACTMHz)) 883 outp += sprintf(outp, "%sGFXAMHz", (printed++ ? delim : "")); 884 885 if (DO_BIC(BIC_Totl_c0)) 886 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : "")); 887 if (DO_BIC(BIC_Any_c0)) 888 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : "")); 889 if (DO_BIC(BIC_GFX_c0)) 890 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : "")); 891 if (DO_BIC(BIC_CPUGFX)) 892 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : "")); 893 894 if (DO_BIC(BIC_Pkgpc2)) 895 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : "")); 896 if (DO_BIC(BIC_Pkgpc3)) 897 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : "")); 898 if (DO_BIC(BIC_Pkgpc6)) 899 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : "")); 900 if (DO_BIC(BIC_Pkgpc7)) 901 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : "")); 902 if (DO_BIC(BIC_Pkgpc8)) 903 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : "")); 904 if (DO_BIC(BIC_Pkgpc9)) 905 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : "")); 906 if (DO_BIC(BIC_Pkgpc10)) 907 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : "")); 908 if (DO_BIC(BIC_CPU_LPI)) 909 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : "")); 910 if (DO_BIC(BIC_SYS_LPI)) 911 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : "")); 912 913 if (do_rapl && !rapl_joules) { 914 if (DO_BIC(BIC_PkgWatt)) 915 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : "")); 916 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 917 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 918 if (DO_BIC(BIC_GFXWatt)) 919 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : "")); 920 if (DO_BIC(BIC_RAMWatt)) 921 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : "")); 922 if (DO_BIC(BIC_PKG__)) 923 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 924 if (DO_BIC(BIC_RAM__)) 925 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 926 } else if (do_rapl && rapl_joules) { 927 if (DO_BIC(BIC_Pkg_J)) 928 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : "")); 929 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 930 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 931 if (DO_BIC(BIC_GFX_J)) 932 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : "")); 933 if (DO_BIC(BIC_RAM_J)) 934 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : "")); 935 if (DO_BIC(BIC_PKG__)) 936 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 937 if (DO_BIC(BIC_RAM__)) 938 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 939 } 940 for (mp = sys.pp; mp; mp = mp->next) { 941 if (mp->format == FORMAT_RAW) { 942 if (mp->width == 64) 943 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 944 else 945 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 946 } else { 947 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 948 outp += sprintf(outp, "%s%8s", delim, mp->name); 949 else 950 outp += sprintf(outp, "%s%s", delim, mp->name); 951 } 952 } 953 954 outp += sprintf(outp, "\n"); 955 } 956 957 int dump_counters(struct thread_data *t, struct core_data *c, 958 struct pkg_data *p) 959 { 960 int i; 961 struct msr_counter *mp; 962 963 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); 964 965 if (t) { 966 outp += sprintf(outp, "CPU: %d flags 0x%x\n", 967 t->cpu_id, t->flags); 968 outp += sprintf(outp, "TSC: %016llX\n", t->tsc); 969 outp += sprintf(outp, "aperf: %016llX\n", t->aperf); 970 outp += sprintf(outp, "mperf: %016llX\n", t->mperf); 971 outp += sprintf(outp, "c1: %016llX\n", t->c1); 972 973 if (DO_BIC(BIC_IPC)) 974 outp += sprintf(outp, "IPC: %lld\n", t->instr_count); 975 976 if (DO_BIC(BIC_IRQ)) 977 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count); 978 if (DO_BIC(BIC_SMI)) 979 outp += sprintf(outp, "SMI: %d\n", t->smi_count); 980 981 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 982 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", 983 i, mp->msr_num, t->counter[i]); 984 } 985 } 986 987 if (c) { 988 outp += sprintf(outp, "core: %d\n", c->core_id); 989 outp += sprintf(outp, "c3: %016llX\n", c->c3); 990 outp += sprintf(outp, "c6: %016llX\n", c->c6); 991 outp += sprintf(outp, "c7: %016llX\n", c->c7); 992 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); 993 outp += sprintf(outp, "Joules: %0X\n", c->core_energy); 994 995 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 996 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", 997 i, mp->msr_num, c->counter[i]); 998 } 999 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us); 1000 } 1001 1002 if (p) { 1003 outp += sprintf(outp, "package: %d\n", p->package_id); 1004 1005 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); 1006 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); 1007 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); 1008 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); 1009 1010 outp += sprintf(outp, "pc2: %016llX\n", p->pc2); 1011 if (DO_BIC(BIC_Pkgpc3)) 1012 outp += sprintf(outp, "pc3: %016llX\n", p->pc3); 1013 if (DO_BIC(BIC_Pkgpc6)) 1014 outp += sprintf(outp, "pc6: %016llX\n", p->pc6); 1015 if (DO_BIC(BIC_Pkgpc7)) 1016 outp += sprintf(outp, "pc7: %016llX\n", p->pc7); 1017 outp += sprintf(outp, "pc8: %016llX\n", p->pc8); 1018 outp += sprintf(outp, "pc9: %016llX\n", p->pc9); 1019 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 1020 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi); 1021 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi); 1022 outp += sprintf(outp, "Joules PKG: %0llX\n", p->energy_pkg); 1023 outp += sprintf(outp, "Joules COR: %0llX\n", p->energy_cores); 1024 outp += sprintf(outp, "Joules GFX: %0llX\n", p->energy_gfx); 1025 outp += sprintf(outp, "Joules RAM: %0llX\n", p->energy_dram); 1026 outp += sprintf(outp, "Throttle PKG: %0llX\n", 1027 p->rapl_pkg_perf_status); 1028 outp += sprintf(outp, "Throttle RAM: %0llX\n", 1029 p->rapl_dram_perf_status); 1030 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); 1031 1032 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1033 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", 1034 i, mp->msr_num, p->counter[i]); 1035 } 1036 } 1037 1038 outp += sprintf(outp, "\n"); 1039 1040 return 0; 1041 } 1042 1043 /* 1044 * column formatting convention & formats 1045 */ 1046 int format_counters(struct thread_data *t, struct core_data *c, 1047 struct pkg_data *p) 1048 { 1049 double interval_float, tsc; 1050 char *fmt8; 1051 int i; 1052 struct msr_counter *mp; 1053 char *delim = "\t"; 1054 int printed = 0; 1055 1056 /* if showing only 1st thread in core and this isn't one, bail out */ 1057 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1058 return 0; 1059 1060 /* if showing only 1st thread in pkg and this isn't one, bail out */ 1061 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1062 return 0; 1063 1064 /*if not summary line and --cpu is used */ 1065 if ((t != &average.threads) && 1066 (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset))) 1067 return 0; 1068 1069 if (DO_BIC(BIC_USEC)) { 1070 /* on each row, print how many usec each timestamp took to gather */ 1071 struct timeval tv; 1072 1073 timersub(&t->tv_end, &t->tv_begin, &tv); 1074 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec); 1075 } 1076 1077 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */ 1078 if (DO_BIC(BIC_TOD)) 1079 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec); 1080 1081 interval_float = t->tv_delta.tv_sec + t->tv_delta.tv_usec/1000000.0; 1082 1083 tsc = t->tsc * tsc_tweak; 1084 1085 /* topo columns, print blanks on 1st (average) line */ 1086 if (t == &average.threads) { 1087 if (DO_BIC(BIC_Package)) 1088 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1089 if (DO_BIC(BIC_Die)) 1090 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1091 if (DO_BIC(BIC_Node)) 1092 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1093 if (DO_BIC(BIC_Core)) 1094 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1095 if (DO_BIC(BIC_CPU)) 1096 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1097 if (DO_BIC(BIC_APIC)) 1098 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1099 if (DO_BIC(BIC_X2APIC)) 1100 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1101 } else { 1102 if (DO_BIC(BIC_Package)) { 1103 if (p) 1104 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id); 1105 else 1106 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1107 } 1108 if (DO_BIC(BIC_Die)) { 1109 if (c) 1110 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), cpus[t->cpu_id].die_id); 1111 else 1112 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1113 } 1114 if (DO_BIC(BIC_Node)) { 1115 if (t) 1116 outp += sprintf(outp, "%s%d", 1117 (printed++ ? delim : ""), 1118 cpus[t->cpu_id].physical_node_id); 1119 else 1120 outp += sprintf(outp, "%s-", 1121 (printed++ ? delim : "")); 1122 } 1123 if (DO_BIC(BIC_Core)) { 1124 if (c) 1125 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id); 1126 else 1127 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 1128 } 1129 if (DO_BIC(BIC_CPU)) 1130 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id); 1131 if (DO_BIC(BIC_APIC)) 1132 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id); 1133 if (DO_BIC(BIC_X2APIC)) 1134 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id); 1135 } 1136 1137 if (DO_BIC(BIC_Avg_MHz)) 1138 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1139 1.0 / units * t->aperf / interval_float); 1140 1141 if (DO_BIC(BIC_Busy)) 1142 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf/tsc); 1143 1144 if (DO_BIC(BIC_Bzy_MHz)) { 1145 if (has_base_hz) 1146 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf); 1147 else 1148 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1149 tsc / units * t->aperf / t->mperf / interval_float); 1150 } 1151 1152 if (DO_BIC(BIC_TSC_MHz)) 1153 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc/units/interval_float); 1154 1155 if (DO_BIC(BIC_IPC)) 1156 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1.0 * t->instr_count / t->aperf); 1157 1158 /* IRQ */ 1159 if (DO_BIC(BIC_IRQ)) { 1160 if (sums_need_wide_columns) 1161 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count); 1162 else 1163 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count); 1164 } 1165 1166 /* SMI */ 1167 if (DO_BIC(BIC_SMI)) 1168 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count); 1169 1170 /* Added counters */ 1171 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1172 if (mp->format == FORMAT_RAW) { 1173 if (mp->width == 32) 1174 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) t->counter[i]); 1175 else 1176 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]); 1177 } else if (mp->format == FORMAT_DELTA) { 1178 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1179 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]); 1180 else 1181 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]); 1182 } else if (mp->format == FORMAT_PERCENT) { 1183 if (mp->type == COUNTER_USEC) 1184 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), t->counter[i]/interval_float/10000); 1185 else 1186 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i]/tsc); 1187 } 1188 } 1189 1190 /* C1 */ 1191 if (DO_BIC(BIC_CPU_c1)) 1192 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1/tsc); 1193 1194 1195 /* print per-core data only for 1st thread in core */ 1196 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1197 goto done; 1198 1199 if (DO_BIC(BIC_CPU_c3)) 1200 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3/tsc); 1201 if (DO_BIC(BIC_CPU_c6)) 1202 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6/tsc); 1203 if (DO_BIC(BIC_CPU_c7)) 1204 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7/tsc); 1205 1206 /* Mod%c6 */ 1207 if (DO_BIC(BIC_Mod_c6)) 1208 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc); 1209 1210 if (DO_BIC(BIC_CoreTmp)) 1211 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c); 1212 1213 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1214 if (mp->format == FORMAT_RAW) { 1215 if (mp->width == 32) 1216 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) c->counter[i]); 1217 else 1218 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]); 1219 } else if (mp->format == FORMAT_DELTA) { 1220 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1221 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]); 1222 else 1223 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]); 1224 } else if (mp->format == FORMAT_PERCENT) { 1225 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i]/tsc); 1226 } 1227 } 1228 1229 fmt8 = "%s%.2f"; 1230 1231 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY)) 1232 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units / interval_float); 1233 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY)) 1234 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units); 1235 1236 /* print per-package data only for 1st core in package */ 1237 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1238 goto done; 1239 1240 /* PkgTmp */ 1241 if (DO_BIC(BIC_PkgTmp)) 1242 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c); 1243 1244 /* GFXrc6 */ 1245 if (DO_BIC(BIC_GFX_rc6)) { 1246 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */ 1247 outp += sprintf(outp, "%s**.**", (printed++ ? delim : "")); 1248 } else { 1249 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1250 p->gfx_rc6_ms / 10.0 / interval_float); 1251 } 1252 } 1253 1254 /* GFXMHz */ 1255 if (DO_BIC(BIC_GFXMHz)) 1256 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz); 1257 1258 /* GFXACTMHz */ 1259 if (DO_BIC(BIC_GFXACTMHz)) 1260 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_act_mhz); 1261 1262 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ 1263 if (DO_BIC(BIC_Totl_c0)) 1264 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0/tsc); 1265 if (DO_BIC(BIC_Any_c0)) 1266 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0/tsc); 1267 if (DO_BIC(BIC_GFX_c0)) 1268 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0/tsc); 1269 if (DO_BIC(BIC_CPUGFX)) 1270 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0/tsc); 1271 1272 if (DO_BIC(BIC_Pkgpc2)) 1273 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2/tsc); 1274 if (DO_BIC(BIC_Pkgpc3)) 1275 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3/tsc); 1276 if (DO_BIC(BIC_Pkgpc6)) 1277 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6/tsc); 1278 if (DO_BIC(BIC_Pkgpc7)) 1279 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7/tsc); 1280 if (DO_BIC(BIC_Pkgpc8)) 1281 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8/tsc); 1282 if (DO_BIC(BIC_Pkgpc9)) 1283 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9/tsc); 1284 if (DO_BIC(BIC_Pkgpc10)) 1285 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10/tsc); 1286 1287 if (DO_BIC(BIC_CPU_LPI)) 1288 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float); 1289 if (DO_BIC(BIC_SYS_LPI)) 1290 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float); 1291 1292 if (DO_BIC(BIC_PkgWatt)) 1293 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float); 1294 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 1295 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float); 1296 if (DO_BIC(BIC_GFXWatt)) 1297 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float); 1298 if (DO_BIC(BIC_RAMWatt)) 1299 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units / interval_float); 1300 if (DO_BIC(BIC_Pkg_J)) 1301 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units); 1302 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 1303 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units); 1304 if (DO_BIC(BIC_GFX_J)) 1305 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units); 1306 if (DO_BIC(BIC_RAM_J)) 1307 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units); 1308 if (DO_BIC(BIC_PKG__)) 1309 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 1310 if (DO_BIC(BIC_RAM__)) 1311 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 1312 1313 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1314 if (mp->format == FORMAT_RAW) { 1315 if (mp->width == 32) 1316 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) p->counter[i]); 1317 else 1318 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]); 1319 } else if (mp->format == FORMAT_DELTA) { 1320 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1321 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]); 1322 else 1323 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]); 1324 } else if (mp->format == FORMAT_PERCENT) { 1325 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i]/tsc); 1326 } 1327 } 1328 1329 done: 1330 if (*(outp - 1) != '\n') 1331 outp += sprintf(outp, "\n"); 1332 1333 return 0; 1334 } 1335 1336 void flush_output_stdout(void) 1337 { 1338 FILE *filep; 1339 1340 if (outf == stderr) 1341 filep = stdout; 1342 else 1343 filep = outf; 1344 1345 fputs(output_buffer, filep); 1346 fflush(filep); 1347 1348 outp = output_buffer; 1349 } 1350 void flush_output_stderr(void) 1351 { 1352 fputs(output_buffer, outf); 1353 fflush(outf); 1354 outp = output_buffer; 1355 } 1356 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1357 { 1358 static int printed; 1359 1360 if (!printed || !summary_only) 1361 print_header("\t"); 1362 1363 format_counters(&average.threads, &average.cores, &average.packages); 1364 1365 printed = 1; 1366 1367 if (summary_only) 1368 return; 1369 1370 for_all_cpus(format_counters, t, c, p); 1371 } 1372 1373 #define DELTA_WRAP32(new, old) \ 1374 old = ((((unsigned long long)new << 32) - ((unsigned long long)old << 32)) >> 32); 1375 1376 int 1377 delta_package(struct pkg_data *new, struct pkg_data *old) 1378 { 1379 int i; 1380 struct msr_counter *mp; 1381 1382 1383 if (DO_BIC(BIC_Totl_c0)) 1384 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; 1385 if (DO_BIC(BIC_Any_c0)) 1386 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; 1387 if (DO_BIC(BIC_GFX_c0)) 1388 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; 1389 if (DO_BIC(BIC_CPUGFX)) 1390 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; 1391 1392 old->pc2 = new->pc2 - old->pc2; 1393 if (DO_BIC(BIC_Pkgpc3)) 1394 old->pc3 = new->pc3 - old->pc3; 1395 if (DO_BIC(BIC_Pkgpc6)) 1396 old->pc6 = new->pc6 - old->pc6; 1397 if (DO_BIC(BIC_Pkgpc7)) 1398 old->pc7 = new->pc7 - old->pc7; 1399 old->pc8 = new->pc8 - old->pc8; 1400 old->pc9 = new->pc9 - old->pc9; 1401 old->pc10 = new->pc10 - old->pc10; 1402 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi; 1403 old->sys_lpi = new->sys_lpi - old->sys_lpi; 1404 old->pkg_temp_c = new->pkg_temp_c; 1405 1406 /* flag an error when rc6 counter resets/wraps */ 1407 if (old->gfx_rc6_ms > new->gfx_rc6_ms) 1408 old->gfx_rc6_ms = -1; 1409 else 1410 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; 1411 1412 old->gfx_mhz = new->gfx_mhz; 1413 old->gfx_act_mhz = new->gfx_act_mhz; 1414 1415 old->energy_pkg = new->energy_pkg - old->energy_pkg; 1416 old->energy_cores = new->energy_cores - old->energy_cores; 1417 old->energy_gfx = new->energy_gfx - old->energy_gfx; 1418 old->energy_dram = new->energy_dram - old->energy_dram; 1419 old->rapl_pkg_perf_status = new->rapl_pkg_perf_status - old->rapl_pkg_perf_status; 1420 old->rapl_dram_perf_status = new->rapl_dram_perf_status - old->rapl_dram_perf_status; 1421 1422 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1423 if (mp->format == FORMAT_RAW) 1424 old->counter[i] = new->counter[i]; 1425 else 1426 old->counter[i] = new->counter[i] - old->counter[i]; 1427 } 1428 1429 return 0; 1430 } 1431 1432 void 1433 delta_core(struct core_data *new, struct core_data *old) 1434 { 1435 int i; 1436 struct msr_counter *mp; 1437 1438 old->c3 = new->c3 - old->c3; 1439 old->c6 = new->c6 - old->c6; 1440 old->c7 = new->c7 - old->c7; 1441 old->core_temp_c = new->core_temp_c; 1442 old->mc6_us = new->mc6_us - old->mc6_us; 1443 1444 DELTA_WRAP32(new->core_energy, old->core_energy); 1445 1446 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1447 if (mp->format == FORMAT_RAW) 1448 old->counter[i] = new->counter[i]; 1449 else 1450 old->counter[i] = new->counter[i] - old->counter[i]; 1451 } 1452 } 1453 1454 int soft_c1_residency_display(int bic) 1455 { 1456 if (!DO_BIC(BIC_CPU_c1) || use_c1_residency_msr) 1457 return 0; 1458 1459 return DO_BIC_READ(bic); 1460 } 1461 1462 /* 1463 * old = new - old 1464 */ 1465 int 1466 delta_thread(struct thread_data *new, struct thread_data *old, 1467 struct core_data *core_delta) 1468 { 1469 int i; 1470 struct msr_counter *mp; 1471 1472 /* we run cpuid just the 1st time, copy the results */ 1473 if (DO_BIC(BIC_APIC)) 1474 new->apic_id = old->apic_id; 1475 if (DO_BIC(BIC_X2APIC)) 1476 new->x2apic_id = old->x2apic_id; 1477 1478 /* 1479 * the timestamps from start of measurement interval are in "old" 1480 * the timestamp from end of measurement interval are in "new" 1481 * over-write old w/ new so we can print end of interval values 1482 */ 1483 1484 timersub(&new->tv_begin, &old->tv_begin, &old->tv_delta); 1485 old->tv_begin = new->tv_begin; 1486 old->tv_end = new->tv_end; 1487 1488 old->tsc = new->tsc - old->tsc; 1489 1490 /* check for TSC < 1 Mcycles over interval */ 1491 if (old->tsc < (1000 * 1000)) 1492 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" 1493 "You can disable all c-states by booting with \"idle=poll\"\n" 1494 "or just the deep ones with \"processor.max_cstate=1\""); 1495 1496 old->c1 = new->c1 - old->c1; 1497 1498 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || 1499 soft_c1_residency_display(BIC_Avg_MHz)) { 1500 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { 1501 old->aperf = new->aperf - old->aperf; 1502 old->mperf = new->mperf - old->mperf; 1503 } else { 1504 return -1; 1505 } 1506 } 1507 1508 1509 if (use_c1_residency_msr) { 1510 /* 1511 * Some models have a dedicated C1 residency MSR, 1512 * which should be more accurate than the derivation below. 1513 */ 1514 } else { 1515 /* 1516 * As counter collection is not atomic, 1517 * it is possible for mperf's non-halted cycles + idle states 1518 * to exceed TSC's all cycles: show c1 = 0% in that case. 1519 */ 1520 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak)) 1521 old->c1 = 0; 1522 else { 1523 /* normal case, derive c1 */ 1524 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3 1525 - core_delta->c6 - core_delta->c7; 1526 } 1527 } 1528 1529 if (old->mperf == 0) { 1530 if (debug > 1) 1531 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); 1532 old->mperf = 1; /* divide by 0 protection */ 1533 } 1534 1535 if (DO_BIC(BIC_IPC)) 1536 old->instr_count = new->instr_count - old->instr_count; 1537 1538 if (DO_BIC(BIC_IRQ)) 1539 old->irq_count = new->irq_count - old->irq_count; 1540 1541 if (DO_BIC(BIC_SMI)) 1542 old->smi_count = new->smi_count - old->smi_count; 1543 1544 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1545 if (mp->format == FORMAT_RAW) 1546 old->counter[i] = new->counter[i]; 1547 else 1548 old->counter[i] = new->counter[i] - old->counter[i]; 1549 } 1550 return 0; 1551 } 1552 1553 int delta_cpu(struct thread_data *t, struct core_data *c, 1554 struct pkg_data *p, struct thread_data *t2, 1555 struct core_data *c2, struct pkg_data *p2) 1556 { 1557 int retval = 0; 1558 1559 /* calculate core delta only for 1st thread in core */ 1560 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) 1561 delta_core(c, c2); 1562 1563 /* always calculate thread delta */ 1564 retval = delta_thread(t, t2, c2); /* c2 is core delta */ 1565 if (retval) 1566 return retval; 1567 1568 /* calculate package delta only for 1st core in package */ 1569 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) 1570 retval = delta_package(p, p2); 1571 1572 return retval; 1573 } 1574 1575 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1576 { 1577 int i; 1578 struct msr_counter *mp; 1579 1580 t->tv_begin.tv_sec = 0; 1581 t->tv_begin.tv_usec = 0; 1582 t->tv_end.tv_sec = 0; 1583 t->tv_end.tv_usec = 0; 1584 t->tv_delta.tv_sec = 0; 1585 t->tv_delta.tv_usec = 0; 1586 1587 t->tsc = 0; 1588 t->aperf = 0; 1589 t->mperf = 0; 1590 t->c1 = 0; 1591 1592 t->instr_count = 0; 1593 1594 t->irq_count = 0; 1595 t->smi_count = 0; 1596 1597 /* tells format_counters to dump all fields from this set */ 1598 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; 1599 1600 c->c3 = 0; 1601 c->c6 = 0; 1602 c->c7 = 0; 1603 c->mc6_us = 0; 1604 c->core_temp_c = 0; 1605 c->core_energy = 0; 1606 1607 p->pkg_wtd_core_c0 = 0; 1608 p->pkg_any_core_c0 = 0; 1609 p->pkg_any_gfxe_c0 = 0; 1610 p->pkg_both_core_gfxe_c0 = 0; 1611 1612 p->pc2 = 0; 1613 if (DO_BIC(BIC_Pkgpc3)) 1614 p->pc3 = 0; 1615 if (DO_BIC(BIC_Pkgpc6)) 1616 p->pc6 = 0; 1617 if (DO_BIC(BIC_Pkgpc7)) 1618 p->pc7 = 0; 1619 p->pc8 = 0; 1620 p->pc9 = 0; 1621 p->pc10 = 0; 1622 p->cpu_lpi = 0; 1623 p->sys_lpi = 0; 1624 1625 p->energy_pkg = 0; 1626 p->energy_dram = 0; 1627 p->energy_cores = 0; 1628 p->energy_gfx = 0; 1629 p->rapl_pkg_perf_status = 0; 1630 p->rapl_dram_perf_status = 0; 1631 p->pkg_temp_c = 0; 1632 1633 p->gfx_rc6_ms = 0; 1634 p->gfx_mhz = 0; 1635 p->gfx_act_mhz = 0; 1636 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) 1637 t->counter[i] = 0; 1638 1639 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) 1640 c->counter[i] = 0; 1641 1642 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) 1643 p->counter[i] = 0; 1644 } 1645 int sum_counters(struct thread_data *t, struct core_data *c, 1646 struct pkg_data *p) 1647 { 1648 int i; 1649 struct msr_counter *mp; 1650 1651 /* copy un-changing apic_id's */ 1652 if (DO_BIC(BIC_APIC)) 1653 average.threads.apic_id = t->apic_id; 1654 if (DO_BIC(BIC_X2APIC)) 1655 average.threads.x2apic_id = t->x2apic_id; 1656 1657 /* remember first tv_begin */ 1658 if (average.threads.tv_begin.tv_sec == 0) 1659 average.threads.tv_begin = t->tv_begin; 1660 1661 /* remember last tv_end */ 1662 average.threads.tv_end = t->tv_end; 1663 1664 average.threads.tsc += t->tsc; 1665 average.threads.aperf += t->aperf; 1666 average.threads.mperf += t->mperf; 1667 average.threads.c1 += t->c1; 1668 1669 average.threads.instr_count += t->instr_count; 1670 1671 average.threads.irq_count += t->irq_count; 1672 average.threads.smi_count += t->smi_count; 1673 1674 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1675 if (mp->format == FORMAT_RAW) 1676 continue; 1677 average.threads.counter[i] += t->counter[i]; 1678 } 1679 1680 /* sum per-core values only for 1st thread in core */ 1681 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1682 return 0; 1683 1684 average.cores.c3 += c->c3; 1685 average.cores.c6 += c->c6; 1686 average.cores.c7 += c->c7; 1687 average.cores.mc6_us += c->mc6_us; 1688 1689 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); 1690 1691 average.cores.core_energy += c->core_energy; 1692 1693 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1694 if (mp->format == FORMAT_RAW) 1695 continue; 1696 average.cores.counter[i] += c->counter[i]; 1697 } 1698 1699 /* sum per-pkg values only for 1st core in pkg */ 1700 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1701 return 0; 1702 1703 if (DO_BIC(BIC_Totl_c0)) 1704 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; 1705 if (DO_BIC(BIC_Any_c0)) 1706 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; 1707 if (DO_BIC(BIC_GFX_c0)) 1708 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; 1709 if (DO_BIC(BIC_CPUGFX)) 1710 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; 1711 1712 average.packages.pc2 += p->pc2; 1713 if (DO_BIC(BIC_Pkgpc3)) 1714 average.packages.pc3 += p->pc3; 1715 if (DO_BIC(BIC_Pkgpc6)) 1716 average.packages.pc6 += p->pc6; 1717 if (DO_BIC(BIC_Pkgpc7)) 1718 average.packages.pc7 += p->pc7; 1719 average.packages.pc8 += p->pc8; 1720 average.packages.pc9 += p->pc9; 1721 average.packages.pc10 += p->pc10; 1722 1723 average.packages.cpu_lpi = p->cpu_lpi; 1724 average.packages.sys_lpi = p->sys_lpi; 1725 1726 average.packages.energy_pkg += p->energy_pkg; 1727 average.packages.energy_dram += p->energy_dram; 1728 average.packages.energy_cores += p->energy_cores; 1729 average.packages.energy_gfx += p->energy_gfx; 1730 1731 average.packages.gfx_rc6_ms = p->gfx_rc6_ms; 1732 average.packages.gfx_mhz = p->gfx_mhz; 1733 average.packages.gfx_act_mhz = p->gfx_act_mhz; 1734 1735 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); 1736 1737 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; 1738 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; 1739 1740 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1741 if (mp->format == FORMAT_RAW) 1742 continue; 1743 average.packages.counter[i] += p->counter[i]; 1744 } 1745 return 0; 1746 } 1747 /* 1748 * sum the counters for all cpus in the system 1749 * compute the weighted average 1750 */ 1751 void compute_average(struct thread_data *t, struct core_data *c, 1752 struct pkg_data *p) 1753 { 1754 int i; 1755 struct msr_counter *mp; 1756 1757 clear_counters(&average.threads, &average.cores, &average.packages); 1758 1759 for_all_cpus(sum_counters, t, c, p); 1760 1761 /* Use the global time delta for the average. */ 1762 average.threads.tv_delta = tv_delta; 1763 1764 average.threads.tsc /= topo.num_cpus; 1765 average.threads.aperf /= topo.num_cpus; 1766 average.threads.mperf /= topo.num_cpus; 1767 average.threads.instr_count /= topo.num_cpus; 1768 average.threads.c1 /= topo.num_cpus; 1769 1770 if (average.threads.irq_count > 9999999) 1771 sums_need_wide_columns = 1; 1772 1773 average.cores.c3 /= topo.num_cores; 1774 average.cores.c6 /= topo.num_cores; 1775 average.cores.c7 /= topo.num_cores; 1776 average.cores.mc6_us /= topo.num_cores; 1777 1778 if (DO_BIC(BIC_Totl_c0)) 1779 average.packages.pkg_wtd_core_c0 /= topo.num_packages; 1780 if (DO_BIC(BIC_Any_c0)) 1781 average.packages.pkg_any_core_c0 /= topo.num_packages; 1782 if (DO_BIC(BIC_GFX_c0)) 1783 average.packages.pkg_any_gfxe_c0 /= topo.num_packages; 1784 if (DO_BIC(BIC_CPUGFX)) 1785 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages; 1786 1787 average.packages.pc2 /= topo.num_packages; 1788 if (DO_BIC(BIC_Pkgpc3)) 1789 average.packages.pc3 /= topo.num_packages; 1790 if (DO_BIC(BIC_Pkgpc6)) 1791 average.packages.pc6 /= topo.num_packages; 1792 if (DO_BIC(BIC_Pkgpc7)) 1793 average.packages.pc7 /= topo.num_packages; 1794 1795 average.packages.pc8 /= topo.num_packages; 1796 average.packages.pc9 /= topo.num_packages; 1797 average.packages.pc10 /= topo.num_packages; 1798 1799 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1800 if (mp->format == FORMAT_RAW) 1801 continue; 1802 if (mp->type == COUNTER_ITEMS) { 1803 if (average.threads.counter[i] > 9999999) 1804 sums_need_wide_columns = 1; 1805 continue; 1806 } 1807 average.threads.counter[i] /= topo.num_cpus; 1808 } 1809 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1810 if (mp->format == FORMAT_RAW) 1811 continue; 1812 if (mp->type == COUNTER_ITEMS) { 1813 if (average.cores.counter[i] > 9999999) 1814 sums_need_wide_columns = 1; 1815 } 1816 average.cores.counter[i] /= topo.num_cores; 1817 } 1818 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1819 if (mp->format == FORMAT_RAW) 1820 continue; 1821 if (mp->type == COUNTER_ITEMS) { 1822 if (average.packages.counter[i] > 9999999) 1823 sums_need_wide_columns = 1; 1824 } 1825 average.packages.counter[i] /= topo.num_packages; 1826 } 1827 } 1828 1829 static unsigned long long rdtsc(void) 1830 { 1831 unsigned int low, high; 1832 1833 asm volatile("rdtsc" : "=a" (low), "=d" (high)); 1834 1835 return low | ((unsigned long long)high) << 32; 1836 } 1837 1838 /* 1839 * Open a file, and exit on failure 1840 */ 1841 FILE *fopen_or_die(const char *path, const char *mode) 1842 { 1843 FILE *filep = fopen(path, mode); 1844 1845 if (!filep) 1846 err(1, "%s: open failed", path); 1847 return filep; 1848 } 1849 /* 1850 * snapshot_sysfs_counter() 1851 * 1852 * return snapshot of given counter 1853 */ 1854 unsigned long long snapshot_sysfs_counter(char *path) 1855 { 1856 FILE *fp; 1857 int retval; 1858 unsigned long long counter; 1859 1860 fp = fopen_or_die(path, "r"); 1861 1862 retval = fscanf(fp, "%lld", &counter); 1863 if (retval != 1) 1864 err(1, "snapshot_sysfs_counter(%s)", path); 1865 1866 fclose(fp); 1867 1868 return counter; 1869 } 1870 1871 int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp) 1872 { 1873 if (mp->msr_num != 0) { 1874 if (get_msr(cpu, mp->msr_num, counterp)) 1875 return -1; 1876 } else { 1877 char path[128 + PATH_BYTES]; 1878 1879 if (mp->flags & SYSFS_PERCPU) { 1880 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s", 1881 cpu, mp->path); 1882 1883 *counterp = snapshot_sysfs_counter(path); 1884 } else { 1885 *counterp = snapshot_sysfs_counter(mp->path); 1886 } 1887 } 1888 1889 return 0; 1890 } 1891 1892 int get_epb(int cpu) 1893 { 1894 char path[128 + PATH_BYTES]; 1895 unsigned long long msr; 1896 int ret, epb = -1; 1897 FILE *fp; 1898 1899 sprintf(path, "/sys/devices/system/cpu/cpu%d/power/energy_perf_bias", cpu); 1900 1901 fp = fopen(path, "r"); 1902 if (!fp) 1903 goto msr_fallback; 1904 1905 ret = fscanf(fp, "%d", &epb); 1906 if (ret != 1) 1907 err(1, "%s(%s)", __func__, path); 1908 1909 fclose(fp); 1910 1911 return epb; 1912 1913 msr_fallback: 1914 get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr); 1915 1916 return msr & 0xf; 1917 } 1918 1919 void get_apic_id(struct thread_data *t) 1920 { 1921 unsigned int eax, ebx, ecx, edx; 1922 1923 if (DO_BIC(BIC_APIC)) { 1924 eax = ebx = ecx = edx = 0; 1925 __cpuid(1, eax, ebx, ecx, edx); 1926 1927 t->apic_id = (ebx >> 24) & 0xff; 1928 } 1929 1930 if (!DO_BIC(BIC_X2APIC)) 1931 return; 1932 1933 if (authentic_amd || hygon_genuine) { 1934 unsigned int topology_extensions; 1935 1936 if (max_extended_level < 0x8000001e) 1937 return; 1938 1939 eax = ebx = ecx = edx = 0; 1940 __cpuid(0x80000001, eax, ebx, ecx, edx); 1941 topology_extensions = ecx & (1 << 22); 1942 1943 if (topology_extensions == 0) 1944 return; 1945 1946 eax = ebx = ecx = edx = 0; 1947 __cpuid(0x8000001e, eax, ebx, ecx, edx); 1948 1949 t->x2apic_id = eax; 1950 return; 1951 } 1952 1953 if (!genuine_intel) 1954 return; 1955 1956 if (max_level < 0xb) 1957 return; 1958 1959 ecx = 0; 1960 __cpuid(0xb, eax, ebx, ecx, edx); 1961 t->x2apic_id = edx; 1962 1963 if (debug && (t->apic_id != (t->x2apic_id & 0xff))) 1964 fprintf(outf, "cpu%d: BIOS BUG: apic 0x%x x2apic 0x%x\n", 1965 t->cpu_id, t->apic_id, t->x2apic_id); 1966 } 1967 1968 /* 1969 * get_counters(...) 1970 * migrate to cpu 1971 * acquire and record local counters for that cpu 1972 */ 1973 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1974 { 1975 int cpu = t->cpu_id; 1976 unsigned long long msr; 1977 int aperf_mperf_retry_count = 0; 1978 struct msr_counter *mp; 1979 int i; 1980 1981 if (cpu_migrate(cpu)) { 1982 fprintf(outf, "get_counters: Could not migrate to CPU %d\n", cpu); 1983 return -1; 1984 } 1985 1986 gettimeofday(&t->tv_begin, (struct timezone *)NULL); 1987 1988 if (first_counter_read) 1989 get_apic_id(t); 1990 retry: 1991 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 1992 1993 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || 1994 soft_c1_residency_display(BIC_Avg_MHz)) { 1995 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; 1996 1997 /* 1998 * The TSC, APERF and MPERF must be read together for 1999 * APERF/MPERF and MPERF/TSC to give accurate results. 2000 * 2001 * Unfortunately, APERF and MPERF are read by 2002 * individual system call, so delays may occur 2003 * between them. If the time to read them 2004 * varies by a large amount, we re-read them. 2005 */ 2006 2007 /* 2008 * This initial dummy APERF read has been seen to 2009 * reduce jitter in the subsequent reads. 2010 */ 2011 2012 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 2013 return -3; 2014 2015 t->tsc = rdtsc(); /* re-read close to APERF */ 2016 2017 tsc_before = t->tsc; 2018 2019 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 2020 return -3; 2021 2022 tsc_between = rdtsc(); 2023 2024 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) 2025 return -4; 2026 2027 tsc_after = rdtsc(); 2028 2029 aperf_time = tsc_between - tsc_before; 2030 mperf_time = tsc_after - tsc_between; 2031 2032 /* 2033 * If the system call latency to read APERF and MPERF 2034 * differ by more than 2x, then try again. 2035 */ 2036 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { 2037 aperf_mperf_retry_count++; 2038 if (aperf_mperf_retry_count < 5) 2039 goto retry; 2040 else 2041 warnx("cpu%d jitter %lld %lld", 2042 cpu, aperf_time, mperf_time); 2043 } 2044 aperf_mperf_retry_count = 0; 2045 2046 t->aperf = t->aperf * aperf_mperf_multiplier; 2047 t->mperf = t->mperf * aperf_mperf_multiplier; 2048 } 2049 2050 if (DO_BIC(BIC_IPC)) 2051 if (read(get_instr_count_fd(cpu), &t->instr_count, sizeof(long long)) != sizeof(long long)) 2052 return -4; 2053 2054 if (DO_BIC(BIC_IRQ)) 2055 t->irq_count = irqs_per_cpu[cpu]; 2056 if (DO_BIC(BIC_SMI)) { 2057 if (get_msr(cpu, MSR_SMI_COUNT, &msr)) 2058 return -5; 2059 t->smi_count = msr & 0xFFFFFFFF; 2060 } 2061 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) { 2062 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) 2063 return -6; 2064 } 2065 2066 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 2067 if (get_mp(cpu, mp, &t->counter[i])) 2068 return -10; 2069 } 2070 2071 /* collect core counters only for 1st thread in core */ 2072 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 2073 goto done; 2074 2075 if (DO_BIC(BIC_CPU_c3) || soft_c1_residency_display(BIC_CPU_c3)) { 2076 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) 2077 return -6; 2078 } 2079 2080 if ((DO_BIC(BIC_CPU_c6) || soft_c1_residency_display(BIC_CPU_c6)) && !do_knl_cstates) { 2081 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) 2082 return -7; 2083 } else if (do_knl_cstates || soft_c1_residency_display(BIC_CPU_c6)) { 2084 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) 2085 return -7; 2086 } 2087 2088 if (DO_BIC(BIC_CPU_c7) || soft_c1_residency_display(BIC_CPU_c7)) 2089 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 2090 return -8; 2091 2092 if (DO_BIC(BIC_Mod_c6)) 2093 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us)) 2094 return -8; 2095 2096 if (DO_BIC(BIC_CoreTmp)) { 2097 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 2098 return -9; 2099 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 2100 } 2101 2102 if (do_rapl & RAPL_AMD_F17H) { 2103 if (get_msr(cpu, MSR_CORE_ENERGY_STAT, &msr)) 2104 return -14; 2105 c->core_energy = msr & 0xFFFFFFFF; 2106 } 2107 2108 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 2109 if (get_mp(cpu, mp, &c->counter[i])) 2110 return -10; 2111 } 2112 2113 /* collect package counters only for 1st core in package */ 2114 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2115 goto done; 2116 2117 if (DO_BIC(BIC_Totl_c0)) { 2118 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) 2119 return -10; 2120 } 2121 if (DO_BIC(BIC_Any_c0)) { 2122 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) 2123 return -11; 2124 } 2125 if (DO_BIC(BIC_GFX_c0)) { 2126 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) 2127 return -12; 2128 } 2129 if (DO_BIC(BIC_CPUGFX)) { 2130 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) 2131 return -13; 2132 } 2133 if (DO_BIC(BIC_Pkgpc3)) 2134 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) 2135 return -9; 2136 if (DO_BIC(BIC_Pkgpc6)) { 2137 if (do_slm_cstates) { 2138 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6)) 2139 return -10; 2140 } else { 2141 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) 2142 return -10; 2143 } 2144 } 2145 2146 if (DO_BIC(BIC_Pkgpc2)) 2147 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) 2148 return -11; 2149 if (DO_BIC(BIC_Pkgpc7)) 2150 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) 2151 return -12; 2152 if (DO_BIC(BIC_Pkgpc8)) 2153 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) 2154 return -13; 2155 if (DO_BIC(BIC_Pkgpc9)) 2156 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) 2157 return -13; 2158 if (DO_BIC(BIC_Pkgpc10)) 2159 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) 2160 return -13; 2161 2162 if (DO_BIC(BIC_CPU_LPI)) 2163 p->cpu_lpi = cpuidle_cur_cpu_lpi_us; 2164 if (DO_BIC(BIC_SYS_LPI)) 2165 p->sys_lpi = cpuidle_cur_sys_lpi_us; 2166 2167 if (do_rapl & RAPL_PKG) { 2168 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STATUS, &msr)) 2169 return -13; 2170 p->energy_pkg = msr; 2171 } 2172 if (do_rapl & RAPL_CORES_ENERGY_STATUS) { 2173 if (get_msr_sum(cpu, MSR_PP0_ENERGY_STATUS, &msr)) 2174 return -14; 2175 p->energy_cores = msr; 2176 } 2177 if (do_rapl & RAPL_DRAM) { 2178 if (get_msr_sum(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) 2179 return -15; 2180 p->energy_dram = msr; 2181 } 2182 if (do_rapl & RAPL_GFX) { 2183 if (get_msr_sum(cpu, MSR_PP1_ENERGY_STATUS, &msr)) 2184 return -16; 2185 p->energy_gfx = msr; 2186 } 2187 if (do_rapl & RAPL_PKG_PERF_STATUS) { 2188 if (get_msr_sum(cpu, MSR_PKG_PERF_STATUS, &msr)) 2189 return -16; 2190 p->rapl_pkg_perf_status = msr; 2191 } 2192 if (do_rapl & RAPL_DRAM_PERF_STATUS) { 2193 if (get_msr_sum(cpu, MSR_DRAM_PERF_STATUS, &msr)) 2194 return -16; 2195 p->rapl_dram_perf_status = msr; 2196 } 2197 if (do_rapl & RAPL_AMD_F17H) { 2198 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STAT, &msr)) 2199 return -13; 2200 p->energy_pkg = msr; 2201 } 2202 if (DO_BIC(BIC_PkgTmp)) { 2203 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 2204 return -17; 2205 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 2206 } 2207 2208 if (DO_BIC(BIC_GFX_rc6)) 2209 p->gfx_rc6_ms = gfx_cur_rc6_ms; 2210 2211 if (DO_BIC(BIC_GFXMHz)) 2212 p->gfx_mhz = gfx_cur_mhz; 2213 2214 if (DO_BIC(BIC_GFXACTMHz)) 2215 p->gfx_act_mhz = gfx_act_mhz; 2216 2217 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 2218 if (get_mp(cpu, mp, &p->counter[i])) 2219 return -10; 2220 } 2221 done: 2222 gettimeofday(&t->tv_end, (struct timezone *)NULL); 2223 2224 return 0; 2225 } 2226 2227 /* 2228 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: 2229 * If you change the values, note they are used both in comparisons 2230 * (>= PCL__7) and to index pkg_cstate_limit_strings[]. 2231 */ 2232 2233 #define PCLUKN 0 /* Unknown */ 2234 #define PCLRSV 1 /* Reserved */ 2235 #define PCL__0 2 /* PC0 */ 2236 #define PCL__1 3 /* PC1 */ 2237 #define PCL__2 4 /* PC2 */ 2238 #define PCL__3 5 /* PC3 */ 2239 #define PCL__4 6 /* PC4 */ 2240 #define PCL__6 7 /* PC6 */ 2241 #define PCL_6N 8 /* PC6 No Retention */ 2242 #define PCL_6R 9 /* PC6 Retention */ 2243 #define PCL__7 10 /* PC7 */ 2244 #define PCL_7S 11 /* PC7 Shrink */ 2245 #define PCL__8 12 /* PC8 */ 2246 #define PCL__9 13 /* PC9 */ 2247 #define PCL_10 14 /* PC10 */ 2248 #define PCLUNL 15 /* Unlimited */ 2249 2250 int pkg_cstate_limit = PCLUKN; 2251 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", 2252 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "pc10", "unlimited"}; 2253 2254 int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2255 int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2256 int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2257 int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7}; 2258 int amt_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2259 int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2260 int glm_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCL_10, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2261 int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2262 2263 2264 static void 2265 calculate_tsc_tweak() 2266 { 2267 tsc_tweak = base_hz / tsc_hz; 2268 } 2269 2270 static void 2271 dump_nhm_platform_info(void) 2272 { 2273 unsigned long long msr; 2274 unsigned int ratio; 2275 2276 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 2277 2278 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 2279 2280 ratio = (msr >> 40) & 0xFF; 2281 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", 2282 ratio, bclk, ratio * bclk); 2283 2284 ratio = (msr >> 8) & 0xFF; 2285 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", 2286 ratio, bclk, ratio * bclk); 2287 2288 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); 2289 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", 2290 base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); 2291 2292 return; 2293 } 2294 2295 static void 2296 dump_hsw_turbo_ratio_limits(void) 2297 { 2298 unsigned long long msr; 2299 unsigned int ratio; 2300 2301 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); 2302 2303 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); 2304 2305 ratio = (msr >> 8) & 0xFF; 2306 if (ratio) 2307 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", 2308 ratio, bclk, ratio * bclk); 2309 2310 ratio = (msr >> 0) & 0xFF; 2311 if (ratio) 2312 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", 2313 ratio, bclk, ratio * bclk); 2314 return; 2315 } 2316 2317 static void 2318 dump_ivt_turbo_ratio_limits(void) 2319 { 2320 unsigned long long msr; 2321 unsigned int ratio; 2322 2323 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); 2324 2325 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); 2326 2327 ratio = (msr >> 56) & 0xFF; 2328 if (ratio) 2329 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", 2330 ratio, bclk, ratio * bclk); 2331 2332 ratio = (msr >> 48) & 0xFF; 2333 if (ratio) 2334 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", 2335 ratio, bclk, ratio * bclk); 2336 2337 ratio = (msr >> 40) & 0xFF; 2338 if (ratio) 2339 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", 2340 ratio, bclk, ratio * bclk); 2341 2342 ratio = (msr >> 32) & 0xFF; 2343 if (ratio) 2344 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", 2345 ratio, bclk, ratio * bclk); 2346 2347 ratio = (msr >> 24) & 0xFF; 2348 if (ratio) 2349 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", 2350 ratio, bclk, ratio * bclk); 2351 2352 ratio = (msr >> 16) & 0xFF; 2353 if (ratio) 2354 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", 2355 ratio, bclk, ratio * bclk); 2356 2357 ratio = (msr >> 8) & 0xFF; 2358 if (ratio) 2359 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", 2360 ratio, bclk, ratio * bclk); 2361 2362 ratio = (msr >> 0) & 0xFF; 2363 if (ratio) 2364 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", 2365 ratio, bclk, ratio * bclk); 2366 return; 2367 } 2368 int has_turbo_ratio_group_limits(int family, int model) 2369 { 2370 2371 if (!genuine_intel) 2372 return 0; 2373 2374 switch (model) { 2375 case INTEL_FAM6_ATOM_GOLDMONT: 2376 case INTEL_FAM6_SKYLAKE_X: 2377 case INTEL_FAM6_ATOM_GOLDMONT_D: 2378 case INTEL_FAM6_ATOM_TREMONT_D: 2379 return 1; 2380 } 2381 return 0; 2382 } 2383 2384 static void 2385 dump_turbo_ratio_limits(int family, int model) 2386 { 2387 unsigned long long msr, core_counts; 2388 unsigned int ratio, group_size; 2389 2390 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2391 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 2392 2393 if (has_turbo_ratio_group_limits(family, model)) { 2394 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts); 2395 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts); 2396 } else { 2397 core_counts = 0x0807060504030201; 2398 } 2399 2400 ratio = (msr >> 56) & 0xFF; 2401 group_size = (core_counts >> 56) & 0xFF; 2402 if (ratio) 2403 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2404 ratio, bclk, ratio * bclk, group_size); 2405 2406 ratio = (msr >> 48) & 0xFF; 2407 group_size = (core_counts >> 48) & 0xFF; 2408 if (ratio) 2409 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2410 ratio, bclk, ratio * bclk, group_size); 2411 2412 ratio = (msr >> 40) & 0xFF; 2413 group_size = (core_counts >> 40) & 0xFF; 2414 if (ratio) 2415 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2416 ratio, bclk, ratio * bclk, group_size); 2417 2418 ratio = (msr >> 32) & 0xFF; 2419 group_size = (core_counts >> 32) & 0xFF; 2420 if (ratio) 2421 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2422 ratio, bclk, ratio * bclk, group_size); 2423 2424 ratio = (msr >> 24) & 0xFF; 2425 group_size = (core_counts >> 24) & 0xFF; 2426 if (ratio) 2427 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2428 ratio, bclk, ratio * bclk, group_size); 2429 2430 ratio = (msr >> 16) & 0xFF; 2431 group_size = (core_counts >> 16) & 0xFF; 2432 if (ratio) 2433 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2434 ratio, bclk, ratio * bclk, group_size); 2435 2436 ratio = (msr >> 8) & 0xFF; 2437 group_size = (core_counts >> 8) & 0xFF; 2438 if (ratio) 2439 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2440 ratio, bclk, ratio * bclk, group_size); 2441 2442 ratio = (msr >> 0) & 0xFF; 2443 group_size = (core_counts >> 0) & 0xFF; 2444 if (ratio) 2445 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2446 ratio, bclk, ratio * bclk, group_size); 2447 return; 2448 } 2449 2450 static void 2451 dump_atom_turbo_ratio_limits(void) 2452 { 2453 unsigned long long msr; 2454 unsigned int ratio; 2455 2456 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr); 2457 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2458 2459 ratio = (msr >> 0) & 0x3F; 2460 if (ratio) 2461 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", 2462 ratio, bclk, ratio * bclk); 2463 2464 ratio = (msr >> 8) & 0x3F; 2465 if (ratio) 2466 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", 2467 ratio, bclk, ratio * bclk); 2468 2469 ratio = (msr >> 16) & 0x3F; 2470 if (ratio) 2471 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", 2472 ratio, bclk, ratio * bclk); 2473 2474 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr); 2475 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2476 2477 ratio = (msr >> 24) & 0x3F; 2478 if (ratio) 2479 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", 2480 ratio, bclk, ratio * bclk); 2481 2482 ratio = (msr >> 16) & 0x3F; 2483 if (ratio) 2484 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", 2485 ratio, bclk, ratio * bclk); 2486 2487 ratio = (msr >> 8) & 0x3F; 2488 if (ratio) 2489 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", 2490 ratio, bclk, ratio * bclk); 2491 2492 ratio = (msr >> 0) & 0x3F; 2493 if (ratio) 2494 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", 2495 ratio, bclk, ratio * bclk); 2496 } 2497 2498 static void 2499 dump_knl_turbo_ratio_limits(void) 2500 { 2501 const unsigned int buckets_no = 7; 2502 2503 unsigned long long msr; 2504 int delta_cores, delta_ratio; 2505 int i, b_nr; 2506 unsigned int cores[buckets_no]; 2507 unsigned int ratio[buckets_no]; 2508 2509 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2510 2511 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", 2512 base_cpu, msr); 2513 2514 /** 2515 * Turbo encoding in KNL is as follows: 2516 * [0] -- Reserved 2517 * [7:1] -- Base value of number of active cores of bucket 1. 2518 * [15:8] -- Base value of freq ratio of bucket 1. 2519 * [20:16] -- +ve delta of number of active cores of bucket 2. 2520 * i.e. active cores of bucket 2 = 2521 * active cores of bucket 1 + delta 2522 * [23:21] -- Negative delta of freq ratio of bucket 2. 2523 * i.e. freq ratio of bucket 2 = 2524 * freq ratio of bucket 1 - delta 2525 * [28:24]-- +ve delta of number of active cores of bucket 3. 2526 * [31:29]-- -ve delta of freq ratio of bucket 3. 2527 * [36:32]-- +ve delta of number of active cores of bucket 4. 2528 * [39:37]-- -ve delta of freq ratio of bucket 4. 2529 * [44:40]-- +ve delta of number of active cores of bucket 5. 2530 * [47:45]-- -ve delta of freq ratio of bucket 5. 2531 * [52:48]-- +ve delta of number of active cores of bucket 6. 2532 * [55:53]-- -ve delta of freq ratio of bucket 6. 2533 * [60:56]-- +ve delta of number of active cores of bucket 7. 2534 * [63:61]-- -ve delta of freq ratio of bucket 7. 2535 */ 2536 2537 b_nr = 0; 2538 cores[b_nr] = (msr & 0xFF) >> 1; 2539 ratio[b_nr] = (msr >> 8) & 0xFF; 2540 2541 for (i = 16; i < 64; i += 8) { 2542 delta_cores = (msr >> i) & 0x1F; 2543 delta_ratio = (msr >> (i + 5)) & 0x7; 2544 2545 cores[b_nr + 1] = cores[b_nr] + delta_cores; 2546 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; 2547 b_nr++; 2548 } 2549 2550 for (i = buckets_no - 1; i >= 0; i--) 2551 if (i > 0 ? ratio[i] != ratio[i - 1] : 1) 2552 fprintf(outf, 2553 "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2554 ratio[i], bclk, ratio[i] * bclk, cores[i]); 2555 } 2556 2557 static void 2558 dump_nhm_cst_cfg(void) 2559 { 2560 unsigned long long msr; 2561 2562 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 2563 2564 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr); 2565 2566 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)", 2567 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", 2568 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", 2569 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", 2570 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", 2571 (msr & (1 << 15)) ? "" : "UN", 2572 (unsigned int)msr & 0xF, 2573 pkg_cstate_limit_strings[pkg_cstate_limit]); 2574 2575 #define AUTOMATIC_CSTATE_CONVERSION (1UL << 16) 2576 if (has_automatic_cstate_conversion) { 2577 fprintf(outf, ", automatic c-state conversion=%s", 2578 (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off"); 2579 } 2580 2581 fprintf(outf, ")\n"); 2582 2583 return; 2584 } 2585 2586 static void 2587 dump_config_tdp(void) 2588 { 2589 unsigned long long msr; 2590 2591 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); 2592 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); 2593 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); 2594 2595 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); 2596 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); 2597 if (msr) { 2598 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2599 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2600 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2601 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); 2602 } 2603 fprintf(outf, ")\n"); 2604 2605 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); 2606 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); 2607 if (msr) { 2608 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2609 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2610 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2611 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); 2612 } 2613 fprintf(outf, ")\n"); 2614 2615 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); 2616 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); 2617 if ((msr) & 0x3) 2618 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); 2619 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2620 fprintf(outf, ")\n"); 2621 2622 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); 2623 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); 2624 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); 2625 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2626 fprintf(outf, ")\n"); 2627 } 2628 2629 unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; 2630 2631 void print_irtl(void) 2632 { 2633 unsigned long long msr; 2634 2635 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr); 2636 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr); 2637 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2638 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2639 2640 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr); 2641 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr); 2642 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2643 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2644 2645 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr); 2646 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr); 2647 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2648 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2649 2650 if (!do_irtl_hsw) 2651 return; 2652 2653 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr); 2654 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr); 2655 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2656 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2657 2658 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr); 2659 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr); 2660 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2661 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2662 2663 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr); 2664 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr); 2665 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2666 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2667 2668 } 2669 void free_fd_percpu(void) 2670 { 2671 int i; 2672 2673 for (i = 0; i < topo.max_cpu_num + 1; ++i) { 2674 if (fd_percpu[i] != 0) 2675 close(fd_percpu[i]); 2676 } 2677 2678 free(fd_percpu); 2679 } 2680 2681 void free_all_buffers(void) 2682 { 2683 int i; 2684 2685 CPU_FREE(cpu_present_set); 2686 cpu_present_set = NULL; 2687 cpu_present_setsize = 0; 2688 2689 CPU_FREE(cpu_affinity_set); 2690 cpu_affinity_set = NULL; 2691 cpu_affinity_setsize = 0; 2692 2693 free(thread_even); 2694 free(core_even); 2695 free(package_even); 2696 2697 thread_even = NULL; 2698 core_even = NULL; 2699 package_even = NULL; 2700 2701 free(thread_odd); 2702 free(core_odd); 2703 free(package_odd); 2704 2705 thread_odd = NULL; 2706 core_odd = NULL; 2707 package_odd = NULL; 2708 2709 free(output_buffer); 2710 output_buffer = NULL; 2711 outp = NULL; 2712 2713 free_fd_percpu(); 2714 2715 free(irq_column_2_cpu); 2716 free(irqs_per_cpu); 2717 2718 for (i = 0; i <= topo.max_cpu_num; ++i) { 2719 if (cpus[i].put_ids) 2720 CPU_FREE(cpus[i].put_ids); 2721 } 2722 free(cpus); 2723 } 2724 2725 2726 /* 2727 * Parse a file containing a single int. 2728 * Return 0 if file can not be opened 2729 * Exit if file can be opened, but can not be parsed 2730 */ 2731 int parse_int_file(const char *fmt, ...) 2732 { 2733 va_list args; 2734 char path[PATH_MAX]; 2735 FILE *filep; 2736 int value; 2737 2738 va_start(args, fmt); 2739 vsnprintf(path, sizeof(path), fmt, args); 2740 va_end(args); 2741 filep = fopen(path, "r"); 2742 if (!filep) 2743 return 0; 2744 if (fscanf(filep, "%d", &value) != 1) 2745 err(1, "%s: failed to parse number from file", path); 2746 fclose(filep); 2747 return value; 2748 } 2749 2750 /* 2751 * cpu_is_first_core_in_package(cpu) 2752 * return 1 if given CPU is 1st core in package 2753 */ 2754 int cpu_is_first_core_in_package(int cpu) 2755 { 2756 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); 2757 } 2758 2759 int get_physical_package_id(int cpu) 2760 { 2761 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); 2762 } 2763 2764 int get_die_id(int cpu) 2765 { 2766 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/die_id", cpu); 2767 } 2768 2769 int get_core_id(int cpu) 2770 { 2771 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); 2772 } 2773 2774 void set_node_data(void) 2775 { 2776 int pkg, node, lnode, cpu, cpux; 2777 int cpu_count; 2778 2779 /* initialize logical_node_id */ 2780 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) 2781 cpus[cpu].logical_node_id = -1; 2782 2783 cpu_count = 0; 2784 for (pkg = 0; pkg < topo.num_packages; pkg++) { 2785 lnode = 0; 2786 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) { 2787 if (cpus[cpu].physical_package_id != pkg) 2788 continue; 2789 /* find a cpu with an unset logical_node_id */ 2790 if (cpus[cpu].logical_node_id != -1) 2791 continue; 2792 cpus[cpu].logical_node_id = lnode; 2793 node = cpus[cpu].physical_node_id; 2794 cpu_count++; 2795 /* 2796 * find all matching cpus on this pkg and set 2797 * the logical_node_id 2798 */ 2799 for (cpux = cpu; cpux <= topo.max_cpu_num; cpux++) { 2800 if ((cpus[cpux].physical_package_id == pkg) && 2801 (cpus[cpux].physical_node_id == node)) { 2802 cpus[cpux].logical_node_id = lnode; 2803 cpu_count++; 2804 } 2805 } 2806 lnode++; 2807 if (lnode > topo.nodes_per_pkg) 2808 topo.nodes_per_pkg = lnode; 2809 } 2810 if (cpu_count >= topo.max_cpu_num) 2811 break; 2812 } 2813 } 2814 2815 int get_physical_node_id(struct cpu_topology *thiscpu) 2816 { 2817 char path[80]; 2818 FILE *filep; 2819 int i; 2820 int cpu = thiscpu->logical_cpu_id; 2821 2822 for (i = 0; i <= topo.max_cpu_num; i++) { 2823 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist", 2824 cpu, i); 2825 filep = fopen(path, "r"); 2826 if (!filep) 2827 continue; 2828 fclose(filep); 2829 return i; 2830 } 2831 return -1; 2832 } 2833 2834 int get_thread_siblings(struct cpu_topology *thiscpu) 2835 { 2836 char path[80], character; 2837 FILE *filep; 2838 unsigned long map; 2839 int so, shift, sib_core; 2840 int cpu = thiscpu->logical_cpu_id; 2841 int offset = topo.max_cpu_num + 1; 2842 size_t size; 2843 int thread_id = 0; 2844 2845 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1)); 2846 if (thiscpu->thread_id < 0) 2847 thiscpu->thread_id = thread_id++; 2848 if (!thiscpu->put_ids) 2849 return -1; 2850 2851 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 2852 CPU_ZERO_S(size, thiscpu->put_ids); 2853 2854 sprintf(path, 2855 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu); 2856 filep = fopen(path, "r"); 2857 2858 if (!filep) { 2859 warnx("%s: open failed", path); 2860 return -1; 2861 } 2862 do { 2863 offset -= BITMASK_SIZE; 2864 if (fscanf(filep, "%lx%c", &map, &character) != 2) 2865 err(1, "%s: failed to parse file", path); 2866 for (shift = 0; shift < BITMASK_SIZE; shift++) { 2867 if ((map >> shift) & 0x1) { 2868 so = shift + offset; 2869 sib_core = get_core_id(so); 2870 if (sib_core == thiscpu->physical_core_id) { 2871 CPU_SET_S(so, size, thiscpu->put_ids); 2872 if ((so != cpu) && 2873 (cpus[so].thread_id < 0)) 2874 cpus[so].thread_id = 2875 thread_id++; 2876 } 2877 } 2878 } 2879 } while (!strncmp(&character, ",", 1)); 2880 fclose(filep); 2881 2882 return CPU_COUNT_S(size, thiscpu->put_ids); 2883 } 2884 2885 /* 2886 * run func(thread, core, package) in topology order 2887 * skip non-present cpus 2888 */ 2889 2890 int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *, 2891 struct pkg_data *, struct thread_data *, struct core_data *, 2892 struct pkg_data *), struct thread_data *thread_base, 2893 struct core_data *core_base, struct pkg_data *pkg_base, 2894 struct thread_data *thread_base2, struct core_data *core_base2, 2895 struct pkg_data *pkg_base2) 2896 { 2897 int retval, pkg_no, node_no, core_no, thread_no; 2898 2899 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 2900 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) { 2901 for (core_no = 0; core_no < topo.cores_per_node; 2902 ++core_no) { 2903 for (thread_no = 0; thread_no < 2904 topo.threads_per_core; ++thread_no) { 2905 struct thread_data *t, *t2; 2906 struct core_data *c, *c2; 2907 struct pkg_data *p, *p2; 2908 2909 t = GET_THREAD(thread_base, thread_no, 2910 core_no, node_no, 2911 pkg_no); 2912 2913 if (cpu_is_not_present(t->cpu_id)) 2914 continue; 2915 2916 t2 = GET_THREAD(thread_base2, thread_no, 2917 core_no, node_no, 2918 pkg_no); 2919 2920 c = GET_CORE(core_base, core_no, 2921 node_no, pkg_no); 2922 c2 = GET_CORE(core_base2, core_no, 2923 node_no, 2924 pkg_no); 2925 2926 p = GET_PKG(pkg_base, pkg_no); 2927 p2 = GET_PKG(pkg_base2, pkg_no); 2928 2929 retval = func(t, c, p, t2, c2, p2); 2930 if (retval) 2931 return retval; 2932 } 2933 } 2934 } 2935 } 2936 return 0; 2937 } 2938 2939 /* 2940 * run func(cpu) on every cpu in /proc/stat 2941 * return max_cpu number 2942 */ 2943 int for_all_proc_cpus(int (func)(int)) 2944 { 2945 FILE *fp; 2946 int cpu_num; 2947 int retval; 2948 2949 fp = fopen_or_die(proc_stat, "r"); 2950 2951 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); 2952 if (retval != 0) 2953 err(1, "%s: failed to parse format", proc_stat); 2954 2955 while (1) { 2956 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); 2957 if (retval != 1) 2958 break; 2959 2960 retval = func(cpu_num); 2961 if (retval) { 2962 fclose(fp); 2963 return(retval); 2964 } 2965 } 2966 fclose(fp); 2967 return 0; 2968 } 2969 2970 void re_initialize(void) 2971 { 2972 free_all_buffers(); 2973 setup_all_buffers(); 2974 fprintf(outf, "turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); 2975 } 2976 2977 void set_max_cpu_num(void) 2978 { 2979 FILE *filep; 2980 int base_cpu; 2981 unsigned long dummy; 2982 char pathname[64]; 2983 2984 base_cpu = sched_getcpu(); 2985 if (base_cpu < 0) 2986 err(1, "cannot find calling cpu ID"); 2987 sprintf(pathname, 2988 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", 2989 base_cpu); 2990 2991 filep = fopen_or_die(pathname, "r"); 2992 topo.max_cpu_num = 0; 2993 while (fscanf(filep, "%lx,", &dummy) == 1) 2994 topo.max_cpu_num += BITMASK_SIZE; 2995 fclose(filep); 2996 topo.max_cpu_num--; /* 0 based */ 2997 } 2998 2999 /* 3000 * count_cpus() 3001 * remember the last one seen, it will be the max 3002 */ 3003 int count_cpus(int cpu) 3004 { 3005 topo.num_cpus++; 3006 return 0; 3007 } 3008 int mark_cpu_present(int cpu) 3009 { 3010 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); 3011 return 0; 3012 } 3013 3014 int init_thread_id(int cpu) 3015 { 3016 cpus[cpu].thread_id = -1; 3017 return 0; 3018 } 3019 3020 /* 3021 * snapshot_proc_interrupts() 3022 * 3023 * read and record summary of /proc/interrupts 3024 * 3025 * return 1 if config change requires a restart, else return 0 3026 */ 3027 int snapshot_proc_interrupts(void) 3028 { 3029 static FILE *fp; 3030 int column, retval; 3031 3032 if (fp == NULL) 3033 fp = fopen_or_die("/proc/interrupts", "r"); 3034 else 3035 rewind(fp); 3036 3037 /* read 1st line of /proc/interrupts to get cpu* name for each column */ 3038 for (column = 0; column < topo.num_cpus; ++column) { 3039 int cpu_number; 3040 3041 retval = fscanf(fp, " CPU%d", &cpu_number); 3042 if (retval != 1) 3043 break; 3044 3045 if (cpu_number > topo.max_cpu_num) { 3046 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); 3047 return 1; 3048 } 3049 3050 irq_column_2_cpu[column] = cpu_number; 3051 irqs_per_cpu[cpu_number] = 0; 3052 } 3053 3054 /* read /proc/interrupt count lines and sum up irqs per cpu */ 3055 while (1) { 3056 int column; 3057 char buf[64]; 3058 3059 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ 3060 if (retval != 1) 3061 break; 3062 3063 /* read the count per cpu */ 3064 for (column = 0; column < topo.num_cpus; ++column) { 3065 3066 int cpu_number, irq_count; 3067 3068 retval = fscanf(fp, " %d", &irq_count); 3069 if (retval != 1) 3070 break; 3071 3072 cpu_number = irq_column_2_cpu[column]; 3073 irqs_per_cpu[cpu_number] += irq_count; 3074 3075 } 3076 3077 while (getc(fp) != '\n') 3078 ; /* flush interrupt description */ 3079 3080 } 3081 return 0; 3082 } 3083 /* 3084 * snapshot_gfx_rc6_ms() 3085 * 3086 * record snapshot of 3087 * /sys/class/drm/card0/power/rc6_residency_ms 3088 * 3089 * return 1 if config change requires a restart, else return 0 3090 */ 3091 int snapshot_gfx_rc6_ms(void) 3092 { 3093 FILE *fp; 3094 int retval; 3095 3096 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); 3097 3098 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); 3099 if (retval != 1) 3100 err(1, "GFX rc6"); 3101 3102 fclose(fp); 3103 3104 return 0; 3105 } 3106 /* 3107 * snapshot_gfx_mhz() 3108 * 3109 * record snapshot of 3110 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz 3111 * 3112 * return 1 if config change requires a restart, else return 0 3113 */ 3114 int snapshot_gfx_mhz(void) 3115 { 3116 static FILE *fp; 3117 int retval; 3118 3119 if (fp == NULL) 3120 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); 3121 else { 3122 rewind(fp); 3123 fflush(fp); 3124 } 3125 3126 retval = fscanf(fp, "%d", &gfx_cur_mhz); 3127 if (retval != 1) 3128 err(1, "GFX MHz"); 3129 3130 return 0; 3131 } 3132 3133 /* 3134 * snapshot_gfx_cur_mhz() 3135 * 3136 * record snapshot of 3137 * /sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz 3138 * 3139 * return 1 if config change requires a restart, else return 0 3140 */ 3141 int snapshot_gfx_act_mhz(void) 3142 { 3143 static FILE *fp; 3144 int retval; 3145 3146 if (fp == NULL) 3147 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", "r"); 3148 else { 3149 rewind(fp); 3150 fflush(fp); 3151 } 3152 3153 retval = fscanf(fp, "%d", &gfx_act_mhz); 3154 if (retval != 1) 3155 err(1, "GFX ACT MHz"); 3156 3157 return 0; 3158 } 3159 3160 /* 3161 * snapshot_cpu_lpi() 3162 * 3163 * record snapshot of 3164 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us 3165 */ 3166 int snapshot_cpu_lpi_us(void) 3167 { 3168 FILE *fp; 3169 int retval; 3170 3171 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r"); 3172 3173 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us); 3174 if (retval != 1) { 3175 fprintf(stderr, "Disabling Low Power Idle CPU output\n"); 3176 BIC_NOT_PRESENT(BIC_CPU_LPI); 3177 fclose(fp); 3178 return -1; 3179 } 3180 3181 fclose(fp); 3182 3183 return 0; 3184 } 3185 /* 3186 * snapshot_sys_lpi() 3187 * 3188 * record snapshot of sys_lpi_file 3189 */ 3190 int snapshot_sys_lpi_us(void) 3191 { 3192 FILE *fp; 3193 int retval; 3194 3195 fp = fopen_or_die(sys_lpi_file, "r"); 3196 3197 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us); 3198 if (retval != 1) { 3199 fprintf(stderr, "Disabling Low Power Idle System output\n"); 3200 BIC_NOT_PRESENT(BIC_SYS_LPI); 3201 fclose(fp); 3202 return -1; 3203 } 3204 fclose(fp); 3205 3206 return 0; 3207 } 3208 /* 3209 * snapshot /proc and /sys files 3210 * 3211 * return 1 if configuration restart needed, else return 0 3212 */ 3213 int snapshot_proc_sysfs_files(void) 3214 { 3215 if (DO_BIC(BIC_IRQ)) 3216 if (snapshot_proc_interrupts()) 3217 return 1; 3218 3219 if (DO_BIC(BIC_GFX_rc6)) 3220 snapshot_gfx_rc6_ms(); 3221 3222 if (DO_BIC(BIC_GFXMHz)) 3223 snapshot_gfx_mhz(); 3224 3225 if (DO_BIC(BIC_GFXACTMHz)) 3226 snapshot_gfx_act_mhz(); 3227 3228 if (DO_BIC(BIC_CPU_LPI)) 3229 snapshot_cpu_lpi_us(); 3230 3231 if (DO_BIC(BIC_SYS_LPI)) 3232 snapshot_sys_lpi_us(); 3233 3234 return 0; 3235 } 3236 3237 int exit_requested; 3238 3239 static void signal_handler (int signal) 3240 { 3241 switch (signal) { 3242 case SIGINT: 3243 exit_requested = 1; 3244 if (debug) 3245 fprintf(stderr, " SIGINT\n"); 3246 break; 3247 case SIGUSR1: 3248 if (debug > 1) 3249 fprintf(stderr, "SIGUSR1\n"); 3250 break; 3251 } 3252 } 3253 3254 void setup_signal_handler(void) 3255 { 3256 struct sigaction sa; 3257 3258 memset(&sa, 0, sizeof(sa)); 3259 3260 sa.sa_handler = &signal_handler; 3261 3262 if (sigaction(SIGINT, &sa, NULL) < 0) 3263 err(1, "sigaction SIGINT"); 3264 if (sigaction(SIGUSR1, &sa, NULL) < 0) 3265 err(1, "sigaction SIGUSR1"); 3266 } 3267 3268 void do_sleep(void) 3269 { 3270 struct timeval tout; 3271 struct timespec rest; 3272 fd_set readfds; 3273 int retval; 3274 3275 FD_ZERO(&readfds); 3276 FD_SET(0, &readfds); 3277 3278 if (ignore_stdin) { 3279 nanosleep(&interval_ts, NULL); 3280 return; 3281 } 3282 3283 tout = interval_tv; 3284 retval = select(1, &readfds, NULL, NULL, &tout); 3285 3286 if (retval == 1) { 3287 switch (getc(stdin)) { 3288 case 'q': 3289 exit_requested = 1; 3290 break; 3291 case EOF: 3292 /* 3293 * 'stdin' is a pipe closed on the other end. There 3294 * won't be any further input. 3295 */ 3296 ignore_stdin = 1; 3297 /* Sleep the rest of the time */ 3298 rest.tv_sec = (tout.tv_sec + tout.tv_usec / 1000000); 3299 rest.tv_nsec = (tout.tv_usec % 1000000) * 1000; 3300 nanosleep(&rest, NULL); 3301 } 3302 } 3303 } 3304 3305 int get_msr_sum(int cpu, off_t offset, unsigned long long *msr) 3306 { 3307 int ret, idx; 3308 unsigned long long msr_cur, msr_last; 3309 3310 if (!per_cpu_msr_sum) 3311 return 1; 3312 3313 idx = offset_to_idx(offset); 3314 if (idx < 0) 3315 return idx; 3316 /* get_msr_sum() = sum + (get_msr() - last) */ 3317 ret = get_msr(cpu, offset, &msr_cur); 3318 if (ret) 3319 return ret; 3320 msr_last = per_cpu_msr_sum[cpu].entries[idx].last; 3321 DELTA_WRAP32(msr_cur, msr_last); 3322 *msr = msr_last + per_cpu_msr_sum[cpu].entries[idx].sum; 3323 3324 return 0; 3325 } 3326 3327 timer_t timerid; 3328 3329 /* Timer callback, update the sum of MSRs periodically. */ 3330 static int update_msr_sum(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3331 { 3332 int i, ret; 3333 int cpu = t->cpu_id; 3334 3335 for (i = IDX_PKG_ENERGY; i < IDX_COUNT; i++) { 3336 unsigned long long msr_cur, msr_last; 3337 int offset; 3338 3339 if (!idx_valid(i)) 3340 continue; 3341 offset = idx_to_offset(i); 3342 if (offset < 0) 3343 continue; 3344 ret = get_msr(cpu, offset, &msr_cur); 3345 if (ret) { 3346 fprintf(outf, "Can not update msr(0x%x)\n", offset); 3347 continue; 3348 } 3349 3350 msr_last = per_cpu_msr_sum[cpu].entries[i].last; 3351 per_cpu_msr_sum[cpu].entries[i].last = msr_cur & 0xffffffff; 3352 3353 DELTA_WRAP32(msr_cur, msr_last); 3354 per_cpu_msr_sum[cpu].entries[i].sum += msr_last; 3355 } 3356 return 0; 3357 } 3358 3359 static void 3360 msr_record_handler(union sigval v) 3361 { 3362 for_all_cpus(update_msr_sum, EVEN_COUNTERS); 3363 } 3364 3365 void msr_sum_record(void) 3366 { 3367 struct itimerspec its; 3368 struct sigevent sev; 3369 3370 per_cpu_msr_sum = calloc(topo.max_cpu_num + 1, sizeof(struct msr_sum_array)); 3371 if (!per_cpu_msr_sum) { 3372 fprintf(outf, "Can not allocate memory for long time MSR.\n"); 3373 return; 3374 } 3375 /* 3376 * Signal handler might be restricted, so use thread notifier instead. 3377 */ 3378 memset(&sev, 0, sizeof(struct sigevent)); 3379 sev.sigev_notify = SIGEV_THREAD; 3380 sev.sigev_notify_function = msr_record_handler; 3381 3382 sev.sigev_value.sival_ptr = &timerid; 3383 if (timer_create(CLOCK_REALTIME, &sev, &timerid) == -1) { 3384 fprintf(outf, "Can not create timer.\n"); 3385 goto release_msr; 3386 } 3387 3388 its.it_value.tv_sec = 0; 3389 its.it_value.tv_nsec = 1; 3390 /* 3391 * A wraparound time has been calculated early. 3392 * Some sources state that the peak power for a 3393 * microprocessor is usually 1.5 times the TDP rating, 3394 * use 2 * TDP for safety. 3395 */ 3396 its.it_interval.tv_sec = rapl_joule_counter_range / 2; 3397 its.it_interval.tv_nsec = 0; 3398 3399 if (timer_settime(timerid, 0, &its, NULL) == -1) { 3400 fprintf(outf, "Can not set timer.\n"); 3401 goto release_timer; 3402 } 3403 return; 3404 3405 release_timer: 3406 timer_delete(timerid); 3407 release_msr: 3408 free(per_cpu_msr_sum); 3409 } 3410 3411 void turbostat_loop() 3412 { 3413 int retval; 3414 int restarted = 0; 3415 int done_iters = 0; 3416 3417 setup_signal_handler(); 3418 3419 restart: 3420 restarted++; 3421 3422 snapshot_proc_sysfs_files(); 3423 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3424 first_counter_read = 0; 3425 if (retval < -1) { 3426 exit(retval); 3427 } else if (retval == -1) { 3428 if (restarted > 10) { 3429 exit(retval); 3430 } 3431 re_initialize(); 3432 goto restart; 3433 } 3434 restarted = 0; 3435 done_iters = 0; 3436 gettimeofday(&tv_even, (struct timezone *)NULL); 3437 3438 while (1) { 3439 if (for_all_proc_cpus(cpu_is_not_present)) { 3440 re_initialize(); 3441 goto restart; 3442 } 3443 do_sleep(); 3444 if (snapshot_proc_sysfs_files()) 3445 goto restart; 3446 retval = for_all_cpus(get_counters, ODD_COUNTERS); 3447 if (retval < -1) { 3448 exit(retval); 3449 } else if (retval == -1) { 3450 re_initialize(); 3451 goto restart; 3452 } 3453 gettimeofday(&tv_odd, (struct timezone *)NULL); 3454 timersub(&tv_odd, &tv_even, &tv_delta); 3455 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) { 3456 re_initialize(); 3457 goto restart; 3458 } 3459 compute_average(EVEN_COUNTERS); 3460 format_all_counters(EVEN_COUNTERS); 3461 flush_output_stdout(); 3462 if (exit_requested) 3463 break; 3464 if (num_iterations && ++done_iters >= num_iterations) 3465 break; 3466 do_sleep(); 3467 if (snapshot_proc_sysfs_files()) 3468 goto restart; 3469 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3470 if (retval < -1) { 3471 exit(retval); 3472 } else if (retval == -1) { 3473 re_initialize(); 3474 goto restart; 3475 } 3476 gettimeofday(&tv_even, (struct timezone *)NULL); 3477 timersub(&tv_even, &tv_odd, &tv_delta); 3478 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) { 3479 re_initialize(); 3480 goto restart; 3481 } 3482 compute_average(ODD_COUNTERS); 3483 format_all_counters(ODD_COUNTERS); 3484 flush_output_stdout(); 3485 if (exit_requested) 3486 break; 3487 if (num_iterations && ++done_iters >= num_iterations) 3488 break; 3489 } 3490 } 3491 3492 void check_dev_msr() 3493 { 3494 struct stat sb; 3495 char pathname[32]; 3496 3497 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3498 if (stat(pathname, &sb)) 3499 if (system("/sbin/modprobe msr > /dev/null 2>&1")) 3500 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); 3501 } 3502 3503 /* 3504 * check for CAP_SYS_RAWIO 3505 * return 0 on success 3506 * return 1 on fail 3507 */ 3508 int check_for_cap_sys_rawio(void) 3509 { 3510 cap_t caps; 3511 cap_flag_value_t cap_flag_value; 3512 3513 caps = cap_get_proc(); 3514 if (caps == NULL) 3515 err(-6, "cap_get_proc\n"); 3516 3517 if (cap_get_flag(caps, CAP_SYS_RAWIO, CAP_EFFECTIVE, &cap_flag_value)) 3518 err(-6, "cap_get\n"); 3519 3520 if (cap_flag_value != CAP_SET) { 3521 warnx("capget(CAP_SYS_RAWIO) failed," 3522 " try \"# setcap cap_sys_rawio=ep %s\"", progname); 3523 return 1; 3524 } 3525 3526 if (cap_free(caps) == -1) 3527 err(-6, "cap_free\n"); 3528 3529 return 0; 3530 } 3531 void check_permissions(void) 3532 { 3533 int do_exit = 0; 3534 char pathname[32]; 3535 3536 /* check for CAP_SYS_RAWIO */ 3537 do_exit += check_for_cap_sys_rawio(); 3538 3539 /* test file permissions */ 3540 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3541 if (euidaccess(pathname, R_OK)) { 3542 do_exit++; 3543 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); 3544 } 3545 3546 /* if all else fails, thell them to be root */ 3547 if (do_exit) 3548 if (getuid() != 0) 3549 warnx("... or simply run as root"); 3550 3551 if (do_exit) 3552 exit(-6); 3553 } 3554 3555 /* 3556 * NHM adds support for additional MSRs: 3557 * 3558 * MSR_SMI_COUNT 0x00000034 3559 * 3560 * MSR_PLATFORM_INFO 0x000000ce 3561 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 3562 * 3563 * MSR_MISC_PWR_MGMT 0x000001aa 3564 * 3565 * MSR_PKG_C3_RESIDENCY 0x000003f8 3566 * MSR_PKG_C6_RESIDENCY 0x000003f9 3567 * MSR_CORE_C3_RESIDENCY 0x000003fc 3568 * MSR_CORE_C6_RESIDENCY 0x000003fd 3569 * 3570 * Side effect: 3571 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL 3572 * sets has_misc_feature_control 3573 */ 3574 int probe_nhm_msrs(unsigned int family, unsigned int model) 3575 { 3576 unsigned long long msr; 3577 unsigned int base_ratio; 3578 int *pkg_cstate_limits; 3579 3580 if (!genuine_intel) 3581 return 0; 3582 3583 if (family != 6) 3584 return 0; 3585 3586 bclk = discover_bclk(family, model); 3587 3588 switch (model) { 3589 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 3590 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3591 pkg_cstate_limits = nhm_pkg_cstate_limits; 3592 break; 3593 case INTEL_FAM6_SANDYBRIDGE: /* SNB */ 3594 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */ 3595 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3596 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3597 pkg_cstate_limits = snb_pkg_cstate_limits; 3598 has_misc_feature_control = 1; 3599 break; 3600 case INTEL_FAM6_HASWELL: /* HSW */ 3601 case INTEL_FAM6_HASWELL_G: /* HSW */ 3602 case INTEL_FAM6_HASWELL_X: /* HSX */ 3603 case INTEL_FAM6_HASWELL_L: /* HSW */ 3604 case INTEL_FAM6_BROADWELL: /* BDW */ 3605 case INTEL_FAM6_BROADWELL_G: /* BDW */ 3606 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3607 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 3608 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 3609 pkg_cstate_limits = hsw_pkg_cstate_limits; 3610 has_misc_feature_control = 1; 3611 break; 3612 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3613 pkg_cstate_limits = skx_pkg_cstate_limits; 3614 has_misc_feature_control = 1; 3615 break; 3616 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 3617 no_MSR_MISC_PWR_MGMT = 1; 3618 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 3619 pkg_cstate_limits = slv_pkg_cstate_limits; 3620 break; 3621 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */ 3622 pkg_cstate_limits = amt_pkg_cstate_limits; 3623 no_MSR_MISC_PWR_MGMT = 1; 3624 break; 3625 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */ 3626 pkg_cstate_limits = phi_pkg_cstate_limits; 3627 break; 3628 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3629 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 3630 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 3631 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 3632 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */ 3633 pkg_cstate_limits = glm_pkg_cstate_limits; 3634 break; 3635 default: 3636 return 0; 3637 } 3638 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 3639 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; 3640 3641 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 3642 base_ratio = (msr >> 8) & 0xFF; 3643 3644 base_hz = base_ratio * bclk * 1000000; 3645 has_base_hz = 1; 3646 return 1; 3647 } 3648 /* 3649 * SLV client has support for unique MSRs: 3650 * 3651 * MSR_CC6_DEMOTION_POLICY_CONFIG 3652 * MSR_MC6_DEMOTION_POLICY_CONFIG 3653 */ 3654 3655 int has_slv_msrs(unsigned int family, unsigned int model) 3656 { 3657 if (!genuine_intel) 3658 return 0; 3659 3660 switch (model) { 3661 case INTEL_FAM6_ATOM_SILVERMONT: 3662 case INTEL_FAM6_ATOM_SILVERMONT_MID: 3663 case INTEL_FAM6_ATOM_AIRMONT_MID: 3664 return 1; 3665 } 3666 return 0; 3667 } 3668 int is_dnv(unsigned int family, unsigned int model) 3669 { 3670 3671 if (!genuine_intel) 3672 return 0; 3673 3674 switch (model) { 3675 case INTEL_FAM6_ATOM_GOLDMONT_D: 3676 return 1; 3677 } 3678 return 0; 3679 } 3680 int is_bdx(unsigned int family, unsigned int model) 3681 { 3682 3683 if (!genuine_intel) 3684 return 0; 3685 3686 switch (model) { 3687 case INTEL_FAM6_BROADWELL_X: 3688 return 1; 3689 } 3690 return 0; 3691 } 3692 int is_skx(unsigned int family, unsigned int model) 3693 { 3694 3695 if (!genuine_intel) 3696 return 0; 3697 3698 switch (model) { 3699 case INTEL_FAM6_SKYLAKE_X: 3700 return 1; 3701 } 3702 return 0; 3703 } 3704 int is_ehl(unsigned int family, unsigned int model) 3705 { 3706 if (!genuine_intel) 3707 return 0; 3708 3709 switch (model) { 3710 case INTEL_FAM6_ATOM_TREMONT: 3711 return 1; 3712 } 3713 return 0; 3714 } 3715 int is_jvl(unsigned int family, unsigned int model) 3716 { 3717 if (!genuine_intel) 3718 return 0; 3719 3720 switch (model) { 3721 case INTEL_FAM6_ATOM_TREMONT_D: 3722 return 1; 3723 } 3724 return 0; 3725 } 3726 3727 int has_turbo_ratio_limit(unsigned int family, unsigned int model) 3728 { 3729 if (has_slv_msrs(family, model)) 3730 return 0; 3731 3732 switch (model) { 3733 /* Nehalem compatible, but do not include turbo-ratio limit support */ 3734 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3735 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */ 3736 return 0; 3737 default: 3738 return 1; 3739 } 3740 } 3741 int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model) 3742 { 3743 if (has_slv_msrs(family, model)) 3744 return 1; 3745 3746 return 0; 3747 } 3748 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) 3749 { 3750 if (!genuine_intel) 3751 return 0; 3752 3753 if (family != 6) 3754 return 0; 3755 3756 switch (model) { 3757 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3758 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3759 return 1; 3760 default: 3761 return 0; 3762 } 3763 } 3764 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) 3765 { 3766 if (!genuine_intel) 3767 return 0; 3768 3769 if (family != 6) 3770 return 0; 3771 3772 switch (model) { 3773 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3774 return 1; 3775 default: 3776 return 0; 3777 } 3778 } 3779 3780 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) 3781 { 3782 if (!genuine_intel) 3783 return 0; 3784 3785 if (family != 6) 3786 return 0; 3787 3788 switch (model) { 3789 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 3790 return 1; 3791 default: 3792 return 0; 3793 } 3794 } 3795 int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model) 3796 { 3797 if (!genuine_intel) 3798 return 0; 3799 3800 if (family != 6) 3801 return 0; 3802 3803 switch (model) { 3804 case INTEL_FAM6_ATOM_GOLDMONT: 3805 case INTEL_FAM6_SKYLAKE_X: 3806 return 1; 3807 default: 3808 return 0; 3809 } 3810 } 3811 int has_config_tdp(unsigned int family, unsigned int model) 3812 { 3813 if (!genuine_intel) 3814 return 0; 3815 3816 if (family != 6) 3817 return 0; 3818 3819 switch (model) { 3820 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3821 case INTEL_FAM6_HASWELL: /* HSW */ 3822 case INTEL_FAM6_HASWELL_X: /* HSX */ 3823 case INTEL_FAM6_HASWELL_L: /* HSW */ 3824 case INTEL_FAM6_HASWELL_G: /* HSW */ 3825 case INTEL_FAM6_BROADWELL: /* BDW */ 3826 case INTEL_FAM6_BROADWELL_G: /* BDW */ 3827 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3828 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 3829 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 3830 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3831 3832 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 3833 return 1; 3834 default: 3835 return 0; 3836 } 3837 } 3838 3839 static void 3840 remove_underbar(char *s) 3841 { 3842 char *to = s; 3843 3844 while (*s) { 3845 if (*s != '_') 3846 *to++ = *s; 3847 s++; 3848 } 3849 3850 *to = 0; 3851 } 3852 3853 static void 3854 dump_cstate_pstate_config_info(unsigned int family, unsigned int model) 3855 { 3856 if (!do_nhm_platform_info) 3857 return; 3858 3859 dump_nhm_platform_info(); 3860 3861 if (has_hsw_turbo_ratio_limit(family, model)) 3862 dump_hsw_turbo_ratio_limits(); 3863 3864 if (has_ivt_turbo_ratio_limit(family, model)) 3865 dump_ivt_turbo_ratio_limits(); 3866 3867 if (has_turbo_ratio_limit(family, model)) 3868 dump_turbo_ratio_limits(family, model); 3869 3870 if (has_atom_turbo_ratio_limit(family, model)) 3871 dump_atom_turbo_ratio_limits(); 3872 3873 if (has_knl_turbo_ratio_limit(family, model)) 3874 dump_knl_turbo_ratio_limits(); 3875 3876 if (has_config_tdp(family, model)) 3877 dump_config_tdp(); 3878 3879 dump_nhm_cst_cfg(); 3880 } 3881 3882 static void dump_sysfs_file(char *path) 3883 { 3884 FILE *input; 3885 char cpuidle_buf[64]; 3886 3887 input = fopen(path, "r"); 3888 if (input == NULL) { 3889 if (debug) 3890 fprintf(outf, "NSFOD %s\n", path); 3891 return; 3892 } 3893 if (!fgets(cpuidle_buf, sizeof(cpuidle_buf), input)) 3894 err(1, "%s: failed to read file", path); 3895 fclose(input); 3896 3897 fprintf(outf, "%s: %s", strrchr(path, '/') + 1, cpuidle_buf); 3898 } 3899 static void 3900 dump_sysfs_cstate_config(void) 3901 { 3902 char path[64]; 3903 char name_buf[16]; 3904 char desc[64]; 3905 FILE *input; 3906 int state; 3907 char *sp; 3908 3909 if (access("/sys/devices/system/cpu/cpuidle", R_OK)) { 3910 fprintf(outf, "cpuidle not loaded\n"); 3911 return; 3912 } 3913 3914 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_driver"); 3915 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor"); 3916 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor_ro"); 3917 3918 for (state = 0; state < 10; ++state) { 3919 3920 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 3921 base_cpu, state); 3922 input = fopen(path, "r"); 3923 if (input == NULL) 3924 continue; 3925 if (!fgets(name_buf, sizeof(name_buf), input)) 3926 err(1, "%s: failed to read file", path); 3927 3928 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 3929 sp = strchr(name_buf, '-'); 3930 if (!sp) 3931 sp = strchrnul(name_buf, '\n'); 3932 *sp = '\0'; 3933 fclose(input); 3934 3935 remove_underbar(name_buf); 3936 3937 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc", 3938 base_cpu, state); 3939 input = fopen(path, "r"); 3940 if (input == NULL) 3941 continue; 3942 if (!fgets(desc, sizeof(desc), input)) 3943 err(1, "%s: failed to read file", path); 3944 3945 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc); 3946 fclose(input); 3947 } 3948 } 3949 static void 3950 dump_sysfs_pstate_config(void) 3951 { 3952 char path[64]; 3953 char driver_buf[64]; 3954 char governor_buf[64]; 3955 FILE *input; 3956 int turbo; 3957 3958 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver", 3959 base_cpu); 3960 input = fopen(path, "r"); 3961 if (input == NULL) { 3962 fprintf(outf, "NSFOD %s\n", path); 3963 return; 3964 } 3965 if (!fgets(driver_buf, sizeof(driver_buf), input)) 3966 err(1, "%s: failed to read file", path); 3967 fclose(input); 3968 3969 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor", 3970 base_cpu); 3971 input = fopen(path, "r"); 3972 if (input == NULL) { 3973 fprintf(outf, "NSFOD %s\n", path); 3974 return; 3975 } 3976 if (!fgets(governor_buf, sizeof(governor_buf), input)) 3977 err(1, "%s: failed to read file", path); 3978 fclose(input); 3979 3980 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf); 3981 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf); 3982 3983 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost"); 3984 input = fopen(path, "r"); 3985 if (input != NULL) { 3986 if (fscanf(input, "%d", &turbo) != 1) 3987 err(1, "%s: failed to parse number from file", path); 3988 fprintf(outf, "cpufreq boost: %d\n", turbo); 3989 fclose(input); 3990 } 3991 3992 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo"); 3993 input = fopen(path, "r"); 3994 if (input != NULL) { 3995 if (fscanf(input, "%d", &turbo) != 1) 3996 err(1, "%s: failed to parse number from file", path); 3997 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo); 3998 fclose(input); 3999 } 4000 } 4001 4002 4003 /* 4004 * print_epb() 4005 * Decode the ENERGY_PERF_BIAS MSR 4006 */ 4007 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4008 { 4009 char *epb_string; 4010 int cpu, epb; 4011 4012 if (!has_epb) 4013 return 0; 4014 4015 cpu = t->cpu_id; 4016 4017 /* EPB is per-package */ 4018 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4019 return 0; 4020 4021 if (cpu_migrate(cpu)) { 4022 fprintf(outf, "print_epb: Could not migrate to CPU %d\n", cpu); 4023 return -1; 4024 } 4025 4026 epb = get_epb(cpu); 4027 if (epb < 0) 4028 return 0; 4029 4030 switch (epb) { 4031 case ENERGY_PERF_BIAS_PERFORMANCE: 4032 epb_string = "performance"; 4033 break; 4034 case ENERGY_PERF_BIAS_NORMAL: 4035 epb_string = "balanced"; 4036 break; 4037 case ENERGY_PERF_BIAS_POWERSAVE: 4038 epb_string = "powersave"; 4039 break; 4040 default: 4041 epb_string = "custom"; 4042 break; 4043 } 4044 fprintf(outf, "cpu%d: EPB: %d (%s)\n", cpu, epb, epb_string); 4045 4046 return 0; 4047 } 4048 /* 4049 * print_hwp() 4050 * Decode the MSR_HWP_CAPABILITIES 4051 */ 4052 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4053 { 4054 unsigned long long msr; 4055 int cpu; 4056 4057 if (!has_hwp) 4058 return 0; 4059 4060 cpu = t->cpu_id; 4061 4062 /* MSR_HWP_CAPABILITIES is per-package */ 4063 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4064 return 0; 4065 4066 if (cpu_migrate(cpu)) { 4067 fprintf(outf, "print_hwp: Could not migrate to CPU %d\n", cpu); 4068 return -1; 4069 } 4070 4071 if (get_msr(cpu, MSR_PM_ENABLE, &msr)) 4072 return 0; 4073 4074 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", 4075 cpu, msr, (msr & (1 << 0)) ? "" : "No-"); 4076 4077 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ 4078 if ((msr & (1 << 0)) == 0) 4079 return 0; 4080 4081 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) 4082 return 0; 4083 4084 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " 4085 "(high %d guar %d eff %d low %d)\n", 4086 cpu, msr, 4087 (unsigned int)HWP_HIGHEST_PERF(msr), 4088 (unsigned int)HWP_GUARANTEED_PERF(msr), 4089 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), 4090 (unsigned int)HWP_LOWEST_PERF(msr)); 4091 4092 if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) 4093 return 0; 4094 4095 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " 4096 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n", 4097 cpu, msr, 4098 (unsigned int)(((msr) >> 0) & 0xff), 4099 (unsigned int)(((msr) >> 8) & 0xff), 4100 (unsigned int)(((msr) >> 16) & 0xff), 4101 (unsigned int)(((msr) >> 24) & 0xff), 4102 (unsigned int)(((msr) >> 32) & 0xff3), 4103 (unsigned int)(((msr) >> 42) & 0x1)); 4104 4105 if (has_hwp_pkg) { 4106 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) 4107 return 0; 4108 4109 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " 4110 "(min %d max %d des %d epp 0x%x window 0x%x)\n", 4111 cpu, msr, 4112 (unsigned int)(((msr) >> 0) & 0xff), 4113 (unsigned int)(((msr) >> 8) & 0xff), 4114 (unsigned int)(((msr) >> 16) & 0xff), 4115 (unsigned int)(((msr) >> 24) & 0xff), 4116 (unsigned int)(((msr) >> 32) & 0xff3)); 4117 } 4118 if (has_hwp_notify) { 4119 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) 4120 return 0; 4121 4122 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " 4123 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", 4124 cpu, msr, 4125 ((msr) & 0x1) ? "EN" : "Dis", 4126 ((msr) & 0x2) ? "EN" : "Dis"); 4127 } 4128 if (get_msr(cpu, MSR_HWP_STATUS, &msr)) 4129 return 0; 4130 4131 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " 4132 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", 4133 cpu, msr, 4134 ((msr) & 0x1) ? "" : "No-", 4135 ((msr) & 0x2) ? "" : "No-"); 4136 4137 return 0; 4138 } 4139 4140 /* 4141 * print_perf_limit() 4142 */ 4143 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4144 { 4145 unsigned long long msr; 4146 int cpu; 4147 4148 cpu = t->cpu_id; 4149 4150 /* per-package */ 4151 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4152 return 0; 4153 4154 if (cpu_migrate(cpu)) { 4155 fprintf(outf, "print_perf_limit: Could not migrate to CPU %d\n", cpu); 4156 return -1; 4157 } 4158 4159 if (do_core_perf_limit_reasons) { 4160 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); 4161 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4162 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", 4163 (msr & 1 << 15) ? "bit15, " : "", 4164 (msr & 1 << 14) ? "bit14, " : "", 4165 (msr & 1 << 13) ? "Transitions, " : "", 4166 (msr & 1 << 12) ? "MultiCoreTurbo, " : "", 4167 (msr & 1 << 11) ? "PkgPwrL2, " : "", 4168 (msr & 1 << 10) ? "PkgPwrL1, " : "", 4169 (msr & 1 << 9) ? "CorePwr, " : "", 4170 (msr & 1 << 8) ? "Amps, " : "", 4171 (msr & 1 << 6) ? "VR-Therm, " : "", 4172 (msr & 1 << 5) ? "Auto-HWP, " : "", 4173 (msr & 1 << 4) ? "Graphics, " : "", 4174 (msr & 1 << 2) ? "bit2, " : "", 4175 (msr & 1 << 1) ? "ThermStatus, " : "", 4176 (msr & 1 << 0) ? "PROCHOT, " : ""); 4177 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 4178 (msr & 1 << 31) ? "bit31, " : "", 4179 (msr & 1 << 30) ? "bit30, " : "", 4180 (msr & 1 << 29) ? "Transitions, " : "", 4181 (msr & 1 << 28) ? "MultiCoreTurbo, " : "", 4182 (msr & 1 << 27) ? "PkgPwrL2, " : "", 4183 (msr & 1 << 26) ? "PkgPwrL1, " : "", 4184 (msr & 1 << 25) ? "CorePwr, " : "", 4185 (msr & 1 << 24) ? "Amps, " : "", 4186 (msr & 1 << 22) ? "VR-Therm, " : "", 4187 (msr & 1 << 21) ? "Auto-HWP, " : "", 4188 (msr & 1 << 20) ? "Graphics, " : "", 4189 (msr & 1 << 18) ? "bit18, " : "", 4190 (msr & 1 << 17) ? "ThermStatus, " : "", 4191 (msr & 1 << 16) ? "PROCHOT, " : ""); 4192 4193 } 4194 if (do_gfx_perf_limit_reasons) { 4195 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); 4196 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4197 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", 4198 (msr & 1 << 0) ? "PROCHOT, " : "", 4199 (msr & 1 << 1) ? "ThermStatus, " : "", 4200 (msr & 1 << 4) ? "Graphics, " : "", 4201 (msr & 1 << 6) ? "VR-Therm, " : "", 4202 (msr & 1 << 8) ? "Amps, " : "", 4203 (msr & 1 << 9) ? "GFXPwr, " : "", 4204 (msr & 1 << 10) ? "PkgPwrL1, " : "", 4205 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 4206 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", 4207 (msr & 1 << 16) ? "PROCHOT, " : "", 4208 (msr & 1 << 17) ? "ThermStatus, " : "", 4209 (msr & 1 << 20) ? "Graphics, " : "", 4210 (msr & 1 << 22) ? "VR-Therm, " : "", 4211 (msr & 1 << 24) ? "Amps, " : "", 4212 (msr & 1 << 25) ? "GFXPwr, " : "", 4213 (msr & 1 << 26) ? "PkgPwrL1, " : "", 4214 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 4215 } 4216 if (do_ring_perf_limit_reasons) { 4217 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); 4218 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 4219 fprintf(outf, " (Active: %s%s%s%s%s%s)", 4220 (msr & 1 << 0) ? "PROCHOT, " : "", 4221 (msr & 1 << 1) ? "ThermStatus, " : "", 4222 (msr & 1 << 6) ? "VR-Therm, " : "", 4223 (msr & 1 << 8) ? "Amps, " : "", 4224 (msr & 1 << 10) ? "PkgPwrL1, " : "", 4225 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 4226 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", 4227 (msr & 1 << 16) ? "PROCHOT, " : "", 4228 (msr & 1 << 17) ? "ThermStatus, " : "", 4229 (msr & 1 << 22) ? "VR-Therm, " : "", 4230 (msr & 1 << 24) ? "Amps, " : "", 4231 (msr & 1 << 26) ? "PkgPwrL1, " : "", 4232 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 4233 } 4234 return 0; 4235 } 4236 4237 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ 4238 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ 4239 4240 double get_tdp_intel(unsigned int model) 4241 { 4242 unsigned long long msr; 4243 4244 if (do_rapl & RAPL_PKG_POWER_INFO) 4245 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) 4246 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; 4247 4248 switch (model) { 4249 case INTEL_FAM6_ATOM_SILVERMONT: 4250 case INTEL_FAM6_ATOM_SILVERMONT_D: 4251 return 30.0; 4252 default: 4253 return 135.0; 4254 } 4255 } 4256 4257 double get_tdp_amd(unsigned int family) 4258 { 4259 /* This is the max stock TDP of HEDT/Server Fam17h+ chips */ 4260 return 280.0; 4261 } 4262 4263 /* 4264 * rapl_dram_energy_units_probe() 4265 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR. 4266 */ 4267 static double 4268 rapl_dram_energy_units_probe(int model, double rapl_energy_units) 4269 { 4270 /* only called for genuine_intel, family 6 */ 4271 4272 switch (model) { 4273 case INTEL_FAM6_HASWELL_X: /* HSX */ 4274 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4275 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4276 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4277 return (rapl_dram_energy_units = 15.3 / 1000000); 4278 default: 4279 return (rapl_energy_units); 4280 } 4281 } 4282 4283 void rapl_probe_intel(unsigned int family, unsigned int model) 4284 { 4285 unsigned long long msr; 4286 unsigned int time_unit; 4287 double tdp; 4288 4289 if (family != 6) 4290 return; 4291 4292 switch (model) { 4293 case INTEL_FAM6_SANDYBRIDGE: 4294 case INTEL_FAM6_IVYBRIDGE: 4295 case INTEL_FAM6_HASWELL: /* HSW */ 4296 case INTEL_FAM6_HASWELL_L: /* HSW */ 4297 case INTEL_FAM6_HASWELL_G: /* HSW */ 4298 case INTEL_FAM6_BROADWELL: /* BDW */ 4299 case INTEL_FAM6_BROADWELL_G: /* BDW */ 4300 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; 4301 if (rapl_joules) { 4302 BIC_PRESENT(BIC_Pkg_J); 4303 BIC_PRESENT(BIC_Cor_J); 4304 BIC_PRESENT(BIC_GFX_J); 4305 } else { 4306 BIC_PRESENT(BIC_PkgWatt); 4307 BIC_PRESENT(BIC_CorWatt); 4308 BIC_PRESENT(BIC_GFXWatt); 4309 } 4310 break; 4311 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4312 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4313 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; 4314 if (rapl_joules) 4315 BIC_PRESENT(BIC_Pkg_J); 4316 else 4317 BIC_PRESENT(BIC_PkgWatt); 4318 break; 4319 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 4320 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_GFX | RAPL_PKG_POWER_INFO; 4321 if (rapl_joules) { 4322 BIC_PRESENT(BIC_Pkg_J); 4323 BIC_PRESENT(BIC_Cor_J); 4324 BIC_PRESENT(BIC_RAM_J); 4325 BIC_PRESENT(BIC_GFX_J); 4326 } else { 4327 BIC_PRESENT(BIC_PkgWatt); 4328 BIC_PRESENT(BIC_CorWatt); 4329 BIC_PRESENT(BIC_RAMWatt); 4330 BIC_PRESENT(BIC_GFXWatt); 4331 } 4332 break; 4333 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */ 4334 do_rapl = RAPL_PKG | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 4335 BIC_PRESENT(BIC_PKG__); 4336 if (rapl_joules) 4337 BIC_PRESENT(BIC_Pkg_J); 4338 else 4339 BIC_PRESENT(BIC_PkgWatt); 4340 break; 4341 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4342 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4343 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_GFX | RAPL_PKG_POWER_INFO; 4344 BIC_PRESENT(BIC_PKG__); 4345 BIC_PRESENT(BIC_RAM__); 4346 if (rapl_joules) { 4347 BIC_PRESENT(BIC_Pkg_J); 4348 BIC_PRESENT(BIC_Cor_J); 4349 BIC_PRESENT(BIC_RAM_J); 4350 BIC_PRESENT(BIC_GFX_J); 4351 } else { 4352 BIC_PRESENT(BIC_PkgWatt); 4353 BIC_PRESENT(BIC_CorWatt); 4354 BIC_PRESENT(BIC_RAMWatt); 4355 BIC_PRESENT(BIC_GFXWatt); 4356 } 4357 break; 4358 case INTEL_FAM6_HASWELL_X: /* HSX */ 4359 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4360 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4361 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4362 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 4363 BIC_PRESENT(BIC_PKG__); 4364 BIC_PRESENT(BIC_RAM__); 4365 if (rapl_joules) { 4366 BIC_PRESENT(BIC_Pkg_J); 4367 BIC_PRESENT(BIC_RAM_J); 4368 } else { 4369 BIC_PRESENT(BIC_PkgWatt); 4370 BIC_PRESENT(BIC_RAMWatt); 4371 } 4372 break; 4373 case INTEL_FAM6_SANDYBRIDGE_X: 4374 case INTEL_FAM6_IVYBRIDGE_X: 4375 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; 4376 BIC_PRESENT(BIC_PKG__); 4377 BIC_PRESENT(BIC_RAM__); 4378 if (rapl_joules) { 4379 BIC_PRESENT(BIC_Pkg_J); 4380 BIC_PRESENT(BIC_Cor_J); 4381 BIC_PRESENT(BIC_RAM_J); 4382 } else { 4383 BIC_PRESENT(BIC_PkgWatt); 4384 BIC_PRESENT(BIC_CorWatt); 4385 BIC_PRESENT(BIC_RAMWatt); 4386 } 4387 break; 4388 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 4389 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 4390 do_rapl = RAPL_PKG | RAPL_CORES; 4391 if (rapl_joules) { 4392 BIC_PRESENT(BIC_Pkg_J); 4393 BIC_PRESENT(BIC_Cor_J); 4394 } else { 4395 BIC_PRESENT(BIC_PkgWatt); 4396 BIC_PRESENT(BIC_CorWatt); 4397 } 4398 break; 4399 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 4400 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS; 4401 BIC_PRESENT(BIC_PKG__); 4402 BIC_PRESENT(BIC_RAM__); 4403 if (rapl_joules) { 4404 BIC_PRESENT(BIC_Pkg_J); 4405 BIC_PRESENT(BIC_Cor_J); 4406 BIC_PRESENT(BIC_RAM_J); 4407 } else { 4408 BIC_PRESENT(BIC_PkgWatt); 4409 BIC_PRESENT(BIC_CorWatt); 4410 BIC_PRESENT(BIC_RAMWatt); 4411 } 4412 break; 4413 default: 4414 return; 4415 } 4416 4417 /* units on package 0, verify later other packages match */ 4418 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) 4419 return; 4420 4421 rapl_power_units = 1.0 / (1 << (msr & 0xF)); 4422 if (model == INTEL_FAM6_ATOM_SILVERMONT) 4423 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; 4424 else 4425 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 4426 4427 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units); 4428 4429 time_unit = msr >> 16 & 0xF; 4430 if (time_unit == 0) 4431 time_unit = 0xA; 4432 4433 rapl_time_units = 1.0 / (1 << (time_unit)); 4434 4435 tdp = get_tdp_intel(model); 4436 4437 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 4438 if (!quiet) 4439 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 4440 } 4441 4442 void rapl_probe_amd(unsigned int family, unsigned int model) 4443 { 4444 unsigned long long msr; 4445 unsigned int eax, ebx, ecx, edx; 4446 unsigned int has_rapl = 0; 4447 double tdp; 4448 4449 if (max_extended_level >= 0x80000007) { 4450 __cpuid(0x80000007, eax, ebx, ecx, edx); 4451 /* RAPL (Fam 17h+) */ 4452 has_rapl = edx & (1 << 14); 4453 } 4454 4455 if (!has_rapl || family < 0x17) 4456 return; 4457 4458 do_rapl = RAPL_AMD_F17H | RAPL_PER_CORE_ENERGY; 4459 if (rapl_joules) { 4460 BIC_PRESENT(BIC_Pkg_J); 4461 BIC_PRESENT(BIC_Cor_J); 4462 } else { 4463 BIC_PRESENT(BIC_PkgWatt); 4464 BIC_PRESENT(BIC_CorWatt); 4465 } 4466 4467 if (get_msr(base_cpu, MSR_RAPL_PWR_UNIT, &msr)) 4468 return; 4469 4470 rapl_time_units = ldexp(1.0, -(msr >> 16 & 0xf)); 4471 rapl_energy_units = ldexp(1.0, -(msr >> 8 & 0x1f)); 4472 rapl_power_units = ldexp(1.0, -(msr & 0xf)); 4473 4474 tdp = get_tdp_amd(family); 4475 4476 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 4477 if (!quiet) 4478 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 4479 } 4480 4481 /* 4482 * rapl_probe() 4483 * 4484 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units 4485 */ 4486 void rapl_probe(unsigned int family, unsigned int model) 4487 { 4488 if (genuine_intel) 4489 rapl_probe_intel(family, model); 4490 if (authentic_amd || hygon_genuine) 4491 rapl_probe_amd(family, model); 4492 } 4493 4494 void perf_limit_reasons_probe(unsigned int family, unsigned int model) 4495 { 4496 if (!genuine_intel) 4497 return; 4498 4499 if (family != 6) 4500 return; 4501 4502 switch (model) { 4503 case INTEL_FAM6_HASWELL: /* HSW */ 4504 case INTEL_FAM6_HASWELL_L: /* HSW */ 4505 case INTEL_FAM6_HASWELL_G: /* HSW */ 4506 do_gfx_perf_limit_reasons = 1; 4507 case INTEL_FAM6_HASWELL_X: /* HSX */ 4508 do_core_perf_limit_reasons = 1; 4509 do_ring_perf_limit_reasons = 1; 4510 default: 4511 return; 4512 } 4513 } 4514 4515 void automatic_cstate_conversion_probe(unsigned int family, unsigned int model) 4516 { 4517 if (is_skx(family, model) || is_bdx(family, model)) 4518 has_automatic_cstate_conversion = 1; 4519 } 4520 4521 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4522 { 4523 unsigned long long msr; 4524 unsigned int dts, dts2; 4525 int cpu; 4526 4527 if (!(do_dts || do_ptm)) 4528 return 0; 4529 4530 cpu = t->cpu_id; 4531 4532 /* DTS is per-core, no need to print for each thread */ 4533 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 4534 return 0; 4535 4536 if (cpu_migrate(cpu)) { 4537 fprintf(outf, "print_thermal: Could not migrate to CPU %d\n", cpu); 4538 return -1; 4539 } 4540 4541 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { 4542 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 4543 return 0; 4544 4545 dts = (msr >> 16) & 0x7F; 4546 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", 4547 cpu, msr, tcc_activation_temp - dts); 4548 4549 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) 4550 return 0; 4551 4552 dts = (msr >> 16) & 0x7F; 4553 dts2 = (msr >> 8) & 0x7F; 4554 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 4555 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 4556 } 4557 4558 4559 if (do_dts && debug) { 4560 unsigned int resolution; 4561 4562 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 4563 return 0; 4564 4565 dts = (msr >> 16) & 0x7F; 4566 resolution = (msr >> 27) & 0xF; 4567 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", 4568 cpu, msr, tcc_activation_temp - dts, resolution); 4569 4570 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) 4571 return 0; 4572 4573 dts = (msr >> 16) & 0x7F; 4574 dts2 = (msr >> 8) & 0x7F; 4575 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 4576 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 4577 } 4578 4579 return 0; 4580 } 4581 4582 void print_power_limit_msr(int cpu, unsigned long long msr, char *label) 4583 { 4584 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n", 4585 cpu, label, 4586 ((msr >> 15) & 1) ? "EN" : "DIS", 4587 ((msr >> 0) & 0x7FFF) * rapl_power_units, 4588 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, 4589 (((msr >> 16) & 1) ? "EN" : "DIS")); 4590 4591 return; 4592 } 4593 4594 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4595 { 4596 unsigned long long msr; 4597 const char *msr_name; 4598 int cpu; 4599 4600 if (!do_rapl) 4601 return 0; 4602 4603 /* RAPL counters are per package, so print only for 1st thread/package */ 4604 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4605 return 0; 4606 4607 cpu = t->cpu_id; 4608 if (cpu_migrate(cpu)) { 4609 fprintf(outf, "print_rapl: Could not migrate to CPU %d\n", cpu); 4610 return -1; 4611 } 4612 4613 if (do_rapl & RAPL_AMD_F17H) { 4614 msr_name = "MSR_RAPL_PWR_UNIT"; 4615 if (get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr)) 4616 return -1; 4617 } else { 4618 msr_name = "MSR_RAPL_POWER_UNIT"; 4619 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) 4620 return -1; 4621 } 4622 4623 fprintf(outf, "cpu%d: %s: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr_name, msr, 4624 rapl_power_units, rapl_energy_units, rapl_time_units); 4625 4626 if (do_rapl & RAPL_PKG_POWER_INFO) { 4627 4628 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) 4629 return -5; 4630 4631 4632 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4633 cpu, msr, 4634 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4635 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4636 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4637 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4638 4639 } 4640 if (do_rapl & RAPL_PKG) { 4641 4642 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) 4643 return -9; 4644 4645 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", 4646 cpu, msr, (msr >> 63) & 1 ? "" : "UN"); 4647 4648 print_power_limit_msr(cpu, msr, "PKG Limit #1"); 4649 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n", 4650 cpu, 4651 ((msr >> 47) & 1) ? "EN" : "DIS", 4652 ((msr >> 32) & 0x7FFF) * rapl_power_units, 4653 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, 4654 ((msr >> 48) & 1) ? "EN" : "DIS"); 4655 } 4656 4657 if (do_rapl & RAPL_DRAM_POWER_INFO) { 4658 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) 4659 return -6; 4660 4661 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4662 cpu, msr, 4663 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4664 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4665 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4666 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4667 } 4668 if (do_rapl & RAPL_DRAM) { 4669 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) 4670 return -9; 4671 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", 4672 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4673 4674 print_power_limit_msr(cpu, msr, "DRAM Limit"); 4675 } 4676 if (do_rapl & RAPL_CORE_POLICY) { 4677 if (get_msr(cpu, MSR_PP0_POLICY, &msr)) 4678 return -7; 4679 4680 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); 4681 } 4682 if (do_rapl & RAPL_CORES_POWER_LIMIT) { 4683 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) 4684 return -9; 4685 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", 4686 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4687 print_power_limit_msr(cpu, msr, "Cores Limit"); 4688 } 4689 if (do_rapl & RAPL_GFX) { 4690 if (get_msr(cpu, MSR_PP1_POLICY, &msr)) 4691 return -8; 4692 4693 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); 4694 4695 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) 4696 return -9; 4697 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", 4698 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4699 print_power_limit_msr(cpu, msr, "GFX Limit"); 4700 } 4701 return 0; 4702 } 4703 4704 /* 4705 * SNB adds support for additional MSRs: 4706 * 4707 * MSR_PKG_C7_RESIDENCY 0x000003fa 4708 * MSR_CORE_C7_RESIDENCY 0x000003fe 4709 * MSR_PKG_C2_RESIDENCY 0x0000060d 4710 */ 4711 4712 int has_snb_msrs(unsigned int family, unsigned int model) 4713 { 4714 if (!genuine_intel) 4715 return 0; 4716 4717 switch (model) { 4718 case INTEL_FAM6_SANDYBRIDGE: 4719 case INTEL_FAM6_SANDYBRIDGE_X: 4720 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 4721 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 4722 case INTEL_FAM6_HASWELL: /* HSW */ 4723 case INTEL_FAM6_HASWELL_X: /* HSW */ 4724 case INTEL_FAM6_HASWELL_L: /* HSW */ 4725 case INTEL_FAM6_HASWELL_G: /* HSW */ 4726 case INTEL_FAM6_BROADWELL: /* BDW */ 4727 case INTEL_FAM6_BROADWELL_G: /* BDW */ 4728 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4729 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4730 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4731 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4732 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4733 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4734 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 4735 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 4736 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */ 4737 return 1; 4738 } 4739 return 0; 4740 } 4741 4742 /* 4743 * HSW ULT added support for C8/C9/C10 MSRs: 4744 * 4745 * MSR_PKG_C8_RESIDENCY 0x00000630 4746 * MSR_PKG_C9_RESIDENCY 0x00000631 4747 * MSR_PKG_C10_RESIDENCY 0x00000632 4748 * 4749 * MSR_PKGC8_IRTL 0x00000633 4750 * MSR_PKGC9_IRTL 0x00000634 4751 * MSR_PKGC10_IRTL 0x00000635 4752 * 4753 */ 4754 int has_c8910_msrs(unsigned int family, unsigned int model) 4755 { 4756 if (!genuine_intel) 4757 return 0; 4758 4759 switch (model) { 4760 case INTEL_FAM6_HASWELL_L: /* HSW */ 4761 case INTEL_FAM6_BROADWELL: /* BDW */ 4762 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4763 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4764 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4765 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4766 case INTEL_FAM6_ATOM_TREMONT: /* EHL */ 4767 return 1; 4768 } 4769 return 0; 4770 } 4771 4772 /* 4773 * SKL adds support for additional MSRS: 4774 * 4775 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 4776 * MSR_PKG_ANY_CORE_C0_RES 0x00000659 4777 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 4778 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 4779 */ 4780 int has_skl_msrs(unsigned int family, unsigned int model) 4781 { 4782 if (!genuine_intel) 4783 return 0; 4784 4785 switch (model) { 4786 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 4787 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4788 return 1; 4789 } 4790 return 0; 4791 } 4792 4793 int is_slm(unsigned int family, unsigned int model) 4794 { 4795 if (!genuine_intel) 4796 return 0; 4797 switch (model) { 4798 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 4799 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */ 4800 return 1; 4801 } 4802 return 0; 4803 } 4804 4805 int is_knl(unsigned int family, unsigned int model) 4806 { 4807 if (!genuine_intel) 4808 return 0; 4809 switch (model) { 4810 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4811 return 1; 4812 } 4813 return 0; 4814 } 4815 4816 int is_cnl(unsigned int family, unsigned int model) 4817 { 4818 if (!genuine_intel) 4819 return 0; 4820 4821 switch (model) { 4822 case INTEL_FAM6_CANNONLAKE_L: /* CNL */ 4823 return 1; 4824 } 4825 4826 return 0; 4827 } 4828 4829 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model) 4830 { 4831 if (is_knl(family, model)) 4832 return 1024; 4833 return 1; 4834 } 4835 4836 #define SLM_BCLK_FREQS 5 4837 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0}; 4838 4839 double slm_bclk(void) 4840 { 4841 unsigned long long msr = 3; 4842 unsigned int i; 4843 double freq; 4844 4845 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) 4846 fprintf(outf, "SLM BCLK: unknown\n"); 4847 4848 i = msr & 0xf; 4849 if (i >= SLM_BCLK_FREQS) { 4850 fprintf(outf, "SLM BCLK[%d] invalid\n", i); 4851 i = 3; 4852 } 4853 freq = slm_freq_table[i]; 4854 4855 if (!quiet) 4856 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); 4857 4858 return freq; 4859 } 4860 4861 double discover_bclk(unsigned int family, unsigned int model) 4862 { 4863 if (has_snb_msrs(family, model) || is_knl(family, model)) 4864 return 100.00; 4865 else if (is_slm(family, model)) 4866 return slm_bclk(); 4867 else 4868 return 133.33; 4869 } 4870 4871 /* 4872 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where 4873 * the Thermal Control Circuit (TCC) activates. 4874 * This is usually equal to tjMax. 4875 * 4876 * Older processors do not have this MSR, so there we guess, 4877 * but also allow cmdline over-ride with -T. 4878 * 4879 * Several MSR temperature values are in units of degrees-C 4880 * below this value, including the Digital Thermal Sensor (DTS), 4881 * Package Thermal Management Sensor (PTM), and thermal event thresholds. 4882 */ 4883 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4884 { 4885 unsigned long long msr; 4886 unsigned int target_c_local; 4887 int cpu; 4888 4889 /* tcc_activation_temp is used only for dts or ptm */ 4890 if (!(do_dts || do_ptm)) 4891 return 0; 4892 4893 /* this is a per-package concept */ 4894 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4895 return 0; 4896 4897 cpu = t->cpu_id; 4898 if (cpu_migrate(cpu)) { 4899 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 4900 return -1; 4901 } 4902 4903 if (tcc_activation_temp_override != 0) { 4904 tcc_activation_temp = tcc_activation_temp_override; 4905 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", 4906 cpu, tcc_activation_temp); 4907 return 0; 4908 } 4909 4910 /* Temperature Target MSR is Nehalem and newer only */ 4911 if (!do_nhm_platform_info) 4912 goto guess; 4913 4914 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) 4915 goto guess; 4916 4917 target_c_local = (msr >> 16) & 0xFF; 4918 4919 if (!quiet) 4920 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", 4921 cpu, msr, target_c_local); 4922 4923 if (!target_c_local) 4924 goto guess; 4925 4926 tcc_activation_temp = target_c_local; 4927 4928 return 0; 4929 4930 guess: 4931 tcc_activation_temp = TJMAX_DEFAULT; 4932 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", 4933 cpu, tcc_activation_temp); 4934 4935 return 0; 4936 } 4937 4938 void decode_feature_control_msr(void) 4939 { 4940 unsigned long long msr; 4941 4942 if (!get_msr(base_cpu, MSR_IA32_FEAT_CTL, &msr)) 4943 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", 4944 base_cpu, msr, 4945 msr & FEAT_CTL_LOCKED ? "" : "UN-", 4946 msr & (1 << 18) ? "SGX" : ""); 4947 } 4948 4949 void decode_misc_enable_msr(void) 4950 { 4951 unsigned long long msr; 4952 4953 if (!genuine_intel) 4954 return; 4955 4956 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) 4957 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n", 4958 base_cpu, msr, 4959 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-", 4960 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-", 4961 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-", 4962 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "", 4963 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : ""); 4964 } 4965 4966 void decode_misc_feature_control(void) 4967 { 4968 unsigned long long msr; 4969 4970 if (!has_misc_feature_control) 4971 return; 4972 4973 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr)) 4974 fprintf(outf, "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n", 4975 base_cpu, msr, 4976 msr & (0 << 0) ? "No-" : "", 4977 msr & (1 << 0) ? "No-" : "", 4978 msr & (2 << 0) ? "No-" : "", 4979 msr & (3 << 0) ? "No-" : ""); 4980 } 4981 /* 4982 * Decode MSR_MISC_PWR_MGMT 4983 * 4984 * Decode the bits according to the Nehalem documentation 4985 * bit[0] seems to continue to have same meaning going forward 4986 * bit[1] less so... 4987 */ 4988 void decode_misc_pwr_mgmt_msr(void) 4989 { 4990 unsigned long long msr; 4991 4992 if (!do_nhm_platform_info) 4993 return; 4994 4995 if (no_MSR_MISC_PWR_MGMT) 4996 return; 4997 4998 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) 4999 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n", 5000 base_cpu, msr, 5001 msr & (1 << 0) ? "DIS" : "EN", 5002 msr & (1 << 1) ? "EN" : "DIS", 5003 msr & (1 << 8) ? "EN" : "DIS"); 5004 } 5005 /* 5006 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG 5007 * 5008 * This MSRs are present on Silvermont processors, 5009 * Intel Atom processor E3000 series (Baytrail), and friends. 5010 */ 5011 void decode_c6_demotion_policy_msr(void) 5012 { 5013 unsigned long long msr; 5014 5015 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr)) 5016 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n", 5017 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 5018 5019 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr)) 5020 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n", 5021 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 5022 } 5023 5024 /* 5025 * When models are the same, for the purpose of turbostat, reuse 5026 */ 5027 unsigned int intel_model_duplicates(unsigned int model) 5028 { 5029 5030 switch(model) { 5031 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ 5032 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 5033 case 0x1F: /* Core i7 and i5 Processor - Nehalem */ 5034 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */ 5035 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */ 5036 return INTEL_FAM6_NEHALEM; 5037 5038 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 5039 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 5040 return INTEL_FAM6_NEHALEM_EX; 5041 5042 case INTEL_FAM6_XEON_PHI_KNM: 5043 return INTEL_FAM6_XEON_PHI_KNL; 5044 5045 case INTEL_FAM6_BROADWELL_X: 5046 case INTEL_FAM6_BROADWELL_D: /* BDX-DE */ 5047 return INTEL_FAM6_BROADWELL_X; 5048 5049 case INTEL_FAM6_SKYLAKE_L: 5050 case INTEL_FAM6_SKYLAKE: 5051 case INTEL_FAM6_KABYLAKE_L: 5052 case INTEL_FAM6_KABYLAKE: 5053 case INTEL_FAM6_COMETLAKE_L: 5054 case INTEL_FAM6_COMETLAKE: 5055 return INTEL_FAM6_SKYLAKE_L; 5056 5057 case INTEL_FAM6_ICELAKE_L: 5058 case INTEL_FAM6_ICELAKE_NNPI: 5059 case INTEL_FAM6_TIGERLAKE_L: 5060 case INTEL_FAM6_TIGERLAKE: 5061 case INTEL_FAM6_ROCKETLAKE: 5062 case INTEL_FAM6_LAKEFIELD: 5063 case INTEL_FAM6_ALDERLAKE: 5064 case INTEL_FAM6_ALDERLAKE_L: 5065 return INTEL_FAM6_CANNONLAKE_L; 5066 5067 case INTEL_FAM6_ATOM_TREMONT_L: 5068 return INTEL_FAM6_ATOM_TREMONT; 5069 5070 case INTEL_FAM6_ICELAKE_X: 5071 case INTEL_FAM6_ICELAKE_D: 5072 case INTEL_FAM6_SAPPHIRERAPIDS_X: 5073 return INTEL_FAM6_SKYLAKE_X; 5074 } 5075 return model; 5076 } 5077 5078 void print_dev_latency(void) 5079 { 5080 char *path = "/dev/cpu_dma_latency"; 5081 int fd; 5082 int value; 5083 int retval; 5084 5085 fd = open(path, O_RDONLY); 5086 if (fd < 0) { 5087 warn("fopen %s\n", path); 5088 return; 5089 } 5090 5091 retval = read(fd, (void *)&value, sizeof(int)); 5092 if (retval != sizeof(int)) { 5093 warn("read %s\n", path); 5094 close(fd); 5095 return; 5096 } 5097 fprintf(outf, "/dev/cpu_dma_latency: %d usec (%s)\n", 5098 value, value == 2000000000 ? "default" : "constrained"); 5099 5100 close(fd); 5101 } 5102 5103 5104 /* 5105 * Linux-perf manages the the HW instructions-retired counter 5106 * by enabling when requested, and hiding rollover 5107 */ 5108 void linux_perf_init(void) 5109 { 5110 if (!BIC_IS_ENABLED(BIC_IPC)) 5111 return; 5112 5113 if (access("/proc/sys/kernel/perf_event_paranoid", F_OK)) 5114 return; 5115 5116 fd_instr_count_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 5117 if (fd_instr_count_percpu == NULL) 5118 err(-1, "calloc fd_instr_count_percpu"); 5119 5120 BIC_PRESENT(BIC_IPC); 5121 } 5122 5123 void process_cpuid() 5124 { 5125 unsigned int eax, ebx, ecx, edx; 5126 unsigned int fms, family, model, stepping, ecx_flags, edx_flags; 5127 unsigned int has_turbo; 5128 unsigned long long ucode_patch = 0; 5129 5130 eax = ebx = ecx = edx = 0; 5131 5132 __cpuid(0, max_level, ebx, ecx, edx); 5133 5134 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69) 5135 genuine_intel = 1; 5136 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) 5137 authentic_amd = 1; 5138 else if (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e) 5139 hygon_genuine = 1; 5140 5141 if (!quiet) 5142 fprintf(outf, "CPUID(0): %.4s%.4s%.4s 0x%x CPUID levels\n", 5143 (char *)&ebx, (char *)&edx, (char *)&ecx, max_level); 5144 5145 __cpuid(1, fms, ebx, ecx, edx); 5146 family = (fms >> 8) & 0xf; 5147 model = (fms >> 4) & 0xf; 5148 stepping = fms & 0xf; 5149 if (family == 0xf) 5150 family += (fms >> 20) & 0xff; 5151 if (family >= 6) 5152 model += ((fms >> 16) & 0xf) << 4; 5153 ecx_flags = ecx; 5154 edx_flags = edx; 5155 5156 if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch)) 5157 warnx("get_msr(UCODE)\n"); 5158 5159 /* 5160 * check max extended function levels of CPUID. 5161 * This is needed to check for invariant TSC. 5162 * This check is valid for both Intel and AMD. 5163 */ 5164 ebx = ecx = edx = 0; 5165 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); 5166 5167 if (!quiet) { 5168 fprintf(outf, "CPUID(1): family:model:stepping 0x%x:%x:%x (%d:%d:%d) microcode 0x%x\n", 5169 family, model, stepping, family, model, stepping, (unsigned int)((ucode_patch >> 32) & 0xFFFFFFFF)); 5170 fprintf(outf, "CPUID(0x80000000): max_extended_levels: 0x%x\n", max_extended_level); 5171 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n", 5172 ecx_flags & (1 << 0) ? "SSE3" : "-", 5173 ecx_flags & (1 << 3) ? "MONITOR" : "-", 5174 ecx_flags & (1 << 6) ? "SMX" : "-", 5175 ecx_flags & (1 << 7) ? "EIST" : "-", 5176 ecx_flags & (1 << 8) ? "TM2" : "-", 5177 edx_flags & (1 << 4) ? "TSC" : "-", 5178 edx_flags & (1 << 5) ? "MSR" : "-", 5179 edx_flags & (1 << 22) ? "ACPI-TM" : "-", 5180 edx_flags & (1 << 28) ? "HT" : "-", 5181 edx_flags & (1 << 29) ? "TM" : "-"); 5182 } 5183 if (genuine_intel) 5184 model = intel_model_duplicates(model); 5185 5186 if (!(edx_flags & (1 << 5))) 5187 errx(1, "CPUID: no MSR"); 5188 5189 if (max_extended_level >= 0x80000007) { 5190 5191 /* 5192 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 5193 * this check is valid for both Intel and AMD 5194 */ 5195 __cpuid(0x80000007, eax, ebx, ecx, edx); 5196 has_invariant_tsc = edx & (1 << 8); 5197 } 5198 5199 /* 5200 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 5201 * this check is valid for both Intel and AMD 5202 */ 5203 5204 __cpuid(0x6, eax, ebx, ecx, edx); 5205 has_aperf = ecx & (1 << 0); 5206 if (has_aperf) { 5207 BIC_PRESENT(BIC_Avg_MHz); 5208 BIC_PRESENT(BIC_Busy); 5209 BIC_PRESENT(BIC_Bzy_MHz); 5210 } 5211 do_dts = eax & (1 << 0); 5212 if (do_dts) 5213 BIC_PRESENT(BIC_CoreTmp); 5214 has_turbo = eax & (1 << 1); 5215 do_ptm = eax & (1 << 6); 5216 if (do_ptm) 5217 BIC_PRESENT(BIC_PkgTmp); 5218 has_hwp = eax & (1 << 7); 5219 has_hwp_notify = eax & (1 << 8); 5220 has_hwp_activity_window = eax & (1 << 9); 5221 has_hwp_epp = eax & (1 << 10); 5222 has_hwp_pkg = eax & (1 << 11); 5223 has_epb = ecx & (1 << 3); 5224 5225 if (!quiet) 5226 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, " 5227 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", 5228 has_aperf ? "" : "No-", 5229 has_turbo ? "" : "No-", 5230 do_dts ? "" : "No-", 5231 do_ptm ? "" : "No-", 5232 has_hwp ? "" : "No-", 5233 has_hwp_notify ? "" : "No-", 5234 has_hwp_activity_window ? "" : "No-", 5235 has_hwp_epp ? "" : "No-", 5236 has_hwp_pkg ? "" : "No-", 5237 has_epb ? "" : "No-"); 5238 5239 if (!quiet) 5240 decode_misc_enable_msr(); 5241 5242 5243 if (max_level >= 0x7 && !quiet) { 5244 int has_sgx; 5245 5246 ecx = 0; 5247 5248 __cpuid_count(0x7, 0, eax, ebx, ecx, edx); 5249 5250 has_sgx = ebx & (1 << 2); 5251 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-"); 5252 5253 if (has_sgx) 5254 decode_feature_control_msr(); 5255 } 5256 5257 if (max_level >= 0x15) { 5258 unsigned int eax_crystal; 5259 unsigned int ebx_tsc; 5260 5261 /* 5262 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz 5263 */ 5264 eax_crystal = ebx_tsc = crystal_hz = edx = 0; 5265 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); 5266 5267 if (ebx_tsc != 0) { 5268 5269 if (!quiet && (ebx != 0)) 5270 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", 5271 eax_crystal, ebx_tsc, crystal_hz); 5272 5273 if (crystal_hz == 0) 5274 switch(model) { 5275 case INTEL_FAM6_SKYLAKE_L: /* SKL */ 5276 crystal_hz = 24000000; /* 24.0 MHz */ 5277 break; 5278 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */ 5279 crystal_hz = 25000000; /* 25.0 MHz */ 5280 break; 5281 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 5282 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 5283 crystal_hz = 19200000; /* 19.2 MHz */ 5284 break; 5285 default: 5286 crystal_hz = 0; 5287 } 5288 5289 if (crystal_hz) { 5290 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal; 5291 if (!quiet) 5292 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", 5293 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); 5294 } 5295 } 5296 } 5297 if (max_level >= 0x16) { 5298 unsigned int base_mhz, max_mhz, bus_mhz, edx; 5299 5300 /* 5301 * CPUID 16H Base MHz, Max MHz, Bus MHz 5302 */ 5303 base_mhz = max_mhz = bus_mhz = edx = 0; 5304 5305 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); 5306 if (!quiet) 5307 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", 5308 base_mhz, max_mhz, bus_mhz); 5309 } 5310 5311 if (has_aperf) 5312 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model); 5313 5314 BIC_PRESENT(BIC_IRQ); 5315 BIC_PRESENT(BIC_TSC_MHz); 5316 5317 if (probe_nhm_msrs(family, model)) { 5318 do_nhm_platform_info = 1; 5319 BIC_PRESENT(BIC_CPU_c1); 5320 BIC_PRESENT(BIC_CPU_c3); 5321 BIC_PRESENT(BIC_CPU_c6); 5322 BIC_PRESENT(BIC_SMI); 5323 } 5324 do_snb_cstates = has_snb_msrs(family, model); 5325 5326 if (do_snb_cstates) 5327 BIC_PRESENT(BIC_CPU_c7); 5328 5329 do_irtl_snb = has_snb_msrs(family, model); 5330 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2)) 5331 BIC_PRESENT(BIC_Pkgpc2); 5332 if (pkg_cstate_limit >= PCL__3) 5333 BIC_PRESENT(BIC_Pkgpc3); 5334 if (pkg_cstate_limit >= PCL__6) 5335 BIC_PRESENT(BIC_Pkgpc6); 5336 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7)) 5337 BIC_PRESENT(BIC_Pkgpc7); 5338 if (has_slv_msrs(family, model)) { 5339 BIC_NOT_PRESENT(BIC_Pkgpc2); 5340 BIC_NOT_PRESENT(BIC_Pkgpc3); 5341 BIC_PRESENT(BIC_Pkgpc6); 5342 BIC_NOT_PRESENT(BIC_Pkgpc7); 5343 BIC_PRESENT(BIC_Mod_c6); 5344 use_c1_residency_msr = 1; 5345 } 5346 if (is_jvl(family, model)) { 5347 BIC_NOT_PRESENT(BIC_CPU_c3); 5348 BIC_NOT_PRESENT(BIC_CPU_c7); 5349 BIC_NOT_PRESENT(BIC_Pkgpc2); 5350 BIC_NOT_PRESENT(BIC_Pkgpc3); 5351 BIC_NOT_PRESENT(BIC_Pkgpc6); 5352 BIC_NOT_PRESENT(BIC_Pkgpc7); 5353 } 5354 if (is_dnv(family, model)) { 5355 BIC_PRESENT(BIC_CPU_c1); 5356 BIC_NOT_PRESENT(BIC_CPU_c3); 5357 BIC_NOT_PRESENT(BIC_Pkgpc3); 5358 BIC_NOT_PRESENT(BIC_CPU_c7); 5359 BIC_NOT_PRESENT(BIC_Pkgpc7); 5360 use_c1_residency_msr = 1; 5361 } 5362 if (is_skx(family, model)) { 5363 BIC_NOT_PRESENT(BIC_CPU_c3); 5364 BIC_NOT_PRESENT(BIC_Pkgpc3); 5365 BIC_NOT_PRESENT(BIC_CPU_c7); 5366 BIC_NOT_PRESENT(BIC_Pkgpc7); 5367 } 5368 if (is_bdx(family, model)) { 5369 BIC_NOT_PRESENT(BIC_CPU_c7); 5370 BIC_NOT_PRESENT(BIC_Pkgpc7); 5371 } 5372 if (has_c8910_msrs(family, model)) { 5373 if (pkg_cstate_limit >= PCL__8) 5374 BIC_PRESENT(BIC_Pkgpc8); 5375 if (pkg_cstate_limit >= PCL__9) 5376 BIC_PRESENT(BIC_Pkgpc9); 5377 if (pkg_cstate_limit >= PCL_10) 5378 BIC_PRESENT(BIC_Pkgpc10); 5379 } 5380 do_irtl_hsw = has_c8910_msrs(family, model); 5381 if (has_skl_msrs(family, model)) { 5382 BIC_PRESENT(BIC_Totl_c0); 5383 BIC_PRESENT(BIC_Any_c0); 5384 BIC_PRESENT(BIC_GFX_c0); 5385 BIC_PRESENT(BIC_CPUGFX); 5386 } 5387 do_slm_cstates = is_slm(family, model); 5388 do_knl_cstates = is_knl(family, model); 5389 5390 if (do_slm_cstates || do_knl_cstates || is_cnl(family, model) || 5391 is_ehl(family, model)) 5392 BIC_NOT_PRESENT(BIC_CPU_c3); 5393 5394 if (!quiet) 5395 decode_misc_pwr_mgmt_msr(); 5396 5397 if (!quiet && has_slv_msrs(family, model)) 5398 decode_c6_demotion_policy_msr(); 5399 5400 rapl_probe(family, model); 5401 perf_limit_reasons_probe(family, model); 5402 automatic_cstate_conversion_probe(family, model); 5403 5404 if (!quiet) 5405 dump_cstate_pstate_config_info(family, model); 5406 5407 if (!quiet) 5408 print_dev_latency(); 5409 if (!quiet) 5410 dump_sysfs_cstate_config(); 5411 if (!quiet) 5412 dump_sysfs_pstate_config(); 5413 5414 if (has_skl_msrs(family, model)) 5415 calculate_tsc_tweak(); 5416 5417 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK)) 5418 BIC_PRESENT(BIC_GFX_rc6); 5419 5420 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK)) 5421 BIC_PRESENT(BIC_GFXMHz); 5422 5423 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", R_OK)) 5424 BIC_PRESENT(BIC_GFXACTMHz); 5425 5426 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK)) 5427 BIC_PRESENT(BIC_CPU_LPI); 5428 else 5429 BIC_NOT_PRESENT(BIC_CPU_LPI); 5430 5431 if (!access(sys_lpi_file_sysfs, R_OK)) { 5432 sys_lpi_file = sys_lpi_file_sysfs; 5433 BIC_PRESENT(BIC_SYS_LPI); 5434 } else if (!access(sys_lpi_file_debugfs, R_OK)) { 5435 sys_lpi_file = sys_lpi_file_debugfs; 5436 BIC_PRESENT(BIC_SYS_LPI); 5437 } else { 5438 sys_lpi_file_sysfs = NULL; 5439 BIC_NOT_PRESENT(BIC_SYS_LPI); 5440 } 5441 5442 if (!quiet) 5443 decode_misc_feature_control(); 5444 5445 return; 5446 } 5447 5448 /* 5449 * in /dev/cpu/ return success for names that are numbers 5450 * ie. filter out ".", "..", "microcode". 5451 */ 5452 int dir_filter(const struct dirent *dirp) 5453 { 5454 if (isdigit(dirp->d_name[0])) 5455 return 1; 5456 else 5457 return 0; 5458 } 5459 5460 int open_dev_cpu_msr(int dummy1) 5461 { 5462 return 0; 5463 } 5464 5465 void topology_probe() 5466 { 5467 int i; 5468 int max_core_id = 0; 5469 int max_package_id = 0; 5470 int max_die_id = 0; 5471 int max_siblings = 0; 5472 5473 /* Initialize num_cpus, max_cpu_num */ 5474 set_max_cpu_num(); 5475 topo.num_cpus = 0; 5476 for_all_proc_cpus(count_cpus); 5477 if (!summary_only && topo.num_cpus > 1) 5478 BIC_PRESENT(BIC_CPU); 5479 5480 if (debug > 1) 5481 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); 5482 5483 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); 5484 if (cpus == NULL) 5485 err(1, "calloc cpus"); 5486 5487 /* 5488 * Allocate and initialize cpu_present_set 5489 */ 5490 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); 5491 if (cpu_present_set == NULL) 5492 err(3, "CPU_ALLOC"); 5493 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 5494 CPU_ZERO_S(cpu_present_setsize, cpu_present_set); 5495 for_all_proc_cpus(mark_cpu_present); 5496 5497 /* 5498 * Validate that all cpus in cpu_subset are also in cpu_present_set 5499 */ 5500 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) { 5501 if (CPU_ISSET_S(i, cpu_subset_size, cpu_subset)) 5502 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set)) 5503 err(1, "cpu%d not present", i); 5504 } 5505 5506 /* 5507 * Allocate and initialize cpu_affinity_set 5508 */ 5509 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); 5510 if (cpu_affinity_set == NULL) 5511 err(3, "CPU_ALLOC"); 5512 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 5513 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 5514 5515 for_all_proc_cpus(init_thread_id); 5516 5517 /* 5518 * For online cpus 5519 * find max_core_id, max_package_id 5520 */ 5521 for (i = 0; i <= topo.max_cpu_num; ++i) { 5522 int siblings; 5523 5524 if (cpu_is_not_present(i)) { 5525 if (debug > 1) 5526 fprintf(outf, "cpu%d NOT PRESENT\n", i); 5527 continue; 5528 } 5529 5530 cpus[i].logical_cpu_id = i; 5531 5532 /* get package information */ 5533 cpus[i].physical_package_id = get_physical_package_id(i); 5534 if (cpus[i].physical_package_id > max_package_id) 5535 max_package_id = cpus[i].physical_package_id; 5536 5537 /* get die information */ 5538 cpus[i].die_id = get_die_id(i); 5539 if (cpus[i].die_id > max_die_id) 5540 max_die_id = cpus[i].die_id; 5541 5542 /* get numa node information */ 5543 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]); 5544 if (cpus[i].physical_node_id > topo.max_node_num) 5545 topo.max_node_num = cpus[i].physical_node_id; 5546 5547 /* get core information */ 5548 cpus[i].physical_core_id = get_core_id(i); 5549 if (cpus[i].physical_core_id > max_core_id) 5550 max_core_id = cpus[i].physical_core_id; 5551 5552 /* get thread information */ 5553 siblings = get_thread_siblings(&cpus[i]); 5554 if (siblings > max_siblings) 5555 max_siblings = siblings; 5556 if (cpus[i].thread_id == 0) 5557 topo.num_cores++; 5558 } 5559 5560 topo.cores_per_node = max_core_id + 1; 5561 if (debug > 1) 5562 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", 5563 max_core_id, topo.cores_per_node); 5564 if (!summary_only && topo.cores_per_node > 1) 5565 BIC_PRESENT(BIC_Core); 5566 5567 topo.num_die = max_die_id + 1; 5568 if (debug > 1) 5569 fprintf(outf, "max_die_id %d, sizing for %d die\n", 5570 max_die_id, topo.num_die); 5571 if (!summary_only && topo.num_die > 1) 5572 BIC_PRESENT(BIC_Die); 5573 5574 topo.num_packages = max_package_id + 1; 5575 if (debug > 1) 5576 fprintf(outf, "max_package_id %d, sizing for %d packages\n", 5577 max_package_id, topo.num_packages); 5578 if (!summary_only && topo.num_packages > 1) 5579 BIC_PRESENT(BIC_Package); 5580 5581 set_node_data(); 5582 if (debug > 1) 5583 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg); 5584 if (!summary_only && topo.nodes_per_pkg > 1) 5585 BIC_PRESENT(BIC_Node); 5586 5587 topo.threads_per_core = max_siblings; 5588 if (debug > 1) 5589 fprintf(outf, "max_siblings %d\n", max_siblings); 5590 5591 if (debug < 1) 5592 return; 5593 5594 for (i = 0; i <= topo.max_cpu_num; ++i) { 5595 if (cpu_is_not_present(i)) 5596 continue; 5597 fprintf(outf, 5598 "cpu %d pkg %d die %d node %d lnode %d core %d thread %d\n", 5599 i, cpus[i].physical_package_id, cpus[i].die_id, 5600 cpus[i].physical_node_id, 5601 cpus[i].logical_node_id, 5602 cpus[i].physical_core_id, 5603 cpus[i].thread_id); 5604 } 5605 5606 } 5607 5608 void 5609 allocate_counters(struct thread_data **t, struct core_data **c, 5610 struct pkg_data **p) 5611 { 5612 int i; 5613 int num_cores = topo.cores_per_node * topo.nodes_per_pkg * 5614 topo.num_packages; 5615 int num_threads = topo.threads_per_core * num_cores; 5616 5617 *t = calloc(num_threads, sizeof(struct thread_data)); 5618 if (*t == NULL) 5619 goto error; 5620 5621 for (i = 0; i < num_threads; i++) 5622 (*t)[i].cpu_id = -1; 5623 5624 *c = calloc(num_cores, sizeof(struct core_data)); 5625 if (*c == NULL) 5626 goto error; 5627 5628 for (i = 0; i < num_cores; i++) 5629 (*c)[i].core_id = -1; 5630 5631 *p = calloc(topo.num_packages, sizeof(struct pkg_data)); 5632 if (*p == NULL) 5633 goto error; 5634 5635 for (i = 0; i < topo.num_packages; i++) 5636 (*p)[i].package_id = i; 5637 5638 return; 5639 error: 5640 err(1, "calloc counters"); 5641 } 5642 /* 5643 * init_counter() 5644 * 5645 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE 5646 */ 5647 void init_counter(struct thread_data *thread_base, struct core_data *core_base, 5648 struct pkg_data *pkg_base, int cpu_id) 5649 { 5650 int pkg_id = cpus[cpu_id].physical_package_id; 5651 int node_id = cpus[cpu_id].logical_node_id; 5652 int core_id = cpus[cpu_id].physical_core_id; 5653 int thread_id = cpus[cpu_id].thread_id; 5654 struct thread_data *t; 5655 struct core_data *c; 5656 struct pkg_data *p; 5657 5658 5659 /* Workaround for systems where physical_node_id==-1 5660 * and logical_node_id==(-1 - topo.num_cpus) 5661 */ 5662 if (node_id < 0) 5663 node_id = 0; 5664 5665 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id); 5666 c = GET_CORE(core_base, core_id, node_id, pkg_id); 5667 p = GET_PKG(pkg_base, pkg_id); 5668 5669 t->cpu_id = cpu_id; 5670 if (thread_id == 0) { 5671 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; 5672 if (cpu_is_first_core_in_package(cpu_id)) 5673 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; 5674 } 5675 5676 c->core_id = core_id; 5677 p->package_id = pkg_id; 5678 } 5679 5680 5681 int initialize_counters(int cpu_id) 5682 { 5683 init_counter(EVEN_COUNTERS, cpu_id); 5684 init_counter(ODD_COUNTERS, cpu_id); 5685 return 0; 5686 } 5687 5688 void allocate_output_buffer() 5689 { 5690 output_buffer = calloc(1, (1 + topo.num_cpus) * 2048); 5691 outp = output_buffer; 5692 if (outp == NULL) 5693 err(-1, "calloc output buffer"); 5694 } 5695 void allocate_fd_percpu(void) 5696 { 5697 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 5698 if (fd_percpu == NULL) 5699 err(-1, "calloc fd_percpu"); 5700 } 5701 void allocate_irq_buffers(void) 5702 { 5703 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); 5704 if (irq_column_2_cpu == NULL) 5705 err(-1, "calloc %d", topo.num_cpus); 5706 5707 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 5708 if (irqs_per_cpu == NULL) 5709 err(-1, "calloc %d", topo.max_cpu_num + 1); 5710 } 5711 void setup_all_buffers(void) 5712 { 5713 topology_probe(); 5714 allocate_irq_buffers(); 5715 allocate_fd_percpu(); 5716 allocate_counters(&thread_even, &core_even, &package_even); 5717 allocate_counters(&thread_odd, &core_odd, &package_odd); 5718 allocate_output_buffer(); 5719 for_all_proc_cpus(initialize_counters); 5720 } 5721 5722 void set_base_cpu(void) 5723 { 5724 base_cpu = sched_getcpu(); 5725 if (base_cpu < 0) 5726 err(-ENODEV, "No valid cpus found"); 5727 5728 if (debug > 1) 5729 fprintf(outf, "base_cpu = %d\n", base_cpu); 5730 } 5731 5732 void turbostat_init() 5733 { 5734 setup_all_buffers(); 5735 set_base_cpu(); 5736 check_dev_msr(); 5737 check_permissions(); 5738 process_cpuid(); 5739 linux_perf_init(); 5740 5741 5742 if (!quiet) 5743 for_all_cpus(print_hwp, ODD_COUNTERS); 5744 5745 if (!quiet) 5746 for_all_cpus(print_epb, ODD_COUNTERS); 5747 5748 if (!quiet) 5749 for_all_cpus(print_perf_limit, ODD_COUNTERS); 5750 5751 if (!quiet) 5752 for_all_cpus(print_rapl, ODD_COUNTERS); 5753 5754 for_all_cpus(set_temperature_target, ODD_COUNTERS); 5755 5756 if (!quiet) 5757 for_all_cpus(print_thermal, ODD_COUNTERS); 5758 5759 if (!quiet && do_irtl_snb) 5760 print_irtl(); 5761 } 5762 5763 int fork_it(char **argv) 5764 { 5765 pid_t child_pid; 5766 int status; 5767 5768 snapshot_proc_sysfs_files(); 5769 status = for_all_cpus(get_counters, EVEN_COUNTERS); 5770 first_counter_read = 0; 5771 if (status) 5772 exit(status); 5773 /* clear affinity side-effect of get_counters() */ 5774 sched_setaffinity(0, cpu_present_setsize, cpu_present_set); 5775 gettimeofday(&tv_even, (struct timezone *)NULL); 5776 5777 child_pid = fork(); 5778 if (!child_pid) { 5779 /* child */ 5780 execvp(argv[0], argv); 5781 err(errno, "exec %s", argv[0]); 5782 } else { 5783 5784 /* parent */ 5785 if (child_pid == -1) 5786 err(1, "fork"); 5787 5788 signal(SIGINT, SIG_IGN); 5789 signal(SIGQUIT, SIG_IGN); 5790 if (waitpid(child_pid, &status, 0) == -1) 5791 err(status, "waitpid"); 5792 5793 if (WIFEXITED(status)) 5794 status = WEXITSTATUS(status); 5795 } 5796 /* 5797 * n.b. fork_it() does not check for errors from for_all_cpus() 5798 * because re-starting is problematic when forking 5799 */ 5800 snapshot_proc_sysfs_files(); 5801 for_all_cpus(get_counters, ODD_COUNTERS); 5802 gettimeofday(&tv_odd, (struct timezone *)NULL); 5803 timersub(&tv_odd, &tv_even, &tv_delta); 5804 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) 5805 fprintf(outf, "%s: Counter reset detected\n", progname); 5806 else { 5807 compute_average(EVEN_COUNTERS); 5808 format_all_counters(EVEN_COUNTERS); 5809 } 5810 5811 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0); 5812 5813 flush_output_stderr(); 5814 5815 return status; 5816 } 5817 5818 int get_and_dump_counters(void) 5819 { 5820 int status; 5821 5822 snapshot_proc_sysfs_files(); 5823 status = for_all_cpus(get_counters, ODD_COUNTERS); 5824 if (status) 5825 return status; 5826 5827 status = for_all_cpus(dump_counters, ODD_COUNTERS); 5828 if (status) 5829 return status; 5830 5831 flush_output_stdout(); 5832 5833 return status; 5834 } 5835 5836 void print_version() { 5837 fprintf(outf, "turbostat version 20.09.30" 5838 " - Len Brown <lenb@kernel.org>\n"); 5839 } 5840 5841 int add_counter(unsigned int msr_num, char *path, char *name, 5842 unsigned int width, enum counter_scope scope, 5843 enum counter_type type, enum counter_format format, int flags) 5844 { 5845 struct msr_counter *msrp; 5846 5847 msrp = calloc(1, sizeof(struct msr_counter)); 5848 if (msrp == NULL) { 5849 perror("calloc"); 5850 exit(1); 5851 } 5852 5853 msrp->msr_num = msr_num; 5854 strncpy(msrp->name, name, NAME_BYTES - 1); 5855 if (path) 5856 strncpy(msrp->path, path, PATH_BYTES - 1); 5857 msrp->width = width; 5858 msrp->type = type; 5859 msrp->format = format; 5860 msrp->flags = flags; 5861 5862 switch (scope) { 5863 5864 case SCOPE_CPU: 5865 msrp->next = sys.tp; 5866 sys.tp = msrp; 5867 sys.added_thread_counters++; 5868 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) { 5869 fprintf(stderr, "exceeded max %d added thread counters\n", 5870 MAX_ADDED_COUNTERS); 5871 exit(-1); 5872 } 5873 break; 5874 5875 case SCOPE_CORE: 5876 msrp->next = sys.cp; 5877 sys.cp = msrp; 5878 sys.added_core_counters++; 5879 if (sys.added_core_counters > MAX_ADDED_COUNTERS) { 5880 fprintf(stderr, "exceeded max %d added core counters\n", 5881 MAX_ADDED_COUNTERS); 5882 exit(-1); 5883 } 5884 break; 5885 5886 case SCOPE_PACKAGE: 5887 msrp->next = sys.pp; 5888 sys.pp = msrp; 5889 sys.added_package_counters++; 5890 if (sys.added_package_counters > MAX_ADDED_COUNTERS) { 5891 fprintf(stderr, "exceeded max %d added package counters\n", 5892 MAX_ADDED_COUNTERS); 5893 exit(-1); 5894 } 5895 break; 5896 } 5897 5898 return 0; 5899 } 5900 5901 void parse_add_command(char *add_command) 5902 { 5903 int msr_num = 0; 5904 char *path = NULL; 5905 char name_buffer[NAME_BYTES] = ""; 5906 int width = 64; 5907 int fail = 0; 5908 enum counter_scope scope = SCOPE_CPU; 5909 enum counter_type type = COUNTER_CYCLES; 5910 enum counter_format format = FORMAT_DELTA; 5911 5912 while (add_command) { 5913 5914 if (sscanf(add_command, "msr0x%x", &msr_num) == 1) 5915 goto next; 5916 5917 if (sscanf(add_command, "msr%d", &msr_num) == 1) 5918 goto next; 5919 5920 if (*add_command == '/') { 5921 path = add_command; 5922 goto next; 5923 } 5924 5925 if (sscanf(add_command, "u%d", &width) == 1) { 5926 if ((width == 32) || (width == 64)) 5927 goto next; 5928 width = 64; 5929 } 5930 if (!strncmp(add_command, "cpu", strlen("cpu"))) { 5931 scope = SCOPE_CPU; 5932 goto next; 5933 } 5934 if (!strncmp(add_command, "core", strlen("core"))) { 5935 scope = SCOPE_CORE; 5936 goto next; 5937 } 5938 if (!strncmp(add_command, "package", strlen("package"))) { 5939 scope = SCOPE_PACKAGE; 5940 goto next; 5941 } 5942 if (!strncmp(add_command, "cycles", strlen("cycles"))) { 5943 type = COUNTER_CYCLES; 5944 goto next; 5945 } 5946 if (!strncmp(add_command, "seconds", strlen("seconds"))) { 5947 type = COUNTER_SECONDS; 5948 goto next; 5949 } 5950 if (!strncmp(add_command, "usec", strlen("usec"))) { 5951 type = COUNTER_USEC; 5952 goto next; 5953 } 5954 if (!strncmp(add_command, "raw", strlen("raw"))) { 5955 format = FORMAT_RAW; 5956 goto next; 5957 } 5958 if (!strncmp(add_command, "delta", strlen("delta"))) { 5959 format = FORMAT_DELTA; 5960 goto next; 5961 } 5962 if (!strncmp(add_command, "percent", strlen("percent"))) { 5963 format = FORMAT_PERCENT; 5964 goto next; 5965 } 5966 5967 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */ 5968 char *eos; 5969 5970 eos = strchr(name_buffer, ','); 5971 if (eos) 5972 *eos = '\0'; 5973 goto next; 5974 } 5975 5976 next: 5977 add_command = strchr(add_command, ','); 5978 if (add_command) { 5979 *add_command = '\0'; 5980 add_command++; 5981 } 5982 5983 } 5984 if ((msr_num == 0) && (path == NULL)) { 5985 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n"); 5986 fail++; 5987 } 5988 5989 /* generate default column header */ 5990 if (*name_buffer == '\0') { 5991 if (width == 32) 5992 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 5993 else 5994 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 5995 } 5996 5997 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0)) 5998 fail++; 5999 6000 if (fail) { 6001 help(); 6002 exit(1); 6003 } 6004 } 6005 6006 int is_deferred_skip(char *name) 6007 { 6008 int i; 6009 6010 for (i = 0; i < deferred_skip_index; ++i) 6011 if (!strcmp(name, deferred_skip_names[i])) 6012 return 1; 6013 return 0; 6014 } 6015 6016 void probe_sysfs(void) 6017 { 6018 char path[64]; 6019 char name_buf[16]; 6020 FILE *input; 6021 int state; 6022 char *sp; 6023 6024 if (!DO_BIC(BIC_sysfs)) 6025 return; 6026 6027 for (state = 10; state >= 0; --state) { 6028 6029 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 6030 base_cpu, state); 6031 input = fopen(path, "r"); 6032 if (input == NULL) 6033 continue; 6034 if (!fgets(name_buf, sizeof(name_buf), input)) 6035 err(1, "%s: failed to read file", path); 6036 6037 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 6038 sp = strchr(name_buf, '-'); 6039 if (!sp) 6040 sp = strchrnul(name_buf, '\n'); 6041 *sp = '%'; 6042 *(sp + 1) = '\0'; 6043 6044 remove_underbar(name_buf); 6045 6046 fclose(input); 6047 6048 sprintf(path, "cpuidle/state%d/time", state); 6049 6050 if (is_deferred_skip(name_buf)) 6051 continue; 6052 6053 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC, 6054 FORMAT_PERCENT, SYSFS_PERCPU); 6055 } 6056 6057 for (state = 10; state >= 0; --state) { 6058 6059 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 6060 base_cpu, state); 6061 input = fopen(path, "r"); 6062 if (input == NULL) 6063 continue; 6064 if (!fgets(name_buf, sizeof(name_buf), input)) 6065 err(1, "%s: failed to read file", path); 6066 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 6067 sp = strchr(name_buf, '-'); 6068 if (!sp) 6069 sp = strchrnul(name_buf, '\n'); 6070 *sp = '\0'; 6071 fclose(input); 6072 6073 remove_underbar(name_buf); 6074 6075 sprintf(path, "cpuidle/state%d/usage", state); 6076 6077 if (is_deferred_skip(name_buf)) 6078 continue; 6079 6080 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS, 6081 FORMAT_DELTA, SYSFS_PERCPU); 6082 } 6083 6084 } 6085 6086 6087 /* 6088 * parse cpuset with following syntax 6089 * 1,2,4..6,8-10 and set bits in cpu_subset 6090 */ 6091 void parse_cpu_command(char *optarg) 6092 { 6093 unsigned int start, end; 6094 char *next; 6095 6096 if (!strcmp(optarg, "core")) { 6097 if (cpu_subset) 6098 goto error; 6099 show_core_only++; 6100 return; 6101 } 6102 if (!strcmp(optarg, "package")) { 6103 if (cpu_subset) 6104 goto error; 6105 show_pkg_only++; 6106 return; 6107 } 6108 if (show_core_only || show_pkg_only) 6109 goto error; 6110 6111 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS); 6112 if (cpu_subset == NULL) 6113 err(3, "CPU_ALLOC"); 6114 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS); 6115 6116 CPU_ZERO_S(cpu_subset_size, cpu_subset); 6117 6118 next = optarg; 6119 6120 while (next && *next) { 6121 6122 if (*next == '-') /* no negative cpu numbers */ 6123 goto error; 6124 6125 start = strtoul(next, &next, 10); 6126 6127 if (start >= CPU_SUBSET_MAXCPUS) 6128 goto error; 6129 CPU_SET_S(start, cpu_subset_size, cpu_subset); 6130 6131 if (*next == '\0') 6132 break; 6133 6134 if (*next == ',') { 6135 next += 1; 6136 continue; 6137 } 6138 6139 if (*next == '-') { 6140 next += 1; /* start range */ 6141 } else if (*next == '.') { 6142 next += 1; 6143 if (*next == '.') 6144 next += 1; /* start range */ 6145 else 6146 goto error; 6147 } 6148 6149 end = strtoul(next, &next, 10); 6150 if (end <= start) 6151 goto error; 6152 6153 while (++start <= end) { 6154 if (start >= CPU_SUBSET_MAXCPUS) 6155 goto error; 6156 CPU_SET_S(start, cpu_subset_size, cpu_subset); 6157 } 6158 6159 if (*next == ',') 6160 next += 1; 6161 else if (*next != '\0') 6162 goto error; 6163 } 6164 6165 return; 6166 6167 error: 6168 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg); 6169 help(); 6170 exit(-1); 6171 } 6172 6173 6174 void cmdline(int argc, char **argv) 6175 { 6176 int opt; 6177 int option_index = 0; 6178 static struct option long_options[] = { 6179 {"add", required_argument, 0, 'a'}, 6180 {"cpu", required_argument, 0, 'c'}, 6181 {"Dump", no_argument, 0, 'D'}, 6182 {"debug", no_argument, 0, 'd'}, /* internal, not documented */ 6183 {"enable", required_argument, 0, 'e'}, 6184 {"interval", required_argument, 0, 'i'}, 6185 {"IPC", no_argument, 0, 'I'}, 6186 {"num_iterations", required_argument, 0, 'n'}, 6187 {"help", no_argument, 0, 'h'}, 6188 {"hide", required_argument, 0, 'H'}, // meh, -h taken by --help 6189 {"Joules", no_argument, 0, 'J'}, 6190 {"list", no_argument, 0, 'l'}, 6191 {"out", required_argument, 0, 'o'}, 6192 {"quiet", no_argument, 0, 'q'}, 6193 {"show", required_argument, 0, 's'}, 6194 {"Summary", no_argument, 0, 'S'}, 6195 {"TCC", required_argument, 0, 'T'}, 6196 {"version", no_argument, 0, 'v' }, 6197 {0, 0, 0, 0 } 6198 }; 6199 6200 progname = argv[0]; 6201 6202 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v", 6203 long_options, &option_index)) != -1) { 6204 switch (opt) { 6205 case 'a': 6206 parse_add_command(optarg); 6207 break; 6208 case 'c': 6209 parse_cpu_command(optarg); 6210 break; 6211 case 'D': 6212 dump_only++; 6213 break; 6214 case 'e': 6215 /* --enable specified counter */ 6216 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST); 6217 break; 6218 case 'd': 6219 debug++; 6220 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 6221 break; 6222 case 'H': 6223 /* 6224 * --hide: do not show those specified 6225 * multiple invocations simply clear more bits in enabled mask 6226 */ 6227 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST); 6228 break; 6229 case 'h': 6230 default: 6231 help(); 6232 exit(1); 6233 case 'i': 6234 { 6235 double interval = strtod(optarg, NULL); 6236 6237 if (interval < 0.001) { 6238 fprintf(outf, "interval %f seconds is too small\n", 6239 interval); 6240 exit(2); 6241 } 6242 6243 interval_tv.tv_sec = interval_ts.tv_sec = interval; 6244 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000; 6245 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; 6246 } 6247 break; 6248 case 'J': 6249 rapl_joules++; 6250 break; 6251 case 'l': 6252 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 6253 list_header_only++; 6254 quiet++; 6255 break; 6256 case 'o': 6257 outf = fopen_or_die(optarg, "w"); 6258 break; 6259 case 'q': 6260 quiet = 1; 6261 break; 6262 case 'n': 6263 num_iterations = strtod(optarg, NULL); 6264 6265 if (num_iterations <= 0) { 6266 fprintf(outf, "iterations %d should be positive number\n", 6267 num_iterations); 6268 exit(2); 6269 } 6270 break; 6271 case 's': 6272 /* 6273 * --show: show only those specified 6274 * The 1st invocation will clear and replace the enabled mask 6275 * subsequent invocations can add to it. 6276 */ 6277 if (shown == 0) 6278 bic_enabled = bic_lookup(optarg, SHOW_LIST); 6279 else 6280 bic_enabled |= bic_lookup(optarg, SHOW_LIST); 6281 shown = 1; 6282 break; 6283 case 'S': 6284 summary_only++; 6285 break; 6286 case 'T': 6287 tcc_activation_temp_override = atoi(optarg); 6288 break; 6289 case 'v': 6290 print_version(); 6291 exit(0); 6292 break; 6293 } 6294 } 6295 } 6296 6297 int main(int argc, char **argv) 6298 { 6299 outf = stderr; 6300 cmdline(argc, argv); 6301 6302 if (!quiet) 6303 print_version(); 6304 6305 probe_sysfs(); 6306 6307 turbostat_init(); 6308 6309 /* dump counters and exit */ 6310 if (dump_only) 6311 return get_and_dump_counters(); 6312 6313 /* list header and exit */ 6314 if (list_header_only) { 6315 print_header(","); 6316 flush_output_stdout(); 6317 return 0; 6318 } 6319 6320 msr_sum_record(); 6321 /* 6322 * if any params left, it must be a command to fork 6323 */ 6324 if (argc - optind) 6325 return fork_it(argv + optind); 6326 else 6327 turbostat_loop(); 6328 6329 return 0; 6330 } 6331