1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * turbostat -- show CPU frequency and C-state residency 4 * on modern Intel and AMD processors. 5 * 6 * Copyright (c) 2013 Intel Corporation. 7 * Len Brown <len.brown@intel.com> 8 */ 9 10 #define _GNU_SOURCE 11 #include MSRHEADER 12 #include INTEL_FAMILY_HEADER 13 #include <stdarg.h> 14 #include <stdio.h> 15 #include <err.h> 16 #include <unistd.h> 17 #include <sys/types.h> 18 #include <sys/wait.h> 19 #include <sys/stat.h> 20 #include <sys/select.h> 21 #include <sys/resource.h> 22 #include <fcntl.h> 23 #include <signal.h> 24 #include <sys/time.h> 25 #include <stdlib.h> 26 #include <getopt.h> 27 #include <dirent.h> 28 #include <string.h> 29 #include <ctype.h> 30 #include <sched.h> 31 #include <time.h> 32 #include <cpuid.h> 33 #include <linux/capability.h> 34 #include <errno.h> 35 #include <math.h> 36 37 char *proc_stat = "/proc/stat"; 38 FILE *outf; 39 int *fd_percpu; 40 struct timeval interval_tv = {5, 0}; 41 struct timespec interval_ts = {5, 0}; 42 unsigned int num_iterations; 43 unsigned int debug; 44 unsigned int quiet; 45 unsigned int shown; 46 unsigned int sums_need_wide_columns; 47 unsigned int rapl_joules; 48 unsigned int summary_only; 49 unsigned int list_header_only; 50 unsigned int dump_only; 51 unsigned int do_snb_cstates; 52 unsigned int do_knl_cstates; 53 unsigned int do_slm_cstates; 54 unsigned int use_c1_residency_msr; 55 unsigned int has_aperf; 56 unsigned int has_epb; 57 unsigned int do_irtl_snb; 58 unsigned int do_irtl_hsw; 59 unsigned int units = 1000000; /* MHz etc */ 60 unsigned int genuine_intel; 61 unsigned int authentic_amd; 62 unsigned int max_level, max_extended_level; 63 unsigned int has_invariant_tsc; 64 unsigned int do_nhm_platform_info; 65 unsigned int no_MSR_MISC_PWR_MGMT; 66 unsigned int aperf_mperf_multiplier = 1; 67 double bclk; 68 double base_hz; 69 unsigned int has_base_hz; 70 double tsc_tweak = 1.0; 71 unsigned int show_pkg_only; 72 unsigned int show_core_only; 73 char *output_buffer, *outp; 74 unsigned int do_rapl; 75 unsigned int do_dts; 76 unsigned int do_ptm; 77 unsigned long long gfx_cur_rc6_ms; 78 unsigned long long cpuidle_cur_cpu_lpi_us; 79 unsigned long long cpuidle_cur_sys_lpi_us; 80 unsigned int gfx_cur_mhz; 81 unsigned int tcc_activation_temp; 82 unsigned int tcc_activation_temp_override; 83 double rapl_power_units, rapl_time_units; 84 double rapl_dram_energy_units, rapl_energy_units; 85 double rapl_joule_counter_range; 86 unsigned int do_core_perf_limit_reasons; 87 unsigned int has_automatic_cstate_conversion; 88 unsigned int do_gfx_perf_limit_reasons; 89 unsigned int do_ring_perf_limit_reasons; 90 unsigned int crystal_hz; 91 unsigned long long tsc_hz; 92 int base_cpu; 93 double discover_bclk(unsigned int family, unsigned int model); 94 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ 95 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ 96 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ 97 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ 98 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ 99 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ 100 unsigned int has_misc_feature_control; 101 unsigned int first_counter_read = 1; 102 int ignore_stdin; 103 104 #define RAPL_PKG (1 << 0) 105 /* 0x610 MSR_PKG_POWER_LIMIT */ 106 /* 0x611 MSR_PKG_ENERGY_STATUS */ 107 #define RAPL_PKG_PERF_STATUS (1 << 1) 108 /* 0x613 MSR_PKG_PERF_STATUS */ 109 #define RAPL_PKG_POWER_INFO (1 << 2) 110 /* 0x614 MSR_PKG_POWER_INFO */ 111 112 #define RAPL_DRAM (1 << 3) 113 /* 0x618 MSR_DRAM_POWER_LIMIT */ 114 /* 0x619 MSR_DRAM_ENERGY_STATUS */ 115 #define RAPL_DRAM_PERF_STATUS (1 << 4) 116 /* 0x61b MSR_DRAM_PERF_STATUS */ 117 #define RAPL_DRAM_POWER_INFO (1 << 5) 118 /* 0x61c MSR_DRAM_POWER_INFO */ 119 120 #define RAPL_CORES_POWER_LIMIT (1 << 6) 121 /* 0x638 MSR_PP0_POWER_LIMIT */ 122 #define RAPL_CORE_POLICY (1 << 7) 123 /* 0x63a MSR_PP0_POLICY */ 124 125 #define RAPL_GFX (1 << 8) 126 /* 0x640 MSR_PP1_POWER_LIMIT */ 127 /* 0x641 MSR_PP1_ENERGY_STATUS */ 128 /* 0x642 MSR_PP1_POLICY */ 129 130 #define RAPL_CORES_ENERGY_STATUS (1 << 9) 131 /* 0x639 MSR_PP0_ENERGY_STATUS */ 132 #define RAPL_PER_CORE_ENERGY (1 << 10) 133 /* Indicates cores energy collection is per-core, 134 * not per-package. */ 135 #define RAPL_AMD_F17H (1 << 11) 136 /* 0xc0010299 MSR_RAPL_PWR_UNIT */ 137 /* 0xc001029a MSR_CORE_ENERGY_STAT */ 138 /* 0xc001029b MSR_PKG_ENERGY_STAT */ 139 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT) 140 #define TJMAX_DEFAULT 100 141 142 /* MSRs that are not yet in the kernel-provided header. */ 143 #define MSR_RAPL_PWR_UNIT 0xc0010299 144 #define MSR_CORE_ENERGY_STAT 0xc001029a 145 #define MSR_PKG_ENERGY_STAT 0xc001029b 146 147 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 148 149 /* 150 * buffer size used by sscanf() for added column names 151 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters 152 */ 153 #define NAME_BYTES 20 154 #define PATH_BYTES 128 155 156 int backwards_count; 157 char *progname; 158 159 #define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */ 160 cpu_set_t *cpu_present_set, *cpu_affinity_set, *cpu_subset; 161 size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size; 162 #define MAX_ADDED_COUNTERS 8 163 #define MAX_ADDED_THREAD_COUNTERS 24 164 #define BITMASK_SIZE 32 165 166 struct thread_data { 167 struct timeval tv_begin; 168 struct timeval tv_end; 169 struct timeval tv_delta; 170 unsigned long long tsc; 171 unsigned long long aperf; 172 unsigned long long mperf; 173 unsigned long long c1; 174 unsigned long long irq_count; 175 unsigned int smi_count; 176 unsigned int cpu_id; 177 unsigned int apic_id; 178 unsigned int x2apic_id; 179 unsigned int flags; 180 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2 181 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 182 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS]; 183 } *thread_even, *thread_odd; 184 185 struct core_data { 186 unsigned long long c3; 187 unsigned long long c6; 188 unsigned long long c7; 189 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */ 190 unsigned int core_temp_c; 191 unsigned int core_energy; /* MSR_CORE_ENERGY_STAT */ 192 unsigned int core_id; 193 unsigned long long counter[MAX_ADDED_COUNTERS]; 194 } *core_even, *core_odd; 195 196 struct pkg_data { 197 unsigned long long pc2; 198 unsigned long long pc3; 199 unsigned long long pc6; 200 unsigned long long pc7; 201 unsigned long long pc8; 202 unsigned long long pc9; 203 unsigned long long pc10; 204 unsigned long long cpu_lpi; 205 unsigned long long sys_lpi; 206 unsigned long long pkg_wtd_core_c0; 207 unsigned long long pkg_any_core_c0; 208 unsigned long long pkg_any_gfxe_c0; 209 unsigned long long pkg_both_core_gfxe_c0; 210 long long gfx_rc6_ms; 211 unsigned int gfx_mhz; 212 unsigned int package_id; 213 unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */ 214 unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */ 215 unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */ 216 unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */ 217 unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ 218 unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ 219 unsigned int pkg_temp_c; 220 unsigned long long counter[MAX_ADDED_COUNTERS]; 221 } *package_even, *package_odd; 222 223 #define ODD_COUNTERS thread_odd, core_odd, package_odd 224 #define EVEN_COUNTERS thread_even, core_even, package_even 225 226 #define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \ 227 ((thread_base) + \ 228 ((pkg_no) * \ 229 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \ 230 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \ 231 ((core_no) * topo.threads_per_core) + \ 232 (thread_no)) 233 234 #define GET_CORE(core_base, core_no, node_no, pkg_no) \ 235 ((core_base) + \ 236 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \ 237 ((node_no) * topo.cores_per_node) + \ 238 (core_no)) 239 240 241 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) 242 243 enum counter_scope {SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE}; 244 enum counter_type {COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC}; 245 enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT}; 246 247 struct msr_counter { 248 unsigned int msr_num; 249 char name[NAME_BYTES]; 250 char path[PATH_BYTES]; 251 unsigned int width; 252 enum counter_type type; 253 enum counter_format format; 254 struct msr_counter *next; 255 unsigned int flags; 256 #define FLAGS_HIDE (1 << 0) 257 #define FLAGS_SHOW (1 << 1) 258 #define SYSFS_PERCPU (1 << 1) 259 }; 260 261 struct sys_counters { 262 unsigned int added_thread_counters; 263 unsigned int added_core_counters; 264 unsigned int added_package_counters; 265 struct msr_counter *tp; 266 struct msr_counter *cp; 267 struct msr_counter *pp; 268 } sys; 269 270 struct system_summary { 271 struct thread_data threads; 272 struct core_data cores; 273 struct pkg_data packages; 274 } average; 275 276 struct cpu_topology { 277 int physical_package_id; 278 int die_id; 279 int logical_cpu_id; 280 int physical_node_id; 281 int logical_node_id; /* 0-based count within the package */ 282 int physical_core_id; 283 int thread_id; 284 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */ 285 } *cpus; 286 287 struct topo_params { 288 int num_packages; 289 int num_die; 290 int num_cpus; 291 int num_cores; 292 int max_cpu_num; 293 int max_node_num; 294 int nodes_per_pkg; 295 int cores_per_node; 296 int threads_per_core; 297 } topo; 298 299 struct timeval tv_even, tv_odd, tv_delta; 300 301 int *irq_column_2_cpu; /* /proc/interrupts column numbers */ 302 int *irqs_per_cpu; /* indexed by cpu_num */ 303 304 void setup_all_buffers(void); 305 306 int cpu_is_not_present(int cpu) 307 { 308 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); 309 } 310 /* 311 * run func(thread, core, package) in topology order 312 * skip non-present cpus 313 */ 314 315 int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *), 316 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) 317 { 318 int retval, pkg_no, core_no, thread_no, node_no; 319 320 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 321 for (node_no = 0; node_no < topo.nodes_per_pkg; node_no++) { 322 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) { 323 for (thread_no = 0; thread_no < 324 topo.threads_per_core; ++thread_no) { 325 struct thread_data *t; 326 struct core_data *c; 327 struct pkg_data *p; 328 329 t = GET_THREAD(thread_base, thread_no, 330 core_no, node_no, 331 pkg_no); 332 333 if (cpu_is_not_present(t->cpu_id)) 334 continue; 335 336 c = GET_CORE(core_base, core_no, 337 node_no, pkg_no); 338 p = GET_PKG(pkg_base, pkg_no); 339 340 retval = func(t, c, p); 341 if (retval) 342 return retval; 343 } 344 } 345 } 346 } 347 return 0; 348 } 349 350 int cpu_migrate(int cpu) 351 { 352 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 353 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); 354 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) 355 return -1; 356 else 357 return 0; 358 } 359 int get_msr_fd(int cpu) 360 { 361 char pathname[32]; 362 int fd; 363 364 fd = fd_percpu[cpu]; 365 366 if (fd) 367 return fd; 368 369 sprintf(pathname, "/dev/cpu/%d/msr", cpu); 370 fd = open(pathname, O_RDONLY); 371 if (fd < 0) 372 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); 373 374 fd_percpu[cpu] = fd; 375 376 return fd; 377 } 378 379 int get_msr(int cpu, off_t offset, unsigned long long *msr) 380 { 381 ssize_t retval; 382 383 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); 384 385 if (retval != sizeof *msr) 386 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset); 387 388 return 0; 389 } 390 391 /* 392 * This list matches the column headers, except 393 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time 394 * 2. Core and CPU are moved to the end, we can't have strings that contain them 395 * matching on them for --show and --hide. 396 */ 397 struct msr_counter bic[] = { 398 { 0x0, "usec" }, 399 { 0x0, "Time_Of_Day_Seconds" }, 400 { 0x0, "Package" }, 401 { 0x0, "Node" }, 402 { 0x0, "Avg_MHz" }, 403 { 0x0, "Busy%" }, 404 { 0x0, "Bzy_MHz" }, 405 { 0x0, "TSC_MHz" }, 406 { 0x0, "IRQ" }, 407 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL}, 408 { 0x0, "sysfs" }, 409 { 0x0, "CPU%c1" }, 410 { 0x0, "CPU%c3" }, 411 { 0x0, "CPU%c6" }, 412 { 0x0, "CPU%c7" }, 413 { 0x0, "ThreadC" }, 414 { 0x0, "CoreTmp" }, 415 { 0x0, "CoreCnt" }, 416 { 0x0, "PkgTmp" }, 417 { 0x0, "GFX%rc6" }, 418 { 0x0, "GFXMHz" }, 419 { 0x0, "Pkg%pc2" }, 420 { 0x0, "Pkg%pc3" }, 421 { 0x0, "Pkg%pc6" }, 422 { 0x0, "Pkg%pc7" }, 423 { 0x0, "Pkg%pc8" }, 424 { 0x0, "Pkg%pc9" }, 425 { 0x0, "Pk%pc10" }, 426 { 0x0, "CPU%LPI" }, 427 { 0x0, "SYS%LPI" }, 428 { 0x0, "PkgWatt" }, 429 { 0x0, "CorWatt" }, 430 { 0x0, "GFXWatt" }, 431 { 0x0, "PkgCnt" }, 432 { 0x0, "RAMWatt" }, 433 { 0x0, "PKG_%" }, 434 { 0x0, "RAM_%" }, 435 { 0x0, "Pkg_J" }, 436 { 0x0, "Cor_J" }, 437 { 0x0, "GFX_J" }, 438 { 0x0, "RAM_J" }, 439 { 0x0, "Mod%c6" }, 440 { 0x0, "Totl%C0" }, 441 { 0x0, "Any%C0" }, 442 { 0x0, "GFX%C0" }, 443 { 0x0, "CPUGFX%" }, 444 { 0x0, "Core" }, 445 { 0x0, "CPU" }, 446 { 0x0, "APIC" }, 447 { 0x0, "X2APIC" }, 448 { 0x0, "Die" }, 449 }; 450 451 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter)) 452 #define BIC_USEC (1ULL << 0) 453 #define BIC_TOD (1ULL << 1) 454 #define BIC_Package (1ULL << 2) 455 #define BIC_Node (1ULL << 3) 456 #define BIC_Avg_MHz (1ULL << 4) 457 #define BIC_Busy (1ULL << 5) 458 #define BIC_Bzy_MHz (1ULL << 6) 459 #define BIC_TSC_MHz (1ULL << 7) 460 #define BIC_IRQ (1ULL << 8) 461 #define BIC_SMI (1ULL << 9) 462 #define BIC_sysfs (1ULL << 10) 463 #define BIC_CPU_c1 (1ULL << 11) 464 #define BIC_CPU_c3 (1ULL << 12) 465 #define BIC_CPU_c6 (1ULL << 13) 466 #define BIC_CPU_c7 (1ULL << 14) 467 #define BIC_ThreadC (1ULL << 15) 468 #define BIC_CoreTmp (1ULL << 16) 469 #define BIC_CoreCnt (1ULL << 17) 470 #define BIC_PkgTmp (1ULL << 18) 471 #define BIC_GFX_rc6 (1ULL << 19) 472 #define BIC_GFXMHz (1ULL << 20) 473 #define BIC_Pkgpc2 (1ULL << 21) 474 #define BIC_Pkgpc3 (1ULL << 22) 475 #define BIC_Pkgpc6 (1ULL << 23) 476 #define BIC_Pkgpc7 (1ULL << 24) 477 #define BIC_Pkgpc8 (1ULL << 25) 478 #define BIC_Pkgpc9 (1ULL << 26) 479 #define BIC_Pkgpc10 (1ULL << 27) 480 #define BIC_CPU_LPI (1ULL << 28) 481 #define BIC_SYS_LPI (1ULL << 29) 482 #define BIC_PkgWatt (1ULL << 30) 483 #define BIC_CorWatt (1ULL << 31) 484 #define BIC_GFXWatt (1ULL << 32) 485 #define BIC_PkgCnt (1ULL << 33) 486 #define BIC_RAMWatt (1ULL << 34) 487 #define BIC_PKG__ (1ULL << 35) 488 #define BIC_RAM__ (1ULL << 36) 489 #define BIC_Pkg_J (1ULL << 37) 490 #define BIC_Cor_J (1ULL << 38) 491 #define BIC_GFX_J (1ULL << 39) 492 #define BIC_RAM_J (1ULL << 40) 493 #define BIC_Mod_c6 (1ULL << 41) 494 #define BIC_Totl_c0 (1ULL << 42) 495 #define BIC_Any_c0 (1ULL << 43) 496 #define BIC_GFX_c0 (1ULL << 44) 497 #define BIC_CPUGFX (1ULL << 45) 498 #define BIC_Core (1ULL << 46) 499 #define BIC_CPU (1ULL << 47) 500 #define BIC_APIC (1ULL << 48) 501 #define BIC_X2APIC (1ULL << 49) 502 #define BIC_Die (1ULL << 50) 503 504 #define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC) 505 506 unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT); 507 unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC; 508 509 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME) 510 #define DO_BIC_READ(COUNTER_NAME) (bic_present & COUNTER_NAME) 511 #define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME) 512 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT) 513 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT) 514 515 516 #define MAX_DEFERRED 16 517 char *deferred_skip_names[MAX_DEFERRED]; 518 int deferred_skip_index; 519 520 /* 521 * HIDE_LIST - hide this list of counters, show the rest [default] 522 * SHOW_LIST - show this list of counters, hide the rest 523 */ 524 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST; 525 526 void help(void) 527 { 528 fprintf(outf, 529 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" 530 "\n" 531 "Turbostat forks the specified COMMAND and prints statistics\n" 532 "when COMMAND completes.\n" 533 "If no COMMAND is specified, turbostat wakes every 5-seconds\n" 534 "to print statistics, until interrupted.\n" 535 " -a, --add add a counter\n" 536 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n" 537 " -c, --cpu cpu-set limit output to summary plus cpu-set:\n" 538 " {core | package | j,k,l..m,n-p }\n" 539 " -d, --debug displays usec, Time_Of_Day_Seconds and more debugging\n" 540 " -D, --Dump displays the raw counter values\n" 541 " -e, --enable [all | column]\n" 542 " shows all or the specified disabled column\n" 543 " -H, --hide [column|column,column,...]\n" 544 " hide the specified column(s)\n" 545 " -i, --interval sec.subsec\n" 546 " Override default 5-second measurement interval\n" 547 " -J, --Joules displays energy in Joules instead of Watts\n" 548 " -l, --list list column headers only\n" 549 " -n, --num_iterations num\n" 550 " number of the measurement iterations\n" 551 " -o, --out file\n" 552 " create or truncate \"file\" for all output\n" 553 " -q, --quiet skip decoding system configuration header\n" 554 " -s, --show [column|column,column,...]\n" 555 " show only the specified column(s)\n" 556 " -S, --Summary\n" 557 " limits output to 1-line system summary per interval\n" 558 " -T, --TCC temperature\n" 559 " sets the Thermal Control Circuit temperature in\n" 560 " degrees Celsius\n" 561 " -h, --help print this help message\n" 562 " -v, --version print version information\n" 563 "\n" 564 "For more help, run \"man turbostat\"\n"); 565 } 566 567 /* 568 * bic_lookup 569 * for all the strings in comma separate name_list, 570 * set the approprate bit in return value. 571 */ 572 unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode) 573 { 574 int i; 575 unsigned long long retval = 0; 576 577 while (name_list) { 578 char *comma; 579 580 comma = strchr(name_list, ','); 581 582 if (comma) 583 *comma = '\0'; 584 585 if (!strcmp(name_list, "all")) 586 return ~0; 587 588 for (i = 0; i < MAX_BIC; ++i) { 589 if (!strcmp(name_list, bic[i].name)) { 590 retval |= (1ULL << i); 591 break; 592 } 593 } 594 if (i == MAX_BIC) { 595 if (mode == SHOW_LIST) { 596 fprintf(stderr, "Invalid counter name: %s\n", name_list); 597 exit(-1); 598 } 599 deferred_skip_names[deferred_skip_index++] = name_list; 600 if (debug) 601 fprintf(stderr, "deferred \"%s\"\n", name_list); 602 if (deferred_skip_index >= MAX_DEFERRED) { 603 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n", 604 MAX_DEFERRED, name_list); 605 help(); 606 exit(1); 607 } 608 } 609 610 name_list = comma; 611 if (name_list) 612 name_list++; 613 614 } 615 return retval; 616 } 617 618 619 void print_header(char *delim) 620 { 621 struct msr_counter *mp; 622 int printed = 0; 623 624 if (DO_BIC(BIC_USEC)) 625 outp += sprintf(outp, "%susec", (printed++ ? delim : "")); 626 if (DO_BIC(BIC_TOD)) 627 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : "")); 628 if (DO_BIC(BIC_Package)) 629 outp += sprintf(outp, "%sPackage", (printed++ ? delim : "")); 630 if (DO_BIC(BIC_Die)) 631 outp += sprintf(outp, "%sDie", (printed++ ? delim : "")); 632 if (DO_BIC(BIC_Node)) 633 outp += sprintf(outp, "%sNode", (printed++ ? delim : "")); 634 if (DO_BIC(BIC_Core)) 635 outp += sprintf(outp, "%sCore", (printed++ ? delim : "")); 636 if (DO_BIC(BIC_CPU)) 637 outp += sprintf(outp, "%sCPU", (printed++ ? delim : "")); 638 if (DO_BIC(BIC_APIC)) 639 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : "")); 640 if (DO_BIC(BIC_X2APIC)) 641 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : "")); 642 if (DO_BIC(BIC_Avg_MHz)) 643 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : "")); 644 if (DO_BIC(BIC_Busy)) 645 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : "")); 646 if (DO_BIC(BIC_Bzy_MHz)) 647 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : "")); 648 if (DO_BIC(BIC_TSC_MHz)) 649 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : "")); 650 651 if (DO_BIC(BIC_IRQ)) { 652 if (sums_need_wide_columns) 653 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : "")); 654 else 655 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : "")); 656 } 657 658 if (DO_BIC(BIC_SMI)) 659 outp += sprintf(outp, "%sSMI", (printed++ ? delim : "")); 660 661 for (mp = sys.tp; mp; mp = mp->next) { 662 663 if (mp->format == FORMAT_RAW) { 664 if (mp->width == 64) 665 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name); 666 else 667 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name); 668 } else { 669 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 670 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name); 671 else 672 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name); 673 } 674 } 675 676 if (DO_BIC(BIC_CPU_c1)) 677 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : "")); 678 if (DO_BIC(BIC_CPU_c3)) 679 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : "")); 680 if (DO_BIC(BIC_CPU_c6)) 681 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : "")); 682 if (DO_BIC(BIC_CPU_c7)) 683 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : "")); 684 685 if (DO_BIC(BIC_Mod_c6)) 686 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : "")); 687 688 if (DO_BIC(BIC_CoreTmp)) 689 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : "")); 690 691 if (do_rapl && !rapl_joules) { 692 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY)) 693 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 694 } else if (do_rapl && rapl_joules) { 695 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY)) 696 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 697 } 698 699 for (mp = sys.cp; mp; mp = mp->next) { 700 if (mp->format == FORMAT_RAW) { 701 if (mp->width == 64) 702 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 703 else 704 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 705 } else { 706 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 707 outp += sprintf(outp, "%s%8s", delim, mp->name); 708 else 709 outp += sprintf(outp, "%s%s", delim, mp->name); 710 } 711 } 712 713 if (DO_BIC(BIC_PkgTmp)) 714 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : "")); 715 716 if (DO_BIC(BIC_GFX_rc6)) 717 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : "")); 718 719 if (DO_BIC(BIC_GFXMHz)) 720 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : "")); 721 722 if (DO_BIC(BIC_Totl_c0)) 723 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : "")); 724 if (DO_BIC(BIC_Any_c0)) 725 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : "")); 726 if (DO_BIC(BIC_GFX_c0)) 727 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : "")); 728 if (DO_BIC(BIC_CPUGFX)) 729 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : "")); 730 731 if (DO_BIC(BIC_Pkgpc2)) 732 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : "")); 733 if (DO_BIC(BIC_Pkgpc3)) 734 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : "")); 735 if (DO_BIC(BIC_Pkgpc6)) 736 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : "")); 737 if (DO_BIC(BIC_Pkgpc7)) 738 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : "")); 739 if (DO_BIC(BIC_Pkgpc8)) 740 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : "")); 741 if (DO_BIC(BIC_Pkgpc9)) 742 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : "")); 743 if (DO_BIC(BIC_Pkgpc10)) 744 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : "")); 745 if (DO_BIC(BIC_CPU_LPI)) 746 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : "")); 747 if (DO_BIC(BIC_SYS_LPI)) 748 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : "")); 749 750 if (do_rapl && !rapl_joules) { 751 if (DO_BIC(BIC_PkgWatt)) 752 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : "")); 753 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 754 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 755 if (DO_BIC(BIC_GFXWatt)) 756 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : "")); 757 if (DO_BIC(BIC_RAMWatt)) 758 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : "")); 759 if (DO_BIC(BIC_PKG__)) 760 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 761 if (DO_BIC(BIC_RAM__)) 762 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 763 } else if (do_rapl && rapl_joules) { 764 if (DO_BIC(BIC_Pkg_J)) 765 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : "")); 766 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 767 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 768 if (DO_BIC(BIC_GFX_J)) 769 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : "")); 770 if (DO_BIC(BIC_RAM_J)) 771 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : "")); 772 if (DO_BIC(BIC_PKG__)) 773 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 774 if (DO_BIC(BIC_RAM__)) 775 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 776 } 777 for (mp = sys.pp; mp; mp = mp->next) { 778 if (mp->format == FORMAT_RAW) { 779 if (mp->width == 64) 780 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 781 else 782 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 783 } else { 784 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 785 outp += sprintf(outp, "%s%8s", delim, mp->name); 786 else 787 outp += sprintf(outp, "%s%s", delim, mp->name); 788 } 789 } 790 791 outp += sprintf(outp, "\n"); 792 } 793 794 int dump_counters(struct thread_data *t, struct core_data *c, 795 struct pkg_data *p) 796 { 797 int i; 798 struct msr_counter *mp; 799 800 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); 801 802 if (t) { 803 outp += sprintf(outp, "CPU: %d flags 0x%x\n", 804 t->cpu_id, t->flags); 805 outp += sprintf(outp, "TSC: %016llX\n", t->tsc); 806 outp += sprintf(outp, "aperf: %016llX\n", t->aperf); 807 outp += sprintf(outp, "mperf: %016llX\n", t->mperf); 808 outp += sprintf(outp, "c1: %016llX\n", t->c1); 809 810 if (DO_BIC(BIC_IRQ)) 811 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count); 812 if (DO_BIC(BIC_SMI)) 813 outp += sprintf(outp, "SMI: %d\n", t->smi_count); 814 815 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 816 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", 817 i, mp->msr_num, t->counter[i]); 818 } 819 } 820 821 if (c) { 822 outp += sprintf(outp, "core: %d\n", c->core_id); 823 outp += sprintf(outp, "c3: %016llX\n", c->c3); 824 outp += sprintf(outp, "c6: %016llX\n", c->c6); 825 outp += sprintf(outp, "c7: %016llX\n", c->c7); 826 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); 827 outp += sprintf(outp, "Joules: %0X\n", c->core_energy); 828 829 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 830 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", 831 i, mp->msr_num, c->counter[i]); 832 } 833 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us); 834 } 835 836 if (p) { 837 outp += sprintf(outp, "package: %d\n", p->package_id); 838 839 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); 840 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); 841 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); 842 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); 843 844 outp += sprintf(outp, "pc2: %016llX\n", p->pc2); 845 if (DO_BIC(BIC_Pkgpc3)) 846 outp += sprintf(outp, "pc3: %016llX\n", p->pc3); 847 if (DO_BIC(BIC_Pkgpc6)) 848 outp += sprintf(outp, "pc6: %016llX\n", p->pc6); 849 if (DO_BIC(BIC_Pkgpc7)) 850 outp += sprintf(outp, "pc7: %016llX\n", p->pc7); 851 outp += sprintf(outp, "pc8: %016llX\n", p->pc8); 852 outp += sprintf(outp, "pc9: %016llX\n", p->pc9); 853 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 854 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi); 855 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi); 856 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg); 857 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores); 858 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx); 859 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram); 860 outp += sprintf(outp, "Throttle PKG: %0X\n", 861 p->rapl_pkg_perf_status); 862 outp += sprintf(outp, "Throttle RAM: %0X\n", 863 p->rapl_dram_perf_status); 864 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); 865 866 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 867 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", 868 i, mp->msr_num, p->counter[i]); 869 } 870 } 871 872 outp += sprintf(outp, "\n"); 873 874 return 0; 875 } 876 877 /* 878 * column formatting convention & formats 879 */ 880 int format_counters(struct thread_data *t, struct core_data *c, 881 struct pkg_data *p) 882 { 883 double interval_float, tsc; 884 char *fmt8; 885 int i; 886 struct msr_counter *mp; 887 char *delim = "\t"; 888 int printed = 0; 889 890 /* if showing only 1st thread in core and this isn't one, bail out */ 891 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 892 return 0; 893 894 /* if showing only 1st thread in pkg and this isn't one, bail out */ 895 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 896 return 0; 897 898 /*if not summary line and --cpu is used */ 899 if ((t != &average.threads) && 900 (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset))) 901 return 0; 902 903 if (DO_BIC(BIC_USEC)) { 904 /* on each row, print how many usec each timestamp took to gather */ 905 struct timeval tv; 906 907 timersub(&t->tv_end, &t->tv_begin, &tv); 908 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec); 909 } 910 911 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */ 912 if (DO_BIC(BIC_TOD)) 913 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec); 914 915 interval_float = t->tv_delta.tv_sec + t->tv_delta.tv_usec/1000000.0; 916 917 tsc = t->tsc * tsc_tweak; 918 919 /* topo columns, print blanks on 1st (average) line */ 920 if (t == &average.threads) { 921 if (DO_BIC(BIC_Package)) 922 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 923 if (DO_BIC(BIC_Die)) 924 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 925 if (DO_BIC(BIC_Node)) 926 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 927 if (DO_BIC(BIC_Core)) 928 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 929 if (DO_BIC(BIC_CPU)) 930 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 931 if (DO_BIC(BIC_APIC)) 932 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 933 if (DO_BIC(BIC_X2APIC)) 934 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 935 } else { 936 if (DO_BIC(BIC_Package)) { 937 if (p) 938 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id); 939 else 940 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 941 } 942 if (DO_BIC(BIC_Die)) { 943 if (c) 944 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), cpus[t->cpu_id].die_id); 945 else 946 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 947 } 948 if (DO_BIC(BIC_Node)) { 949 if (t) 950 outp += sprintf(outp, "%s%d", 951 (printed++ ? delim : ""), 952 cpus[t->cpu_id].physical_node_id); 953 else 954 outp += sprintf(outp, "%s-", 955 (printed++ ? delim : "")); 956 } 957 if (DO_BIC(BIC_Core)) { 958 if (c) 959 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id); 960 else 961 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 962 } 963 if (DO_BIC(BIC_CPU)) 964 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id); 965 if (DO_BIC(BIC_APIC)) 966 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id); 967 if (DO_BIC(BIC_X2APIC)) 968 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id); 969 } 970 971 if (DO_BIC(BIC_Avg_MHz)) 972 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 973 1.0 / units * t->aperf / interval_float); 974 975 if (DO_BIC(BIC_Busy)) 976 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf/tsc); 977 978 if (DO_BIC(BIC_Bzy_MHz)) { 979 if (has_base_hz) 980 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf); 981 else 982 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 983 tsc / units * t->aperf / t->mperf / interval_float); 984 } 985 986 if (DO_BIC(BIC_TSC_MHz)) 987 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc/units/interval_float); 988 989 /* IRQ */ 990 if (DO_BIC(BIC_IRQ)) { 991 if (sums_need_wide_columns) 992 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count); 993 else 994 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count); 995 } 996 997 /* SMI */ 998 if (DO_BIC(BIC_SMI)) 999 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count); 1000 1001 /* Added counters */ 1002 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1003 if (mp->format == FORMAT_RAW) { 1004 if (mp->width == 32) 1005 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) t->counter[i]); 1006 else 1007 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]); 1008 } else if (mp->format == FORMAT_DELTA) { 1009 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1010 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]); 1011 else 1012 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]); 1013 } else if (mp->format == FORMAT_PERCENT) { 1014 if (mp->type == COUNTER_USEC) 1015 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), t->counter[i]/interval_float/10000); 1016 else 1017 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i]/tsc); 1018 } 1019 } 1020 1021 /* C1 */ 1022 if (DO_BIC(BIC_CPU_c1)) 1023 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1/tsc); 1024 1025 1026 /* print per-core data only for 1st thread in core */ 1027 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1028 goto done; 1029 1030 if (DO_BIC(BIC_CPU_c3)) 1031 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3/tsc); 1032 if (DO_BIC(BIC_CPU_c6)) 1033 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6/tsc); 1034 if (DO_BIC(BIC_CPU_c7)) 1035 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7/tsc); 1036 1037 /* Mod%c6 */ 1038 if (DO_BIC(BIC_Mod_c6)) 1039 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc); 1040 1041 if (DO_BIC(BIC_CoreTmp)) 1042 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c); 1043 1044 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1045 if (mp->format == FORMAT_RAW) { 1046 if (mp->width == 32) 1047 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) c->counter[i]); 1048 else 1049 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]); 1050 } else if (mp->format == FORMAT_DELTA) { 1051 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1052 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]); 1053 else 1054 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]); 1055 } else if (mp->format == FORMAT_PERCENT) { 1056 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i]/tsc); 1057 } 1058 } 1059 1060 /* 1061 * If measurement interval exceeds minimum RAPL Joule Counter range, 1062 * indicate that results are suspect by printing "**" in fraction place. 1063 */ 1064 if (interval_float < rapl_joule_counter_range) 1065 fmt8 = "%s%.2f"; 1066 else 1067 fmt8 = "%6.0f**"; 1068 1069 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY)) 1070 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units / interval_float); 1071 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY)) 1072 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units); 1073 1074 /* print per-package data only for 1st core in package */ 1075 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1076 goto done; 1077 1078 /* PkgTmp */ 1079 if (DO_BIC(BIC_PkgTmp)) 1080 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c); 1081 1082 /* GFXrc6 */ 1083 if (DO_BIC(BIC_GFX_rc6)) { 1084 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */ 1085 outp += sprintf(outp, "%s**.**", (printed++ ? delim : "")); 1086 } else { 1087 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1088 p->gfx_rc6_ms / 10.0 / interval_float); 1089 } 1090 } 1091 1092 /* GFXMHz */ 1093 if (DO_BIC(BIC_GFXMHz)) 1094 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz); 1095 1096 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ 1097 if (DO_BIC(BIC_Totl_c0)) 1098 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0/tsc); 1099 if (DO_BIC(BIC_Any_c0)) 1100 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0/tsc); 1101 if (DO_BIC(BIC_GFX_c0)) 1102 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0/tsc); 1103 if (DO_BIC(BIC_CPUGFX)) 1104 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0/tsc); 1105 1106 if (DO_BIC(BIC_Pkgpc2)) 1107 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2/tsc); 1108 if (DO_BIC(BIC_Pkgpc3)) 1109 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3/tsc); 1110 if (DO_BIC(BIC_Pkgpc6)) 1111 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6/tsc); 1112 if (DO_BIC(BIC_Pkgpc7)) 1113 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7/tsc); 1114 if (DO_BIC(BIC_Pkgpc8)) 1115 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8/tsc); 1116 if (DO_BIC(BIC_Pkgpc9)) 1117 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9/tsc); 1118 if (DO_BIC(BIC_Pkgpc10)) 1119 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10/tsc); 1120 1121 if (DO_BIC(BIC_CPU_LPI)) 1122 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float); 1123 if (DO_BIC(BIC_SYS_LPI)) 1124 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float); 1125 1126 if (DO_BIC(BIC_PkgWatt)) 1127 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float); 1128 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 1129 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float); 1130 if (DO_BIC(BIC_GFXWatt)) 1131 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float); 1132 if (DO_BIC(BIC_RAMWatt)) 1133 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units / interval_float); 1134 if (DO_BIC(BIC_Pkg_J)) 1135 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units); 1136 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 1137 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units); 1138 if (DO_BIC(BIC_GFX_J)) 1139 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units); 1140 if (DO_BIC(BIC_RAM_J)) 1141 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units); 1142 if (DO_BIC(BIC_PKG__)) 1143 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 1144 if (DO_BIC(BIC_RAM__)) 1145 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 1146 1147 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1148 if (mp->format == FORMAT_RAW) { 1149 if (mp->width == 32) 1150 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) p->counter[i]); 1151 else 1152 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]); 1153 } else if (mp->format == FORMAT_DELTA) { 1154 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1155 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]); 1156 else 1157 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]); 1158 } else if (mp->format == FORMAT_PERCENT) { 1159 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i]/tsc); 1160 } 1161 } 1162 1163 done: 1164 if (*(outp - 1) != '\n') 1165 outp += sprintf(outp, "\n"); 1166 1167 return 0; 1168 } 1169 1170 void flush_output_stdout(void) 1171 { 1172 FILE *filep; 1173 1174 if (outf == stderr) 1175 filep = stdout; 1176 else 1177 filep = outf; 1178 1179 fputs(output_buffer, filep); 1180 fflush(filep); 1181 1182 outp = output_buffer; 1183 } 1184 void flush_output_stderr(void) 1185 { 1186 fputs(output_buffer, outf); 1187 fflush(outf); 1188 outp = output_buffer; 1189 } 1190 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1191 { 1192 static int printed; 1193 1194 if (!printed || !summary_only) 1195 print_header("\t"); 1196 1197 format_counters(&average.threads, &average.cores, &average.packages); 1198 1199 printed = 1; 1200 1201 if (summary_only) 1202 return; 1203 1204 for_all_cpus(format_counters, t, c, p); 1205 } 1206 1207 #define DELTA_WRAP32(new, old) \ 1208 if (new > old) { \ 1209 old = new - old; \ 1210 } else { \ 1211 old = 0x100000000 + new - old; \ 1212 } 1213 1214 int 1215 delta_package(struct pkg_data *new, struct pkg_data *old) 1216 { 1217 int i; 1218 struct msr_counter *mp; 1219 1220 1221 if (DO_BIC(BIC_Totl_c0)) 1222 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; 1223 if (DO_BIC(BIC_Any_c0)) 1224 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; 1225 if (DO_BIC(BIC_GFX_c0)) 1226 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; 1227 if (DO_BIC(BIC_CPUGFX)) 1228 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; 1229 1230 old->pc2 = new->pc2 - old->pc2; 1231 if (DO_BIC(BIC_Pkgpc3)) 1232 old->pc3 = new->pc3 - old->pc3; 1233 if (DO_BIC(BIC_Pkgpc6)) 1234 old->pc6 = new->pc6 - old->pc6; 1235 if (DO_BIC(BIC_Pkgpc7)) 1236 old->pc7 = new->pc7 - old->pc7; 1237 old->pc8 = new->pc8 - old->pc8; 1238 old->pc9 = new->pc9 - old->pc9; 1239 old->pc10 = new->pc10 - old->pc10; 1240 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi; 1241 old->sys_lpi = new->sys_lpi - old->sys_lpi; 1242 old->pkg_temp_c = new->pkg_temp_c; 1243 1244 /* flag an error when rc6 counter resets/wraps */ 1245 if (old->gfx_rc6_ms > new->gfx_rc6_ms) 1246 old->gfx_rc6_ms = -1; 1247 else 1248 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; 1249 1250 old->gfx_mhz = new->gfx_mhz; 1251 1252 DELTA_WRAP32(new->energy_pkg, old->energy_pkg); 1253 DELTA_WRAP32(new->energy_cores, old->energy_cores); 1254 DELTA_WRAP32(new->energy_gfx, old->energy_gfx); 1255 DELTA_WRAP32(new->energy_dram, old->energy_dram); 1256 DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status); 1257 DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status); 1258 1259 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1260 if (mp->format == FORMAT_RAW) 1261 old->counter[i] = new->counter[i]; 1262 else 1263 old->counter[i] = new->counter[i] - old->counter[i]; 1264 } 1265 1266 return 0; 1267 } 1268 1269 void 1270 delta_core(struct core_data *new, struct core_data *old) 1271 { 1272 int i; 1273 struct msr_counter *mp; 1274 1275 old->c3 = new->c3 - old->c3; 1276 old->c6 = new->c6 - old->c6; 1277 old->c7 = new->c7 - old->c7; 1278 old->core_temp_c = new->core_temp_c; 1279 old->mc6_us = new->mc6_us - old->mc6_us; 1280 1281 DELTA_WRAP32(new->core_energy, old->core_energy); 1282 1283 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1284 if (mp->format == FORMAT_RAW) 1285 old->counter[i] = new->counter[i]; 1286 else 1287 old->counter[i] = new->counter[i] - old->counter[i]; 1288 } 1289 } 1290 1291 int soft_c1_residency_display(int bic) 1292 { 1293 if (!DO_BIC(BIC_CPU_c1) || use_c1_residency_msr) 1294 return 0; 1295 1296 return DO_BIC_READ(bic); 1297 } 1298 1299 /* 1300 * old = new - old 1301 */ 1302 int 1303 delta_thread(struct thread_data *new, struct thread_data *old, 1304 struct core_data *core_delta) 1305 { 1306 int i; 1307 struct msr_counter *mp; 1308 1309 /* we run cpuid just the 1st time, copy the results */ 1310 if (DO_BIC(BIC_APIC)) 1311 new->apic_id = old->apic_id; 1312 if (DO_BIC(BIC_X2APIC)) 1313 new->x2apic_id = old->x2apic_id; 1314 1315 /* 1316 * the timestamps from start of measurement interval are in "old" 1317 * the timestamp from end of measurement interval are in "new" 1318 * over-write old w/ new so we can print end of interval values 1319 */ 1320 1321 timersub(&new->tv_begin, &old->tv_begin, &old->tv_delta); 1322 old->tv_begin = new->tv_begin; 1323 old->tv_end = new->tv_end; 1324 1325 old->tsc = new->tsc - old->tsc; 1326 1327 /* check for TSC < 1 Mcycles over interval */ 1328 if (old->tsc < (1000 * 1000)) 1329 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" 1330 "You can disable all c-states by booting with \"idle=poll\"\n" 1331 "or just the deep ones with \"processor.max_cstate=1\""); 1332 1333 old->c1 = new->c1 - old->c1; 1334 1335 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || 1336 soft_c1_residency_display(BIC_Avg_MHz)) { 1337 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { 1338 old->aperf = new->aperf - old->aperf; 1339 old->mperf = new->mperf - old->mperf; 1340 } else { 1341 return -1; 1342 } 1343 } 1344 1345 1346 if (use_c1_residency_msr) { 1347 /* 1348 * Some models have a dedicated C1 residency MSR, 1349 * which should be more accurate than the derivation below. 1350 */ 1351 } else { 1352 /* 1353 * As counter collection is not atomic, 1354 * it is possible for mperf's non-halted cycles + idle states 1355 * to exceed TSC's all cycles: show c1 = 0% in that case. 1356 */ 1357 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak)) 1358 old->c1 = 0; 1359 else { 1360 /* normal case, derive c1 */ 1361 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3 1362 - core_delta->c6 - core_delta->c7; 1363 } 1364 } 1365 1366 if (old->mperf == 0) { 1367 if (debug > 1) 1368 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); 1369 old->mperf = 1; /* divide by 0 protection */ 1370 } 1371 1372 if (DO_BIC(BIC_IRQ)) 1373 old->irq_count = new->irq_count - old->irq_count; 1374 1375 if (DO_BIC(BIC_SMI)) 1376 old->smi_count = new->smi_count - old->smi_count; 1377 1378 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1379 if (mp->format == FORMAT_RAW) 1380 old->counter[i] = new->counter[i]; 1381 else 1382 old->counter[i] = new->counter[i] - old->counter[i]; 1383 } 1384 return 0; 1385 } 1386 1387 int delta_cpu(struct thread_data *t, struct core_data *c, 1388 struct pkg_data *p, struct thread_data *t2, 1389 struct core_data *c2, struct pkg_data *p2) 1390 { 1391 int retval = 0; 1392 1393 /* calculate core delta only for 1st thread in core */ 1394 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) 1395 delta_core(c, c2); 1396 1397 /* always calculate thread delta */ 1398 retval = delta_thread(t, t2, c2); /* c2 is core delta */ 1399 if (retval) 1400 return retval; 1401 1402 /* calculate package delta only for 1st core in package */ 1403 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) 1404 retval = delta_package(p, p2); 1405 1406 return retval; 1407 } 1408 1409 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1410 { 1411 int i; 1412 struct msr_counter *mp; 1413 1414 t->tv_begin.tv_sec = 0; 1415 t->tv_begin.tv_usec = 0; 1416 t->tv_end.tv_sec = 0; 1417 t->tv_end.tv_usec = 0; 1418 t->tv_delta.tv_sec = 0; 1419 t->tv_delta.tv_usec = 0; 1420 1421 t->tsc = 0; 1422 t->aperf = 0; 1423 t->mperf = 0; 1424 t->c1 = 0; 1425 1426 t->irq_count = 0; 1427 t->smi_count = 0; 1428 1429 /* tells format_counters to dump all fields from this set */ 1430 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; 1431 1432 c->c3 = 0; 1433 c->c6 = 0; 1434 c->c7 = 0; 1435 c->mc6_us = 0; 1436 c->core_temp_c = 0; 1437 c->core_energy = 0; 1438 1439 p->pkg_wtd_core_c0 = 0; 1440 p->pkg_any_core_c0 = 0; 1441 p->pkg_any_gfxe_c0 = 0; 1442 p->pkg_both_core_gfxe_c0 = 0; 1443 1444 p->pc2 = 0; 1445 if (DO_BIC(BIC_Pkgpc3)) 1446 p->pc3 = 0; 1447 if (DO_BIC(BIC_Pkgpc6)) 1448 p->pc6 = 0; 1449 if (DO_BIC(BIC_Pkgpc7)) 1450 p->pc7 = 0; 1451 p->pc8 = 0; 1452 p->pc9 = 0; 1453 p->pc10 = 0; 1454 p->cpu_lpi = 0; 1455 p->sys_lpi = 0; 1456 1457 p->energy_pkg = 0; 1458 p->energy_dram = 0; 1459 p->energy_cores = 0; 1460 p->energy_gfx = 0; 1461 p->rapl_pkg_perf_status = 0; 1462 p->rapl_dram_perf_status = 0; 1463 p->pkg_temp_c = 0; 1464 1465 p->gfx_rc6_ms = 0; 1466 p->gfx_mhz = 0; 1467 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) 1468 t->counter[i] = 0; 1469 1470 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) 1471 c->counter[i] = 0; 1472 1473 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) 1474 p->counter[i] = 0; 1475 } 1476 int sum_counters(struct thread_data *t, struct core_data *c, 1477 struct pkg_data *p) 1478 { 1479 int i; 1480 struct msr_counter *mp; 1481 1482 /* copy un-changing apic_id's */ 1483 if (DO_BIC(BIC_APIC)) 1484 average.threads.apic_id = t->apic_id; 1485 if (DO_BIC(BIC_X2APIC)) 1486 average.threads.x2apic_id = t->x2apic_id; 1487 1488 /* remember first tv_begin */ 1489 if (average.threads.tv_begin.tv_sec == 0) 1490 average.threads.tv_begin = t->tv_begin; 1491 1492 /* remember last tv_end */ 1493 average.threads.tv_end = t->tv_end; 1494 1495 average.threads.tsc += t->tsc; 1496 average.threads.aperf += t->aperf; 1497 average.threads.mperf += t->mperf; 1498 average.threads.c1 += t->c1; 1499 1500 average.threads.irq_count += t->irq_count; 1501 average.threads.smi_count += t->smi_count; 1502 1503 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1504 if (mp->format == FORMAT_RAW) 1505 continue; 1506 average.threads.counter[i] += t->counter[i]; 1507 } 1508 1509 /* sum per-core values only for 1st thread in core */ 1510 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1511 return 0; 1512 1513 average.cores.c3 += c->c3; 1514 average.cores.c6 += c->c6; 1515 average.cores.c7 += c->c7; 1516 average.cores.mc6_us += c->mc6_us; 1517 1518 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); 1519 1520 average.cores.core_energy += c->core_energy; 1521 1522 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1523 if (mp->format == FORMAT_RAW) 1524 continue; 1525 average.cores.counter[i] += c->counter[i]; 1526 } 1527 1528 /* sum per-pkg values only for 1st core in pkg */ 1529 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1530 return 0; 1531 1532 if (DO_BIC(BIC_Totl_c0)) 1533 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; 1534 if (DO_BIC(BIC_Any_c0)) 1535 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; 1536 if (DO_BIC(BIC_GFX_c0)) 1537 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; 1538 if (DO_BIC(BIC_CPUGFX)) 1539 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; 1540 1541 average.packages.pc2 += p->pc2; 1542 if (DO_BIC(BIC_Pkgpc3)) 1543 average.packages.pc3 += p->pc3; 1544 if (DO_BIC(BIC_Pkgpc6)) 1545 average.packages.pc6 += p->pc6; 1546 if (DO_BIC(BIC_Pkgpc7)) 1547 average.packages.pc7 += p->pc7; 1548 average.packages.pc8 += p->pc8; 1549 average.packages.pc9 += p->pc9; 1550 average.packages.pc10 += p->pc10; 1551 1552 average.packages.cpu_lpi = p->cpu_lpi; 1553 average.packages.sys_lpi = p->sys_lpi; 1554 1555 average.packages.energy_pkg += p->energy_pkg; 1556 average.packages.energy_dram += p->energy_dram; 1557 average.packages.energy_cores += p->energy_cores; 1558 average.packages.energy_gfx += p->energy_gfx; 1559 1560 average.packages.gfx_rc6_ms = p->gfx_rc6_ms; 1561 average.packages.gfx_mhz = p->gfx_mhz; 1562 1563 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); 1564 1565 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; 1566 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; 1567 1568 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1569 if (mp->format == FORMAT_RAW) 1570 continue; 1571 average.packages.counter[i] += p->counter[i]; 1572 } 1573 return 0; 1574 } 1575 /* 1576 * sum the counters for all cpus in the system 1577 * compute the weighted average 1578 */ 1579 void compute_average(struct thread_data *t, struct core_data *c, 1580 struct pkg_data *p) 1581 { 1582 int i; 1583 struct msr_counter *mp; 1584 1585 clear_counters(&average.threads, &average.cores, &average.packages); 1586 1587 for_all_cpus(sum_counters, t, c, p); 1588 1589 /* Use the global time delta for the average. */ 1590 average.threads.tv_delta = tv_delta; 1591 1592 average.threads.tsc /= topo.num_cpus; 1593 average.threads.aperf /= topo.num_cpus; 1594 average.threads.mperf /= topo.num_cpus; 1595 average.threads.c1 /= topo.num_cpus; 1596 1597 if (average.threads.irq_count > 9999999) 1598 sums_need_wide_columns = 1; 1599 1600 average.cores.c3 /= topo.num_cores; 1601 average.cores.c6 /= topo.num_cores; 1602 average.cores.c7 /= topo.num_cores; 1603 average.cores.mc6_us /= topo.num_cores; 1604 1605 if (DO_BIC(BIC_Totl_c0)) 1606 average.packages.pkg_wtd_core_c0 /= topo.num_packages; 1607 if (DO_BIC(BIC_Any_c0)) 1608 average.packages.pkg_any_core_c0 /= topo.num_packages; 1609 if (DO_BIC(BIC_GFX_c0)) 1610 average.packages.pkg_any_gfxe_c0 /= topo.num_packages; 1611 if (DO_BIC(BIC_CPUGFX)) 1612 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages; 1613 1614 average.packages.pc2 /= topo.num_packages; 1615 if (DO_BIC(BIC_Pkgpc3)) 1616 average.packages.pc3 /= topo.num_packages; 1617 if (DO_BIC(BIC_Pkgpc6)) 1618 average.packages.pc6 /= topo.num_packages; 1619 if (DO_BIC(BIC_Pkgpc7)) 1620 average.packages.pc7 /= topo.num_packages; 1621 1622 average.packages.pc8 /= topo.num_packages; 1623 average.packages.pc9 /= topo.num_packages; 1624 average.packages.pc10 /= topo.num_packages; 1625 1626 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1627 if (mp->format == FORMAT_RAW) 1628 continue; 1629 if (mp->type == COUNTER_ITEMS) { 1630 if (average.threads.counter[i] > 9999999) 1631 sums_need_wide_columns = 1; 1632 continue; 1633 } 1634 average.threads.counter[i] /= topo.num_cpus; 1635 } 1636 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1637 if (mp->format == FORMAT_RAW) 1638 continue; 1639 if (mp->type == COUNTER_ITEMS) { 1640 if (average.cores.counter[i] > 9999999) 1641 sums_need_wide_columns = 1; 1642 } 1643 average.cores.counter[i] /= topo.num_cores; 1644 } 1645 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1646 if (mp->format == FORMAT_RAW) 1647 continue; 1648 if (mp->type == COUNTER_ITEMS) { 1649 if (average.packages.counter[i] > 9999999) 1650 sums_need_wide_columns = 1; 1651 } 1652 average.packages.counter[i] /= topo.num_packages; 1653 } 1654 } 1655 1656 static unsigned long long rdtsc(void) 1657 { 1658 unsigned int low, high; 1659 1660 asm volatile("rdtsc" : "=a" (low), "=d" (high)); 1661 1662 return low | ((unsigned long long)high) << 32; 1663 } 1664 1665 /* 1666 * Open a file, and exit on failure 1667 */ 1668 FILE *fopen_or_die(const char *path, const char *mode) 1669 { 1670 FILE *filep = fopen(path, mode); 1671 1672 if (!filep) 1673 err(1, "%s: open failed", path); 1674 return filep; 1675 } 1676 /* 1677 * snapshot_sysfs_counter() 1678 * 1679 * return snapshot of given counter 1680 */ 1681 unsigned long long snapshot_sysfs_counter(char *path) 1682 { 1683 FILE *fp; 1684 int retval; 1685 unsigned long long counter; 1686 1687 fp = fopen_or_die(path, "r"); 1688 1689 retval = fscanf(fp, "%lld", &counter); 1690 if (retval != 1) 1691 err(1, "snapshot_sysfs_counter(%s)", path); 1692 1693 fclose(fp); 1694 1695 return counter; 1696 } 1697 1698 int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp) 1699 { 1700 if (mp->msr_num != 0) { 1701 if (get_msr(cpu, mp->msr_num, counterp)) 1702 return -1; 1703 } else { 1704 char path[128 + PATH_BYTES]; 1705 1706 if (mp->flags & SYSFS_PERCPU) { 1707 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s", 1708 cpu, mp->path); 1709 1710 *counterp = snapshot_sysfs_counter(path); 1711 } else { 1712 *counterp = snapshot_sysfs_counter(mp->path); 1713 } 1714 } 1715 1716 return 0; 1717 } 1718 1719 void get_apic_id(struct thread_data *t) 1720 { 1721 unsigned int eax, ebx, ecx, edx; 1722 1723 if (DO_BIC(BIC_APIC)) { 1724 eax = ebx = ecx = edx = 0; 1725 __cpuid(1, eax, ebx, ecx, edx); 1726 1727 t->apic_id = (ebx >> 24) & 0xff; 1728 } 1729 1730 if (!DO_BIC(BIC_X2APIC)) 1731 return; 1732 1733 if (authentic_amd) { 1734 unsigned int topology_extensions; 1735 1736 if (max_extended_level < 0x8000001e) 1737 return; 1738 1739 eax = ebx = ecx = edx = 0; 1740 __cpuid(0x80000001, eax, ebx, ecx, edx); 1741 topology_extensions = ecx & (1 << 22); 1742 1743 if (topology_extensions == 0) 1744 return; 1745 1746 eax = ebx = ecx = edx = 0; 1747 __cpuid(0x8000001e, eax, ebx, ecx, edx); 1748 1749 t->x2apic_id = eax; 1750 return; 1751 } 1752 1753 if (!genuine_intel) 1754 return; 1755 1756 if (max_level < 0xb) 1757 return; 1758 1759 ecx = 0; 1760 __cpuid(0xb, eax, ebx, ecx, edx); 1761 t->x2apic_id = edx; 1762 1763 if (debug && (t->apic_id != (t->x2apic_id & 0xff))) 1764 fprintf(outf, "cpu%d: BIOS BUG: apic 0x%x x2apic 0x%x\n", 1765 t->cpu_id, t->apic_id, t->x2apic_id); 1766 } 1767 1768 /* 1769 * get_counters(...) 1770 * migrate to cpu 1771 * acquire and record local counters for that cpu 1772 */ 1773 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1774 { 1775 int cpu = t->cpu_id; 1776 unsigned long long msr; 1777 int aperf_mperf_retry_count = 0; 1778 struct msr_counter *mp; 1779 int i; 1780 1781 if (cpu_migrate(cpu)) { 1782 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 1783 return -1; 1784 } 1785 1786 gettimeofday(&t->tv_begin, (struct timezone *)NULL); 1787 1788 if (first_counter_read) 1789 get_apic_id(t); 1790 retry: 1791 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 1792 1793 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || 1794 soft_c1_residency_display(BIC_Avg_MHz)) { 1795 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; 1796 1797 /* 1798 * The TSC, APERF and MPERF must be read together for 1799 * APERF/MPERF and MPERF/TSC to give accurate results. 1800 * 1801 * Unfortunately, APERF and MPERF are read by 1802 * individual system call, so delays may occur 1803 * between them. If the time to read them 1804 * varies by a large amount, we re-read them. 1805 */ 1806 1807 /* 1808 * This initial dummy APERF read has been seen to 1809 * reduce jitter in the subsequent reads. 1810 */ 1811 1812 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1813 return -3; 1814 1815 t->tsc = rdtsc(); /* re-read close to APERF */ 1816 1817 tsc_before = t->tsc; 1818 1819 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1820 return -3; 1821 1822 tsc_between = rdtsc(); 1823 1824 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) 1825 return -4; 1826 1827 tsc_after = rdtsc(); 1828 1829 aperf_time = tsc_between - tsc_before; 1830 mperf_time = tsc_after - tsc_between; 1831 1832 /* 1833 * If the system call latency to read APERF and MPERF 1834 * differ by more than 2x, then try again. 1835 */ 1836 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { 1837 aperf_mperf_retry_count++; 1838 if (aperf_mperf_retry_count < 5) 1839 goto retry; 1840 else 1841 warnx("cpu%d jitter %lld %lld", 1842 cpu, aperf_time, mperf_time); 1843 } 1844 aperf_mperf_retry_count = 0; 1845 1846 t->aperf = t->aperf * aperf_mperf_multiplier; 1847 t->mperf = t->mperf * aperf_mperf_multiplier; 1848 } 1849 1850 if (DO_BIC(BIC_IRQ)) 1851 t->irq_count = irqs_per_cpu[cpu]; 1852 if (DO_BIC(BIC_SMI)) { 1853 if (get_msr(cpu, MSR_SMI_COUNT, &msr)) 1854 return -5; 1855 t->smi_count = msr & 0xFFFFFFFF; 1856 } 1857 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) { 1858 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) 1859 return -6; 1860 } 1861 1862 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1863 if (get_mp(cpu, mp, &t->counter[i])) 1864 return -10; 1865 } 1866 1867 /* collect core counters only for 1st thread in core */ 1868 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1869 goto done; 1870 1871 if (DO_BIC(BIC_CPU_c3) || soft_c1_residency_display(BIC_CPU_c3)) { 1872 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) 1873 return -6; 1874 } 1875 1876 if ((DO_BIC(BIC_CPU_c6) || soft_c1_residency_display(BIC_CPU_c6)) && !do_knl_cstates) { 1877 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) 1878 return -7; 1879 } else if (do_knl_cstates || soft_c1_residency_display(BIC_CPU_c6)) { 1880 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) 1881 return -7; 1882 } 1883 1884 if (DO_BIC(BIC_CPU_c7) || soft_c1_residency_display(BIC_CPU_c7)) 1885 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 1886 return -8; 1887 1888 if (DO_BIC(BIC_Mod_c6)) 1889 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us)) 1890 return -8; 1891 1892 if (DO_BIC(BIC_CoreTmp)) { 1893 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 1894 return -9; 1895 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1896 } 1897 1898 if (do_rapl & RAPL_AMD_F17H) { 1899 if (get_msr(cpu, MSR_CORE_ENERGY_STAT, &msr)) 1900 return -14; 1901 c->core_energy = msr & 0xFFFFFFFF; 1902 } 1903 1904 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1905 if (get_mp(cpu, mp, &c->counter[i])) 1906 return -10; 1907 } 1908 1909 /* collect package counters only for 1st core in package */ 1910 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1911 goto done; 1912 1913 if (DO_BIC(BIC_Totl_c0)) { 1914 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) 1915 return -10; 1916 } 1917 if (DO_BIC(BIC_Any_c0)) { 1918 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) 1919 return -11; 1920 } 1921 if (DO_BIC(BIC_GFX_c0)) { 1922 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) 1923 return -12; 1924 } 1925 if (DO_BIC(BIC_CPUGFX)) { 1926 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) 1927 return -13; 1928 } 1929 if (DO_BIC(BIC_Pkgpc3)) 1930 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) 1931 return -9; 1932 if (DO_BIC(BIC_Pkgpc6)) { 1933 if (do_slm_cstates) { 1934 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6)) 1935 return -10; 1936 } else { 1937 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) 1938 return -10; 1939 } 1940 } 1941 1942 if (DO_BIC(BIC_Pkgpc2)) 1943 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) 1944 return -11; 1945 if (DO_BIC(BIC_Pkgpc7)) 1946 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) 1947 return -12; 1948 if (DO_BIC(BIC_Pkgpc8)) 1949 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) 1950 return -13; 1951 if (DO_BIC(BIC_Pkgpc9)) 1952 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) 1953 return -13; 1954 if (DO_BIC(BIC_Pkgpc10)) 1955 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) 1956 return -13; 1957 1958 if (DO_BIC(BIC_CPU_LPI)) 1959 p->cpu_lpi = cpuidle_cur_cpu_lpi_us; 1960 if (DO_BIC(BIC_SYS_LPI)) 1961 p->sys_lpi = cpuidle_cur_sys_lpi_us; 1962 1963 if (do_rapl & RAPL_PKG) { 1964 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr)) 1965 return -13; 1966 p->energy_pkg = msr & 0xFFFFFFFF; 1967 } 1968 if (do_rapl & RAPL_CORES_ENERGY_STATUS) { 1969 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr)) 1970 return -14; 1971 p->energy_cores = msr & 0xFFFFFFFF; 1972 } 1973 if (do_rapl & RAPL_DRAM) { 1974 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) 1975 return -15; 1976 p->energy_dram = msr & 0xFFFFFFFF; 1977 } 1978 if (do_rapl & RAPL_GFX) { 1979 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr)) 1980 return -16; 1981 p->energy_gfx = msr & 0xFFFFFFFF; 1982 } 1983 if (do_rapl & RAPL_PKG_PERF_STATUS) { 1984 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr)) 1985 return -16; 1986 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF; 1987 } 1988 if (do_rapl & RAPL_DRAM_PERF_STATUS) { 1989 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr)) 1990 return -16; 1991 p->rapl_dram_perf_status = msr & 0xFFFFFFFF; 1992 } 1993 if (do_rapl & RAPL_AMD_F17H) { 1994 if (get_msr(cpu, MSR_PKG_ENERGY_STAT, &msr)) 1995 return -13; 1996 p->energy_pkg = msr & 0xFFFFFFFF; 1997 } 1998 if (DO_BIC(BIC_PkgTmp)) { 1999 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 2000 return -17; 2001 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 2002 } 2003 2004 if (DO_BIC(BIC_GFX_rc6)) 2005 p->gfx_rc6_ms = gfx_cur_rc6_ms; 2006 2007 if (DO_BIC(BIC_GFXMHz)) 2008 p->gfx_mhz = gfx_cur_mhz; 2009 2010 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 2011 if (get_mp(cpu, mp, &p->counter[i])) 2012 return -10; 2013 } 2014 done: 2015 gettimeofday(&t->tv_end, (struct timezone *)NULL); 2016 2017 return 0; 2018 } 2019 2020 /* 2021 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: 2022 * If you change the values, note they are used both in comparisons 2023 * (>= PCL__7) and to index pkg_cstate_limit_strings[]. 2024 */ 2025 2026 #define PCLUKN 0 /* Unknown */ 2027 #define PCLRSV 1 /* Reserved */ 2028 #define PCL__0 2 /* PC0 */ 2029 #define PCL__1 3 /* PC1 */ 2030 #define PCL__2 4 /* PC2 */ 2031 #define PCL__3 5 /* PC3 */ 2032 #define PCL__4 6 /* PC4 */ 2033 #define PCL__6 7 /* PC6 */ 2034 #define PCL_6N 8 /* PC6 No Retention */ 2035 #define PCL_6R 9 /* PC6 Retention */ 2036 #define PCL__7 10 /* PC7 */ 2037 #define PCL_7S 11 /* PC7 Shrink */ 2038 #define PCL__8 12 /* PC8 */ 2039 #define PCL__9 13 /* PC9 */ 2040 #define PCL_10 14 /* PC10 */ 2041 #define PCLUNL 15 /* Unlimited */ 2042 2043 int pkg_cstate_limit = PCLUKN; 2044 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", 2045 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "pc10", "unlimited"}; 2046 2047 int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2048 int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2049 int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2050 int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7}; 2051 int amt_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2052 int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2053 int glm_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCL_10, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2054 int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2055 2056 2057 static void 2058 calculate_tsc_tweak() 2059 { 2060 tsc_tweak = base_hz / tsc_hz; 2061 } 2062 2063 static void 2064 dump_nhm_platform_info(void) 2065 { 2066 unsigned long long msr; 2067 unsigned int ratio; 2068 2069 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 2070 2071 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 2072 2073 ratio = (msr >> 40) & 0xFF; 2074 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", 2075 ratio, bclk, ratio * bclk); 2076 2077 ratio = (msr >> 8) & 0xFF; 2078 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", 2079 ratio, bclk, ratio * bclk); 2080 2081 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); 2082 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", 2083 base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); 2084 2085 return; 2086 } 2087 2088 static void 2089 dump_hsw_turbo_ratio_limits(void) 2090 { 2091 unsigned long long msr; 2092 unsigned int ratio; 2093 2094 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); 2095 2096 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); 2097 2098 ratio = (msr >> 8) & 0xFF; 2099 if (ratio) 2100 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", 2101 ratio, bclk, ratio * bclk); 2102 2103 ratio = (msr >> 0) & 0xFF; 2104 if (ratio) 2105 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", 2106 ratio, bclk, ratio * bclk); 2107 return; 2108 } 2109 2110 static void 2111 dump_ivt_turbo_ratio_limits(void) 2112 { 2113 unsigned long long msr; 2114 unsigned int ratio; 2115 2116 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); 2117 2118 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); 2119 2120 ratio = (msr >> 56) & 0xFF; 2121 if (ratio) 2122 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", 2123 ratio, bclk, ratio * bclk); 2124 2125 ratio = (msr >> 48) & 0xFF; 2126 if (ratio) 2127 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", 2128 ratio, bclk, ratio * bclk); 2129 2130 ratio = (msr >> 40) & 0xFF; 2131 if (ratio) 2132 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", 2133 ratio, bclk, ratio * bclk); 2134 2135 ratio = (msr >> 32) & 0xFF; 2136 if (ratio) 2137 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", 2138 ratio, bclk, ratio * bclk); 2139 2140 ratio = (msr >> 24) & 0xFF; 2141 if (ratio) 2142 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", 2143 ratio, bclk, ratio * bclk); 2144 2145 ratio = (msr >> 16) & 0xFF; 2146 if (ratio) 2147 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", 2148 ratio, bclk, ratio * bclk); 2149 2150 ratio = (msr >> 8) & 0xFF; 2151 if (ratio) 2152 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", 2153 ratio, bclk, ratio * bclk); 2154 2155 ratio = (msr >> 0) & 0xFF; 2156 if (ratio) 2157 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", 2158 ratio, bclk, ratio * bclk); 2159 return; 2160 } 2161 int has_turbo_ratio_group_limits(int family, int model) 2162 { 2163 2164 if (!genuine_intel) 2165 return 0; 2166 2167 switch (model) { 2168 case INTEL_FAM6_ATOM_GOLDMONT: 2169 case INTEL_FAM6_SKYLAKE_X: 2170 case INTEL_FAM6_ATOM_GOLDMONT_X: 2171 return 1; 2172 } 2173 return 0; 2174 } 2175 2176 static void 2177 dump_turbo_ratio_limits(int family, int model) 2178 { 2179 unsigned long long msr, core_counts; 2180 unsigned int ratio, group_size; 2181 2182 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2183 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 2184 2185 if (has_turbo_ratio_group_limits(family, model)) { 2186 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts); 2187 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts); 2188 } else { 2189 core_counts = 0x0807060504030201; 2190 } 2191 2192 ratio = (msr >> 56) & 0xFF; 2193 group_size = (core_counts >> 56) & 0xFF; 2194 if (ratio) 2195 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2196 ratio, bclk, ratio * bclk, group_size); 2197 2198 ratio = (msr >> 48) & 0xFF; 2199 group_size = (core_counts >> 48) & 0xFF; 2200 if (ratio) 2201 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2202 ratio, bclk, ratio * bclk, group_size); 2203 2204 ratio = (msr >> 40) & 0xFF; 2205 group_size = (core_counts >> 40) & 0xFF; 2206 if (ratio) 2207 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2208 ratio, bclk, ratio * bclk, group_size); 2209 2210 ratio = (msr >> 32) & 0xFF; 2211 group_size = (core_counts >> 32) & 0xFF; 2212 if (ratio) 2213 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2214 ratio, bclk, ratio * bclk, group_size); 2215 2216 ratio = (msr >> 24) & 0xFF; 2217 group_size = (core_counts >> 24) & 0xFF; 2218 if (ratio) 2219 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2220 ratio, bclk, ratio * bclk, group_size); 2221 2222 ratio = (msr >> 16) & 0xFF; 2223 group_size = (core_counts >> 16) & 0xFF; 2224 if (ratio) 2225 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2226 ratio, bclk, ratio * bclk, group_size); 2227 2228 ratio = (msr >> 8) & 0xFF; 2229 group_size = (core_counts >> 8) & 0xFF; 2230 if (ratio) 2231 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2232 ratio, bclk, ratio * bclk, group_size); 2233 2234 ratio = (msr >> 0) & 0xFF; 2235 group_size = (core_counts >> 0) & 0xFF; 2236 if (ratio) 2237 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2238 ratio, bclk, ratio * bclk, group_size); 2239 return; 2240 } 2241 2242 static void 2243 dump_atom_turbo_ratio_limits(void) 2244 { 2245 unsigned long long msr; 2246 unsigned int ratio; 2247 2248 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr); 2249 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2250 2251 ratio = (msr >> 0) & 0x3F; 2252 if (ratio) 2253 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", 2254 ratio, bclk, ratio * bclk); 2255 2256 ratio = (msr >> 8) & 0x3F; 2257 if (ratio) 2258 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", 2259 ratio, bclk, ratio * bclk); 2260 2261 ratio = (msr >> 16) & 0x3F; 2262 if (ratio) 2263 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", 2264 ratio, bclk, ratio * bclk); 2265 2266 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr); 2267 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2268 2269 ratio = (msr >> 24) & 0x3F; 2270 if (ratio) 2271 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", 2272 ratio, bclk, ratio * bclk); 2273 2274 ratio = (msr >> 16) & 0x3F; 2275 if (ratio) 2276 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", 2277 ratio, bclk, ratio * bclk); 2278 2279 ratio = (msr >> 8) & 0x3F; 2280 if (ratio) 2281 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", 2282 ratio, bclk, ratio * bclk); 2283 2284 ratio = (msr >> 0) & 0x3F; 2285 if (ratio) 2286 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", 2287 ratio, bclk, ratio * bclk); 2288 } 2289 2290 static void 2291 dump_knl_turbo_ratio_limits(void) 2292 { 2293 const unsigned int buckets_no = 7; 2294 2295 unsigned long long msr; 2296 int delta_cores, delta_ratio; 2297 int i, b_nr; 2298 unsigned int cores[buckets_no]; 2299 unsigned int ratio[buckets_no]; 2300 2301 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2302 2303 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", 2304 base_cpu, msr); 2305 2306 /** 2307 * Turbo encoding in KNL is as follows: 2308 * [0] -- Reserved 2309 * [7:1] -- Base value of number of active cores of bucket 1. 2310 * [15:8] -- Base value of freq ratio of bucket 1. 2311 * [20:16] -- +ve delta of number of active cores of bucket 2. 2312 * i.e. active cores of bucket 2 = 2313 * active cores of bucket 1 + delta 2314 * [23:21] -- Negative delta of freq ratio of bucket 2. 2315 * i.e. freq ratio of bucket 2 = 2316 * freq ratio of bucket 1 - delta 2317 * [28:24]-- +ve delta of number of active cores of bucket 3. 2318 * [31:29]-- -ve delta of freq ratio of bucket 3. 2319 * [36:32]-- +ve delta of number of active cores of bucket 4. 2320 * [39:37]-- -ve delta of freq ratio of bucket 4. 2321 * [44:40]-- +ve delta of number of active cores of bucket 5. 2322 * [47:45]-- -ve delta of freq ratio of bucket 5. 2323 * [52:48]-- +ve delta of number of active cores of bucket 6. 2324 * [55:53]-- -ve delta of freq ratio of bucket 6. 2325 * [60:56]-- +ve delta of number of active cores of bucket 7. 2326 * [63:61]-- -ve delta of freq ratio of bucket 7. 2327 */ 2328 2329 b_nr = 0; 2330 cores[b_nr] = (msr & 0xFF) >> 1; 2331 ratio[b_nr] = (msr >> 8) & 0xFF; 2332 2333 for (i = 16; i < 64; i += 8) { 2334 delta_cores = (msr >> i) & 0x1F; 2335 delta_ratio = (msr >> (i + 5)) & 0x7; 2336 2337 cores[b_nr + 1] = cores[b_nr] + delta_cores; 2338 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; 2339 b_nr++; 2340 } 2341 2342 for (i = buckets_no - 1; i >= 0; i--) 2343 if (i > 0 ? ratio[i] != ratio[i - 1] : 1) 2344 fprintf(outf, 2345 "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2346 ratio[i], bclk, ratio[i] * bclk, cores[i]); 2347 } 2348 2349 static void 2350 dump_nhm_cst_cfg(void) 2351 { 2352 unsigned long long msr; 2353 2354 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 2355 2356 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr); 2357 2358 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)", 2359 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", 2360 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", 2361 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", 2362 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", 2363 (msr & (1 << 15)) ? "" : "UN", 2364 (unsigned int)msr & 0xF, 2365 pkg_cstate_limit_strings[pkg_cstate_limit]); 2366 2367 #define AUTOMATIC_CSTATE_CONVERSION (1UL << 16) 2368 if (has_automatic_cstate_conversion) { 2369 fprintf(outf, ", automatic c-state conversion=%s", 2370 (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off"); 2371 } 2372 2373 fprintf(outf, ")\n"); 2374 2375 return; 2376 } 2377 2378 static void 2379 dump_config_tdp(void) 2380 { 2381 unsigned long long msr; 2382 2383 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); 2384 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); 2385 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); 2386 2387 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); 2388 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); 2389 if (msr) { 2390 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2391 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2392 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2393 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); 2394 } 2395 fprintf(outf, ")\n"); 2396 2397 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); 2398 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); 2399 if (msr) { 2400 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2401 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2402 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2403 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); 2404 } 2405 fprintf(outf, ")\n"); 2406 2407 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); 2408 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); 2409 if ((msr) & 0x3) 2410 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); 2411 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2412 fprintf(outf, ")\n"); 2413 2414 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); 2415 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); 2416 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); 2417 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2418 fprintf(outf, ")\n"); 2419 } 2420 2421 unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; 2422 2423 void print_irtl(void) 2424 { 2425 unsigned long long msr; 2426 2427 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr); 2428 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr); 2429 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2430 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2431 2432 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr); 2433 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr); 2434 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2435 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2436 2437 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr); 2438 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr); 2439 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2440 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2441 2442 if (!do_irtl_hsw) 2443 return; 2444 2445 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr); 2446 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr); 2447 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2448 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2449 2450 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr); 2451 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr); 2452 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2453 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2454 2455 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr); 2456 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr); 2457 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2458 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2459 2460 } 2461 void free_fd_percpu(void) 2462 { 2463 int i; 2464 2465 for (i = 0; i < topo.max_cpu_num + 1; ++i) { 2466 if (fd_percpu[i] != 0) 2467 close(fd_percpu[i]); 2468 } 2469 2470 free(fd_percpu); 2471 } 2472 2473 void free_all_buffers(void) 2474 { 2475 int i; 2476 2477 CPU_FREE(cpu_present_set); 2478 cpu_present_set = NULL; 2479 cpu_present_setsize = 0; 2480 2481 CPU_FREE(cpu_affinity_set); 2482 cpu_affinity_set = NULL; 2483 cpu_affinity_setsize = 0; 2484 2485 free(thread_even); 2486 free(core_even); 2487 free(package_even); 2488 2489 thread_even = NULL; 2490 core_even = NULL; 2491 package_even = NULL; 2492 2493 free(thread_odd); 2494 free(core_odd); 2495 free(package_odd); 2496 2497 thread_odd = NULL; 2498 core_odd = NULL; 2499 package_odd = NULL; 2500 2501 free(output_buffer); 2502 output_buffer = NULL; 2503 outp = NULL; 2504 2505 free_fd_percpu(); 2506 2507 free(irq_column_2_cpu); 2508 free(irqs_per_cpu); 2509 2510 for (i = 0; i <= topo.max_cpu_num; ++i) { 2511 if (cpus[i].put_ids) 2512 CPU_FREE(cpus[i].put_ids); 2513 } 2514 free(cpus); 2515 } 2516 2517 2518 /* 2519 * Parse a file containing a single int. 2520 * Return 0 if file can not be opened 2521 * Exit if file can be opened, but can not be parsed 2522 */ 2523 int parse_int_file(const char *fmt, ...) 2524 { 2525 va_list args; 2526 char path[PATH_MAX]; 2527 FILE *filep; 2528 int value; 2529 2530 va_start(args, fmt); 2531 vsnprintf(path, sizeof(path), fmt, args); 2532 va_end(args); 2533 filep = fopen(path, "r"); 2534 if (!filep) 2535 return 0; 2536 if (fscanf(filep, "%d", &value) != 1) 2537 err(1, "%s: failed to parse number from file", path); 2538 fclose(filep); 2539 return value; 2540 } 2541 2542 /* 2543 * cpu_is_first_core_in_package(cpu) 2544 * return 1 if given CPU is 1st core in package 2545 */ 2546 int cpu_is_first_core_in_package(int cpu) 2547 { 2548 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); 2549 } 2550 2551 int get_physical_package_id(int cpu) 2552 { 2553 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); 2554 } 2555 2556 int get_die_id(int cpu) 2557 { 2558 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/die_id", cpu); 2559 } 2560 2561 int get_core_id(int cpu) 2562 { 2563 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); 2564 } 2565 2566 void set_node_data(void) 2567 { 2568 int pkg, node, lnode, cpu, cpux; 2569 int cpu_count; 2570 2571 /* initialize logical_node_id */ 2572 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) 2573 cpus[cpu].logical_node_id = -1; 2574 2575 cpu_count = 0; 2576 for (pkg = 0; pkg < topo.num_packages; pkg++) { 2577 lnode = 0; 2578 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) { 2579 if (cpus[cpu].physical_package_id != pkg) 2580 continue; 2581 /* find a cpu with an unset logical_node_id */ 2582 if (cpus[cpu].logical_node_id != -1) 2583 continue; 2584 cpus[cpu].logical_node_id = lnode; 2585 node = cpus[cpu].physical_node_id; 2586 cpu_count++; 2587 /* 2588 * find all matching cpus on this pkg and set 2589 * the logical_node_id 2590 */ 2591 for (cpux = cpu; cpux <= topo.max_cpu_num; cpux++) { 2592 if ((cpus[cpux].physical_package_id == pkg) && 2593 (cpus[cpux].physical_node_id == node)) { 2594 cpus[cpux].logical_node_id = lnode; 2595 cpu_count++; 2596 } 2597 } 2598 lnode++; 2599 if (lnode > topo.nodes_per_pkg) 2600 topo.nodes_per_pkg = lnode; 2601 } 2602 if (cpu_count >= topo.max_cpu_num) 2603 break; 2604 } 2605 } 2606 2607 int get_physical_node_id(struct cpu_topology *thiscpu) 2608 { 2609 char path[80]; 2610 FILE *filep; 2611 int i; 2612 int cpu = thiscpu->logical_cpu_id; 2613 2614 for (i = 0; i <= topo.max_cpu_num; i++) { 2615 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist", 2616 cpu, i); 2617 filep = fopen(path, "r"); 2618 if (!filep) 2619 continue; 2620 fclose(filep); 2621 return i; 2622 } 2623 return -1; 2624 } 2625 2626 int get_thread_siblings(struct cpu_topology *thiscpu) 2627 { 2628 char path[80], character; 2629 FILE *filep; 2630 unsigned long map; 2631 int so, shift, sib_core; 2632 int cpu = thiscpu->logical_cpu_id; 2633 int offset = topo.max_cpu_num + 1; 2634 size_t size; 2635 int thread_id = 0; 2636 2637 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1)); 2638 if (thiscpu->thread_id < 0) 2639 thiscpu->thread_id = thread_id++; 2640 if (!thiscpu->put_ids) 2641 return -1; 2642 2643 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 2644 CPU_ZERO_S(size, thiscpu->put_ids); 2645 2646 sprintf(path, 2647 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu); 2648 filep = fopen_or_die(path, "r"); 2649 do { 2650 offset -= BITMASK_SIZE; 2651 if (fscanf(filep, "%lx%c", &map, &character) != 2) 2652 err(1, "%s: failed to parse file", path); 2653 for (shift = 0; shift < BITMASK_SIZE; shift++) { 2654 if ((map >> shift) & 0x1) { 2655 so = shift + offset; 2656 sib_core = get_core_id(so); 2657 if (sib_core == thiscpu->physical_core_id) { 2658 CPU_SET_S(so, size, thiscpu->put_ids); 2659 if ((so != cpu) && 2660 (cpus[so].thread_id < 0)) 2661 cpus[so].thread_id = 2662 thread_id++; 2663 } 2664 } 2665 } 2666 } while (!strncmp(&character, ",", 1)); 2667 fclose(filep); 2668 2669 return CPU_COUNT_S(size, thiscpu->put_ids); 2670 } 2671 2672 /* 2673 * run func(thread, core, package) in topology order 2674 * skip non-present cpus 2675 */ 2676 2677 int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *, 2678 struct pkg_data *, struct thread_data *, struct core_data *, 2679 struct pkg_data *), struct thread_data *thread_base, 2680 struct core_data *core_base, struct pkg_data *pkg_base, 2681 struct thread_data *thread_base2, struct core_data *core_base2, 2682 struct pkg_data *pkg_base2) 2683 { 2684 int retval, pkg_no, node_no, core_no, thread_no; 2685 2686 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 2687 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) { 2688 for (core_no = 0; core_no < topo.cores_per_node; 2689 ++core_no) { 2690 for (thread_no = 0; thread_no < 2691 topo.threads_per_core; ++thread_no) { 2692 struct thread_data *t, *t2; 2693 struct core_data *c, *c2; 2694 struct pkg_data *p, *p2; 2695 2696 t = GET_THREAD(thread_base, thread_no, 2697 core_no, node_no, 2698 pkg_no); 2699 2700 if (cpu_is_not_present(t->cpu_id)) 2701 continue; 2702 2703 t2 = GET_THREAD(thread_base2, thread_no, 2704 core_no, node_no, 2705 pkg_no); 2706 2707 c = GET_CORE(core_base, core_no, 2708 node_no, pkg_no); 2709 c2 = GET_CORE(core_base2, core_no, 2710 node_no, 2711 pkg_no); 2712 2713 p = GET_PKG(pkg_base, pkg_no); 2714 p2 = GET_PKG(pkg_base2, pkg_no); 2715 2716 retval = func(t, c, p, t2, c2, p2); 2717 if (retval) 2718 return retval; 2719 } 2720 } 2721 } 2722 } 2723 return 0; 2724 } 2725 2726 /* 2727 * run func(cpu) on every cpu in /proc/stat 2728 * return max_cpu number 2729 */ 2730 int for_all_proc_cpus(int (func)(int)) 2731 { 2732 FILE *fp; 2733 int cpu_num; 2734 int retval; 2735 2736 fp = fopen_or_die(proc_stat, "r"); 2737 2738 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); 2739 if (retval != 0) 2740 err(1, "%s: failed to parse format", proc_stat); 2741 2742 while (1) { 2743 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); 2744 if (retval != 1) 2745 break; 2746 2747 retval = func(cpu_num); 2748 if (retval) { 2749 fclose(fp); 2750 return(retval); 2751 } 2752 } 2753 fclose(fp); 2754 return 0; 2755 } 2756 2757 void re_initialize(void) 2758 { 2759 free_all_buffers(); 2760 setup_all_buffers(); 2761 printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); 2762 } 2763 2764 void set_max_cpu_num(void) 2765 { 2766 FILE *filep; 2767 unsigned long dummy; 2768 2769 topo.max_cpu_num = 0; 2770 filep = fopen_or_die( 2771 "/sys/devices/system/cpu/cpu0/topology/thread_siblings", 2772 "r"); 2773 while (fscanf(filep, "%lx,", &dummy) == 1) 2774 topo.max_cpu_num += BITMASK_SIZE; 2775 fclose(filep); 2776 topo.max_cpu_num--; /* 0 based */ 2777 } 2778 2779 /* 2780 * count_cpus() 2781 * remember the last one seen, it will be the max 2782 */ 2783 int count_cpus(int cpu) 2784 { 2785 topo.num_cpus++; 2786 return 0; 2787 } 2788 int mark_cpu_present(int cpu) 2789 { 2790 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); 2791 return 0; 2792 } 2793 2794 int init_thread_id(int cpu) 2795 { 2796 cpus[cpu].thread_id = -1; 2797 return 0; 2798 } 2799 2800 /* 2801 * snapshot_proc_interrupts() 2802 * 2803 * read and record summary of /proc/interrupts 2804 * 2805 * return 1 if config change requires a restart, else return 0 2806 */ 2807 int snapshot_proc_interrupts(void) 2808 { 2809 static FILE *fp; 2810 int column, retval; 2811 2812 if (fp == NULL) 2813 fp = fopen_or_die("/proc/interrupts", "r"); 2814 else 2815 rewind(fp); 2816 2817 /* read 1st line of /proc/interrupts to get cpu* name for each column */ 2818 for (column = 0; column < topo.num_cpus; ++column) { 2819 int cpu_number; 2820 2821 retval = fscanf(fp, " CPU%d", &cpu_number); 2822 if (retval != 1) 2823 break; 2824 2825 if (cpu_number > topo.max_cpu_num) { 2826 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); 2827 return 1; 2828 } 2829 2830 irq_column_2_cpu[column] = cpu_number; 2831 irqs_per_cpu[cpu_number] = 0; 2832 } 2833 2834 /* read /proc/interrupt count lines and sum up irqs per cpu */ 2835 while (1) { 2836 int column; 2837 char buf[64]; 2838 2839 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ 2840 if (retval != 1) 2841 break; 2842 2843 /* read the count per cpu */ 2844 for (column = 0; column < topo.num_cpus; ++column) { 2845 2846 int cpu_number, irq_count; 2847 2848 retval = fscanf(fp, " %d", &irq_count); 2849 if (retval != 1) 2850 break; 2851 2852 cpu_number = irq_column_2_cpu[column]; 2853 irqs_per_cpu[cpu_number] += irq_count; 2854 2855 } 2856 2857 while (getc(fp) != '\n') 2858 ; /* flush interrupt description */ 2859 2860 } 2861 return 0; 2862 } 2863 /* 2864 * snapshot_gfx_rc6_ms() 2865 * 2866 * record snapshot of 2867 * /sys/class/drm/card0/power/rc6_residency_ms 2868 * 2869 * return 1 if config change requires a restart, else return 0 2870 */ 2871 int snapshot_gfx_rc6_ms(void) 2872 { 2873 FILE *fp; 2874 int retval; 2875 2876 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); 2877 2878 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); 2879 if (retval != 1) 2880 err(1, "GFX rc6"); 2881 2882 fclose(fp); 2883 2884 return 0; 2885 } 2886 /* 2887 * snapshot_gfx_mhz() 2888 * 2889 * record snapshot of 2890 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz 2891 * 2892 * return 1 if config change requires a restart, else return 0 2893 */ 2894 int snapshot_gfx_mhz(void) 2895 { 2896 static FILE *fp; 2897 int retval; 2898 2899 if (fp == NULL) 2900 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); 2901 else { 2902 rewind(fp); 2903 fflush(fp); 2904 } 2905 2906 retval = fscanf(fp, "%d", &gfx_cur_mhz); 2907 if (retval != 1) 2908 err(1, "GFX MHz"); 2909 2910 return 0; 2911 } 2912 2913 /* 2914 * snapshot_cpu_lpi() 2915 * 2916 * record snapshot of 2917 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us 2918 * 2919 * return 1 if config change requires a restart, else return 0 2920 */ 2921 int snapshot_cpu_lpi_us(void) 2922 { 2923 FILE *fp; 2924 int retval; 2925 2926 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r"); 2927 2928 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us); 2929 if (retval != 1) { 2930 fprintf(stderr, "Disabling Low Power Idle CPU output\n"); 2931 BIC_NOT_PRESENT(BIC_CPU_LPI); 2932 fclose(fp); 2933 return -1; 2934 } 2935 2936 fclose(fp); 2937 2938 return 0; 2939 } 2940 /* 2941 * snapshot_sys_lpi() 2942 * 2943 * record snapshot of 2944 * /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us 2945 * 2946 * return 1 if config change requires a restart, else return 0 2947 */ 2948 int snapshot_sys_lpi_us(void) 2949 { 2950 FILE *fp; 2951 int retval; 2952 2953 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us", "r"); 2954 2955 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us); 2956 if (retval != 1) { 2957 fprintf(stderr, "Disabling Low Power Idle System output\n"); 2958 BIC_NOT_PRESENT(BIC_SYS_LPI); 2959 fclose(fp); 2960 return -1; 2961 } 2962 fclose(fp); 2963 2964 return 0; 2965 } 2966 /* 2967 * snapshot /proc and /sys files 2968 * 2969 * return 1 if configuration restart needed, else return 0 2970 */ 2971 int snapshot_proc_sysfs_files(void) 2972 { 2973 if (DO_BIC(BIC_IRQ)) 2974 if (snapshot_proc_interrupts()) 2975 return 1; 2976 2977 if (DO_BIC(BIC_GFX_rc6)) 2978 snapshot_gfx_rc6_ms(); 2979 2980 if (DO_BIC(BIC_GFXMHz)) 2981 snapshot_gfx_mhz(); 2982 2983 if (DO_BIC(BIC_CPU_LPI)) 2984 snapshot_cpu_lpi_us(); 2985 2986 if (DO_BIC(BIC_SYS_LPI)) 2987 snapshot_sys_lpi_us(); 2988 2989 return 0; 2990 } 2991 2992 int exit_requested; 2993 2994 static void signal_handler (int signal) 2995 { 2996 switch (signal) { 2997 case SIGINT: 2998 exit_requested = 1; 2999 if (debug) 3000 fprintf(stderr, " SIGINT\n"); 3001 break; 3002 case SIGUSR1: 3003 if (debug > 1) 3004 fprintf(stderr, "SIGUSR1\n"); 3005 break; 3006 } 3007 } 3008 3009 void setup_signal_handler(void) 3010 { 3011 struct sigaction sa; 3012 3013 memset(&sa, 0, sizeof(sa)); 3014 3015 sa.sa_handler = &signal_handler; 3016 3017 if (sigaction(SIGINT, &sa, NULL) < 0) 3018 err(1, "sigaction SIGINT"); 3019 if (sigaction(SIGUSR1, &sa, NULL) < 0) 3020 err(1, "sigaction SIGUSR1"); 3021 } 3022 3023 void do_sleep(void) 3024 { 3025 struct timeval tout; 3026 struct timespec rest; 3027 fd_set readfds; 3028 int retval; 3029 3030 FD_ZERO(&readfds); 3031 FD_SET(0, &readfds); 3032 3033 if (ignore_stdin) { 3034 nanosleep(&interval_ts, NULL); 3035 return; 3036 } 3037 3038 tout = interval_tv; 3039 retval = select(1, &readfds, NULL, NULL, &tout); 3040 3041 if (retval == 1) { 3042 switch (getc(stdin)) { 3043 case 'q': 3044 exit_requested = 1; 3045 break; 3046 case EOF: 3047 /* 3048 * 'stdin' is a pipe closed on the other end. There 3049 * won't be any further input. 3050 */ 3051 ignore_stdin = 1; 3052 /* Sleep the rest of the time */ 3053 rest.tv_sec = (tout.tv_sec + tout.tv_usec / 1000000); 3054 rest.tv_nsec = (tout.tv_usec % 1000000) * 1000; 3055 nanosleep(&rest, NULL); 3056 } 3057 } 3058 } 3059 3060 3061 void turbostat_loop() 3062 { 3063 int retval; 3064 int restarted = 0; 3065 int done_iters = 0; 3066 3067 setup_signal_handler(); 3068 3069 restart: 3070 restarted++; 3071 3072 snapshot_proc_sysfs_files(); 3073 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3074 first_counter_read = 0; 3075 if (retval < -1) { 3076 exit(retval); 3077 } else if (retval == -1) { 3078 if (restarted > 1) { 3079 exit(retval); 3080 } 3081 re_initialize(); 3082 goto restart; 3083 } 3084 restarted = 0; 3085 done_iters = 0; 3086 gettimeofday(&tv_even, (struct timezone *)NULL); 3087 3088 while (1) { 3089 if (for_all_proc_cpus(cpu_is_not_present)) { 3090 re_initialize(); 3091 goto restart; 3092 } 3093 do_sleep(); 3094 if (snapshot_proc_sysfs_files()) 3095 goto restart; 3096 retval = for_all_cpus(get_counters, ODD_COUNTERS); 3097 if (retval < -1) { 3098 exit(retval); 3099 } else if (retval == -1) { 3100 re_initialize(); 3101 goto restart; 3102 } 3103 gettimeofday(&tv_odd, (struct timezone *)NULL); 3104 timersub(&tv_odd, &tv_even, &tv_delta); 3105 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) { 3106 re_initialize(); 3107 goto restart; 3108 } 3109 compute_average(EVEN_COUNTERS); 3110 format_all_counters(EVEN_COUNTERS); 3111 flush_output_stdout(); 3112 if (exit_requested) 3113 break; 3114 if (num_iterations && ++done_iters >= num_iterations) 3115 break; 3116 do_sleep(); 3117 if (snapshot_proc_sysfs_files()) 3118 goto restart; 3119 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3120 if (retval < -1) { 3121 exit(retval); 3122 } else if (retval == -1) { 3123 re_initialize(); 3124 goto restart; 3125 } 3126 gettimeofday(&tv_even, (struct timezone *)NULL); 3127 timersub(&tv_even, &tv_odd, &tv_delta); 3128 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) { 3129 re_initialize(); 3130 goto restart; 3131 } 3132 compute_average(ODD_COUNTERS); 3133 format_all_counters(ODD_COUNTERS); 3134 flush_output_stdout(); 3135 if (exit_requested) 3136 break; 3137 if (num_iterations && ++done_iters >= num_iterations) 3138 break; 3139 } 3140 } 3141 3142 void check_dev_msr() 3143 { 3144 struct stat sb; 3145 char pathname[32]; 3146 3147 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3148 if (stat(pathname, &sb)) 3149 if (system("/sbin/modprobe msr > /dev/null 2>&1")) 3150 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); 3151 } 3152 3153 void check_permissions() 3154 { 3155 struct __user_cap_header_struct cap_header_data; 3156 cap_user_header_t cap_header = &cap_header_data; 3157 struct __user_cap_data_struct cap_data_data; 3158 cap_user_data_t cap_data = &cap_data_data; 3159 extern int capget(cap_user_header_t hdrp, cap_user_data_t datap); 3160 int do_exit = 0; 3161 char pathname[32]; 3162 3163 /* check for CAP_SYS_RAWIO */ 3164 cap_header->pid = getpid(); 3165 cap_header->version = _LINUX_CAPABILITY_VERSION; 3166 if (capget(cap_header, cap_data) < 0) 3167 err(-6, "capget(2) failed"); 3168 3169 if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) { 3170 do_exit++; 3171 warnx("capget(CAP_SYS_RAWIO) failed," 3172 " try \"# setcap cap_sys_rawio=ep %s\"", progname); 3173 } 3174 3175 /* test file permissions */ 3176 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3177 if (euidaccess(pathname, R_OK)) { 3178 do_exit++; 3179 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); 3180 } 3181 3182 /* if all else fails, thell them to be root */ 3183 if (do_exit) 3184 if (getuid() != 0) 3185 warnx("... or simply run as root"); 3186 3187 if (do_exit) 3188 exit(-6); 3189 } 3190 3191 /* 3192 * NHM adds support for additional MSRs: 3193 * 3194 * MSR_SMI_COUNT 0x00000034 3195 * 3196 * MSR_PLATFORM_INFO 0x000000ce 3197 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 3198 * 3199 * MSR_MISC_PWR_MGMT 0x000001aa 3200 * 3201 * MSR_PKG_C3_RESIDENCY 0x000003f8 3202 * MSR_PKG_C6_RESIDENCY 0x000003f9 3203 * MSR_CORE_C3_RESIDENCY 0x000003fc 3204 * MSR_CORE_C6_RESIDENCY 0x000003fd 3205 * 3206 * Side effect: 3207 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL 3208 * sets has_misc_feature_control 3209 */ 3210 int probe_nhm_msrs(unsigned int family, unsigned int model) 3211 { 3212 unsigned long long msr; 3213 unsigned int base_ratio; 3214 int *pkg_cstate_limits; 3215 3216 if (!genuine_intel) 3217 return 0; 3218 3219 if (family != 6) 3220 return 0; 3221 3222 bclk = discover_bclk(family, model); 3223 3224 switch (model) { 3225 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 3226 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3227 pkg_cstate_limits = nhm_pkg_cstate_limits; 3228 break; 3229 case INTEL_FAM6_SANDYBRIDGE: /* SNB */ 3230 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */ 3231 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3232 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3233 pkg_cstate_limits = snb_pkg_cstate_limits; 3234 has_misc_feature_control = 1; 3235 break; 3236 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3237 case INTEL_FAM6_HASWELL_X: /* HSX */ 3238 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3239 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3240 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3241 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3242 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3243 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3244 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 3245 pkg_cstate_limits = hsw_pkg_cstate_limits; 3246 has_misc_feature_control = 1; 3247 break; 3248 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3249 pkg_cstate_limits = skx_pkg_cstate_limits; 3250 has_misc_feature_control = 1; 3251 break; 3252 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 3253 no_MSR_MISC_PWR_MGMT = 1; 3254 case INTEL_FAM6_ATOM_SILVERMONT_X: /* AVN */ 3255 pkg_cstate_limits = slv_pkg_cstate_limits; 3256 break; 3257 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */ 3258 pkg_cstate_limits = amt_pkg_cstate_limits; 3259 no_MSR_MISC_PWR_MGMT = 1; 3260 break; 3261 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */ 3262 pkg_cstate_limits = phi_pkg_cstate_limits; 3263 break; 3264 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3265 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 3266 case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */ 3267 pkg_cstate_limits = glm_pkg_cstate_limits; 3268 break; 3269 default: 3270 return 0; 3271 } 3272 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 3273 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; 3274 3275 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 3276 base_ratio = (msr >> 8) & 0xFF; 3277 3278 base_hz = base_ratio * bclk * 1000000; 3279 has_base_hz = 1; 3280 return 1; 3281 } 3282 /* 3283 * SLV client has support for unique MSRs: 3284 * 3285 * MSR_CC6_DEMOTION_POLICY_CONFIG 3286 * MSR_MC6_DEMOTION_POLICY_CONFIG 3287 */ 3288 3289 int has_slv_msrs(unsigned int family, unsigned int model) 3290 { 3291 if (!genuine_intel) 3292 return 0; 3293 3294 switch (model) { 3295 case INTEL_FAM6_ATOM_SILVERMONT: 3296 case INTEL_FAM6_ATOM_SILVERMONT_MID: 3297 case INTEL_FAM6_ATOM_AIRMONT_MID: 3298 return 1; 3299 } 3300 return 0; 3301 } 3302 int is_dnv(unsigned int family, unsigned int model) 3303 { 3304 3305 if (!genuine_intel) 3306 return 0; 3307 3308 switch (model) { 3309 case INTEL_FAM6_ATOM_GOLDMONT_X: 3310 return 1; 3311 } 3312 return 0; 3313 } 3314 int is_bdx(unsigned int family, unsigned int model) 3315 { 3316 3317 if (!genuine_intel) 3318 return 0; 3319 3320 switch (model) { 3321 case INTEL_FAM6_BROADWELL_X: 3322 return 1; 3323 } 3324 return 0; 3325 } 3326 int is_skx(unsigned int family, unsigned int model) 3327 { 3328 3329 if (!genuine_intel) 3330 return 0; 3331 3332 switch (model) { 3333 case INTEL_FAM6_SKYLAKE_X: 3334 return 1; 3335 } 3336 return 0; 3337 } 3338 3339 int has_turbo_ratio_limit(unsigned int family, unsigned int model) 3340 { 3341 if (has_slv_msrs(family, model)) 3342 return 0; 3343 3344 switch (model) { 3345 /* Nehalem compatible, but do not include turbo-ratio limit support */ 3346 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3347 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */ 3348 return 0; 3349 default: 3350 return 1; 3351 } 3352 } 3353 int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model) 3354 { 3355 if (has_slv_msrs(family, model)) 3356 return 1; 3357 3358 return 0; 3359 } 3360 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) 3361 { 3362 if (!genuine_intel) 3363 return 0; 3364 3365 if (family != 6) 3366 return 0; 3367 3368 switch (model) { 3369 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3370 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3371 return 1; 3372 default: 3373 return 0; 3374 } 3375 } 3376 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) 3377 { 3378 if (!genuine_intel) 3379 return 0; 3380 3381 if (family != 6) 3382 return 0; 3383 3384 switch (model) { 3385 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3386 return 1; 3387 default: 3388 return 0; 3389 } 3390 } 3391 3392 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) 3393 { 3394 if (!genuine_intel) 3395 return 0; 3396 3397 if (family != 6) 3398 return 0; 3399 3400 switch (model) { 3401 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 3402 return 1; 3403 default: 3404 return 0; 3405 } 3406 } 3407 int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model) 3408 { 3409 if (!genuine_intel) 3410 return 0; 3411 3412 if (family != 6) 3413 return 0; 3414 3415 switch (model) { 3416 case INTEL_FAM6_ATOM_GOLDMONT: 3417 case INTEL_FAM6_SKYLAKE_X: 3418 return 1; 3419 default: 3420 return 0; 3421 } 3422 } 3423 int has_config_tdp(unsigned int family, unsigned int model) 3424 { 3425 if (!genuine_intel) 3426 return 0; 3427 3428 if (family != 6) 3429 return 0; 3430 3431 switch (model) { 3432 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3433 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3434 case INTEL_FAM6_HASWELL_X: /* HSX */ 3435 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3436 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3437 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3438 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3439 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3440 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3441 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 3442 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3443 3444 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 3445 return 1; 3446 default: 3447 return 0; 3448 } 3449 } 3450 3451 static void 3452 dump_cstate_pstate_config_info(unsigned int family, unsigned int model) 3453 { 3454 if (!do_nhm_platform_info) 3455 return; 3456 3457 dump_nhm_platform_info(); 3458 3459 if (has_hsw_turbo_ratio_limit(family, model)) 3460 dump_hsw_turbo_ratio_limits(); 3461 3462 if (has_ivt_turbo_ratio_limit(family, model)) 3463 dump_ivt_turbo_ratio_limits(); 3464 3465 if (has_turbo_ratio_limit(family, model)) 3466 dump_turbo_ratio_limits(family, model); 3467 3468 if (has_atom_turbo_ratio_limit(family, model)) 3469 dump_atom_turbo_ratio_limits(); 3470 3471 if (has_knl_turbo_ratio_limit(family, model)) 3472 dump_knl_turbo_ratio_limits(); 3473 3474 if (has_config_tdp(family, model)) 3475 dump_config_tdp(); 3476 3477 dump_nhm_cst_cfg(); 3478 } 3479 3480 static void 3481 dump_sysfs_cstate_config(void) 3482 { 3483 char path[64]; 3484 char name_buf[16]; 3485 char desc[64]; 3486 FILE *input; 3487 int state; 3488 char *sp; 3489 3490 if (!DO_BIC(BIC_sysfs)) 3491 return; 3492 3493 for (state = 0; state < 10; ++state) { 3494 3495 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 3496 base_cpu, state); 3497 input = fopen(path, "r"); 3498 if (input == NULL) 3499 continue; 3500 if (!fgets(name_buf, sizeof(name_buf), input)) 3501 err(1, "%s: failed to read file", path); 3502 3503 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 3504 sp = strchr(name_buf, '-'); 3505 if (!sp) 3506 sp = strchrnul(name_buf, '\n'); 3507 *sp = '\0'; 3508 fclose(input); 3509 3510 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc", 3511 base_cpu, state); 3512 input = fopen(path, "r"); 3513 if (input == NULL) 3514 continue; 3515 if (!fgets(desc, sizeof(desc), input)) 3516 err(1, "%s: failed to read file", path); 3517 3518 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc); 3519 fclose(input); 3520 } 3521 } 3522 static void 3523 dump_sysfs_pstate_config(void) 3524 { 3525 char path[64]; 3526 char driver_buf[64]; 3527 char governor_buf[64]; 3528 FILE *input; 3529 int turbo; 3530 3531 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver", 3532 base_cpu); 3533 input = fopen(path, "r"); 3534 if (input == NULL) { 3535 fprintf(outf, "NSFOD %s\n", path); 3536 return; 3537 } 3538 if (!fgets(driver_buf, sizeof(driver_buf), input)) 3539 err(1, "%s: failed to read file", path); 3540 fclose(input); 3541 3542 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor", 3543 base_cpu); 3544 input = fopen(path, "r"); 3545 if (input == NULL) { 3546 fprintf(outf, "NSFOD %s\n", path); 3547 return; 3548 } 3549 if (!fgets(governor_buf, sizeof(governor_buf), input)) 3550 err(1, "%s: failed to read file", path); 3551 fclose(input); 3552 3553 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf); 3554 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf); 3555 3556 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost"); 3557 input = fopen(path, "r"); 3558 if (input != NULL) { 3559 if (fscanf(input, "%d", &turbo) != 1) 3560 err(1, "%s: failed to parse number from file", path); 3561 fprintf(outf, "cpufreq boost: %d\n", turbo); 3562 fclose(input); 3563 } 3564 3565 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo"); 3566 input = fopen(path, "r"); 3567 if (input != NULL) { 3568 if (fscanf(input, "%d", &turbo) != 1) 3569 err(1, "%s: failed to parse number from file", path); 3570 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo); 3571 fclose(input); 3572 } 3573 } 3574 3575 3576 /* 3577 * print_epb() 3578 * Decode the ENERGY_PERF_BIAS MSR 3579 */ 3580 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3581 { 3582 unsigned long long msr; 3583 char *epb_string; 3584 int cpu; 3585 3586 if (!has_epb) 3587 return 0; 3588 3589 cpu = t->cpu_id; 3590 3591 /* EPB is per-package */ 3592 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3593 return 0; 3594 3595 if (cpu_migrate(cpu)) { 3596 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3597 return -1; 3598 } 3599 3600 if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr)) 3601 return 0; 3602 3603 switch (msr & 0xF) { 3604 case ENERGY_PERF_BIAS_PERFORMANCE: 3605 epb_string = "performance"; 3606 break; 3607 case ENERGY_PERF_BIAS_NORMAL: 3608 epb_string = "balanced"; 3609 break; 3610 case ENERGY_PERF_BIAS_POWERSAVE: 3611 epb_string = "powersave"; 3612 break; 3613 default: 3614 epb_string = "custom"; 3615 break; 3616 } 3617 fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string); 3618 3619 return 0; 3620 } 3621 /* 3622 * print_hwp() 3623 * Decode the MSR_HWP_CAPABILITIES 3624 */ 3625 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3626 { 3627 unsigned long long msr; 3628 int cpu; 3629 3630 if (!has_hwp) 3631 return 0; 3632 3633 cpu = t->cpu_id; 3634 3635 /* MSR_HWP_CAPABILITIES is per-package */ 3636 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3637 return 0; 3638 3639 if (cpu_migrate(cpu)) { 3640 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3641 return -1; 3642 } 3643 3644 if (get_msr(cpu, MSR_PM_ENABLE, &msr)) 3645 return 0; 3646 3647 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", 3648 cpu, msr, (msr & (1 << 0)) ? "" : "No-"); 3649 3650 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ 3651 if ((msr & (1 << 0)) == 0) 3652 return 0; 3653 3654 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) 3655 return 0; 3656 3657 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " 3658 "(high %d guar %d eff %d low %d)\n", 3659 cpu, msr, 3660 (unsigned int)HWP_HIGHEST_PERF(msr), 3661 (unsigned int)HWP_GUARANTEED_PERF(msr), 3662 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), 3663 (unsigned int)HWP_LOWEST_PERF(msr)); 3664 3665 if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) 3666 return 0; 3667 3668 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " 3669 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n", 3670 cpu, msr, 3671 (unsigned int)(((msr) >> 0) & 0xff), 3672 (unsigned int)(((msr) >> 8) & 0xff), 3673 (unsigned int)(((msr) >> 16) & 0xff), 3674 (unsigned int)(((msr) >> 24) & 0xff), 3675 (unsigned int)(((msr) >> 32) & 0xff3), 3676 (unsigned int)(((msr) >> 42) & 0x1)); 3677 3678 if (has_hwp_pkg) { 3679 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) 3680 return 0; 3681 3682 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " 3683 "(min %d max %d des %d epp 0x%x window 0x%x)\n", 3684 cpu, msr, 3685 (unsigned int)(((msr) >> 0) & 0xff), 3686 (unsigned int)(((msr) >> 8) & 0xff), 3687 (unsigned int)(((msr) >> 16) & 0xff), 3688 (unsigned int)(((msr) >> 24) & 0xff), 3689 (unsigned int)(((msr) >> 32) & 0xff3)); 3690 } 3691 if (has_hwp_notify) { 3692 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) 3693 return 0; 3694 3695 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " 3696 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", 3697 cpu, msr, 3698 ((msr) & 0x1) ? "EN" : "Dis", 3699 ((msr) & 0x2) ? "EN" : "Dis"); 3700 } 3701 if (get_msr(cpu, MSR_HWP_STATUS, &msr)) 3702 return 0; 3703 3704 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " 3705 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", 3706 cpu, msr, 3707 ((msr) & 0x1) ? "" : "No-", 3708 ((msr) & 0x2) ? "" : "No-"); 3709 3710 return 0; 3711 } 3712 3713 /* 3714 * print_perf_limit() 3715 */ 3716 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3717 { 3718 unsigned long long msr; 3719 int cpu; 3720 3721 cpu = t->cpu_id; 3722 3723 /* per-package */ 3724 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3725 return 0; 3726 3727 if (cpu_migrate(cpu)) { 3728 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3729 return -1; 3730 } 3731 3732 if (do_core_perf_limit_reasons) { 3733 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); 3734 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 3735 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", 3736 (msr & 1 << 15) ? "bit15, " : "", 3737 (msr & 1 << 14) ? "bit14, " : "", 3738 (msr & 1 << 13) ? "Transitions, " : "", 3739 (msr & 1 << 12) ? "MultiCoreTurbo, " : "", 3740 (msr & 1 << 11) ? "PkgPwrL2, " : "", 3741 (msr & 1 << 10) ? "PkgPwrL1, " : "", 3742 (msr & 1 << 9) ? "CorePwr, " : "", 3743 (msr & 1 << 8) ? "Amps, " : "", 3744 (msr & 1 << 6) ? "VR-Therm, " : "", 3745 (msr & 1 << 5) ? "Auto-HWP, " : "", 3746 (msr & 1 << 4) ? "Graphics, " : "", 3747 (msr & 1 << 2) ? "bit2, " : "", 3748 (msr & 1 << 1) ? "ThermStatus, " : "", 3749 (msr & 1 << 0) ? "PROCHOT, " : ""); 3750 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 3751 (msr & 1 << 31) ? "bit31, " : "", 3752 (msr & 1 << 30) ? "bit30, " : "", 3753 (msr & 1 << 29) ? "Transitions, " : "", 3754 (msr & 1 << 28) ? "MultiCoreTurbo, " : "", 3755 (msr & 1 << 27) ? "PkgPwrL2, " : "", 3756 (msr & 1 << 26) ? "PkgPwrL1, " : "", 3757 (msr & 1 << 25) ? "CorePwr, " : "", 3758 (msr & 1 << 24) ? "Amps, " : "", 3759 (msr & 1 << 22) ? "VR-Therm, " : "", 3760 (msr & 1 << 21) ? "Auto-HWP, " : "", 3761 (msr & 1 << 20) ? "Graphics, " : "", 3762 (msr & 1 << 18) ? "bit18, " : "", 3763 (msr & 1 << 17) ? "ThermStatus, " : "", 3764 (msr & 1 << 16) ? "PROCHOT, " : ""); 3765 3766 } 3767 if (do_gfx_perf_limit_reasons) { 3768 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); 3769 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 3770 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", 3771 (msr & 1 << 0) ? "PROCHOT, " : "", 3772 (msr & 1 << 1) ? "ThermStatus, " : "", 3773 (msr & 1 << 4) ? "Graphics, " : "", 3774 (msr & 1 << 6) ? "VR-Therm, " : "", 3775 (msr & 1 << 8) ? "Amps, " : "", 3776 (msr & 1 << 9) ? "GFXPwr, " : "", 3777 (msr & 1 << 10) ? "PkgPwrL1, " : "", 3778 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 3779 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", 3780 (msr & 1 << 16) ? "PROCHOT, " : "", 3781 (msr & 1 << 17) ? "ThermStatus, " : "", 3782 (msr & 1 << 20) ? "Graphics, " : "", 3783 (msr & 1 << 22) ? "VR-Therm, " : "", 3784 (msr & 1 << 24) ? "Amps, " : "", 3785 (msr & 1 << 25) ? "GFXPwr, " : "", 3786 (msr & 1 << 26) ? "PkgPwrL1, " : "", 3787 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 3788 } 3789 if (do_ring_perf_limit_reasons) { 3790 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); 3791 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 3792 fprintf(outf, " (Active: %s%s%s%s%s%s)", 3793 (msr & 1 << 0) ? "PROCHOT, " : "", 3794 (msr & 1 << 1) ? "ThermStatus, " : "", 3795 (msr & 1 << 6) ? "VR-Therm, " : "", 3796 (msr & 1 << 8) ? "Amps, " : "", 3797 (msr & 1 << 10) ? "PkgPwrL1, " : "", 3798 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 3799 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", 3800 (msr & 1 << 16) ? "PROCHOT, " : "", 3801 (msr & 1 << 17) ? "ThermStatus, " : "", 3802 (msr & 1 << 22) ? "VR-Therm, " : "", 3803 (msr & 1 << 24) ? "Amps, " : "", 3804 (msr & 1 << 26) ? "PkgPwrL1, " : "", 3805 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 3806 } 3807 return 0; 3808 } 3809 3810 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ 3811 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ 3812 3813 double get_tdp_intel(unsigned int model) 3814 { 3815 unsigned long long msr; 3816 3817 if (do_rapl & RAPL_PKG_POWER_INFO) 3818 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) 3819 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; 3820 3821 switch (model) { 3822 case INTEL_FAM6_ATOM_SILVERMONT: 3823 case INTEL_FAM6_ATOM_SILVERMONT_X: 3824 return 30.0; 3825 default: 3826 return 135.0; 3827 } 3828 } 3829 3830 double get_tdp_amd(unsigned int family) 3831 { 3832 switch (family) { 3833 case 0x17: 3834 default: 3835 /* This is the max stock TDP of HEDT/Server Fam17h chips */ 3836 return 250.0; 3837 } 3838 } 3839 3840 /* 3841 * rapl_dram_energy_units_probe() 3842 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR. 3843 */ 3844 static double 3845 rapl_dram_energy_units_probe(int model, double rapl_energy_units) 3846 { 3847 /* only called for genuine_intel, family 6 */ 3848 3849 switch (model) { 3850 case INTEL_FAM6_HASWELL_X: /* HSX */ 3851 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3852 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 3853 return (rapl_dram_energy_units = 15.3 / 1000000); 3854 default: 3855 return (rapl_energy_units); 3856 } 3857 } 3858 3859 void rapl_probe_intel(unsigned int family, unsigned int model) 3860 { 3861 unsigned long long msr; 3862 unsigned int time_unit; 3863 double tdp; 3864 3865 if (family != 6) 3866 return; 3867 3868 switch (model) { 3869 case INTEL_FAM6_SANDYBRIDGE: 3870 case INTEL_FAM6_IVYBRIDGE: 3871 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3872 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3873 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3874 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3875 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3876 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; 3877 if (rapl_joules) { 3878 BIC_PRESENT(BIC_Pkg_J); 3879 BIC_PRESENT(BIC_Cor_J); 3880 BIC_PRESENT(BIC_GFX_J); 3881 } else { 3882 BIC_PRESENT(BIC_PkgWatt); 3883 BIC_PRESENT(BIC_CorWatt); 3884 BIC_PRESENT(BIC_GFXWatt); 3885 } 3886 break; 3887 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3888 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 3889 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; 3890 if (rapl_joules) 3891 BIC_PRESENT(BIC_Pkg_J); 3892 else 3893 BIC_PRESENT(BIC_PkgWatt); 3894 break; 3895 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3896 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 3897 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_GFX | RAPL_PKG_POWER_INFO; 3898 BIC_PRESENT(BIC_PKG__); 3899 BIC_PRESENT(BIC_RAM__); 3900 if (rapl_joules) { 3901 BIC_PRESENT(BIC_Pkg_J); 3902 BIC_PRESENT(BIC_Cor_J); 3903 BIC_PRESENT(BIC_RAM_J); 3904 BIC_PRESENT(BIC_GFX_J); 3905 } else { 3906 BIC_PRESENT(BIC_PkgWatt); 3907 BIC_PRESENT(BIC_CorWatt); 3908 BIC_PRESENT(BIC_RAMWatt); 3909 BIC_PRESENT(BIC_GFXWatt); 3910 } 3911 break; 3912 case INTEL_FAM6_HASWELL_X: /* HSX */ 3913 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3914 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3915 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 3916 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 3917 BIC_PRESENT(BIC_PKG__); 3918 BIC_PRESENT(BIC_RAM__); 3919 if (rapl_joules) { 3920 BIC_PRESENT(BIC_Pkg_J); 3921 BIC_PRESENT(BIC_RAM_J); 3922 } else { 3923 BIC_PRESENT(BIC_PkgWatt); 3924 BIC_PRESENT(BIC_RAMWatt); 3925 } 3926 break; 3927 case INTEL_FAM6_SANDYBRIDGE_X: 3928 case INTEL_FAM6_IVYBRIDGE_X: 3929 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; 3930 BIC_PRESENT(BIC_PKG__); 3931 BIC_PRESENT(BIC_RAM__); 3932 if (rapl_joules) { 3933 BIC_PRESENT(BIC_Pkg_J); 3934 BIC_PRESENT(BIC_Cor_J); 3935 BIC_PRESENT(BIC_RAM_J); 3936 } else { 3937 BIC_PRESENT(BIC_PkgWatt); 3938 BIC_PRESENT(BIC_CorWatt); 3939 BIC_PRESENT(BIC_RAMWatt); 3940 } 3941 break; 3942 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 3943 case INTEL_FAM6_ATOM_SILVERMONT_X: /* AVN */ 3944 do_rapl = RAPL_PKG | RAPL_CORES; 3945 if (rapl_joules) { 3946 BIC_PRESENT(BIC_Pkg_J); 3947 BIC_PRESENT(BIC_Cor_J); 3948 } else { 3949 BIC_PRESENT(BIC_PkgWatt); 3950 BIC_PRESENT(BIC_CorWatt); 3951 } 3952 break; 3953 case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */ 3954 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS; 3955 BIC_PRESENT(BIC_PKG__); 3956 BIC_PRESENT(BIC_RAM__); 3957 if (rapl_joules) { 3958 BIC_PRESENT(BIC_Pkg_J); 3959 BIC_PRESENT(BIC_Cor_J); 3960 BIC_PRESENT(BIC_RAM_J); 3961 } else { 3962 BIC_PRESENT(BIC_PkgWatt); 3963 BIC_PRESENT(BIC_CorWatt); 3964 BIC_PRESENT(BIC_RAMWatt); 3965 } 3966 break; 3967 default: 3968 return; 3969 } 3970 3971 /* units on package 0, verify later other packages match */ 3972 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) 3973 return; 3974 3975 rapl_power_units = 1.0 / (1 << (msr & 0xF)); 3976 if (model == INTEL_FAM6_ATOM_SILVERMONT) 3977 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; 3978 else 3979 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 3980 3981 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units); 3982 3983 time_unit = msr >> 16 & 0xF; 3984 if (time_unit == 0) 3985 time_unit = 0xA; 3986 3987 rapl_time_units = 1.0 / (1 << (time_unit)); 3988 3989 tdp = get_tdp_intel(model); 3990 3991 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 3992 if (!quiet) 3993 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 3994 } 3995 3996 void rapl_probe_amd(unsigned int family, unsigned int model) 3997 { 3998 unsigned long long msr; 3999 unsigned int eax, ebx, ecx, edx; 4000 unsigned int has_rapl = 0; 4001 double tdp; 4002 4003 if (max_extended_level >= 0x80000007) { 4004 __cpuid(0x80000007, eax, ebx, ecx, edx); 4005 /* RAPL (Fam 17h) */ 4006 has_rapl = edx & (1 << 14); 4007 } 4008 4009 if (!has_rapl) 4010 return; 4011 4012 switch (family) { 4013 case 0x17: /* Zen, Zen+ */ 4014 do_rapl = RAPL_AMD_F17H | RAPL_PER_CORE_ENERGY; 4015 if (rapl_joules) { 4016 BIC_PRESENT(BIC_Pkg_J); 4017 BIC_PRESENT(BIC_Cor_J); 4018 } else { 4019 BIC_PRESENT(BIC_PkgWatt); 4020 BIC_PRESENT(BIC_CorWatt); 4021 } 4022 break; 4023 default: 4024 return; 4025 } 4026 4027 if (get_msr(base_cpu, MSR_RAPL_PWR_UNIT, &msr)) 4028 return; 4029 4030 rapl_time_units = ldexp(1.0, -(msr >> 16 & 0xf)); 4031 rapl_energy_units = ldexp(1.0, -(msr >> 8 & 0x1f)); 4032 rapl_power_units = ldexp(1.0, -(msr & 0xf)); 4033 4034 tdp = get_tdp_amd(family); 4035 4036 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 4037 if (!quiet) 4038 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 4039 } 4040 4041 /* 4042 * rapl_probe() 4043 * 4044 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units 4045 */ 4046 void rapl_probe(unsigned int family, unsigned int model) 4047 { 4048 if (genuine_intel) 4049 rapl_probe_intel(family, model); 4050 if (authentic_amd) 4051 rapl_probe_amd(family, model); 4052 } 4053 4054 void perf_limit_reasons_probe(unsigned int family, unsigned int model) 4055 { 4056 if (!genuine_intel) 4057 return; 4058 4059 if (family != 6) 4060 return; 4061 4062 switch (model) { 4063 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 4064 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 4065 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 4066 do_gfx_perf_limit_reasons = 1; 4067 case INTEL_FAM6_HASWELL_X: /* HSX */ 4068 do_core_perf_limit_reasons = 1; 4069 do_ring_perf_limit_reasons = 1; 4070 default: 4071 return; 4072 } 4073 } 4074 4075 void automatic_cstate_conversion_probe(unsigned int family, unsigned int model) 4076 { 4077 if (is_skx(family, model) || is_bdx(family, model)) 4078 has_automatic_cstate_conversion = 1; 4079 } 4080 4081 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4082 { 4083 unsigned long long msr; 4084 unsigned int dts, dts2; 4085 int cpu; 4086 4087 if (!(do_dts || do_ptm)) 4088 return 0; 4089 4090 cpu = t->cpu_id; 4091 4092 /* DTS is per-core, no need to print for each thread */ 4093 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 4094 return 0; 4095 4096 if (cpu_migrate(cpu)) { 4097 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 4098 return -1; 4099 } 4100 4101 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { 4102 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 4103 return 0; 4104 4105 dts = (msr >> 16) & 0x7F; 4106 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", 4107 cpu, msr, tcc_activation_temp - dts); 4108 4109 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) 4110 return 0; 4111 4112 dts = (msr >> 16) & 0x7F; 4113 dts2 = (msr >> 8) & 0x7F; 4114 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 4115 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 4116 } 4117 4118 4119 if (do_dts && debug) { 4120 unsigned int resolution; 4121 4122 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 4123 return 0; 4124 4125 dts = (msr >> 16) & 0x7F; 4126 resolution = (msr >> 27) & 0xF; 4127 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", 4128 cpu, msr, tcc_activation_temp - dts, resolution); 4129 4130 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) 4131 return 0; 4132 4133 dts = (msr >> 16) & 0x7F; 4134 dts2 = (msr >> 8) & 0x7F; 4135 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 4136 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 4137 } 4138 4139 return 0; 4140 } 4141 4142 void print_power_limit_msr(int cpu, unsigned long long msr, char *label) 4143 { 4144 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n", 4145 cpu, label, 4146 ((msr >> 15) & 1) ? "EN" : "DIS", 4147 ((msr >> 0) & 0x7FFF) * rapl_power_units, 4148 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, 4149 (((msr >> 16) & 1) ? "EN" : "DIS")); 4150 4151 return; 4152 } 4153 4154 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4155 { 4156 unsigned long long msr; 4157 const char *msr_name; 4158 int cpu; 4159 4160 if (!do_rapl) 4161 return 0; 4162 4163 /* RAPL counters are per package, so print only for 1st thread/package */ 4164 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4165 return 0; 4166 4167 cpu = t->cpu_id; 4168 if (cpu_migrate(cpu)) { 4169 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 4170 return -1; 4171 } 4172 4173 if (do_rapl & RAPL_AMD_F17H) { 4174 msr_name = "MSR_RAPL_PWR_UNIT"; 4175 if (get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr)) 4176 return -1; 4177 } else { 4178 msr_name = "MSR_RAPL_POWER_UNIT"; 4179 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) 4180 return -1; 4181 } 4182 4183 fprintf(outf, "cpu%d: %s: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr_name, msr, 4184 rapl_power_units, rapl_energy_units, rapl_time_units); 4185 4186 if (do_rapl & RAPL_PKG_POWER_INFO) { 4187 4188 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) 4189 return -5; 4190 4191 4192 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4193 cpu, msr, 4194 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4195 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4196 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4197 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4198 4199 } 4200 if (do_rapl & RAPL_PKG) { 4201 4202 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) 4203 return -9; 4204 4205 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", 4206 cpu, msr, (msr >> 63) & 1 ? "" : "UN"); 4207 4208 print_power_limit_msr(cpu, msr, "PKG Limit #1"); 4209 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n", 4210 cpu, 4211 ((msr >> 47) & 1) ? "EN" : "DIS", 4212 ((msr >> 32) & 0x7FFF) * rapl_power_units, 4213 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, 4214 ((msr >> 48) & 1) ? "EN" : "DIS"); 4215 } 4216 4217 if (do_rapl & RAPL_DRAM_POWER_INFO) { 4218 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) 4219 return -6; 4220 4221 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4222 cpu, msr, 4223 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4224 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4225 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4226 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4227 } 4228 if (do_rapl & RAPL_DRAM) { 4229 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) 4230 return -9; 4231 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", 4232 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4233 4234 print_power_limit_msr(cpu, msr, "DRAM Limit"); 4235 } 4236 if (do_rapl & RAPL_CORE_POLICY) { 4237 if (get_msr(cpu, MSR_PP0_POLICY, &msr)) 4238 return -7; 4239 4240 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); 4241 } 4242 if (do_rapl & RAPL_CORES_POWER_LIMIT) { 4243 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) 4244 return -9; 4245 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", 4246 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4247 print_power_limit_msr(cpu, msr, "Cores Limit"); 4248 } 4249 if (do_rapl & RAPL_GFX) { 4250 if (get_msr(cpu, MSR_PP1_POLICY, &msr)) 4251 return -8; 4252 4253 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); 4254 4255 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) 4256 return -9; 4257 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", 4258 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4259 print_power_limit_msr(cpu, msr, "GFX Limit"); 4260 } 4261 return 0; 4262 } 4263 4264 /* 4265 * SNB adds support for additional MSRs: 4266 * 4267 * MSR_PKG_C7_RESIDENCY 0x000003fa 4268 * MSR_CORE_C7_RESIDENCY 0x000003fe 4269 * MSR_PKG_C2_RESIDENCY 0x0000060d 4270 */ 4271 4272 int has_snb_msrs(unsigned int family, unsigned int model) 4273 { 4274 if (!genuine_intel) 4275 return 0; 4276 4277 switch (model) { 4278 case INTEL_FAM6_SANDYBRIDGE: 4279 case INTEL_FAM6_SANDYBRIDGE_X: 4280 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 4281 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 4282 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 4283 case INTEL_FAM6_HASWELL_X: /* HSW */ 4284 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 4285 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 4286 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 4287 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 4288 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4289 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4290 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 4291 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4292 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4293 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4294 case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */ 4295 return 1; 4296 } 4297 return 0; 4298 } 4299 4300 /* 4301 * HSW ULT added support for C8/C9/C10 MSRs: 4302 * 4303 * MSR_PKG_C8_RESIDENCY 0x00000630 4304 * MSR_PKG_C9_RESIDENCY 0x00000631 4305 * MSR_PKG_C10_RESIDENCY 0x00000632 4306 * 4307 * MSR_PKGC8_IRTL 0x00000633 4308 * MSR_PKGC9_IRTL 0x00000634 4309 * MSR_PKGC10_IRTL 0x00000635 4310 * 4311 */ 4312 int has_c8910_msrs(unsigned int family, unsigned int model) 4313 { 4314 if (!genuine_intel) 4315 return 0; 4316 4317 switch (model) { 4318 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 4319 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 4320 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4321 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 4322 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4323 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4324 return 1; 4325 } 4326 return 0; 4327 } 4328 4329 /* 4330 * SKL adds support for additional MSRS: 4331 * 4332 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 4333 * MSR_PKG_ANY_CORE_C0_RES 0x00000659 4334 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 4335 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 4336 */ 4337 int has_skl_msrs(unsigned int family, unsigned int model) 4338 { 4339 if (!genuine_intel) 4340 return 0; 4341 4342 switch (model) { 4343 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4344 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 4345 return 1; 4346 } 4347 return 0; 4348 } 4349 4350 int is_slm(unsigned int family, unsigned int model) 4351 { 4352 if (!genuine_intel) 4353 return 0; 4354 switch (model) { 4355 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 4356 case INTEL_FAM6_ATOM_SILVERMONT_X: /* AVN */ 4357 return 1; 4358 } 4359 return 0; 4360 } 4361 4362 int is_knl(unsigned int family, unsigned int model) 4363 { 4364 if (!genuine_intel) 4365 return 0; 4366 switch (model) { 4367 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4368 return 1; 4369 } 4370 return 0; 4371 } 4372 4373 int is_cnl(unsigned int family, unsigned int model) 4374 { 4375 if (!genuine_intel) 4376 return 0; 4377 4378 switch (model) { 4379 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 4380 return 1; 4381 } 4382 4383 return 0; 4384 } 4385 4386 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model) 4387 { 4388 if (is_knl(family, model)) 4389 return 1024; 4390 return 1; 4391 } 4392 4393 #define SLM_BCLK_FREQS 5 4394 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0}; 4395 4396 double slm_bclk(void) 4397 { 4398 unsigned long long msr = 3; 4399 unsigned int i; 4400 double freq; 4401 4402 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) 4403 fprintf(outf, "SLM BCLK: unknown\n"); 4404 4405 i = msr & 0xf; 4406 if (i >= SLM_BCLK_FREQS) { 4407 fprintf(outf, "SLM BCLK[%d] invalid\n", i); 4408 i = 3; 4409 } 4410 freq = slm_freq_table[i]; 4411 4412 if (!quiet) 4413 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); 4414 4415 return freq; 4416 } 4417 4418 double discover_bclk(unsigned int family, unsigned int model) 4419 { 4420 if (has_snb_msrs(family, model) || is_knl(family, model)) 4421 return 100.00; 4422 else if (is_slm(family, model)) 4423 return slm_bclk(); 4424 else 4425 return 133.33; 4426 } 4427 4428 /* 4429 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where 4430 * the Thermal Control Circuit (TCC) activates. 4431 * This is usually equal to tjMax. 4432 * 4433 * Older processors do not have this MSR, so there we guess, 4434 * but also allow cmdline over-ride with -T. 4435 * 4436 * Several MSR temperature values are in units of degrees-C 4437 * below this value, including the Digital Thermal Sensor (DTS), 4438 * Package Thermal Management Sensor (PTM), and thermal event thresholds. 4439 */ 4440 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4441 { 4442 unsigned long long msr; 4443 unsigned int target_c_local; 4444 int cpu; 4445 4446 /* tcc_activation_temp is used only for dts or ptm */ 4447 if (!(do_dts || do_ptm)) 4448 return 0; 4449 4450 /* this is a per-package concept */ 4451 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4452 return 0; 4453 4454 cpu = t->cpu_id; 4455 if (cpu_migrate(cpu)) { 4456 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 4457 return -1; 4458 } 4459 4460 if (tcc_activation_temp_override != 0) { 4461 tcc_activation_temp = tcc_activation_temp_override; 4462 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", 4463 cpu, tcc_activation_temp); 4464 return 0; 4465 } 4466 4467 /* Temperature Target MSR is Nehalem and newer only */ 4468 if (!do_nhm_platform_info) 4469 goto guess; 4470 4471 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) 4472 goto guess; 4473 4474 target_c_local = (msr >> 16) & 0xFF; 4475 4476 if (!quiet) 4477 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", 4478 cpu, msr, target_c_local); 4479 4480 if (!target_c_local) 4481 goto guess; 4482 4483 tcc_activation_temp = target_c_local; 4484 4485 return 0; 4486 4487 guess: 4488 tcc_activation_temp = TJMAX_DEFAULT; 4489 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", 4490 cpu, tcc_activation_temp); 4491 4492 return 0; 4493 } 4494 4495 void decode_feature_control_msr(void) 4496 { 4497 unsigned long long msr; 4498 4499 if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr)) 4500 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", 4501 base_cpu, msr, 4502 msr & FEATURE_CONTROL_LOCKED ? "" : "UN-", 4503 msr & (1 << 18) ? "SGX" : ""); 4504 } 4505 4506 void decode_misc_enable_msr(void) 4507 { 4508 unsigned long long msr; 4509 4510 if (!genuine_intel) 4511 return; 4512 4513 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) 4514 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n", 4515 base_cpu, msr, 4516 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-", 4517 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-", 4518 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-", 4519 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "", 4520 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : ""); 4521 } 4522 4523 void decode_misc_feature_control(void) 4524 { 4525 unsigned long long msr; 4526 4527 if (!has_misc_feature_control) 4528 return; 4529 4530 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr)) 4531 fprintf(outf, "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n", 4532 base_cpu, msr, 4533 msr & (0 << 0) ? "No-" : "", 4534 msr & (1 << 0) ? "No-" : "", 4535 msr & (2 << 0) ? "No-" : "", 4536 msr & (3 << 0) ? "No-" : ""); 4537 } 4538 /* 4539 * Decode MSR_MISC_PWR_MGMT 4540 * 4541 * Decode the bits according to the Nehalem documentation 4542 * bit[0] seems to continue to have same meaning going forward 4543 * bit[1] less so... 4544 */ 4545 void decode_misc_pwr_mgmt_msr(void) 4546 { 4547 unsigned long long msr; 4548 4549 if (!do_nhm_platform_info) 4550 return; 4551 4552 if (no_MSR_MISC_PWR_MGMT) 4553 return; 4554 4555 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) 4556 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n", 4557 base_cpu, msr, 4558 msr & (1 << 0) ? "DIS" : "EN", 4559 msr & (1 << 1) ? "EN" : "DIS", 4560 msr & (1 << 8) ? "EN" : "DIS"); 4561 } 4562 /* 4563 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG 4564 * 4565 * This MSRs are present on Silvermont processors, 4566 * Intel Atom processor E3000 series (Baytrail), and friends. 4567 */ 4568 void decode_c6_demotion_policy_msr(void) 4569 { 4570 unsigned long long msr; 4571 4572 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr)) 4573 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n", 4574 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 4575 4576 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr)) 4577 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n", 4578 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 4579 } 4580 4581 /* 4582 * When models are the same, for the purpose of turbostat, reuse 4583 */ 4584 unsigned int intel_model_duplicates(unsigned int model) 4585 { 4586 4587 switch(model) { 4588 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ 4589 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 4590 case 0x1F: /* Core i7 and i5 Processor - Nehalem */ 4591 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */ 4592 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */ 4593 return INTEL_FAM6_NEHALEM; 4594 4595 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 4596 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 4597 return INTEL_FAM6_NEHALEM_EX; 4598 4599 case INTEL_FAM6_XEON_PHI_KNM: 4600 return INTEL_FAM6_XEON_PHI_KNL; 4601 4602 case INTEL_FAM6_BROADWELL_X: 4603 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 4604 return INTEL_FAM6_BROADWELL_X; 4605 4606 case INTEL_FAM6_SKYLAKE_MOBILE: 4607 case INTEL_FAM6_SKYLAKE_DESKTOP: 4608 case INTEL_FAM6_KABYLAKE_MOBILE: 4609 case INTEL_FAM6_KABYLAKE_DESKTOP: 4610 return INTEL_FAM6_SKYLAKE_MOBILE; 4611 4612 case INTEL_FAM6_ICELAKE_MOBILE: 4613 case INTEL_FAM6_ICELAKE_NNPI: 4614 return INTEL_FAM6_CANNONLAKE_MOBILE; 4615 4616 case INTEL_FAM6_ATOM_TREMONT_X: 4617 return INTEL_FAM6_ATOM_GOLDMONT_X; 4618 } 4619 return model; 4620 } 4621 void process_cpuid() 4622 { 4623 unsigned int eax, ebx, ecx, edx; 4624 unsigned int fms, family, model, stepping, ecx_flags, edx_flags; 4625 unsigned int has_turbo; 4626 4627 eax = ebx = ecx = edx = 0; 4628 4629 __cpuid(0, max_level, ebx, ecx, edx); 4630 4631 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69) 4632 genuine_intel = 1; 4633 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) 4634 authentic_amd = 1; 4635 4636 if (!quiet) 4637 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ", 4638 (char *)&ebx, (char *)&edx, (char *)&ecx); 4639 4640 __cpuid(1, fms, ebx, ecx, edx); 4641 family = (fms >> 8) & 0xf; 4642 model = (fms >> 4) & 0xf; 4643 stepping = fms & 0xf; 4644 if (family == 0xf) 4645 family += (fms >> 20) & 0xff; 4646 if (family >= 6) 4647 model += ((fms >> 16) & 0xf) << 4; 4648 ecx_flags = ecx; 4649 edx_flags = edx; 4650 4651 /* 4652 * check max extended function levels of CPUID. 4653 * This is needed to check for invariant TSC. 4654 * This check is valid for both Intel and AMD. 4655 */ 4656 ebx = ecx = edx = 0; 4657 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); 4658 4659 if (!quiet) { 4660 fprintf(outf, "0x%x CPUID levels; 0x%x xlevels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n", 4661 max_level, max_extended_level, family, model, stepping, family, model, stepping); 4662 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n", 4663 ecx_flags & (1 << 0) ? "SSE3" : "-", 4664 ecx_flags & (1 << 3) ? "MONITOR" : "-", 4665 ecx_flags & (1 << 6) ? "SMX" : "-", 4666 ecx_flags & (1 << 7) ? "EIST" : "-", 4667 ecx_flags & (1 << 8) ? "TM2" : "-", 4668 edx_flags & (1 << 4) ? "TSC" : "-", 4669 edx_flags & (1 << 5) ? "MSR" : "-", 4670 edx_flags & (1 << 22) ? "ACPI-TM" : "-", 4671 edx_flags & (1 << 28) ? "HT" : "-", 4672 edx_flags & (1 << 29) ? "TM" : "-"); 4673 } 4674 if (genuine_intel) 4675 model = intel_model_duplicates(model); 4676 4677 if (!(edx_flags & (1 << 5))) 4678 errx(1, "CPUID: no MSR"); 4679 4680 if (max_extended_level >= 0x80000007) { 4681 4682 /* 4683 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 4684 * this check is valid for both Intel and AMD 4685 */ 4686 __cpuid(0x80000007, eax, ebx, ecx, edx); 4687 has_invariant_tsc = edx & (1 << 8); 4688 } 4689 4690 /* 4691 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 4692 * this check is valid for both Intel and AMD 4693 */ 4694 4695 __cpuid(0x6, eax, ebx, ecx, edx); 4696 has_aperf = ecx & (1 << 0); 4697 if (has_aperf) { 4698 BIC_PRESENT(BIC_Avg_MHz); 4699 BIC_PRESENT(BIC_Busy); 4700 BIC_PRESENT(BIC_Bzy_MHz); 4701 } 4702 do_dts = eax & (1 << 0); 4703 if (do_dts) 4704 BIC_PRESENT(BIC_CoreTmp); 4705 has_turbo = eax & (1 << 1); 4706 do_ptm = eax & (1 << 6); 4707 if (do_ptm) 4708 BIC_PRESENT(BIC_PkgTmp); 4709 has_hwp = eax & (1 << 7); 4710 has_hwp_notify = eax & (1 << 8); 4711 has_hwp_activity_window = eax & (1 << 9); 4712 has_hwp_epp = eax & (1 << 10); 4713 has_hwp_pkg = eax & (1 << 11); 4714 has_epb = ecx & (1 << 3); 4715 4716 if (!quiet) 4717 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, " 4718 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", 4719 has_aperf ? "" : "No-", 4720 has_turbo ? "" : "No-", 4721 do_dts ? "" : "No-", 4722 do_ptm ? "" : "No-", 4723 has_hwp ? "" : "No-", 4724 has_hwp_notify ? "" : "No-", 4725 has_hwp_activity_window ? "" : "No-", 4726 has_hwp_epp ? "" : "No-", 4727 has_hwp_pkg ? "" : "No-", 4728 has_epb ? "" : "No-"); 4729 4730 if (!quiet) 4731 decode_misc_enable_msr(); 4732 4733 4734 if (max_level >= 0x7 && !quiet) { 4735 int has_sgx; 4736 4737 ecx = 0; 4738 4739 __cpuid_count(0x7, 0, eax, ebx, ecx, edx); 4740 4741 has_sgx = ebx & (1 << 2); 4742 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-"); 4743 4744 if (has_sgx) 4745 decode_feature_control_msr(); 4746 } 4747 4748 if (max_level >= 0x15) { 4749 unsigned int eax_crystal; 4750 unsigned int ebx_tsc; 4751 4752 /* 4753 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz 4754 */ 4755 eax_crystal = ebx_tsc = crystal_hz = edx = 0; 4756 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); 4757 4758 if (ebx_tsc != 0) { 4759 4760 if (!quiet && (ebx != 0)) 4761 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", 4762 eax_crystal, ebx_tsc, crystal_hz); 4763 4764 if (crystal_hz == 0) 4765 switch(model) { 4766 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4767 crystal_hz = 24000000; /* 24.0 MHz */ 4768 break; 4769 case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */ 4770 crystal_hz = 25000000; /* 25.0 MHz */ 4771 break; 4772 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4773 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4774 crystal_hz = 19200000; /* 19.2 MHz */ 4775 break; 4776 default: 4777 crystal_hz = 0; 4778 } 4779 4780 if (crystal_hz) { 4781 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal; 4782 if (!quiet) 4783 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", 4784 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); 4785 } 4786 } 4787 } 4788 if (max_level >= 0x16) { 4789 unsigned int base_mhz, max_mhz, bus_mhz, edx; 4790 4791 /* 4792 * CPUID 16H Base MHz, Max MHz, Bus MHz 4793 */ 4794 base_mhz = max_mhz = bus_mhz = edx = 0; 4795 4796 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); 4797 if (!quiet) 4798 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", 4799 base_mhz, max_mhz, bus_mhz); 4800 } 4801 4802 if (has_aperf) 4803 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model); 4804 4805 BIC_PRESENT(BIC_IRQ); 4806 BIC_PRESENT(BIC_TSC_MHz); 4807 4808 if (probe_nhm_msrs(family, model)) { 4809 do_nhm_platform_info = 1; 4810 BIC_PRESENT(BIC_CPU_c1); 4811 BIC_PRESENT(BIC_CPU_c3); 4812 BIC_PRESENT(BIC_CPU_c6); 4813 BIC_PRESENT(BIC_SMI); 4814 } 4815 do_snb_cstates = has_snb_msrs(family, model); 4816 4817 if (do_snb_cstates) 4818 BIC_PRESENT(BIC_CPU_c7); 4819 4820 do_irtl_snb = has_snb_msrs(family, model); 4821 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2)) 4822 BIC_PRESENT(BIC_Pkgpc2); 4823 if (pkg_cstate_limit >= PCL__3) 4824 BIC_PRESENT(BIC_Pkgpc3); 4825 if (pkg_cstate_limit >= PCL__6) 4826 BIC_PRESENT(BIC_Pkgpc6); 4827 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7)) 4828 BIC_PRESENT(BIC_Pkgpc7); 4829 if (has_slv_msrs(family, model)) { 4830 BIC_NOT_PRESENT(BIC_Pkgpc2); 4831 BIC_NOT_PRESENT(BIC_Pkgpc3); 4832 BIC_PRESENT(BIC_Pkgpc6); 4833 BIC_NOT_PRESENT(BIC_Pkgpc7); 4834 BIC_PRESENT(BIC_Mod_c6); 4835 use_c1_residency_msr = 1; 4836 } 4837 if (is_dnv(family, model)) { 4838 BIC_PRESENT(BIC_CPU_c1); 4839 BIC_NOT_PRESENT(BIC_CPU_c3); 4840 BIC_NOT_PRESENT(BIC_Pkgpc3); 4841 BIC_NOT_PRESENT(BIC_CPU_c7); 4842 BIC_NOT_PRESENT(BIC_Pkgpc7); 4843 use_c1_residency_msr = 1; 4844 } 4845 if (is_skx(family, model)) { 4846 BIC_NOT_PRESENT(BIC_CPU_c3); 4847 BIC_NOT_PRESENT(BIC_Pkgpc3); 4848 BIC_NOT_PRESENT(BIC_CPU_c7); 4849 BIC_NOT_PRESENT(BIC_Pkgpc7); 4850 } 4851 if (is_bdx(family, model)) { 4852 BIC_NOT_PRESENT(BIC_CPU_c7); 4853 BIC_NOT_PRESENT(BIC_Pkgpc7); 4854 } 4855 if (has_c8910_msrs(family, model)) { 4856 BIC_PRESENT(BIC_Pkgpc8); 4857 BIC_PRESENT(BIC_Pkgpc9); 4858 BIC_PRESENT(BIC_Pkgpc10); 4859 } 4860 do_irtl_hsw = has_c8910_msrs(family, model); 4861 if (has_skl_msrs(family, model)) { 4862 BIC_PRESENT(BIC_Totl_c0); 4863 BIC_PRESENT(BIC_Any_c0); 4864 BIC_PRESENT(BIC_GFX_c0); 4865 BIC_PRESENT(BIC_CPUGFX); 4866 } 4867 do_slm_cstates = is_slm(family, model); 4868 do_knl_cstates = is_knl(family, model); 4869 4870 if (do_slm_cstates || do_knl_cstates || is_cnl(family, model)) 4871 BIC_NOT_PRESENT(BIC_CPU_c3); 4872 4873 if (!quiet) 4874 decode_misc_pwr_mgmt_msr(); 4875 4876 if (!quiet && has_slv_msrs(family, model)) 4877 decode_c6_demotion_policy_msr(); 4878 4879 rapl_probe(family, model); 4880 perf_limit_reasons_probe(family, model); 4881 automatic_cstate_conversion_probe(family, model); 4882 4883 if (!quiet) 4884 dump_cstate_pstate_config_info(family, model); 4885 4886 if (!quiet) 4887 dump_sysfs_cstate_config(); 4888 if (!quiet) 4889 dump_sysfs_pstate_config(); 4890 4891 if (has_skl_msrs(family, model)) 4892 calculate_tsc_tweak(); 4893 4894 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK)) 4895 BIC_PRESENT(BIC_GFX_rc6); 4896 4897 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK)) 4898 BIC_PRESENT(BIC_GFXMHz); 4899 4900 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK)) 4901 BIC_PRESENT(BIC_CPU_LPI); 4902 else 4903 BIC_NOT_PRESENT(BIC_CPU_LPI); 4904 4905 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us", R_OK)) 4906 BIC_PRESENT(BIC_SYS_LPI); 4907 else 4908 BIC_NOT_PRESENT(BIC_SYS_LPI); 4909 4910 if (!quiet) 4911 decode_misc_feature_control(); 4912 4913 return; 4914 } 4915 4916 /* 4917 * in /dev/cpu/ return success for names that are numbers 4918 * ie. filter out ".", "..", "microcode". 4919 */ 4920 int dir_filter(const struct dirent *dirp) 4921 { 4922 if (isdigit(dirp->d_name[0])) 4923 return 1; 4924 else 4925 return 0; 4926 } 4927 4928 int open_dev_cpu_msr(int dummy1) 4929 { 4930 return 0; 4931 } 4932 4933 void topology_probe() 4934 { 4935 int i; 4936 int max_core_id = 0; 4937 int max_package_id = 0; 4938 int max_die_id = 0; 4939 int max_siblings = 0; 4940 4941 /* Initialize num_cpus, max_cpu_num */ 4942 set_max_cpu_num(); 4943 topo.num_cpus = 0; 4944 for_all_proc_cpus(count_cpus); 4945 if (!summary_only && topo.num_cpus > 1) 4946 BIC_PRESENT(BIC_CPU); 4947 4948 if (debug > 1) 4949 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); 4950 4951 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); 4952 if (cpus == NULL) 4953 err(1, "calloc cpus"); 4954 4955 /* 4956 * Allocate and initialize cpu_present_set 4957 */ 4958 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); 4959 if (cpu_present_set == NULL) 4960 err(3, "CPU_ALLOC"); 4961 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 4962 CPU_ZERO_S(cpu_present_setsize, cpu_present_set); 4963 for_all_proc_cpus(mark_cpu_present); 4964 4965 /* 4966 * Validate that all cpus in cpu_subset are also in cpu_present_set 4967 */ 4968 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) { 4969 if (CPU_ISSET_S(i, cpu_subset_size, cpu_subset)) 4970 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set)) 4971 err(1, "cpu%d not present", i); 4972 } 4973 4974 /* 4975 * Allocate and initialize cpu_affinity_set 4976 */ 4977 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); 4978 if (cpu_affinity_set == NULL) 4979 err(3, "CPU_ALLOC"); 4980 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 4981 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 4982 4983 for_all_proc_cpus(init_thread_id); 4984 4985 /* 4986 * For online cpus 4987 * find max_core_id, max_package_id 4988 */ 4989 for (i = 0; i <= topo.max_cpu_num; ++i) { 4990 int siblings; 4991 4992 if (cpu_is_not_present(i)) { 4993 if (debug > 1) 4994 fprintf(outf, "cpu%d NOT PRESENT\n", i); 4995 continue; 4996 } 4997 4998 cpus[i].logical_cpu_id = i; 4999 5000 /* get package information */ 5001 cpus[i].physical_package_id = get_physical_package_id(i); 5002 if (cpus[i].physical_package_id > max_package_id) 5003 max_package_id = cpus[i].physical_package_id; 5004 5005 /* get die information */ 5006 cpus[i].die_id = get_die_id(i); 5007 if (cpus[i].die_id > max_die_id) 5008 max_die_id = cpus[i].die_id; 5009 5010 /* get numa node information */ 5011 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]); 5012 if (cpus[i].physical_node_id > topo.max_node_num) 5013 topo.max_node_num = cpus[i].physical_node_id; 5014 5015 /* get core information */ 5016 cpus[i].physical_core_id = get_core_id(i); 5017 if (cpus[i].physical_core_id > max_core_id) 5018 max_core_id = cpus[i].physical_core_id; 5019 5020 /* get thread information */ 5021 siblings = get_thread_siblings(&cpus[i]); 5022 if (siblings > max_siblings) 5023 max_siblings = siblings; 5024 if (cpus[i].thread_id == 0) 5025 topo.num_cores++; 5026 } 5027 5028 topo.cores_per_node = max_core_id + 1; 5029 if (debug > 1) 5030 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", 5031 max_core_id, topo.cores_per_node); 5032 if (!summary_only && topo.cores_per_node > 1) 5033 BIC_PRESENT(BIC_Core); 5034 5035 topo.num_die = max_die_id + 1; 5036 if (debug > 1) 5037 fprintf(outf, "max_die_id %d, sizing for %d die\n", 5038 max_die_id, topo.num_die); 5039 if (!summary_only && topo.num_die > 1) 5040 BIC_PRESENT(BIC_Die); 5041 5042 topo.num_packages = max_package_id + 1; 5043 if (debug > 1) 5044 fprintf(outf, "max_package_id %d, sizing for %d packages\n", 5045 max_package_id, topo.num_packages); 5046 if (!summary_only && topo.num_packages > 1) 5047 BIC_PRESENT(BIC_Package); 5048 5049 set_node_data(); 5050 if (debug > 1) 5051 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg); 5052 if (!summary_only && topo.nodes_per_pkg > 1) 5053 BIC_PRESENT(BIC_Node); 5054 5055 topo.threads_per_core = max_siblings; 5056 if (debug > 1) 5057 fprintf(outf, "max_siblings %d\n", max_siblings); 5058 5059 if (debug < 1) 5060 return; 5061 5062 for (i = 0; i <= topo.max_cpu_num; ++i) { 5063 if (cpu_is_not_present(i)) 5064 continue; 5065 fprintf(outf, 5066 "cpu %d pkg %d die %d node %d lnode %d core %d thread %d\n", 5067 i, cpus[i].physical_package_id, cpus[i].die_id, 5068 cpus[i].physical_node_id, 5069 cpus[i].logical_node_id, 5070 cpus[i].physical_core_id, 5071 cpus[i].thread_id); 5072 } 5073 5074 } 5075 5076 void 5077 allocate_counters(struct thread_data **t, struct core_data **c, 5078 struct pkg_data **p) 5079 { 5080 int i; 5081 int num_cores = topo.cores_per_node * topo.nodes_per_pkg * 5082 topo.num_packages; 5083 int num_threads = topo.threads_per_core * num_cores; 5084 5085 *t = calloc(num_threads, sizeof(struct thread_data)); 5086 if (*t == NULL) 5087 goto error; 5088 5089 for (i = 0; i < num_threads; i++) 5090 (*t)[i].cpu_id = -1; 5091 5092 *c = calloc(num_cores, sizeof(struct core_data)); 5093 if (*c == NULL) 5094 goto error; 5095 5096 for (i = 0; i < num_cores; i++) 5097 (*c)[i].core_id = -1; 5098 5099 *p = calloc(topo.num_packages, sizeof(struct pkg_data)); 5100 if (*p == NULL) 5101 goto error; 5102 5103 for (i = 0; i < topo.num_packages; i++) 5104 (*p)[i].package_id = i; 5105 5106 return; 5107 error: 5108 err(1, "calloc counters"); 5109 } 5110 /* 5111 * init_counter() 5112 * 5113 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE 5114 */ 5115 void init_counter(struct thread_data *thread_base, struct core_data *core_base, 5116 struct pkg_data *pkg_base, int cpu_id) 5117 { 5118 int pkg_id = cpus[cpu_id].physical_package_id; 5119 int node_id = cpus[cpu_id].logical_node_id; 5120 int core_id = cpus[cpu_id].physical_core_id; 5121 int thread_id = cpus[cpu_id].thread_id; 5122 struct thread_data *t; 5123 struct core_data *c; 5124 struct pkg_data *p; 5125 5126 5127 /* Workaround for systems where physical_node_id==-1 5128 * and logical_node_id==(-1 - topo.num_cpus) 5129 */ 5130 if (node_id < 0) 5131 node_id = 0; 5132 5133 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id); 5134 c = GET_CORE(core_base, core_id, node_id, pkg_id); 5135 p = GET_PKG(pkg_base, pkg_id); 5136 5137 t->cpu_id = cpu_id; 5138 if (thread_id == 0) { 5139 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; 5140 if (cpu_is_first_core_in_package(cpu_id)) 5141 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; 5142 } 5143 5144 c->core_id = core_id; 5145 p->package_id = pkg_id; 5146 } 5147 5148 5149 int initialize_counters(int cpu_id) 5150 { 5151 init_counter(EVEN_COUNTERS, cpu_id); 5152 init_counter(ODD_COUNTERS, cpu_id); 5153 return 0; 5154 } 5155 5156 void allocate_output_buffer() 5157 { 5158 output_buffer = calloc(1, (1 + topo.num_cpus) * 2048); 5159 outp = output_buffer; 5160 if (outp == NULL) 5161 err(-1, "calloc output buffer"); 5162 } 5163 void allocate_fd_percpu(void) 5164 { 5165 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 5166 if (fd_percpu == NULL) 5167 err(-1, "calloc fd_percpu"); 5168 } 5169 void allocate_irq_buffers(void) 5170 { 5171 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); 5172 if (irq_column_2_cpu == NULL) 5173 err(-1, "calloc %d", topo.num_cpus); 5174 5175 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 5176 if (irqs_per_cpu == NULL) 5177 err(-1, "calloc %d", topo.max_cpu_num + 1); 5178 } 5179 void setup_all_buffers(void) 5180 { 5181 topology_probe(); 5182 allocate_irq_buffers(); 5183 allocate_fd_percpu(); 5184 allocate_counters(&thread_even, &core_even, &package_even); 5185 allocate_counters(&thread_odd, &core_odd, &package_odd); 5186 allocate_output_buffer(); 5187 for_all_proc_cpus(initialize_counters); 5188 } 5189 5190 void set_base_cpu(void) 5191 { 5192 base_cpu = sched_getcpu(); 5193 if (base_cpu < 0) 5194 err(-ENODEV, "No valid cpus found"); 5195 5196 if (debug > 1) 5197 fprintf(outf, "base_cpu = %d\n", base_cpu); 5198 } 5199 5200 void turbostat_init() 5201 { 5202 setup_all_buffers(); 5203 set_base_cpu(); 5204 check_dev_msr(); 5205 check_permissions(); 5206 process_cpuid(); 5207 5208 5209 if (!quiet) 5210 for_all_cpus(print_hwp, ODD_COUNTERS); 5211 5212 if (!quiet) 5213 for_all_cpus(print_epb, ODD_COUNTERS); 5214 5215 if (!quiet) 5216 for_all_cpus(print_perf_limit, ODD_COUNTERS); 5217 5218 if (!quiet) 5219 for_all_cpus(print_rapl, ODD_COUNTERS); 5220 5221 for_all_cpus(set_temperature_target, ODD_COUNTERS); 5222 5223 if (!quiet) 5224 for_all_cpus(print_thermal, ODD_COUNTERS); 5225 5226 if (!quiet && do_irtl_snb) 5227 print_irtl(); 5228 } 5229 5230 int fork_it(char **argv) 5231 { 5232 pid_t child_pid; 5233 int status; 5234 5235 snapshot_proc_sysfs_files(); 5236 status = for_all_cpus(get_counters, EVEN_COUNTERS); 5237 first_counter_read = 0; 5238 if (status) 5239 exit(status); 5240 /* clear affinity side-effect of get_counters() */ 5241 sched_setaffinity(0, cpu_present_setsize, cpu_present_set); 5242 gettimeofday(&tv_even, (struct timezone *)NULL); 5243 5244 child_pid = fork(); 5245 if (!child_pid) { 5246 /* child */ 5247 execvp(argv[0], argv); 5248 err(errno, "exec %s", argv[0]); 5249 } else { 5250 5251 /* parent */ 5252 if (child_pid == -1) 5253 err(1, "fork"); 5254 5255 signal(SIGINT, SIG_IGN); 5256 signal(SIGQUIT, SIG_IGN); 5257 if (waitpid(child_pid, &status, 0) == -1) 5258 err(status, "waitpid"); 5259 5260 if (WIFEXITED(status)) 5261 status = WEXITSTATUS(status); 5262 } 5263 /* 5264 * n.b. fork_it() does not check for errors from for_all_cpus() 5265 * because re-starting is problematic when forking 5266 */ 5267 snapshot_proc_sysfs_files(); 5268 for_all_cpus(get_counters, ODD_COUNTERS); 5269 gettimeofday(&tv_odd, (struct timezone *)NULL); 5270 timersub(&tv_odd, &tv_even, &tv_delta); 5271 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) 5272 fprintf(outf, "%s: Counter reset detected\n", progname); 5273 else { 5274 compute_average(EVEN_COUNTERS); 5275 format_all_counters(EVEN_COUNTERS); 5276 } 5277 5278 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0); 5279 5280 flush_output_stderr(); 5281 5282 return status; 5283 } 5284 5285 int get_and_dump_counters(void) 5286 { 5287 int status; 5288 5289 snapshot_proc_sysfs_files(); 5290 status = for_all_cpus(get_counters, ODD_COUNTERS); 5291 if (status) 5292 return status; 5293 5294 status = for_all_cpus(dump_counters, ODD_COUNTERS); 5295 if (status) 5296 return status; 5297 5298 flush_output_stdout(); 5299 5300 return status; 5301 } 5302 5303 void print_version() { 5304 fprintf(outf, "turbostat version 19.03.20" 5305 " - Len Brown <lenb@kernel.org>\n"); 5306 } 5307 5308 int add_counter(unsigned int msr_num, char *path, char *name, 5309 unsigned int width, enum counter_scope scope, 5310 enum counter_type type, enum counter_format format, int flags) 5311 { 5312 struct msr_counter *msrp; 5313 5314 msrp = calloc(1, sizeof(struct msr_counter)); 5315 if (msrp == NULL) { 5316 perror("calloc"); 5317 exit(1); 5318 } 5319 5320 msrp->msr_num = msr_num; 5321 strncpy(msrp->name, name, NAME_BYTES); 5322 if (path) 5323 strncpy(msrp->path, path, PATH_BYTES); 5324 msrp->width = width; 5325 msrp->type = type; 5326 msrp->format = format; 5327 msrp->flags = flags; 5328 5329 switch (scope) { 5330 5331 case SCOPE_CPU: 5332 msrp->next = sys.tp; 5333 sys.tp = msrp; 5334 sys.added_thread_counters++; 5335 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) { 5336 fprintf(stderr, "exceeded max %d added thread counters\n", 5337 MAX_ADDED_COUNTERS); 5338 exit(-1); 5339 } 5340 break; 5341 5342 case SCOPE_CORE: 5343 msrp->next = sys.cp; 5344 sys.cp = msrp; 5345 sys.added_core_counters++; 5346 if (sys.added_core_counters > MAX_ADDED_COUNTERS) { 5347 fprintf(stderr, "exceeded max %d added core counters\n", 5348 MAX_ADDED_COUNTERS); 5349 exit(-1); 5350 } 5351 break; 5352 5353 case SCOPE_PACKAGE: 5354 msrp->next = sys.pp; 5355 sys.pp = msrp; 5356 sys.added_package_counters++; 5357 if (sys.added_package_counters > MAX_ADDED_COUNTERS) { 5358 fprintf(stderr, "exceeded max %d added package counters\n", 5359 MAX_ADDED_COUNTERS); 5360 exit(-1); 5361 } 5362 break; 5363 } 5364 5365 return 0; 5366 } 5367 5368 void parse_add_command(char *add_command) 5369 { 5370 int msr_num = 0; 5371 char *path = NULL; 5372 char name_buffer[NAME_BYTES] = ""; 5373 int width = 64; 5374 int fail = 0; 5375 enum counter_scope scope = SCOPE_CPU; 5376 enum counter_type type = COUNTER_CYCLES; 5377 enum counter_format format = FORMAT_DELTA; 5378 5379 while (add_command) { 5380 5381 if (sscanf(add_command, "msr0x%x", &msr_num) == 1) 5382 goto next; 5383 5384 if (sscanf(add_command, "msr%d", &msr_num) == 1) 5385 goto next; 5386 5387 if (*add_command == '/') { 5388 path = add_command; 5389 goto next; 5390 } 5391 5392 if (sscanf(add_command, "u%d", &width) == 1) { 5393 if ((width == 32) || (width == 64)) 5394 goto next; 5395 width = 64; 5396 } 5397 if (!strncmp(add_command, "cpu", strlen("cpu"))) { 5398 scope = SCOPE_CPU; 5399 goto next; 5400 } 5401 if (!strncmp(add_command, "core", strlen("core"))) { 5402 scope = SCOPE_CORE; 5403 goto next; 5404 } 5405 if (!strncmp(add_command, "package", strlen("package"))) { 5406 scope = SCOPE_PACKAGE; 5407 goto next; 5408 } 5409 if (!strncmp(add_command, "cycles", strlen("cycles"))) { 5410 type = COUNTER_CYCLES; 5411 goto next; 5412 } 5413 if (!strncmp(add_command, "seconds", strlen("seconds"))) { 5414 type = COUNTER_SECONDS; 5415 goto next; 5416 } 5417 if (!strncmp(add_command, "usec", strlen("usec"))) { 5418 type = COUNTER_USEC; 5419 goto next; 5420 } 5421 if (!strncmp(add_command, "raw", strlen("raw"))) { 5422 format = FORMAT_RAW; 5423 goto next; 5424 } 5425 if (!strncmp(add_command, "delta", strlen("delta"))) { 5426 format = FORMAT_DELTA; 5427 goto next; 5428 } 5429 if (!strncmp(add_command, "percent", strlen("percent"))) { 5430 format = FORMAT_PERCENT; 5431 goto next; 5432 } 5433 5434 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */ 5435 char *eos; 5436 5437 eos = strchr(name_buffer, ','); 5438 if (eos) 5439 *eos = '\0'; 5440 goto next; 5441 } 5442 5443 next: 5444 add_command = strchr(add_command, ','); 5445 if (add_command) { 5446 *add_command = '\0'; 5447 add_command++; 5448 } 5449 5450 } 5451 if ((msr_num == 0) && (path == NULL)) { 5452 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n"); 5453 fail++; 5454 } 5455 5456 /* generate default column header */ 5457 if (*name_buffer == '\0') { 5458 if (width == 32) 5459 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 5460 else 5461 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 5462 } 5463 5464 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0)) 5465 fail++; 5466 5467 if (fail) { 5468 help(); 5469 exit(1); 5470 } 5471 } 5472 5473 int is_deferred_skip(char *name) 5474 { 5475 int i; 5476 5477 for (i = 0; i < deferred_skip_index; ++i) 5478 if (!strcmp(name, deferred_skip_names[i])) 5479 return 1; 5480 return 0; 5481 } 5482 5483 void probe_sysfs(void) 5484 { 5485 char path[64]; 5486 char name_buf[16]; 5487 FILE *input; 5488 int state; 5489 char *sp; 5490 5491 if (!DO_BIC(BIC_sysfs)) 5492 return; 5493 5494 for (state = 10; state >= 0; --state) { 5495 5496 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 5497 base_cpu, state); 5498 input = fopen(path, "r"); 5499 if (input == NULL) 5500 continue; 5501 if (!fgets(name_buf, sizeof(name_buf), input)) 5502 err(1, "%s: failed to read file", path); 5503 5504 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 5505 sp = strchr(name_buf, '-'); 5506 if (!sp) 5507 sp = strchrnul(name_buf, '\n'); 5508 *sp = '%'; 5509 *(sp + 1) = '\0'; 5510 5511 fclose(input); 5512 5513 sprintf(path, "cpuidle/state%d/time", state); 5514 5515 if (is_deferred_skip(name_buf)) 5516 continue; 5517 5518 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC, 5519 FORMAT_PERCENT, SYSFS_PERCPU); 5520 } 5521 5522 for (state = 10; state >= 0; --state) { 5523 5524 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 5525 base_cpu, state); 5526 input = fopen(path, "r"); 5527 if (input == NULL) 5528 continue; 5529 if (!fgets(name_buf, sizeof(name_buf), input)) 5530 err(1, "%s: failed to read file", path); 5531 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 5532 sp = strchr(name_buf, '-'); 5533 if (!sp) 5534 sp = strchrnul(name_buf, '\n'); 5535 *sp = '\0'; 5536 fclose(input); 5537 5538 sprintf(path, "cpuidle/state%d/usage", state); 5539 5540 if (is_deferred_skip(name_buf)) 5541 continue; 5542 5543 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS, 5544 FORMAT_DELTA, SYSFS_PERCPU); 5545 } 5546 5547 } 5548 5549 5550 /* 5551 * parse cpuset with following syntax 5552 * 1,2,4..6,8-10 and set bits in cpu_subset 5553 */ 5554 void parse_cpu_command(char *optarg) 5555 { 5556 unsigned int start, end; 5557 char *next; 5558 5559 if (!strcmp(optarg, "core")) { 5560 if (cpu_subset) 5561 goto error; 5562 show_core_only++; 5563 return; 5564 } 5565 if (!strcmp(optarg, "package")) { 5566 if (cpu_subset) 5567 goto error; 5568 show_pkg_only++; 5569 return; 5570 } 5571 if (show_core_only || show_pkg_only) 5572 goto error; 5573 5574 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS); 5575 if (cpu_subset == NULL) 5576 err(3, "CPU_ALLOC"); 5577 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS); 5578 5579 CPU_ZERO_S(cpu_subset_size, cpu_subset); 5580 5581 next = optarg; 5582 5583 while (next && *next) { 5584 5585 if (*next == '-') /* no negative cpu numbers */ 5586 goto error; 5587 5588 start = strtoul(next, &next, 10); 5589 5590 if (start >= CPU_SUBSET_MAXCPUS) 5591 goto error; 5592 CPU_SET_S(start, cpu_subset_size, cpu_subset); 5593 5594 if (*next == '\0') 5595 break; 5596 5597 if (*next == ',') { 5598 next += 1; 5599 continue; 5600 } 5601 5602 if (*next == '-') { 5603 next += 1; /* start range */ 5604 } else if (*next == '.') { 5605 next += 1; 5606 if (*next == '.') 5607 next += 1; /* start range */ 5608 else 5609 goto error; 5610 } 5611 5612 end = strtoul(next, &next, 10); 5613 if (end <= start) 5614 goto error; 5615 5616 while (++start <= end) { 5617 if (start >= CPU_SUBSET_MAXCPUS) 5618 goto error; 5619 CPU_SET_S(start, cpu_subset_size, cpu_subset); 5620 } 5621 5622 if (*next == ',') 5623 next += 1; 5624 else if (*next != '\0') 5625 goto error; 5626 } 5627 5628 return; 5629 5630 error: 5631 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg); 5632 help(); 5633 exit(-1); 5634 } 5635 5636 5637 void cmdline(int argc, char **argv) 5638 { 5639 int opt; 5640 int option_index = 0; 5641 static struct option long_options[] = { 5642 {"add", required_argument, 0, 'a'}, 5643 {"cpu", required_argument, 0, 'c'}, 5644 {"Dump", no_argument, 0, 'D'}, 5645 {"debug", no_argument, 0, 'd'}, /* internal, not documented */ 5646 {"enable", required_argument, 0, 'e'}, 5647 {"interval", required_argument, 0, 'i'}, 5648 {"num_iterations", required_argument, 0, 'n'}, 5649 {"help", no_argument, 0, 'h'}, 5650 {"hide", required_argument, 0, 'H'}, // meh, -h taken by --help 5651 {"Joules", no_argument, 0, 'J'}, 5652 {"list", no_argument, 0, 'l'}, 5653 {"out", required_argument, 0, 'o'}, 5654 {"quiet", no_argument, 0, 'q'}, 5655 {"show", required_argument, 0, 's'}, 5656 {"Summary", no_argument, 0, 'S'}, 5657 {"TCC", required_argument, 0, 'T'}, 5658 {"version", no_argument, 0, 'v' }, 5659 {0, 0, 0, 0 } 5660 }; 5661 5662 progname = argv[0]; 5663 5664 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v", 5665 long_options, &option_index)) != -1) { 5666 switch (opt) { 5667 case 'a': 5668 parse_add_command(optarg); 5669 break; 5670 case 'c': 5671 parse_cpu_command(optarg); 5672 break; 5673 case 'D': 5674 dump_only++; 5675 break; 5676 case 'e': 5677 /* --enable specified counter */ 5678 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST); 5679 break; 5680 case 'd': 5681 debug++; 5682 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 5683 break; 5684 case 'H': 5685 /* 5686 * --hide: do not show those specified 5687 * multiple invocations simply clear more bits in enabled mask 5688 */ 5689 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST); 5690 break; 5691 case 'h': 5692 default: 5693 help(); 5694 exit(1); 5695 case 'i': 5696 { 5697 double interval = strtod(optarg, NULL); 5698 5699 if (interval < 0.001) { 5700 fprintf(outf, "interval %f seconds is too small\n", 5701 interval); 5702 exit(2); 5703 } 5704 5705 interval_tv.tv_sec = interval_ts.tv_sec = interval; 5706 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000; 5707 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; 5708 } 5709 break; 5710 case 'J': 5711 rapl_joules++; 5712 break; 5713 case 'l': 5714 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 5715 list_header_only++; 5716 quiet++; 5717 break; 5718 case 'o': 5719 outf = fopen_or_die(optarg, "w"); 5720 break; 5721 case 'q': 5722 quiet = 1; 5723 break; 5724 case 'n': 5725 num_iterations = strtod(optarg, NULL); 5726 5727 if (num_iterations <= 0) { 5728 fprintf(outf, "iterations %d should be positive number\n", 5729 num_iterations); 5730 exit(2); 5731 } 5732 break; 5733 case 's': 5734 /* 5735 * --show: show only those specified 5736 * The 1st invocation will clear and replace the enabled mask 5737 * subsequent invocations can add to it. 5738 */ 5739 if (shown == 0) 5740 bic_enabled = bic_lookup(optarg, SHOW_LIST); 5741 else 5742 bic_enabled |= bic_lookup(optarg, SHOW_LIST); 5743 shown = 1; 5744 break; 5745 case 'S': 5746 summary_only++; 5747 break; 5748 case 'T': 5749 tcc_activation_temp_override = atoi(optarg); 5750 break; 5751 case 'v': 5752 print_version(); 5753 exit(0); 5754 break; 5755 } 5756 } 5757 } 5758 5759 int main(int argc, char **argv) 5760 { 5761 outf = stderr; 5762 cmdline(argc, argv); 5763 5764 if (!quiet) 5765 print_version(); 5766 5767 probe_sysfs(); 5768 5769 turbostat_init(); 5770 5771 /* dump counters and exit */ 5772 if (dump_only) 5773 return get_and_dump_counters(); 5774 5775 /* list header and exit */ 5776 if (list_header_only) { 5777 print_header(","); 5778 flush_output_stdout(); 5779 return 0; 5780 } 5781 5782 /* 5783 * if any params left, it must be a command to fork 5784 */ 5785 if (argc - optind) 5786 return fork_it(argv + optind); 5787 else 5788 turbostat_loop(); 5789 5790 return 0; 5791 } 5792