1 /* 2 * turbostat -- show CPU frequency and C-state residency 3 * on modern Intel and AMD processors. 4 * 5 * Copyright (c) 2013 Intel Corporation. 6 * Len Brown <len.brown@intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 20 */ 21 22 #define _GNU_SOURCE 23 #include MSRHEADER 24 #include INTEL_FAMILY_HEADER 25 #include <stdarg.h> 26 #include <stdio.h> 27 #include <err.h> 28 #include <unistd.h> 29 #include <sys/types.h> 30 #include <sys/wait.h> 31 #include <sys/stat.h> 32 #include <sys/select.h> 33 #include <sys/resource.h> 34 #include <fcntl.h> 35 #include <signal.h> 36 #include <sys/time.h> 37 #include <stdlib.h> 38 #include <getopt.h> 39 #include <dirent.h> 40 #include <string.h> 41 #include <ctype.h> 42 #include <sched.h> 43 #include <time.h> 44 #include <cpuid.h> 45 #include <linux/capability.h> 46 #include <errno.h> 47 48 char *proc_stat = "/proc/stat"; 49 FILE *outf; 50 int *fd_percpu; 51 struct timeval interval_tv = {5, 0}; 52 struct timespec interval_ts = {5, 0}; 53 struct timespec one_msec = {0, 1000000}; 54 unsigned int num_iterations; 55 unsigned int debug; 56 unsigned int quiet; 57 unsigned int shown; 58 unsigned int sums_need_wide_columns; 59 unsigned int rapl_joules; 60 unsigned int summary_only; 61 unsigned int list_header_only; 62 unsigned int dump_only; 63 unsigned int do_snb_cstates; 64 unsigned int do_knl_cstates; 65 unsigned int do_slm_cstates; 66 unsigned int use_c1_residency_msr; 67 unsigned int has_aperf; 68 unsigned int has_epb; 69 unsigned int do_irtl_snb; 70 unsigned int do_irtl_hsw; 71 unsigned int units = 1000000; /* MHz etc */ 72 unsigned int genuine_intel; 73 unsigned int authentic_amd; 74 unsigned int max_level, max_extended_level; 75 unsigned int has_invariant_tsc; 76 unsigned int do_nhm_platform_info; 77 unsigned int no_MSR_MISC_PWR_MGMT; 78 unsigned int aperf_mperf_multiplier = 1; 79 double bclk; 80 double base_hz; 81 unsigned int has_base_hz; 82 double tsc_tweak = 1.0; 83 unsigned int show_pkg_only; 84 unsigned int show_core_only; 85 char *output_buffer, *outp; 86 unsigned int do_rapl; 87 unsigned int do_dts; 88 unsigned int do_ptm; 89 unsigned long long gfx_cur_rc6_ms; 90 unsigned long long cpuidle_cur_cpu_lpi_us; 91 unsigned long long cpuidle_cur_sys_lpi_us; 92 unsigned int gfx_cur_mhz; 93 unsigned int tcc_activation_temp; 94 unsigned int tcc_activation_temp_override; 95 double rapl_power_units, rapl_time_units; 96 double rapl_dram_energy_units, rapl_energy_units; 97 double rapl_joule_counter_range; 98 unsigned int do_core_perf_limit_reasons; 99 unsigned int has_automatic_cstate_conversion; 100 unsigned int do_gfx_perf_limit_reasons; 101 unsigned int do_ring_perf_limit_reasons; 102 unsigned int crystal_hz; 103 unsigned long long tsc_hz; 104 int base_cpu; 105 double discover_bclk(unsigned int family, unsigned int model); 106 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ 107 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ 108 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ 109 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ 110 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ 111 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ 112 unsigned int has_misc_feature_control; 113 unsigned int first_counter_read = 1; 114 115 #define RAPL_PKG (1 << 0) 116 /* 0x610 MSR_PKG_POWER_LIMIT */ 117 /* 0x611 MSR_PKG_ENERGY_STATUS */ 118 #define RAPL_PKG_PERF_STATUS (1 << 1) 119 /* 0x613 MSR_PKG_PERF_STATUS */ 120 #define RAPL_PKG_POWER_INFO (1 << 2) 121 /* 0x614 MSR_PKG_POWER_INFO */ 122 123 #define RAPL_DRAM (1 << 3) 124 /* 0x618 MSR_DRAM_POWER_LIMIT */ 125 /* 0x619 MSR_DRAM_ENERGY_STATUS */ 126 #define RAPL_DRAM_PERF_STATUS (1 << 4) 127 /* 0x61b MSR_DRAM_PERF_STATUS */ 128 #define RAPL_DRAM_POWER_INFO (1 << 5) 129 /* 0x61c MSR_DRAM_POWER_INFO */ 130 131 #define RAPL_CORES_POWER_LIMIT (1 << 6) 132 /* 0x638 MSR_PP0_POWER_LIMIT */ 133 #define RAPL_CORE_POLICY (1 << 7) 134 /* 0x63a MSR_PP0_POLICY */ 135 136 #define RAPL_GFX (1 << 8) 137 /* 0x640 MSR_PP1_POWER_LIMIT */ 138 /* 0x641 MSR_PP1_ENERGY_STATUS */ 139 /* 0x642 MSR_PP1_POLICY */ 140 141 #define RAPL_CORES_ENERGY_STATUS (1 << 9) 142 /* 0x639 MSR_PP0_ENERGY_STATUS */ 143 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT) 144 #define TJMAX_DEFAULT 100 145 146 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 147 148 /* 149 * buffer size used by sscanf() for added column names 150 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters 151 */ 152 #define NAME_BYTES 20 153 #define PATH_BYTES 128 154 155 int backwards_count; 156 char *progname; 157 158 #define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */ 159 cpu_set_t *cpu_present_set, *cpu_affinity_set, *cpu_subset; 160 size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size; 161 #define MAX_ADDED_COUNTERS 8 162 #define MAX_ADDED_THREAD_COUNTERS 24 163 #define BITMASK_SIZE 32 164 165 struct thread_data { 166 struct timeval tv_begin; 167 struct timeval tv_end; 168 unsigned long long tsc; 169 unsigned long long aperf; 170 unsigned long long mperf; 171 unsigned long long c1; 172 unsigned long long irq_count; 173 unsigned int smi_count; 174 unsigned int cpu_id; 175 unsigned int apic_id; 176 unsigned int x2apic_id; 177 unsigned int flags; 178 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2 179 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 180 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS]; 181 } *thread_even, *thread_odd; 182 183 struct core_data { 184 unsigned long long c3; 185 unsigned long long c6; 186 unsigned long long c7; 187 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */ 188 unsigned int core_temp_c; 189 unsigned int core_id; 190 unsigned long long counter[MAX_ADDED_COUNTERS]; 191 } *core_even, *core_odd; 192 193 struct pkg_data { 194 unsigned long long pc2; 195 unsigned long long pc3; 196 unsigned long long pc6; 197 unsigned long long pc7; 198 unsigned long long pc8; 199 unsigned long long pc9; 200 unsigned long long pc10; 201 unsigned long long cpu_lpi; 202 unsigned long long sys_lpi; 203 unsigned long long pkg_wtd_core_c0; 204 unsigned long long pkg_any_core_c0; 205 unsigned long long pkg_any_gfxe_c0; 206 unsigned long long pkg_both_core_gfxe_c0; 207 long long gfx_rc6_ms; 208 unsigned int gfx_mhz; 209 unsigned int package_id; 210 unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */ 211 unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */ 212 unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */ 213 unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */ 214 unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ 215 unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ 216 unsigned int pkg_temp_c; 217 unsigned long long counter[MAX_ADDED_COUNTERS]; 218 } *package_even, *package_odd; 219 220 #define ODD_COUNTERS thread_odd, core_odd, package_odd 221 #define EVEN_COUNTERS thread_even, core_even, package_even 222 223 #define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \ 224 ((thread_base) + \ 225 ((pkg_no) * \ 226 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \ 227 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \ 228 ((core_no) * topo.threads_per_core) + \ 229 (thread_no)) 230 231 #define GET_CORE(core_base, core_no, node_no, pkg_no) \ 232 ((core_base) + \ 233 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \ 234 ((node_no) * topo.cores_per_node) + \ 235 (core_no)) 236 237 238 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) 239 240 enum counter_scope {SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE}; 241 enum counter_type {COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC}; 242 enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT}; 243 244 struct msr_counter { 245 unsigned int msr_num; 246 char name[NAME_BYTES]; 247 char path[PATH_BYTES]; 248 unsigned int width; 249 enum counter_type type; 250 enum counter_format format; 251 struct msr_counter *next; 252 unsigned int flags; 253 #define FLAGS_HIDE (1 << 0) 254 #define FLAGS_SHOW (1 << 1) 255 #define SYSFS_PERCPU (1 << 1) 256 }; 257 258 struct sys_counters { 259 unsigned int added_thread_counters; 260 unsigned int added_core_counters; 261 unsigned int added_package_counters; 262 struct msr_counter *tp; 263 struct msr_counter *cp; 264 struct msr_counter *pp; 265 } sys; 266 267 struct system_summary { 268 struct thread_data threads; 269 struct core_data cores; 270 struct pkg_data packages; 271 } average; 272 273 struct cpu_topology { 274 int physical_package_id; 275 int logical_cpu_id; 276 int physical_node_id; 277 int logical_node_id; /* 0-based count within the package */ 278 int physical_core_id; 279 int thread_id; 280 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */ 281 } *cpus; 282 283 struct topo_params { 284 int num_packages; 285 int num_cpus; 286 int num_cores; 287 int max_cpu_num; 288 int max_node_num; 289 int nodes_per_pkg; 290 int cores_per_node; 291 int threads_per_core; 292 } topo; 293 294 struct timeval tv_even, tv_odd, tv_delta; 295 296 int *irq_column_2_cpu; /* /proc/interrupts column numbers */ 297 int *irqs_per_cpu; /* indexed by cpu_num */ 298 299 void setup_all_buffers(void); 300 301 int cpu_is_not_present(int cpu) 302 { 303 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); 304 } 305 /* 306 * run func(thread, core, package) in topology order 307 * skip non-present cpus 308 */ 309 310 int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *), 311 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) 312 { 313 int retval, pkg_no, core_no, thread_no, node_no; 314 315 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 316 for (node_no = 0; node_no < topo.nodes_per_pkg; node_no++) { 317 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) { 318 for (thread_no = 0; thread_no < 319 topo.threads_per_core; ++thread_no) { 320 struct thread_data *t; 321 struct core_data *c; 322 struct pkg_data *p; 323 324 t = GET_THREAD(thread_base, thread_no, 325 core_no, node_no, 326 pkg_no); 327 328 if (cpu_is_not_present(t->cpu_id)) 329 continue; 330 331 c = GET_CORE(core_base, core_no, 332 node_no, pkg_no); 333 p = GET_PKG(pkg_base, pkg_no); 334 335 retval = func(t, c, p); 336 if (retval) 337 return retval; 338 } 339 } 340 } 341 } 342 return 0; 343 } 344 345 int cpu_migrate(int cpu) 346 { 347 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 348 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); 349 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) 350 return -1; 351 else 352 return 0; 353 } 354 int get_msr_fd(int cpu) 355 { 356 char pathname[32]; 357 int fd; 358 359 fd = fd_percpu[cpu]; 360 361 if (fd) 362 return fd; 363 364 sprintf(pathname, "/dev/cpu/%d/msr", cpu); 365 fd = open(pathname, O_RDONLY); 366 if (fd < 0) 367 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); 368 369 fd_percpu[cpu] = fd; 370 371 return fd; 372 } 373 374 int get_msr(int cpu, off_t offset, unsigned long long *msr) 375 { 376 ssize_t retval; 377 378 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); 379 380 if (retval != sizeof *msr) 381 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset); 382 383 return 0; 384 } 385 386 /* 387 * This list matches the column headers, except 388 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time 389 * 2. Core and CPU are moved to the end, we can't have strings that contain them 390 * matching on them for --show and --hide. 391 */ 392 struct msr_counter bic[] = { 393 { 0x0, "usec" }, 394 { 0x0, "Time_Of_Day_Seconds" }, 395 { 0x0, "Package" }, 396 { 0x0, "Node" }, 397 { 0x0, "Avg_MHz" }, 398 { 0x0, "Busy%" }, 399 { 0x0, "Bzy_MHz" }, 400 { 0x0, "TSC_MHz" }, 401 { 0x0, "IRQ" }, 402 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL}, 403 { 0x0, "sysfs" }, 404 { 0x0, "CPU%c1" }, 405 { 0x0, "CPU%c3" }, 406 { 0x0, "CPU%c6" }, 407 { 0x0, "CPU%c7" }, 408 { 0x0, "ThreadC" }, 409 { 0x0, "CoreTmp" }, 410 { 0x0, "CoreCnt" }, 411 { 0x0, "PkgTmp" }, 412 { 0x0, "GFX%rc6" }, 413 { 0x0, "GFXMHz" }, 414 { 0x0, "Pkg%pc2" }, 415 { 0x0, "Pkg%pc3" }, 416 { 0x0, "Pkg%pc6" }, 417 { 0x0, "Pkg%pc7" }, 418 { 0x0, "Pkg%pc8" }, 419 { 0x0, "Pkg%pc9" }, 420 { 0x0, "Pk%pc10" }, 421 { 0x0, "CPU%LPI" }, 422 { 0x0, "SYS%LPI" }, 423 { 0x0, "PkgWatt" }, 424 { 0x0, "CorWatt" }, 425 { 0x0, "GFXWatt" }, 426 { 0x0, "PkgCnt" }, 427 { 0x0, "RAMWatt" }, 428 { 0x0, "PKG_%" }, 429 { 0x0, "RAM_%" }, 430 { 0x0, "Pkg_J" }, 431 { 0x0, "Cor_J" }, 432 { 0x0, "GFX_J" }, 433 { 0x0, "RAM_J" }, 434 { 0x0, "Mod%c6" }, 435 { 0x0, "Totl%C0" }, 436 { 0x0, "Any%C0" }, 437 { 0x0, "GFX%C0" }, 438 { 0x0, "CPUGFX%" }, 439 { 0x0, "Core" }, 440 { 0x0, "CPU" }, 441 { 0x0, "APIC" }, 442 { 0x0, "X2APIC" }, 443 }; 444 445 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter)) 446 #define BIC_USEC (1ULL << 0) 447 #define BIC_TOD (1ULL << 1) 448 #define BIC_Package (1ULL << 2) 449 #define BIC_Node (1ULL << 3) 450 #define BIC_Avg_MHz (1ULL << 4) 451 #define BIC_Busy (1ULL << 5) 452 #define BIC_Bzy_MHz (1ULL << 6) 453 #define BIC_TSC_MHz (1ULL << 7) 454 #define BIC_IRQ (1ULL << 8) 455 #define BIC_SMI (1ULL << 9) 456 #define BIC_sysfs (1ULL << 10) 457 #define BIC_CPU_c1 (1ULL << 11) 458 #define BIC_CPU_c3 (1ULL << 12) 459 #define BIC_CPU_c6 (1ULL << 13) 460 #define BIC_CPU_c7 (1ULL << 14) 461 #define BIC_ThreadC (1ULL << 15) 462 #define BIC_CoreTmp (1ULL << 16) 463 #define BIC_CoreCnt (1ULL << 17) 464 #define BIC_PkgTmp (1ULL << 18) 465 #define BIC_GFX_rc6 (1ULL << 19) 466 #define BIC_GFXMHz (1ULL << 20) 467 #define BIC_Pkgpc2 (1ULL << 21) 468 #define BIC_Pkgpc3 (1ULL << 22) 469 #define BIC_Pkgpc6 (1ULL << 23) 470 #define BIC_Pkgpc7 (1ULL << 24) 471 #define BIC_Pkgpc8 (1ULL << 25) 472 #define BIC_Pkgpc9 (1ULL << 26) 473 #define BIC_Pkgpc10 (1ULL << 27) 474 #define BIC_CPU_LPI (1ULL << 28) 475 #define BIC_SYS_LPI (1ULL << 29) 476 #define BIC_PkgWatt (1ULL << 30) 477 #define BIC_CorWatt (1ULL << 31) 478 #define BIC_GFXWatt (1ULL << 32) 479 #define BIC_PkgCnt (1ULL << 33) 480 #define BIC_RAMWatt (1ULL << 34) 481 #define BIC_PKG__ (1ULL << 35) 482 #define BIC_RAM__ (1ULL << 36) 483 #define BIC_Pkg_J (1ULL << 37) 484 #define BIC_Cor_J (1ULL << 38) 485 #define BIC_GFX_J (1ULL << 39) 486 #define BIC_RAM_J (1ULL << 40) 487 #define BIC_Mod_c6 (1ULL << 41) 488 #define BIC_Totl_c0 (1ULL << 42) 489 #define BIC_Any_c0 (1ULL << 43) 490 #define BIC_GFX_c0 (1ULL << 44) 491 #define BIC_CPUGFX (1ULL << 45) 492 #define BIC_Core (1ULL << 46) 493 #define BIC_CPU (1ULL << 47) 494 #define BIC_APIC (1ULL << 48) 495 #define BIC_X2APIC (1ULL << 49) 496 497 #define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC) 498 499 unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT); 500 unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC; 501 502 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME) 503 #define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME) 504 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT) 505 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT) 506 507 508 #define MAX_DEFERRED 16 509 char *deferred_skip_names[MAX_DEFERRED]; 510 int deferred_skip_index; 511 512 /* 513 * HIDE_LIST - hide this list of counters, show the rest [default] 514 * SHOW_LIST - show this list of counters, hide the rest 515 */ 516 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST; 517 518 void help(void) 519 { 520 fprintf(outf, 521 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" 522 "\n" 523 "Turbostat forks the specified COMMAND and prints statistics\n" 524 "when COMMAND completes.\n" 525 "If no COMMAND is specified, turbostat wakes every 5-seconds\n" 526 "to print statistics, until interrupted.\n" 527 " -a, --add add a counter\n" 528 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n" 529 " -c, --cpu cpu-set limit output to summary plus cpu-set:\n" 530 " {core | package | j,k,l..m,n-p }\n" 531 " -d, --debug displays usec, Time_Of_Day_Seconds and more debugging\n" 532 " -D, --Dump displays the raw counter values\n" 533 " -e, --enable [all | column]\n" 534 " shows all or the specified disabled column\n" 535 " -H, --hide [column|column,column,...]\n" 536 " hide the specified column(s)\n" 537 " -i, --interval sec.subsec\n" 538 " Override default 5-second measurement interval\n" 539 " -J, --Joules displays energy in Joules instead of Watts\n" 540 " -l, --list list column headers only\n" 541 " -n, --num_iterations num\n" 542 " number of the measurement iterations\n" 543 " -o, --out file\n" 544 " create or truncate \"file\" for all output\n" 545 " -q, --quiet skip decoding system configuration header\n" 546 " -s, --show [column|column,column,...]\n" 547 " show only the specified column(s)\n" 548 " -S, --Summary\n" 549 " limits output to 1-line system summary per interval\n" 550 " -T, --TCC temperature\n" 551 " sets the Thermal Control Circuit temperature in\n" 552 " degrees Celsius\n" 553 " -h, --help print this help message\n" 554 " -v, --version print version information\n" 555 "\n" 556 "For more help, run \"man turbostat\"\n"); 557 } 558 559 /* 560 * bic_lookup 561 * for all the strings in comma separate name_list, 562 * set the approprate bit in return value. 563 */ 564 unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode) 565 { 566 int i; 567 unsigned long long retval = 0; 568 569 while (name_list) { 570 char *comma; 571 572 comma = strchr(name_list, ','); 573 574 if (comma) 575 *comma = '\0'; 576 577 if (!strcmp(name_list, "all")) 578 return ~0; 579 580 for (i = 0; i < MAX_BIC; ++i) { 581 if (!strcmp(name_list, bic[i].name)) { 582 retval |= (1ULL << i); 583 break; 584 } 585 } 586 if (i == MAX_BIC) { 587 if (mode == SHOW_LIST) { 588 fprintf(stderr, "Invalid counter name: %s\n", name_list); 589 exit(-1); 590 } 591 deferred_skip_names[deferred_skip_index++] = name_list; 592 if (debug) 593 fprintf(stderr, "deferred \"%s\"\n", name_list); 594 if (deferred_skip_index >= MAX_DEFERRED) { 595 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n", 596 MAX_DEFERRED, name_list); 597 help(); 598 exit(1); 599 } 600 } 601 602 name_list = comma; 603 if (name_list) 604 name_list++; 605 606 } 607 return retval; 608 } 609 610 611 void print_header(char *delim) 612 { 613 struct msr_counter *mp; 614 int printed = 0; 615 616 if (DO_BIC(BIC_USEC)) 617 outp += sprintf(outp, "%susec", (printed++ ? delim : "")); 618 if (DO_BIC(BIC_TOD)) 619 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : "")); 620 if (DO_BIC(BIC_Package)) 621 outp += sprintf(outp, "%sPackage", (printed++ ? delim : "")); 622 if (DO_BIC(BIC_Node)) 623 outp += sprintf(outp, "%sNode", (printed++ ? delim : "")); 624 if (DO_BIC(BIC_Core)) 625 outp += sprintf(outp, "%sCore", (printed++ ? delim : "")); 626 if (DO_BIC(BIC_CPU)) 627 outp += sprintf(outp, "%sCPU", (printed++ ? delim : "")); 628 if (DO_BIC(BIC_APIC)) 629 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : "")); 630 if (DO_BIC(BIC_X2APIC)) 631 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : "")); 632 if (DO_BIC(BIC_Avg_MHz)) 633 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : "")); 634 if (DO_BIC(BIC_Busy)) 635 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : "")); 636 if (DO_BIC(BIC_Bzy_MHz)) 637 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : "")); 638 if (DO_BIC(BIC_TSC_MHz)) 639 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : "")); 640 641 if (DO_BIC(BIC_IRQ)) { 642 if (sums_need_wide_columns) 643 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : "")); 644 else 645 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : "")); 646 } 647 648 if (DO_BIC(BIC_SMI)) 649 outp += sprintf(outp, "%sSMI", (printed++ ? delim : "")); 650 651 for (mp = sys.tp; mp; mp = mp->next) { 652 653 if (mp->format == FORMAT_RAW) { 654 if (mp->width == 64) 655 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name); 656 else 657 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name); 658 } else { 659 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 660 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name); 661 else 662 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name); 663 } 664 } 665 666 if (DO_BIC(BIC_CPU_c1)) 667 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : "")); 668 if (DO_BIC(BIC_CPU_c3)) 669 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : "")); 670 if (DO_BIC(BIC_CPU_c6)) 671 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : "")); 672 if (DO_BIC(BIC_CPU_c7)) 673 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : "")); 674 675 if (DO_BIC(BIC_Mod_c6)) 676 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : "")); 677 678 if (DO_BIC(BIC_CoreTmp)) 679 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : "")); 680 681 for (mp = sys.cp; mp; mp = mp->next) { 682 if (mp->format == FORMAT_RAW) { 683 if (mp->width == 64) 684 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 685 else 686 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 687 } else { 688 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 689 outp += sprintf(outp, "%s%8s", delim, mp->name); 690 else 691 outp += sprintf(outp, "%s%s", delim, mp->name); 692 } 693 } 694 695 if (DO_BIC(BIC_PkgTmp)) 696 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : "")); 697 698 if (DO_BIC(BIC_GFX_rc6)) 699 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : "")); 700 701 if (DO_BIC(BIC_GFXMHz)) 702 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : "")); 703 704 if (DO_BIC(BIC_Totl_c0)) 705 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : "")); 706 if (DO_BIC(BIC_Any_c0)) 707 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : "")); 708 if (DO_BIC(BIC_GFX_c0)) 709 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : "")); 710 if (DO_BIC(BIC_CPUGFX)) 711 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : "")); 712 713 if (DO_BIC(BIC_Pkgpc2)) 714 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : "")); 715 if (DO_BIC(BIC_Pkgpc3)) 716 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : "")); 717 if (DO_BIC(BIC_Pkgpc6)) 718 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : "")); 719 if (DO_BIC(BIC_Pkgpc7)) 720 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : "")); 721 if (DO_BIC(BIC_Pkgpc8)) 722 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : "")); 723 if (DO_BIC(BIC_Pkgpc9)) 724 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : "")); 725 if (DO_BIC(BIC_Pkgpc10)) 726 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : "")); 727 if (DO_BIC(BIC_CPU_LPI)) 728 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : "")); 729 if (DO_BIC(BIC_SYS_LPI)) 730 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : "")); 731 732 if (do_rapl && !rapl_joules) { 733 if (DO_BIC(BIC_PkgWatt)) 734 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : "")); 735 if (DO_BIC(BIC_CorWatt)) 736 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 737 if (DO_BIC(BIC_GFXWatt)) 738 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : "")); 739 if (DO_BIC(BIC_RAMWatt)) 740 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : "")); 741 if (DO_BIC(BIC_PKG__)) 742 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 743 if (DO_BIC(BIC_RAM__)) 744 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 745 } else if (do_rapl && rapl_joules) { 746 if (DO_BIC(BIC_Pkg_J)) 747 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : "")); 748 if (DO_BIC(BIC_Cor_J)) 749 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 750 if (DO_BIC(BIC_GFX_J)) 751 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : "")); 752 if (DO_BIC(BIC_RAM_J)) 753 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : "")); 754 if (DO_BIC(BIC_PKG__)) 755 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 756 if (DO_BIC(BIC_RAM__)) 757 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 758 } 759 for (mp = sys.pp; mp; mp = mp->next) { 760 if (mp->format == FORMAT_RAW) { 761 if (mp->width == 64) 762 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 763 else 764 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 765 } else { 766 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 767 outp += sprintf(outp, "%s%8s", delim, mp->name); 768 else 769 outp += sprintf(outp, "%s%s", delim, mp->name); 770 } 771 } 772 773 outp += sprintf(outp, "\n"); 774 } 775 776 int dump_counters(struct thread_data *t, struct core_data *c, 777 struct pkg_data *p) 778 { 779 int i; 780 struct msr_counter *mp; 781 782 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); 783 784 if (t) { 785 outp += sprintf(outp, "CPU: %d flags 0x%x\n", 786 t->cpu_id, t->flags); 787 outp += sprintf(outp, "TSC: %016llX\n", t->tsc); 788 outp += sprintf(outp, "aperf: %016llX\n", t->aperf); 789 outp += sprintf(outp, "mperf: %016llX\n", t->mperf); 790 outp += sprintf(outp, "c1: %016llX\n", t->c1); 791 792 if (DO_BIC(BIC_IRQ)) 793 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count); 794 if (DO_BIC(BIC_SMI)) 795 outp += sprintf(outp, "SMI: %d\n", t->smi_count); 796 797 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 798 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", 799 i, mp->msr_num, t->counter[i]); 800 } 801 } 802 803 if (c) { 804 outp += sprintf(outp, "core: %d\n", c->core_id); 805 outp += sprintf(outp, "c3: %016llX\n", c->c3); 806 outp += sprintf(outp, "c6: %016llX\n", c->c6); 807 outp += sprintf(outp, "c7: %016llX\n", c->c7); 808 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); 809 810 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 811 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", 812 i, mp->msr_num, c->counter[i]); 813 } 814 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us); 815 } 816 817 if (p) { 818 outp += sprintf(outp, "package: %d\n", p->package_id); 819 820 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); 821 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); 822 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); 823 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); 824 825 outp += sprintf(outp, "pc2: %016llX\n", p->pc2); 826 if (DO_BIC(BIC_Pkgpc3)) 827 outp += sprintf(outp, "pc3: %016llX\n", p->pc3); 828 if (DO_BIC(BIC_Pkgpc6)) 829 outp += sprintf(outp, "pc6: %016llX\n", p->pc6); 830 if (DO_BIC(BIC_Pkgpc7)) 831 outp += sprintf(outp, "pc7: %016llX\n", p->pc7); 832 outp += sprintf(outp, "pc8: %016llX\n", p->pc8); 833 outp += sprintf(outp, "pc9: %016llX\n", p->pc9); 834 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 835 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 836 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi); 837 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi); 838 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg); 839 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores); 840 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx); 841 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram); 842 outp += sprintf(outp, "Throttle PKG: %0X\n", 843 p->rapl_pkg_perf_status); 844 outp += sprintf(outp, "Throttle RAM: %0X\n", 845 p->rapl_dram_perf_status); 846 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); 847 848 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 849 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", 850 i, mp->msr_num, p->counter[i]); 851 } 852 } 853 854 outp += sprintf(outp, "\n"); 855 856 return 0; 857 } 858 859 /* 860 * column formatting convention & formats 861 */ 862 int format_counters(struct thread_data *t, struct core_data *c, 863 struct pkg_data *p) 864 { 865 double interval_float, tsc; 866 char *fmt8; 867 int i; 868 struct msr_counter *mp; 869 char *delim = "\t"; 870 int printed = 0; 871 872 /* if showing only 1st thread in core and this isn't one, bail out */ 873 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 874 return 0; 875 876 /* if showing only 1st thread in pkg and this isn't one, bail out */ 877 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 878 return 0; 879 880 /*if not summary line and --cpu is used */ 881 if ((t != &average.threads) && 882 (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset))) 883 return 0; 884 885 if (DO_BIC(BIC_USEC)) { 886 /* on each row, print how many usec each timestamp took to gather */ 887 struct timeval tv; 888 889 timersub(&t->tv_end, &t->tv_begin, &tv); 890 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec); 891 } 892 893 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */ 894 if (DO_BIC(BIC_TOD)) 895 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec); 896 897 interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0; 898 899 tsc = t->tsc * tsc_tweak; 900 901 /* topo columns, print blanks on 1st (average) line */ 902 if (t == &average.threads) { 903 if (DO_BIC(BIC_Package)) 904 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 905 if (DO_BIC(BIC_Node)) 906 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 907 if (DO_BIC(BIC_Core)) 908 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 909 if (DO_BIC(BIC_CPU)) 910 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 911 if (DO_BIC(BIC_APIC)) 912 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 913 if (DO_BIC(BIC_X2APIC)) 914 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 915 } else { 916 if (DO_BIC(BIC_Package)) { 917 if (p) 918 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id); 919 else 920 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 921 } 922 if (DO_BIC(BIC_Node)) { 923 if (t) 924 outp += sprintf(outp, "%s%d", 925 (printed++ ? delim : ""), 926 cpus[t->cpu_id].physical_node_id); 927 else 928 outp += sprintf(outp, "%s-", 929 (printed++ ? delim : "")); 930 } 931 if (DO_BIC(BIC_Core)) { 932 if (c) 933 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id); 934 else 935 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 936 } 937 if (DO_BIC(BIC_CPU)) 938 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id); 939 if (DO_BIC(BIC_APIC)) 940 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id); 941 if (DO_BIC(BIC_X2APIC)) 942 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id); 943 } 944 945 if (DO_BIC(BIC_Avg_MHz)) 946 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 947 1.0 / units * t->aperf / interval_float); 948 949 if (DO_BIC(BIC_Busy)) 950 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf/tsc); 951 952 if (DO_BIC(BIC_Bzy_MHz)) { 953 if (has_base_hz) 954 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf); 955 else 956 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 957 tsc / units * t->aperf / t->mperf / interval_float); 958 } 959 960 if (DO_BIC(BIC_TSC_MHz)) 961 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc/units/interval_float); 962 963 /* IRQ */ 964 if (DO_BIC(BIC_IRQ)) { 965 if (sums_need_wide_columns) 966 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count); 967 else 968 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count); 969 } 970 971 /* SMI */ 972 if (DO_BIC(BIC_SMI)) 973 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count); 974 975 /* Added counters */ 976 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 977 if (mp->format == FORMAT_RAW) { 978 if (mp->width == 32) 979 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) t->counter[i]); 980 else 981 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]); 982 } else if (mp->format == FORMAT_DELTA) { 983 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 984 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]); 985 else 986 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]); 987 } else if (mp->format == FORMAT_PERCENT) { 988 if (mp->type == COUNTER_USEC) 989 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), t->counter[i]/interval_float/10000); 990 else 991 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i]/tsc); 992 } 993 } 994 995 /* C1 */ 996 if (DO_BIC(BIC_CPU_c1)) 997 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1/tsc); 998 999 1000 /* print per-core data only for 1st thread in core */ 1001 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1002 goto done; 1003 1004 if (DO_BIC(BIC_CPU_c3)) 1005 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3/tsc); 1006 if (DO_BIC(BIC_CPU_c6)) 1007 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6/tsc); 1008 if (DO_BIC(BIC_CPU_c7)) 1009 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7/tsc); 1010 1011 /* Mod%c6 */ 1012 if (DO_BIC(BIC_Mod_c6)) 1013 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc); 1014 1015 if (DO_BIC(BIC_CoreTmp)) 1016 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c); 1017 1018 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1019 if (mp->format == FORMAT_RAW) { 1020 if (mp->width == 32) 1021 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) c->counter[i]); 1022 else 1023 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]); 1024 } else if (mp->format == FORMAT_DELTA) { 1025 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1026 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]); 1027 else 1028 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]); 1029 } else if (mp->format == FORMAT_PERCENT) { 1030 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i]/tsc); 1031 } 1032 } 1033 1034 /* print per-package data only for 1st core in package */ 1035 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1036 goto done; 1037 1038 /* PkgTmp */ 1039 if (DO_BIC(BIC_PkgTmp)) 1040 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c); 1041 1042 /* GFXrc6 */ 1043 if (DO_BIC(BIC_GFX_rc6)) { 1044 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */ 1045 outp += sprintf(outp, "%s**.**", (printed++ ? delim : "")); 1046 } else { 1047 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1048 p->gfx_rc6_ms / 10.0 / interval_float); 1049 } 1050 } 1051 1052 /* GFXMHz */ 1053 if (DO_BIC(BIC_GFXMHz)) 1054 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz); 1055 1056 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ 1057 if (DO_BIC(BIC_Totl_c0)) 1058 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0/tsc); 1059 if (DO_BIC(BIC_Any_c0)) 1060 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0/tsc); 1061 if (DO_BIC(BIC_GFX_c0)) 1062 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0/tsc); 1063 if (DO_BIC(BIC_CPUGFX)) 1064 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0/tsc); 1065 1066 if (DO_BIC(BIC_Pkgpc2)) 1067 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2/tsc); 1068 if (DO_BIC(BIC_Pkgpc3)) 1069 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3/tsc); 1070 if (DO_BIC(BIC_Pkgpc6)) 1071 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6/tsc); 1072 if (DO_BIC(BIC_Pkgpc7)) 1073 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7/tsc); 1074 if (DO_BIC(BIC_Pkgpc8)) 1075 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8/tsc); 1076 if (DO_BIC(BIC_Pkgpc9)) 1077 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9/tsc); 1078 if (DO_BIC(BIC_Pkgpc10)) 1079 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10/tsc); 1080 1081 if (DO_BIC(BIC_CPU_LPI)) 1082 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float); 1083 if (DO_BIC(BIC_SYS_LPI)) 1084 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float); 1085 1086 /* 1087 * If measurement interval exceeds minimum RAPL Joule Counter range, 1088 * indicate that results are suspect by printing "**" in fraction place. 1089 */ 1090 if (interval_float < rapl_joule_counter_range) 1091 fmt8 = "%s%.2f"; 1092 else 1093 fmt8 = "%6.0f**"; 1094 1095 if (DO_BIC(BIC_PkgWatt)) 1096 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float); 1097 if (DO_BIC(BIC_CorWatt)) 1098 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float); 1099 if (DO_BIC(BIC_GFXWatt)) 1100 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float); 1101 if (DO_BIC(BIC_RAMWatt)) 1102 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units / interval_float); 1103 if (DO_BIC(BIC_Pkg_J)) 1104 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units); 1105 if (DO_BIC(BIC_Cor_J)) 1106 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units); 1107 if (DO_BIC(BIC_GFX_J)) 1108 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units); 1109 if (DO_BIC(BIC_RAM_J)) 1110 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units); 1111 if (DO_BIC(BIC_PKG__)) 1112 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 1113 if (DO_BIC(BIC_RAM__)) 1114 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 1115 1116 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1117 if (mp->format == FORMAT_RAW) { 1118 if (mp->width == 32) 1119 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) p->counter[i]); 1120 else 1121 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]); 1122 } else if (mp->format == FORMAT_DELTA) { 1123 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1124 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]); 1125 else 1126 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]); 1127 } else if (mp->format == FORMAT_PERCENT) { 1128 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i]/tsc); 1129 } 1130 } 1131 1132 done: 1133 if (*(outp - 1) != '\n') 1134 outp += sprintf(outp, "\n"); 1135 1136 return 0; 1137 } 1138 1139 void flush_output_stdout(void) 1140 { 1141 FILE *filep; 1142 1143 if (outf == stderr) 1144 filep = stdout; 1145 else 1146 filep = outf; 1147 1148 fputs(output_buffer, filep); 1149 fflush(filep); 1150 1151 outp = output_buffer; 1152 } 1153 void flush_output_stderr(void) 1154 { 1155 fputs(output_buffer, outf); 1156 fflush(outf); 1157 outp = output_buffer; 1158 } 1159 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1160 { 1161 static int printed; 1162 1163 if (!printed || !summary_only) 1164 print_header("\t"); 1165 1166 format_counters(&average.threads, &average.cores, &average.packages); 1167 1168 printed = 1; 1169 1170 if (summary_only) 1171 return; 1172 1173 for_all_cpus(format_counters, t, c, p); 1174 } 1175 1176 #define DELTA_WRAP32(new, old) \ 1177 if (new > old) { \ 1178 old = new - old; \ 1179 } else { \ 1180 old = 0x100000000 + new - old; \ 1181 } 1182 1183 int 1184 delta_package(struct pkg_data *new, struct pkg_data *old) 1185 { 1186 int i; 1187 struct msr_counter *mp; 1188 1189 1190 if (DO_BIC(BIC_Totl_c0)) 1191 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; 1192 if (DO_BIC(BIC_Any_c0)) 1193 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; 1194 if (DO_BIC(BIC_GFX_c0)) 1195 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; 1196 if (DO_BIC(BIC_CPUGFX)) 1197 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; 1198 1199 old->pc2 = new->pc2 - old->pc2; 1200 if (DO_BIC(BIC_Pkgpc3)) 1201 old->pc3 = new->pc3 - old->pc3; 1202 if (DO_BIC(BIC_Pkgpc6)) 1203 old->pc6 = new->pc6 - old->pc6; 1204 if (DO_BIC(BIC_Pkgpc7)) 1205 old->pc7 = new->pc7 - old->pc7; 1206 old->pc8 = new->pc8 - old->pc8; 1207 old->pc9 = new->pc9 - old->pc9; 1208 old->pc10 = new->pc10 - old->pc10; 1209 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi; 1210 old->sys_lpi = new->sys_lpi - old->sys_lpi; 1211 old->pkg_temp_c = new->pkg_temp_c; 1212 1213 /* flag an error when rc6 counter resets/wraps */ 1214 if (old->gfx_rc6_ms > new->gfx_rc6_ms) 1215 old->gfx_rc6_ms = -1; 1216 else 1217 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; 1218 1219 old->gfx_mhz = new->gfx_mhz; 1220 1221 DELTA_WRAP32(new->energy_pkg, old->energy_pkg); 1222 DELTA_WRAP32(new->energy_cores, old->energy_cores); 1223 DELTA_WRAP32(new->energy_gfx, old->energy_gfx); 1224 DELTA_WRAP32(new->energy_dram, old->energy_dram); 1225 DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status); 1226 DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status); 1227 1228 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1229 if (mp->format == FORMAT_RAW) 1230 old->counter[i] = new->counter[i]; 1231 else 1232 old->counter[i] = new->counter[i] - old->counter[i]; 1233 } 1234 1235 return 0; 1236 } 1237 1238 void 1239 delta_core(struct core_data *new, struct core_data *old) 1240 { 1241 int i; 1242 struct msr_counter *mp; 1243 1244 old->c3 = new->c3 - old->c3; 1245 old->c6 = new->c6 - old->c6; 1246 old->c7 = new->c7 - old->c7; 1247 old->core_temp_c = new->core_temp_c; 1248 old->mc6_us = new->mc6_us - old->mc6_us; 1249 1250 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1251 if (mp->format == FORMAT_RAW) 1252 old->counter[i] = new->counter[i]; 1253 else 1254 old->counter[i] = new->counter[i] - old->counter[i]; 1255 } 1256 } 1257 1258 /* 1259 * old = new - old 1260 */ 1261 int 1262 delta_thread(struct thread_data *new, struct thread_data *old, 1263 struct core_data *core_delta) 1264 { 1265 int i; 1266 struct msr_counter *mp; 1267 1268 /* we run cpuid just the 1st time, copy the results */ 1269 if (DO_BIC(BIC_APIC)) 1270 new->apic_id = old->apic_id; 1271 if (DO_BIC(BIC_X2APIC)) 1272 new->x2apic_id = old->x2apic_id; 1273 1274 /* 1275 * the timestamps from start of measurement interval are in "old" 1276 * the timestamp from end of measurement interval are in "new" 1277 * over-write old w/ new so we can print end of interval values 1278 */ 1279 1280 old->tv_begin = new->tv_begin; 1281 old->tv_end = new->tv_end; 1282 1283 old->tsc = new->tsc - old->tsc; 1284 1285 /* check for TSC < 1 Mcycles over interval */ 1286 if (old->tsc < (1000 * 1000)) 1287 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" 1288 "You can disable all c-states by booting with \"idle=poll\"\n" 1289 "or just the deep ones with \"processor.max_cstate=1\""); 1290 1291 old->c1 = new->c1 - old->c1; 1292 1293 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) { 1294 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { 1295 old->aperf = new->aperf - old->aperf; 1296 old->mperf = new->mperf - old->mperf; 1297 } else { 1298 return -1; 1299 } 1300 } 1301 1302 1303 if (use_c1_residency_msr) { 1304 /* 1305 * Some models have a dedicated C1 residency MSR, 1306 * which should be more accurate than the derivation below. 1307 */ 1308 } else { 1309 /* 1310 * As counter collection is not atomic, 1311 * it is possible for mperf's non-halted cycles + idle states 1312 * to exceed TSC's all cycles: show c1 = 0% in that case. 1313 */ 1314 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak)) 1315 old->c1 = 0; 1316 else { 1317 /* normal case, derive c1 */ 1318 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3 1319 - core_delta->c6 - core_delta->c7; 1320 } 1321 } 1322 1323 if (old->mperf == 0) { 1324 if (debug > 1) 1325 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); 1326 old->mperf = 1; /* divide by 0 protection */ 1327 } 1328 1329 if (DO_BIC(BIC_IRQ)) 1330 old->irq_count = new->irq_count - old->irq_count; 1331 1332 if (DO_BIC(BIC_SMI)) 1333 old->smi_count = new->smi_count - old->smi_count; 1334 1335 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1336 if (mp->format == FORMAT_RAW) 1337 old->counter[i] = new->counter[i]; 1338 else 1339 old->counter[i] = new->counter[i] - old->counter[i]; 1340 } 1341 return 0; 1342 } 1343 1344 int delta_cpu(struct thread_data *t, struct core_data *c, 1345 struct pkg_data *p, struct thread_data *t2, 1346 struct core_data *c2, struct pkg_data *p2) 1347 { 1348 int retval = 0; 1349 1350 /* calculate core delta only for 1st thread in core */ 1351 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) 1352 delta_core(c, c2); 1353 1354 /* always calculate thread delta */ 1355 retval = delta_thread(t, t2, c2); /* c2 is core delta */ 1356 if (retval) 1357 return retval; 1358 1359 /* calculate package delta only for 1st core in package */ 1360 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) 1361 retval = delta_package(p, p2); 1362 1363 return retval; 1364 } 1365 1366 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1367 { 1368 int i; 1369 struct msr_counter *mp; 1370 1371 t->tv_begin.tv_sec = 0; 1372 t->tv_begin.tv_usec = 0; 1373 t->tv_end.tv_sec = 0; 1374 t->tv_end.tv_usec = 0; 1375 1376 t->tsc = 0; 1377 t->aperf = 0; 1378 t->mperf = 0; 1379 t->c1 = 0; 1380 1381 t->irq_count = 0; 1382 t->smi_count = 0; 1383 1384 /* tells format_counters to dump all fields from this set */ 1385 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; 1386 1387 c->c3 = 0; 1388 c->c6 = 0; 1389 c->c7 = 0; 1390 c->mc6_us = 0; 1391 c->core_temp_c = 0; 1392 1393 p->pkg_wtd_core_c0 = 0; 1394 p->pkg_any_core_c0 = 0; 1395 p->pkg_any_gfxe_c0 = 0; 1396 p->pkg_both_core_gfxe_c0 = 0; 1397 1398 p->pc2 = 0; 1399 if (DO_BIC(BIC_Pkgpc3)) 1400 p->pc3 = 0; 1401 if (DO_BIC(BIC_Pkgpc6)) 1402 p->pc6 = 0; 1403 if (DO_BIC(BIC_Pkgpc7)) 1404 p->pc7 = 0; 1405 p->pc8 = 0; 1406 p->pc9 = 0; 1407 p->pc10 = 0; 1408 p->cpu_lpi = 0; 1409 p->sys_lpi = 0; 1410 1411 p->energy_pkg = 0; 1412 p->energy_dram = 0; 1413 p->energy_cores = 0; 1414 p->energy_gfx = 0; 1415 p->rapl_pkg_perf_status = 0; 1416 p->rapl_dram_perf_status = 0; 1417 p->pkg_temp_c = 0; 1418 1419 p->gfx_rc6_ms = 0; 1420 p->gfx_mhz = 0; 1421 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) 1422 t->counter[i] = 0; 1423 1424 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) 1425 c->counter[i] = 0; 1426 1427 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) 1428 p->counter[i] = 0; 1429 } 1430 int sum_counters(struct thread_data *t, struct core_data *c, 1431 struct pkg_data *p) 1432 { 1433 int i; 1434 struct msr_counter *mp; 1435 1436 /* copy un-changing apic_id's */ 1437 if (DO_BIC(BIC_APIC)) 1438 average.threads.apic_id = t->apic_id; 1439 if (DO_BIC(BIC_X2APIC)) 1440 average.threads.x2apic_id = t->x2apic_id; 1441 1442 /* remember first tv_begin */ 1443 if (average.threads.tv_begin.tv_sec == 0) 1444 average.threads.tv_begin = t->tv_begin; 1445 1446 /* remember last tv_end */ 1447 average.threads.tv_end = t->tv_end; 1448 1449 average.threads.tsc += t->tsc; 1450 average.threads.aperf += t->aperf; 1451 average.threads.mperf += t->mperf; 1452 average.threads.c1 += t->c1; 1453 1454 average.threads.irq_count += t->irq_count; 1455 average.threads.smi_count += t->smi_count; 1456 1457 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1458 if (mp->format == FORMAT_RAW) 1459 continue; 1460 average.threads.counter[i] += t->counter[i]; 1461 } 1462 1463 /* sum per-core values only for 1st thread in core */ 1464 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1465 return 0; 1466 1467 average.cores.c3 += c->c3; 1468 average.cores.c6 += c->c6; 1469 average.cores.c7 += c->c7; 1470 average.cores.mc6_us += c->mc6_us; 1471 1472 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); 1473 1474 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1475 if (mp->format == FORMAT_RAW) 1476 continue; 1477 average.cores.counter[i] += c->counter[i]; 1478 } 1479 1480 /* sum per-pkg values only for 1st core in pkg */ 1481 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1482 return 0; 1483 1484 if (DO_BIC(BIC_Totl_c0)) 1485 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; 1486 if (DO_BIC(BIC_Any_c0)) 1487 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; 1488 if (DO_BIC(BIC_GFX_c0)) 1489 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; 1490 if (DO_BIC(BIC_CPUGFX)) 1491 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; 1492 1493 average.packages.pc2 += p->pc2; 1494 if (DO_BIC(BIC_Pkgpc3)) 1495 average.packages.pc3 += p->pc3; 1496 if (DO_BIC(BIC_Pkgpc6)) 1497 average.packages.pc6 += p->pc6; 1498 if (DO_BIC(BIC_Pkgpc7)) 1499 average.packages.pc7 += p->pc7; 1500 average.packages.pc8 += p->pc8; 1501 average.packages.pc9 += p->pc9; 1502 average.packages.pc10 += p->pc10; 1503 1504 average.packages.cpu_lpi = p->cpu_lpi; 1505 average.packages.sys_lpi = p->sys_lpi; 1506 1507 average.packages.energy_pkg += p->energy_pkg; 1508 average.packages.energy_dram += p->energy_dram; 1509 average.packages.energy_cores += p->energy_cores; 1510 average.packages.energy_gfx += p->energy_gfx; 1511 1512 average.packages.gfx_rc6_ms = p->gfx_rc6_ms; 1513 average.packages.gfx_mhz = p->gfx_mhz; 1514 1515 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); 1516 1517 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; 1518 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; 1519 1520 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1521 if (mp->format == FORMAT_RAW) 1522 continue; 1523 average.packages.counter[i] += p->counter[i]; 1524 } 1525 return 0; 1526 } 1527 /* 1528 * sum the counters for all cpus in the system 1529 * compute the weighted average 1530 */ 1531 void compute_average(struct thread_data *t, struct core_data *c, 1532 struct pkg_data *p) 1533 { 1534 int i; 1535 struct msr_counter *mp; 1536 1537 clear_counters(&average.threads, &average.cores, &average.packages); 1538 1539 for_all_cpus(sum_counters, t, c, p); 1540 1541 average.threads.tsc /= topo.num_cpus; 1542 average.threads.aperf /= topo.num_cpus; 1543 average.threads.mperf /= topo.num_cpus; 1544 average.threads.c1 /= topo.num_cpus; 1545 1546 if (average.threads.irq_count > 9999999) 1547 sums_need_wide_columns = 1; 1548 1549 average.cores.c3 /= topo.num_cores; 1550 average.cores.c6 /= topo.num_cores; 1551 average.cores.c7 /= topo.num_cores; 1552 average.cores.mc6_us /= topo.num_cores; 1553 1554 if (DO_BIC(BIC_Totl_c0)) 1555 average.packages.pkg_wtd_core_c0 /= topo.num_packages; 1556 if (DO_BIC(BIC_Any_c0)) 1557 average.packages.pkg_any_core_c0 /= topo.num_packages; 1558 if (DO_BIC(BIC_GFX_c0)) 1559 average.packages.pkg_any_gfxe_c0 /= topo.num_packages; 1560 if (DO_BIC(BIC_CPUGFX)) 1561 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages; 1562 1563 average.packages.pc2 /= topo.num_packages; 1564 if (DO_BIC(BIC_Pkgpc3)) 1565 average.packages.pc3 /= topo.num_packages; 1566 if (DO_BIC(BIC_Pkgpc6)) 1567 average.packages.pc6 /= topo.num_packages; 1568 if (DO_BIC(BIC_Pkgpc7)) 1569 average.packages.pc7 /= topo.num_packages; 1570 1571 average.packages.pc8 /= topo.num_packages; 1572 average.packages.pc9 /= topo.num_packages; 1573 average.packages.pc10 /= topo.num_packages; 1574 1575 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1576 if (mp->format == FORMAT_RAW) 1577 continue; 1578 if (mp->type == COUNTER_ITEMS) { 1579 if (average.threads.counter[i] > 9999999) 1580 sums_need_wide_columns = 1; 1581 continue; 1582 } 1583 average.threads.counter[i] /= topo.num_cpus; 1584 } 1585 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1586 if (mp->format == FORMAT_RAW) 1587 continue; 1588 if (mp->type == COUNTER_ITEMS) { 1589 if (average.cores.counter[i] > 9999999) 1590 sums_need_wide_columns = 1; 1591 } 1592 average.cores.counter[i] /= topo.num_cores; 1593 } 1594 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1595 if (mp->format == FORMAT_RAW) 1596 continue; 1597 if (mp->type == COUNTER_ITEMS) { 1598 if (average.packages.counter[i] > 9999999) 1599 sums_need_wide_columns = 1; 1600 } 1601 average.packages.counter[i] /= topo.num_packages; 1602 } 1603 } 1604 1605 static unsigned long long rdtsc(void) 1606 { 1607 unsigned int low, high; 1608 1609 asm volatile("rdtsc" : "=a" (low), "=d" (high)); 1610 1611 return low | ((unsigned long long)high) << 32; 1612 } 1613 1614 /* 1615 * Open a file, and exit on failure 1616 */ 1617 FILE *fopen_or_die(const char *path, const char *mode) 1618 { 1619 FILE *filep = fopen(path, mode); 1620 1621 if (!filep) 1622 err(1, "%s: open failed", path); 1623 return filep; 1624 } 1625 /* 1626 * snapshot_sysfs_counter() 1627 * 1628 * return snapshot of given counter 1629 */ 1630 unsigned long long snapshot_sysfs_counter(char *path) 1631 { 1632 FILE *fp; 1633 int retval; 1634 unsigned long long counter; 1635 1636 fp = fopen_or_die(path, "r"); 1637 1638 retval = fscanf(fp, "%lld", &counter); 1639 if (retval != 1) 1640 err(1, "snapshot_sysfs_counter(%s)", path); 1641 1642 fclose(fp); 1643 1644 return counter; 1645 } 1646 1647 int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp) 1648 { 1649 if (mp->msr_num != 0) { 1650 if (get_msr(cpu, mp->msr_num, counterp)) 1651 return -1; 1652 } else { 1653 char path[128 + PATH_BYTES]; 1654 1655 if (mp->flags & SYSFS_PERCPU) { 1656 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s", 1657 cpu, mp->path); 1658 1659 *counterp = snapshot_sysfs_counter(path); 1660 } else { 1661 *counterp = snapshot_sysfs_counter(mp->path); 1662 } 1663 } 1664 1665 return 0; 1666 } 1667 1668 void get_apic_id(struct thread_data *t) 1669 { 1670 unsigned int eax, ebx, ecx, edx; 1671 1672 if (DO_BIC(BIC_APIC)) { 1673 eax = ebx = ecx = edx = 0; 1674 __cpuid(1, eax, ebx, ecx, edx); 1675 1676 t->apic_id = (ebx >> 24) & 0xff; 1677 } 1678 1679 if (!DO_BIC(BIC_X2APIC)) 1680 return; 1681 1682 if (authentic_amd) { 1683 unsigned int topology_extensions; 1684 1685 if (max_extended_level < 0x8000001e) 1686 return; 1687 1688 eax = ebx = ecx = edx = 0; 1689 __cpuid(0x80000001, eax, ebx, ecx, edx); 1690 topology_extensions = ecx & (1 << 22); 1691 1692 if (topology_extensions == 0) 1693 return; 1694 1695 eax = ebx = ecx = edx = 0; 1696 __cpuid(0x8000001e, eax, ebx, ecx, edx); 1697 1698 t->x2apic_id = eax; 1699 return; 1700 } 1701 1702 if (!genuine_intel) 1703 return; 1704 1705 if (max_level < 0xb) 1706 return; 1707 1708 ecx = 0; 1709 __cpuid(0xb, eax, ebx, ecx, edx); 1710 t->x2apic_id = edx; 1711 1712 if (debug && (t->apic_id != (t->x2apic_id & 0xff))) 1713 fprintf(outf, "cpu%d: BIOS BUG: apic 0x%x x2apic 0x%x\n", 1714 t->cpu_id, t->apic_id, t->x2apic_id); 1715 } 1716 1717 /* 1718 * get_counters(...) 1719 * migrate to cpu 1720 * acquire and record local counters for that cpu 1721 */ 1722 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1723 { 1724 int cpu = t->cpu_id; 1725 unsigned long long msr; 1726 int aperf_mperf_retry_count = 0; 1727 struct msr_counter *mp; 1728 int i; 1729 1730 gettimeofday(&t->tv_begin, (struct timezone *)NULL); 1731 1732 if (cpu_migrate(cpu)) { 1733 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 1734 return -1; 1735 } 1736 1737 if (first_counter_read) 1738 get_apic_id(t); 1739 retry: 1740 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 1741 1742 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) { 1743 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; 1744 1745 /* 1746 * The TSC, APERF and MPERF must be read together for 1747 * APERF/MPERF and MPERF/TSC to give accurate results. 1748 * 1749 * Unfortunately, APERF and MPERF are read by 1750 * individual system call, so delays may occur 1751 * between them. If the time to read them 1752 * varies by a large amount, we re-read them. 1753 */ 1754 1755 /* 1756 * This initial dummy APERF read has been seen to 1757 * reduce jitter in the subsequent reads. 1758 */ 1759 1760 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1761 return -3; 1762 1763 t->tsc = rdtsc(); /* re-read close to APERF */ 1764 1765 tsc_before = t->tsc; 1766 1767 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1768 return -3; 1769 1770 tsc_between = rdtsc(); 1771 1772 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) 1773 return -4; 1774 1775 tsc_after = rdtsc(); 1776 1777 aperf_time = tsc_between - tsc_before; 1778 mperf_time = tsc_after - tsc_between; 1779 1780 /* 1781 * If the system call latency to read APERF and MPERF 1782 * differ by more than 2x, then try again. 1783 */ 1784 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { 1785 aperf_mperf_retry_count++; 1786 if (aperf_mperf_retry_count < 5) 1787 goto retry; 1788 else 1789 warnx("cpu%d jitter %lld %lld", 1790 cpu, aperf_time, mperf_time); 1791 } 1792 aperf_mperf_retry_count = 0; 1793 1794 t->aperf = t->aperf * aperf_mperf_multiplier; 1795 t->mperf = t->mperf * aperf_mperf_multiplier; 1796 } 1797 1798 if (DO_BIC(BIC_IRQ)) 1799 t->irq_count = irqs_per_cpu[cpu]; 1800 if (DO_BIC(BIC_SMI)) { 1801 if (get_msr(cpu, MSR_SMI_COUNT, &msr)) 1802 return -5; 1803 t->smi_count = msr & 0xFFFFFFFF; 1804 } 1805 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) { 1806 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) 1807 return -6; 1808 } 1809 1810 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1811 if (get_mp(cpu, mp, &t->counter[i])) 1812 return -10; 1813 } 1814 1815 /* collect core counters only for 1st thread in core */ 1816 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1817 goto done; 1818 1819 if (DO_BIC(BIC_CPU_c3)) { 1820 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) 1821 return -6; 1822 } 1823 1824 if (DO_BIC(BIC_CPU_c6) && !do_knl_cstates) { 1825 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) 1826 return -7; 1827 } else if (do_knl_cstates) { 1828 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) 1829 return -7; 1830 } 1831 1832 if (DO_BIC(BIC_CPU_c7)) 1833 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 1834 return -8; 1835 1836 if (DO_BIC(BIC_Mod_c6)) 1837 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us)) 1838 return -8; 1839 1840 if (DO_BIC(BIC_CoreTmp)) { 1841 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 1842 return -9; 1843 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1844 } 1845 1846 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1847 if (get_mp(cpu, mp, &c->counter[i])) 1848 return -10; 1849 } 1850 1851 /* collect package counters only for 1st core in package */ 1852 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1853 goto done; 1854 1855 if (DO_BIC(BIC_Totl_c0)) { 1856 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) 1857 return -10; 1858 } 1859 if (DO_BIC(BIC_Any_c0)) { 1860 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) 1861 return -11; 1862 } 1863 if (DO_BIC(BIC_GFX_c0)) { 1864 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) 1865 return -12; 1866 } 1867 if (DO_BIC(BIC_CPUGFX)) { 1868 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) 1869 return -13; 1870 } 1871 if (DO_BIC(BIC_Pkgpc3)) 1872 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) 1873 return -9; 1874 if (DO_BIC(BIC_Pkgpc6)) { 1875 if (do_slm_cstates) { 1876 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6)) 1877 return -10; 1878 } else { 1879 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) 1880 return -10; 1881 } 1882 } 1883 1884 if (DO_BIC(BIC_Pkgpc2)) 1885 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) 1886 return -11; 1887 if (DO_BIC(BIC_Pkgpc7)) 1888 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) 1889 return -12; 1890 if (DO_BIC(BIC_Pkgpc8)) 1891 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) 1892 return -13; 1893 if (DO_BIC(BIC_Pkgpc9)) 1894 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) 1895 return -13; 1896 if (DO_BIC(BIC_Pkgpc10)) 1897 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) 1898 return -13; 1899 1900 if (DO_BIC(BIC_CPU_LPI)) 1901 p->cpu_lpi = cpuidle_cur_cpu_lpi_us; 1902 if (DO_BIC(BIC_SYS_LPI)) 1903 p->sys_lpi = cpuidle_cur_sys_lpi_us; 1904 1905 if (do_rapl & RAPL_PKG) { 1906 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr)) 1907 return -13; 1908 p->energy_pkg = msr & 0xFFFFFFFF; 1909 } 1910 if (do_rapl & RAPL_CORES_ENERGY_STATUS) { 1911 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr)) 1912 return -14; 1913 p->energy_cores = msr & 0xFFFFFFFF; 1914 } 1915 if (do_rapl & RAPL_DRAM) { 1916 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) 1917 return -15; 1918 p->energy_dram = msr & 0xFFFFFFFF; 1919 } 1920 if (do_rapl & RAPL_GFX) { 1921 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr)) 1922 return -16; 1923 p->energy_gfx = msr & 0xFFFFFFFF; 1924 } 1925 if (do_rapl & RAPL_PKG_PERF_STATUS) { 1926 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr)) 1927 return -16; 1928 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF; 1929 } 1930 if (do_rapl & RAPL_DRAM_PERF_STATUS) { 1931 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr)) 1932 return -16; 1933 p->rapl_dram_perf_status = msr & 0xFFFFFFFF; 1934 } 1935 if (DO_BIC(BIC_PkgTmp)) { 1936 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 1937 return -17; 1938 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1939 } 1940 1941 if (DO_BIC(BIC_GFX_rc6)) 1942 p->gfx_rc6_ms = gfx_cur_rc6_ms; 1943 1944 if (DO_BIC(BIC_GFXMHz)) 1945 p->gfx_mhz = gfx_cur_mhz; 1946 1947 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1948 if (get_mp(cpu, mp, &p->counter[i])) 1949 return -10; 1950 } 1951 done: 1952 gettimeofday(&t->tv_end, (struct timezone *)NULL); 1953 1954 return 0; 1955 } 1956 1957 /* 1958 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: 1959 * If you change the values, note they are used both in comparisons 1960 * (>= PCL__7) and to index pkg_cstate_limit_strings[]. 1961 */ 1962 1963 #define PCLUKN 0 /* Unknown */ 1964 #define PCLRSV 1 /* Reserved */ 1965 #define PCL__0 2 /* PC0 */ 1966 #define PCL__1 3 /* PC1 */ 1967 #define PCL__2 4 /* PC2 */ 1968 #define PCL__3 5 /* PC3 */ 1969 #define PCL__4 6 /* PC4 */ 1970 #define PCL__6 7 /* PC6 */ 1971 #define PCL_6N 8 /* PC6 No Retention */ 1972 #define PCL_6R 9 /* PC6 Retention */ 1973 #define PCL__7 10 /* PC7 */ 1974 #define PCL_7S 11 /* PC7 Shrink */ 1975 #define PCL__8 12 /* PC8 */ 1976 #define PCL__9 13 /* PC9 */ 1977 #define PCL_10 14 /* PC10 */ 1978 #define PCLUNL 15 /* Unlimited */ 1979 1980 int pkg_cstate_limit = PCLUKN; 1981 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", 1982 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "pc10", "unlimited"}; 1983 1984 int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1985 int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1986 int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1987 int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7}; 1988 int amt_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1989 int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1990 int glm_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCL_10, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1991 int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1992 1993 1994 static void 1995 calculate_tsc_tweak() 1996 { 1997 tsc_tweak = base_hz / tsc_hz; 1998 } 1999 2000 static void 2001 dump_nhm_platform_info(void) 2002 { 2003 unsigned long long msr; 2004 unsigned int ratio; 2005 2006 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 2007 2008 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 2009 2010 ratio = (msr >> 40) & 0xFF; 2011 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", 2012 ratio, bclk, ratio * bclk); 2013 2014 ratio = (msr >> 8) & 0xFF; 2015 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", 2016 ratio, bclk, ratio * bclk); 2017 2018 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); 2019 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", 2020 base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); 2021 2022 return; 2023 } 2024 2025 static void 2026 dump_hsw_turbo_ratio_limits(void) 2027 { 2028 unsigned long long msr; 2029 unsigned int ratio; 2030 2031 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); 2032 2033 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); 2034 2035 ratio = (msr >> 8) & 0xFF; 2036 if (ratio) 2037 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", 2038 ratio, bclk, ratio * bclk); 2039 2040 ratio = (msr >> 0) & 0xFF; 2041 if (ratio) 2042 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", 2043 ratio, bclk, ratio * bclk); 2044 return; 2045 } 2046 2047 static void 2048 dump_ivt_turbo_ratio_limits(void) 2049 { 2050 unsigned long long msr; 2051 unsigned int ratio; 2052 2053 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); 2054 2055 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); 2056 2057 ratio = (msr >> 56) & 0xFF; 2058 if (ratio) 2059 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", 2060 ratio, bclk, ratio * bclk); 2061 2062 ratio = (msr >> 48) & 0xFF; 2063 if (ratio) 2064 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", 2065 ratio, bclk, ratio * bclk); 2066 2067 ratio = (msr >> 40) & 0xFF; 2068 if (ratio) 2069 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", 2070 ratio, bclk, ratio * bclk); 2071 2072 ratio = (msr >> 32) & 0xFF; 2073 if (ratio) 2074 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", 2075 ratio, bclk, ratio * bclk); 2076 2077 ratio = (msr >> 24) & 0xFF; 2078 if (ratio) 2079 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", 2080 ratio, bclk, ratio * bclk); 2081 2082 ratio = (msr >> 16) & 0xFF; 2083 if (ratio) 2084 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", 2085 ratio, bclk, ratio * bclk); 2086 2087 ratio = (msr >> 8) & 0xFF; 2088 if (ratio) 2089 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", 2090 ratio, bclk, ratio * bclk); 2091 2092 ratio = (msr >> 0) & 0xFF; 2093 if (ratio) 2094 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", 2095 ratio, bclk, ratio * bclk); 2096 return; 2097 } 2098 int has_turbo_ratio_group_limits(int family, int model) 2099 { 2100 2101 if (!genuine_intel) 2102 return 0; 2103 2104 switch (model) { 2105 case INTEL_FAM6_ATOM_GOLDMONT: 2106 case INTEL_FAM6_SKYLAKE_X: 2107 case INTEL_FAM6_ATOM_GOLDMONT_X: 2108 return 1; 2109 } 2110 return 0; 2111 } 2112 2113 static void 2114 dump_turbo_ratio_limits(int family, int model) 2115 { 2116 unsigned long long msr, core_counts; 2117 unsigned int ratio, group_size; 2118 2119 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2120 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 2121 2122 if (has_turbo_ratio_group_limits(family, model)) { 2123 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts); 2124 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts); 2125 } else { 2126 core_counts = 0x0807060504030201; 2127 } 2128 2129 ratio = (msr >> 56) & 0xFF; 2130 group_size = (core_counts >> 56) & 0xFF; 2131 if (ratio) 2132 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2133 ratio, bclk, ratio * bclk, group_size); 2134 2135 ratio = (msr >> 48) & 0xFF; 2136 group_size = (core_counts >> 48) & 0xFF; 2137 if (ratio) 2138 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2139 ratio, bclk, ratio * bclk, group_size); 2140 2141 ratio = (msr >> 40) & 0xFF; 2142 group_size = (core_counts >> 40) & 0xFF; 2143 if (ratio) 2144 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2145 ratio, bclk, ratio * bclk, group_size); 2146 2147 ratio = (msr >> 32) & 0xFF; 2148 group_size = (core_counts >> 32) & 0xFF; 2149 if (ratio) 2150 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2151 ratio, bclk, ratio * bclk, group_size); 2152 2153 ratio = (msr >> 24) & 0xFF; 2154 group_size = (core_counts >> 24) & 0xFF; 2155 if (ratio) 2156 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2157 ratio, bclk, ratio * bclk, group_size); 2158 2159 ratio = (msr >> 16) & 0xFF; 2160 group_size = (core_counts >> 16) & 0xFF; 2161 if (ratio) 2162 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2163 ratio, bclk, ratio * bclk, group_size); 2164 2165 ratio = (msr >> 8) & 0xFF; 2166 group_size = (core_counts >> 8) & 0xFF; 2167 if (ratio) 2168 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2169 ratio, bclk, ratio * bclk, group_size); 2170 2171 ratio = (msr >> 0) & 0xFF; 2172 group_size = (core_counts >> 0) & 0xFF; 2173 if (ratio) 2174 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2175 ratio, bclk, ratio * bclk, group_size); 2176 return; 2177 } 2178 2179 static void 2180 dump_atom_turbo_ratio_limits(void) 2181 { 2182 unsigned long long msr; 2183 unsigned int ratio; 2184 2185 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr); 2186 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2187 2188 ratio = (msr >> 0) & 0x3F; 2189 if (ratio) 2190 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", 2191 ratio, bclk, ratio * bclk); 2192 2193 ratio = (msr >> 8) & 0x3F; 2194 if (ratio) 2195 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", 2196 ratio, bclk, ratio * bclk); 2197 2198 ratio = (msr >> 16) & 0x3F; 2199 if (ratio) 2200 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", 2201 ratio, bclk, ratio * bclk); 2202 2203 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr); 2204 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2205 2206 ratio = (msr >> 24) & 0x3F; 2207 if (ratio) 2208 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", 2209 ratio, bclk, ratio * bclk); 2210 2211 ratio = (msr >> 16) & 0x3F; 2212 if (ratio) 2213 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", 2214 ratio, bclk, ratio * bclk); 2215 2216 ratio = (msr >> 8) & 0x3F; 2217 if (ratio) 2218 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", 2219 ratio, bclk, ratio * bclk); 2220 2221 ratio = (msr >> 0) & 0x3F; 2222 if (ratio) 2223 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", 2224 ratio, bclk, ratio * bclk); 2225 } 2226 2227 static void 2228 dump_knl_turbo_ratio_limits(void) 2229 { 2230 const unsigned int buckets_no = 7; 2231 2232 unsigned long long msr; 2233 int delta_cores, delta_ratio; 2234 int i, b_nr; 2235 unsigned int cores[buckets_no]; 2236 unsigned int ratio[buckets_no]; 2237 2238 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2239 2240 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", 2241 base_cpu, msr); 2242 2243 /** 2244 * Turbo encoding in KNL is as follows: 2245 * [0] -- Reserved 2246 * [7:1] -- Base value of number of active cores of bucket 1. 2247 * [15:8] -- Base value of freq ratio of bucket 1. 2248 * [20:16] -- +ve delta of number of active cores of bucket 2. 2249 * i.e. active cores of bucket 2 = 2250 * active cores of bucket 1 + delta 2251 * [23:21] -- Negative delta of freq ratio of bucket 2. 2252 * i.e. freq ratio of bucket 2 = 2253 * freq ratio of bucket 1 - delta 2254 * [28:24]-- +ve delta of number of active cores of bucket 3. 2255 * [31:29]-- -ve delta of freq ratio of bucket 3. 2256 * [36:32]-- +ve delta of number of active cores of bucket 4. 2257 * [39:37]-- -ve delta of freq ratio of bucket 4. 2258 * [44:40]-- +ve delta of number of active cores of bucket 5. 2259 * [47:45]-- -ve delta of freq ratio of bucket 5. 2260 * [52:48]-- +ve delta of number of active cores of bucket 6. 2261 * [55:53]-- -ve delta of freq ratio of bucket 6. 2262 * [60:56]-- +ve delta of number of active cores of bucket 7. 2263 * [63:61]-- -ve delta of freq ratio of bucket 7. 2264 */ 2265 2266 b_nr = 0; 2267 cores[b_nr] = (msr & 0xFF) >> 1; 2268 ratio[b_nr] = (msr >> 8) & 0xFF; 2269 2270 for (i = 16; i < 64; i += 8) { 2271 delta_cores = (msr >> i) & 0x1F; 2272 delta_ratio = (msr >> (i + 5)) & 0x7; 2273 2274 cores[b_nr + 1] = cores[b_nr] + delta_cores; 2275 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; 2276 b_nr++; 2277 } 2278 2279 for (i = buckets_no - 1; i >= 0; i--) 2280 if (i > 0 ? ratio[i] != ratio[i - 1] : 1) 2281 fprintf(outf, 2282 "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2283 ratio[i], bclk, ratio[i] * bclk, cores[i]); 2284 } 2285 2286 static void 2287 dump_nhm_cst_cfg(void) 2288 { 2289 unsigned long long msr; 2290 2291 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 2292 2293 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr); 2294 2295 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)", 2296 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", 2297 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", 2298 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", 2299 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", 2300 (msr & (1 << 15)) ? "" : "UN", 2301 (unsigned int)msr & 0xF, 2302 pkg_cstate_limit_strings[pkg_cstate_limit]); 2303 2304 #define AUTOMATIC_CSTATE_CONVERSION (1UL << 16) 2305 if (has_automatic_cstate_conversion) { 2306 fprintf(outf, ", automatic c-state conversion=%s", 2307 (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off"); 2308 } 2309 2310 fprintf(outf, ")\n"); 2311 2312 return; 2313 } 2314 2315 static void 2316 dump_config_tdp(void) 2317 { 2318 unsigned long long msr; 2319 2320 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); 2321 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); 2322 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); 2323 2324 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); 2325 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); 2326 if (msr) { 2327 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2328 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2329 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2330 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); 2331 } 2332 fprintf(outf, ")\n"); 2333 2334 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); 2335 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); 2336 if (msr) { 2337 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2338 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2339 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2340 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); 2341 } 2342 fprintf(outf, ")\n"); 2343 2344 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); 2345 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); 2346 if ((msr) & 0x3) 2347 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); 2348 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2349 fprintf(outf, ")\n"); 2350 2351 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); 2352 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); 2353 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); 2354 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2355 fprintf(outf, ")\n"); 2356 } 2357 2358 unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; 2359 2360 void print_irtl(void) 2361 { 2362 unsigned long long msr; 2363 2364 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr); 2365 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr); 2366 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2367 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2368 2369 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr); 2370 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr); 2371 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2372 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2373 2374 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr); 2375 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr); 2376 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2377 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2378 2379 if (!do_irtl_hsw) 2380 return; 2381 2382 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr); 2383 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr); 2384 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2385 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2386 2387 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr); 2388 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr); 2389 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2390 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2391 2392 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr); 2393 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr); 2394 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2395 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2396 2397 } 2398 void free_fd_percpu(void) 2399 { 2400 int i; 2401 2402 for (i = 0; i < topo.max_cpu_num + 1; ++i) { 2403 if (fd_percpu[i] != 0) 2404 close(fd_percpu[i]); 2405 } 2406 2407 free(fd_percpu); 2408 } 2409 2410 void free_all_buffers(void) 2411 { 2412 int i; 2413 2414 CPU_FREE(cpu_present_set); 2415 cpu_present_set = NULL; 2416 cpu_present_setsize = 0; 2417 2418 CPU_FREE(cpu_affinity_set); 2419 cpu_affinity_set = NULL; 2420 cpu_affinity_setsize = 0; 2421 2422 free(thread_even); 2423 free(core_even); 2424 free(package_even); 2425 2426 thread_even = NULL; 2427 core_even = NULL; 2428 package_even = NULL; 2429 2430 free(thread_odd); 2431 free(core_odd); 2432 free(package_odd); 2433 2434 thread_odd = NULL; 2435 core_odd = NULL; 2436 package_odd = NULL; 2437 2438 free(output_buffer); 2439 output_buffer = NULL; 2440 outp = NULL; 2441 2442 free_fd_percpu(); 2443 2444 free(irq_column_2_cpu); 2445 free(irqs_per_cpu); 2446 2447 for (i = 0; i <= topo.max_cpu_num; ++i) { 2448 if (cpus[i].put_ids) 2449 CPU_FREE(cpus[i].put_ids); 2450 } 2451 free(cpus); 2452 } 2453 2454 2455 /* 2456 * Parse a file containing a single int. 2457 */ 2458 int parse_int_file(const char *fmt, ...) 2459 { 2460 va_list args; 2461 char path[PATH_MAX]; 2462 FILE *filep; 2463 int value; 2464 2465 va_start(args, fmt); 2466 vsnprintf(path, sizeof(path), fmt, args); 2467 va_end(args); 2468 filep = fopen_or_die(path, "r"); 2469 if (fscanf(filep, "%d", &value) != 1) 2470 err(1, "%s: failed to parse number from file", path); 2471 fclose(filep); 2472 return value; 2473 } 2474 2475 /* 2476 * cpu_is_first_core_in_package(cpu) 2477 * return 1 if given CPU is 1st core in package 2478 */ 2479 int cpu_is_first_core_in_package(int cpu) 2480 { 2481 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); 2482 } 2483 2484 int get_physical_package_id(int cpu) 2485 { 2486 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); 2487 } 2488 2489 int get_core_id(int cpu) 2490 { 2491 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); 2492 } 2493 2494 void set_node_data(void) 2495 { 2496 int pkg, node, lnode, cpu, cpux; 2497 int cpu_count; 2498 2499 /* initialize logical_node_id */ 2500 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) 2501 cpus[cpu].logical_node_id = -1; 2502 2503 cpu_count = 0; 2504 for (pkg = 0; pkg < topo.num_packages; pkg++) { 2505 lnode = 0; 2506 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) { 2507 if (cpus[cpu].physical_package_id != pkg) 2508 continue; 2509 /* find a cpu with an unset logical_node_id */ 2510 if (cpus[cpu].logical_node_id != -1) 2511 continue; 2512 cpus[cpu].logical_node_id = lnode; 2513 node = cpus[cpu].physical_node_id; 2514 cpu_count++; 2515 /* 2516 * find all matching cpus on this pkg and set 2517 * the logical_node_id 2518 */ 2519 for (cpux = cpu; cpux <= topo.max_cpu_num; cpux++) { 2520 if ((cpus[cpux].physical_package_id == pkg) && 2521 (cpus[cpux].physical_node_id == node)) { 2522 cpus[cpux].logical_node_id = lnode; 2523 cpu_count++; 2524 } 2525 } 2526 lnode++; 2527 if (lnode > topo.nodes_per_pkg) 2528 topo.nodes_per_pkg = lnode; 2529 } 2530 if (cpu_count >= topo.max_cpu_num) 2531 break; 2532 } 2533 } 2534 2535 int get_physical_node_id(struct cpu_topology *thiscpu) 2536 { 2537 char path[80]; 2538 FILE *filep; 2539 int i; 2540 int cpu = thiscpu->logical_cpu_id; 2541 2542 for (i = 0; i <= topo.max_cpu_num; i++) { 2543 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist", 2544 cpu, i); 2545 filep = fopen(path, "r"); 2546 if (!filep) 2547 continue; 2548 fclose(filep); 2549 return i; 2550 } 2551 return -1; 2552 } 2553 2554 int get_thread_siblings(struct cpu_topology *thiscpu) 2555 { 2556 char path[80], character; 2557 FILE *filep; 2558 unsigned long map; 2559 int so, shift, sib_core; 2560 int cpu = thiscpu->logical_cpu_id; 2561 int offset = topo.max_cpu_num + 1; 2562 size_t size; 2563 int thread_id = 0; 2564 2565 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1)); 2566 if (thiscpu->thread_id < 0) 2567 thiscpu->thread_id = thread_id++; 2568 if (!thiscpu->put_ids) 2569 return -1; 2570 2571 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 2572 CPU_ZERO_S(size, thiscpu->put_ids); 2573 2574 sprintf(path, 2575 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu); 2576 filep = fopen_or_die(path, "r"); 2577 do { 2578 offset -= BITMASK_SIZE; 2579 fscanf(filep, "%lx%c", &map, &character); 2580 for (shift = 0; shift < BITMASK_SIZE; shift++) { 2581 if ((map >> shift) & 0x1) { 2582 so = shift + offset; 2583 sib_core = get_core_id(so); 2584 if (sib_core == thiscpu->physical_core_id) { 2585 CPU_SET_S(so, size, thiscpu->put_ids); 2586 if ((so != cpu) && 2587 (cpus[so].thread_id < 0)) 2588 cpus[so].thread_id = 2589 thread_id++; 2590 } 2591 } 2592 } 2593 } while (!strncmp(&character, ",", 1)); 2594 fclose(filep); 2595 2596 return CPU_COUNT_S(size, thiscpu->put_ids); 2597 } 2598 2599 /* 2600 * run func(thread, core, package) in topology order 2601 * skip non-present cpus 2602 */ 2603 2604 int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *, 2605 struct pkg_data *, struct thread_data *, struct core_data *, 2606 struct pkg_data *), struct thread_data *thread_base, 2607 struct core_data *core_base, struct pkg_data *pkg_base, 2608 struct thread_data *thread_base2, struct core_data *core_base2, 2609 struct pkg_data *pkg_base2) 2610 { 2611 int retval, pkg_no, node_no, core_no, thread_no; 2612 2613 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 2614 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) { 2615 for (core_no = 0; core_no < topo.cores_per_node; 2616 ++core_no) { 2617 for (thread_no = 0; thread_no < 2618 topo.threads_per_core; ++thread_no) { 2619 struct thread_data *t, *t2; 2620 struct core_data *c, *c2; 2621 struct pkg_data *p, *p2; 2622 2623 t = GET_THREAD(thread_base, thread_no, 2624 core_no, node_no, 2625 pkg_no); 2626 2627 if (cpu_is_not_present(t->cpu_id)) 2628 continue; 2629 2630 t2 = GET_THREAD(thread_base2, thread_no, 2631 core_no, node_no, 2632 pkg_no); 2633 2634 c = GET_CORE(core_base, core_no, 2635 node_no, pkg_no); 2636 c2 = GET_CORE(core_base2, core_no, 2637 node_no, 2638 pkg_no); 2639 2640 p = GET_PKG(pkg_base, pkg_no); 2641 p2 = GET_PKG(pkg_base2, pkg_no); 2642 2643 retval = func(t, c, p, t2, c2, p2); 2644 if (retval) 2645 return retval; 2646 } 2647 } 2648 } 2649 } 2650 return 0; 2651 } 2652 2653 /* 2654 * run func(cpu) on every cpu in /proc/stat 2655 * return max_cpu number 2656 */ 2657 int for_all_proc_cpus(int (func)(int)) 2658 { 2659 FILE *fp; 2660 int cpu_num; 2661 int retval; 2662 2663 fp = fopen_or_die(proc_stat, "r"); 2664 2665 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); 2666 if (retval != 0) 2667 err(1, "%s: failed to parse format", proc_stat); 2668 2669 while (1) { 2670 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); 2671 if (retval != 1) 2672 break; 2673 2674 retval = func(cpu_num); 2675 if (retval) { 2676 fclose(fp); 2677 return(retval); 2678 } 2679 } 2680 fclose(fp); 2681 return 0; 2682 } 2683 2684 void re_initialize(void) 2685 { 2686 free_all_buffers(); 2687 setup_all_buffers(); 2688 printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); 2689 } 2690 2691 void set_max_cpu_num(void) 2692 { 2693 FILE *filep; 2694 unsigned long dummy; 2695 2696 topo.max_cpu_num = 0; 2697 filep = fopen_or_die( 2698 "/sys/devices/system/cpu/cpu0/topology/thread_siblings", 2699 "r"); 2700 while (fscanf(filep, "%lx,", &dummy) == 1) 2701 topo.max_cpu_num += BITMASK_SIZE; 2702 fclose(filep); 2703 topo.max_cpu_num--; /* 0 based */ 2704 } 2705 2706 /* 2707 * count_cpus() 2708 * remember the last one seen, it will be the max 2709 */ 2710 int count_cpus(int cpu) 2711 { 2712 topo.num_cpus++; 2713 return 0; 2714 } 2715 int mark_cpu_present(int cpu) 2716 { 2717 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); 2718 return 0; 2719 } 2720 2721 int init_thread_id(int cpu) 2722 { 2723 cpus[cpu].thread_id = -1; 2724 return 0; 2725 } 2726 2727 /* 2728 * snapshot_proc_interrupts() 2729 * 2730 * read and record summary of /proc/interrupts 2731 * 2732 * return 1 if config change requires a restart, else return 0 2733 */ 2734 int snapshot_proc_interrupts(void) 2735 { 2736 static FILE *fp; 2737 int column, retval; 2738 2739 if (fp == NULL) 2740 fp = fopen_or_die("/proc/interrupts", "r"); 2741 else 2742 rewind(fp); 2743 2744 /* read 1st line of /proc/interrupts to get cpu* name for each column */ 2745 for (column = 0; column < topo.num_cpus; ++column) { 2746 int cpu_number; 2747 2748 retval = fscanf(fp, " CPU%d", &cpu_number); 2749 if (retval != 1) 2750 break; 2751 2752 if (cpu_number > topo.max_cpu_num) { 2753 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); 2754 return 1; 2755 } 2756 2757 irq_column_2_cpu[column] = cpu_number; 2758 irqs_per_cpu[cpu_number] = 0; 2759 } 2760 2761 /* read /proc/interrupt count lines and sum up irqs per cpu */ 2762 while (1) { 2763 int column; 2764 char buf[64]; 2765 2766 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ 2767 if (retval != 1) 2768 break; 2769 2770 /* read the count per cpu */ 2771 for (column = 0; column < topo.num_cpus; ++column) { 2772 2773 int cpu_number, irq_count; 2774 2775 retval = fscanf(fp, " %d", &irq_count); 2776 if (retval != 1) 2777 break; 2778 2779 cpu_number = irq_column_2_cpu[column]; 2780 irqs_per_cpu[cpu_number] += irq_count; 2781 2782 } 2783 2784 while (getc(fp) != '\n') 2785 ; /* flush interrupt description */ 2786 2787 } 2788 return 0; 2789 } 2790 /* 2791 * snapshot_gfx_rc6_ms() 2792 * 2793 * record snapshot of 2794 * /sys/class/drm/card0/power/rc6_residency_ms 2795 * 2796 * return 1 if config change requires a restart, else return 0 2797 */ 2798 int snapshot_gfx_rc6_ms(void) 2799 { 2800 FILE *fp; 2801 int retval; 2802 2803 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); 2804 2805 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); 2806 if (retval != 1) 2807 err(1, "GFX rc6"); 2808 2809 fclose(fp); 2810 2811 return 0; 2812 } 2813 /* 2814 * snapshot_gfx_mhz() 2815 * 2816 * record snapshot of 2817 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz 2818 * 2819 * return 1 if config change requires a restart, else return 0 2820 */ 2821 int snapshot_gfx_mhz(void) 2822 { 2823 static FILE *fp; 2824 int retval; 2825 2826 if (fp == NULL) 2827 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); 2828 else { 2829 rewind(fp); 2830 fflush(fp); 2831 } 2832 2833 retval = fscanf(fp, "%d", &gfx_cur_mhz); 2834 if (retval != 1) 2835 err(1, "GFX MHz"); 2836 2837 return 0; 2838 } 2839 2840 /* 2841 * snapshot_cpu_lpi() 2842 * 2843 * record snapshot of 2844 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us 2845 * 2846 * return 1 if config change requires a restart, else return 0 2847 */ 2848 int snapshot_cpu_lpi_us(void) 2849 { 2850 FILE *fp; 2851 int retval; 2852 2853 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r"); 2854 2855 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us); 2856 if (retval != 1) 2857 err(1, "CPU LPI"); 2858 2859 fclose(fp); 2860 2861 return 0; 2862 } 2863 /* 2864 * snapshot_sys_lpi() 2865 * 2866 * record snapshot of 2867 * /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us 2868 * 2869 * return 1 if config change requires a restart, else return 0 2870 */ 2871 int snapshot_sys_lpi_us(void) 2872 { 2873 FILE *fp; 2874 int retval; 2875 2876 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us", "r"); 2877 2878 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us); 2879 if (retval != 1) 2880 err(1, "SYS LPI"); 2881 2882 fclose(fp); 2883 2884 return 0; 2885 } 2886 /* 2887 * snapshot /proc and /sys files 2888 * 2889 * return 1 if configuration restart needed, else return 0 2890 */ 2891 int snapshot_proc_sysfs_files(void) 2892 { 2893 if (DO_BIC(BIC_IRQ)) 2894 if (snapshot_proc_interrupts()) 2895 return 1; 2896 2897 if (DO_BIC(BIC_GFX_rc6)) 2898 snapshot_gfx_rc6_ms(); 2899 2900 if (DO_BIC(BIC_GFXMHz)) 2901 snapshot_gfx_mhz(); 2902 2903 if (DO_BIC(BIC_CPU_LPI)) 2904 snapshot_cpu_lpi_us(); 2905 2906 if (DO_BIC(BIC_SYS_LPI)) 2907 snapshot_sys_lpi_us(); 2908 2909 return 0; 2910 } 2911 2912 int exit_requested; 2913 2914 static void signal_handler (int signal) 2915 { 2916 switch (signal) { 2917 case SIGINT: 2918 exit_requested = 1; 2919 if (debug) 2920 fprintf(stderr, " SIGINT\n"); 2921 break; 2922 case SIGUSR1: 2923 if (debug > 1) 2924 fprintf(stderr, "SIGUSR1\n"); 2925 break; 2926 } 2927 /* make sure this manually-invoked interval is at least 1ms long */ 2928 nanosleep(&one_msec, NULL); 2929 } 2930 2931 void setup_signal_handler(void) 2932 { 2933 struct sigaction sa; 2934 2935 memset(&sa, 0, sizeof(sa)); 2936 2937 sa.sa_handler = &signal_handler; 2938 2939 if (sigaction(SIGINT, &sa, NULL) < 0) 2940 err(1, "sigaction SIGINT"); 2941 if (sigaction(SIGUSR1, &sa, NULL) < 0) 2942 err(1, "sigaction SIGUSR1"); 2943 } 2944 2945 void do_sleep(void) 2946 { 2947 struct timeval select_timeout; 2948 fd_set readfds; 2949 int retval; 2950 2951 FD_ZERO(&readfds); 2952 FD_SET(0, &readfds); 2953 2954 if (!isatty(fileno(stdin))) { 2955 nanosleep(&interval_ts, NULL); 2956 return; 2957 } 2958 2959 select_timeout = interval_tv; 2960 retval = select(1, &readfds, NULL, NULL, &select_timeout); 2961 2962 if (retval == 1) { 2963 switch (getc(stdin)) { 2964 case 'q': 2965 exit_requested = 1; 2966 break; 2967 } 2968 /* make sure this manually-invoked interval is at least 1ms long */ 2969 nanosleep(&one_msec, NULL); 2970 } 2971 } 2972 2973 2974 void turbostat_loop() 2975 { 2976 int retval; 2977 int restarted = 0; 2978 int done_iters = 0; 2979 2980 setup_signal_handler(); 2981 2982 restart: 2983 restarted++; 2984 2985 snapshot_proc_sysfs_files(); 2986 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 2987 first_counter_read = 0; 2988 if (retval < -1) { 2989 exit(retval); 2990 } else if (retval == -1) { 2991 if (restarted > 1) { 2992 exit(retval); 2993 } 2994 re_initialize(); 2995 goto restart; 2996 } 2997 restarted = 0; 2998 done_iters = 0; 2999 gettimeofday(&tv_even, (struct timezone *)NULL); 3000 3001 while (1) { 3002 if (for_all_proc_cpus(cpu_is_not_present)) { 3003 re_initialize(); 3004 goto restart; 3005 } 3006 do_sleep(); 3007 if (snapshot_proc_sysfs_files()) 3008 goto restart; 3009 retval = for_all_cpus(get_counters, ODD_COUNTERS); 3010 if (retval < -1) { 3011 exit(retval); 3012 } else if (retval == -1) { 3013 re_initialize(); 3014 goto restart; 3015 } 3016 gettimeofday(&tv_odd, (struct timezone *)NULL); 3017 timersub(&tv_odd, &tv_even, &tv_delta); 3018 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) { 3019 re_initialize(); 3020 goto restart; 3021 } 3022 compute_average(EVEN_COUNTERS); 3023 format_all_counters(EVEN_COUNTERS); 3024 flush_output_stdout(); 3025 if (exit_requested) 3026 break; 3027 if (num_iterations && ++done_iters >= num_iterations) 3028 break; 3029 do_sleep(); 3030 if (snapshot_proc_sysfs_files()) 3031 goto restart; 3032 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3033 if (retval < -1) { 3034 exit(retval); 3035 } else if (retval == -1) { 3036 re_initialize(); 3037 goto restart; 3038 } 3039 gettimeofday(&tv_even, (struct timezone *)NULL); 3040 timersub(&tv_even, &tv_odd, &tv_delta); 3041 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) { 3042 re_initialize(); 3043 goto restart; 3044 } 3045 compute_average(ODD_COUNTERS); 3046 format_all_counters(ODD_COUNTERS); 3047 flush_output_stdout(); 3048 if (exit_requested) 3049 break; 3050 if (num_iterations && ++done_iters >= num_iterations) 3051 break; 3052 } 3053 } 3054 3055 void check_dev_msr() 3056 { 3057 struct stat sb; 3058 char pathname[32]; 3059 3060 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3061 if (stat(pathname, &sb)) 3062 if (system("/sbin/modprobe msr > /dev/null 2>&1")) 3063 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); 3064 } 3065 3066 void check_permissions() 3067 { 3068 struct __user_cap_header_struct cap_header_data; 3069 cap_user_header_t cap_header = &cap_header_data; 3070 struct __user_cap_data_struct cap_data_data; 3071 cap_user_data_t cap_data = &cap_data_data; 3072 extern int capget(cap_user_header_t hdrp, cap_user_data_t datap); 3073 int do_exit = 0; 3074 char pathname[32]; 3075 3076 /* check for CAP_SYS_RAWIO */ 3077 cap_header->pid = getpid(); 3078 cap_header->version = _LINUX_CAPABILITY_VERSION; 3079 if (capget(cap_header, cap_data) < 0) 3080 err(-6, "capget(2) failed"); 3081 3082 if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) { 3083 do_exit++; 3084 warnx("capget(CAP_SYS_RAWIO) failed," 3085 " try \"# setcap cap_sys_rawio=ep %s\"", progname); 3086 } 3087 3088 /* test file permissions */ 3089 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3090 if (euidaccess(pathname, R_OK)) { 3091 do_exit++; 3092 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); 3093 } 3094 3095 /* if all else fails, thell them to be root */ 3096 if (do_exit) 3097 if (getuid() != 0) 3098 warnx("... or simply run as root"); 3099 3100 if (do_exit) 3101 exit(-6); 3102 } 3103 3104 /* 3105 * NHM adds support for additional MSRs: 3106 * 3107 * MSR_SMI_COUNT 0x00000034 3108 * 3109 * MSR_PLATFORM_INFO 0x000000ce 3110 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 3111 * 3112 * MSR_MISC_PWR_MGMT 0x000001aa 3113 * 3114 * MSR_PKG_C3_RESIDENCY 0x000003f8 3115 * MSR_PKG_C6_RESIDENCY 0x000003f9 3116 * MSR_CORE_C3_RESIDENCY 0x000003fc 3117 * MSR_CORE_C6_RESIDENCY 0x000003fd 3118 * 3119 * Side effect: 3120 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL 3121 * sets has_misc_feature_control 3122 */ 3123 int probe_nhm_msrs(unsigned int family, unsigned int model) 3124 { 3125 unsigned long long msr; 3126 unsigned int base_ratio; 3127 int *pkg_cstate_limits; 3128 3129 if (!genuine_intel) 3130 return 0; 3131 3132 if (family != 6) 3133 return 0; 3134 3135 bclk = discover_bclk(family, model); 3136 3137 switch (model) { 3138 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 3139 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3140 pkg_cstate_limits = nhm_pkg_cstate_limits; 3141 break; 3142 case INTEL_FAM6_SANDYBRIDGE: /* SNB */ 3143 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */ 3144 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3145 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3146 pkg_cstate_limits = snb_pkg_cstate_limits; 3147 has_misc_feature_control = 1; 3148 break; 3149 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3150 case INTEL_FAM6_HASWELL_X: /* HSX */ 3151 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3152 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3153 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3154 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3155 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3156 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 3157 pkg_cstate_limits = hsw_pkg_cstate_limits; 3158 has_misc_feature_control = 1; 3159 break; 3160 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3161 pkg_cstate_limits = skx_pkg_cstate_limits; 3162 has_misc_feature_control = 1; 3163 break; 3164 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 3165 no_MSR_MISC_PWR_MGMT = 1; 3166 case INTEL_FAM6_ATOM_SILVERMONT_X: /* AVN */ 3167 pkg_cstate_limits = slv_pkg_cstate_limits; 3168 break; 3169 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */ 3170 pkg_cstate_limits = amt_pkg_cstate_limits; 3171 no_MSR_MISC_PWR_MGMT = 1; 3172 break; 3173 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */ 3174 pkg_cstate_limits = phi_pkg_cstate_limits; 3175 break; 3176 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3177 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 3178 case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */ 3179 pkg_cstate_limits = glm_pkg_cstate_limits; 3180 break; 3181 default: 3182 return 0; 3183 } 3184 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 3185 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; 3186 3187 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 3188 base_ratio = (msr >> 8) & 0xFF; 3189 3190 base_hz = base_ratio * bclk * 1000000; 3191 has_base_hz = 1; 3192 return 1; 3193 } 3194 /* 3195 * SLV client has support for unique MSRs: 3196 * 3197 * MSR_CC6_DEMOTION_POLICY_CONFIG 3198 * MSR_MC6_DEMOTION_POLICY_CONFIG 3199 */ 3200 3201 int has_slv_msrs(unsigned int family, unsigned int model) 3202 { 3203 if (!genuine_intel) 3204 return 0; 3205 3206 switch (model) { 3207 case INTEL_FAM6_ATOM_SILVERMONT: 3208 case INTEL_FAM6_ATOM_SILVERMONT_MID: 3209 case INTEL_FAM6_ATOM_AIRMONT_MID: 3210 return 1; 3211 } 3212 return 0; 3213 } 3214 int is_dnv(unsigned int family, unsigned int model) 3215 { 3216 3217 if (!genuine_intel) 3218 return 0; 3219 3220 switch (model) { 3221 case INTEL_FAM6_ATOM_GOLDMONT_X: 3222 return 1; 3223 } 3224 return 0; 3225 } 3226 int is_bdx(unsigned int family, unsigned int model) 3227 { 3228 3229 if (!genuine_intel) 3230 return 0; 3231 3232 switch (model) { 3233 case INTEL_FAM6_BROADWELL_X: 3234 return 1; 3235 } 3236 return 0; 3237 } 3238 int is_skx(unsigned int family, unsigned int model) 3239 { 3240 3241 if (!genuine_intel) 3242 return 0; 3243 3244 switch (model) { 3245 case INTEL_FAM6_SKYLAKE_X: 3246 return 1; 3247 } 3248 return 0; 3249 } 3250 3251 int has_turbo_ratio_limit(unsigned int family, unsigned int model) 3252 { 3253 if (has_slv_msrs(family, model)) 3254 return 0; 3255 3256 switch (model) { 3257 /* Nehalem compatible, but do not include turbo-ratio limit support */ 3258 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3259 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */ 3260 return 0; 3261 default: 3262 return 1; 3263 } 3264 } 3265 int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model) 3266 { 3267 if (has_slv_msrs(family, model)) 3268 return 1; 3269 3270 return 0; 3271 } 3272 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) 3273 { 3274 if (!genuine_intel) 3275 return 0; 3276 3277 if (family != 6) 3278 return 0; 3279 3280 switch (model) { 3281 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3282 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3283 return 1; 3284 default: 3285 return 0; 3286 } 3287 } 3288 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) 3289 { 3290 if (!genuine_intel) 3291 return 0; 3292 3293 if (family != 6) 3294 return 0; 3295 3296 switch (model) { 3297 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3298 return 1; 3299 default: 3300 return 0; 3301 } 3302 } 3303 3304 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) 3305 { 3306 if (!genuine_intel) 3307 return 0; 3308 3309 if (family != 6) 3310 return 0; 3311 3312 switch (model) { 3313 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 3314 return 1; 3315 default: 3316 return 0; 3317 } 3318 } 3319 int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model) 3320 { 3321 if (!genuine_intel) 3322 return 0; 3323 3324 if (family != 6) 3325 return 0; 3326 3327 switch (model) { 3328 case INTEL_FAM6_ATOM_GOLDMONT: 3329 case INTEL_FAM6_SKYLAKE_X: 3330 return 1; 3331 default: 3332 return 0; 3333 } 3334 } 3335 int has_config_tdp(unsigned int family, unsigned int model) 3336 { 3337 if (!genuine_intel) 3338 return 0; 3339 3340 if (family != 6) 3341 return 0; 3342 3343 switch (model) { 3344 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3345 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3346 case INTEL_FAM6_HASWELL_X: /* HSX */ 3347 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3348 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3349 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3350 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3351 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3352 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 3353 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3354 3355 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 3356 return 1; 3357 default: 3358 return 0; 3359 } 3360 } 3361 3362 static void 3363 dump_cstate_pstate_config_info(unsigned int family, unsigned int model) 3364 { 3365 if (!do_nhm_platform_info) 3366 return; 3367 3368 dump_nhm_platform_info(); 3369 3370 if (has_hsw_turbo_ratio_limit(family, model)) 3371 dump_hsw_turbo_ratio_limits(); 3372 3373 if (has_ivt_turbo_ratio_limit(family, model)) 3374 dump_ivt_turbo_ratio_limits(); 3375 3376 if (has_turbo_ratio_limit(family, model)) 3377 dump_turbo_ratio_limits(family, model); 3378 3379 if (has_atom_turbo_ratio_limit(family, model)) 3380 dump_atom_turbo_ratio_limits(); 3381 3382 if (has_knl_turbo_ratio_limit(family, model)) 3383 dump_knl_turbo_ratio_limits(); 3384 3385 if (has_config_tdp(family, model)) 3386 dump_config_tdp(); 3387 3388 dump_nhm_cst_cfg(); 3389 } 3390 3391 static void 3392 dump_sysfs_cstate_config(void) 3393 { 3394 char path[64]; 3395 char name_buf[16]; 3396 char desc[64]; 3397 FILE *input; 3398 int state; 3399 char *sp; 3400 3401 if (!DO_BIC(BIC_sysfs)) 3402 return; 3403 3404 for (state = 0; state < 10; ++state) { 3405 3406 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 3407 base_cpu, state); 3408 input = fopen(path, "r"); 3409 if (input == NULL) 3410 continue; 3411 fgets(name_buf, sizeof(name_buf), input); 3412 3413 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 3414 sp = strchr(name_buf, '-'); 3415 if (!sp) 3416 sp = strchrnul(name_buf, '\n'); 3417 *sp = '\0'; 3418 3419 fclose(input); 3420 3421 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc", 3422 base_cpu, state); 3423 input = fopen(path, "r"); 3424 if (input == NULL) 3425 continue; 3426 fgets(desc, sizeof(desc), input); 3427 3428 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc); 3429 fclose(input); 3430 } 3431 } 3432 static void 3433 dump_sysfs_pstate_config(void) 3434 { 3435 char path[64]; 3436 char driver_buf[64]; 3437 char governor_buf[64]; 3438 FILE *input; 3439 int turbo; 3440 3441 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver", 3442 base_cpu); 3443 input = fopen(path, "r"); 3444 if (input == NULL) { 3445 fprintf(stderr, "NSFOD %s\n", path); 3446 return; 3447 } 3448 fgets(driver_buf, sizeof(driver_buf), input); 3449 fclose(input); 3450 3451 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor", 3452 base_cpu); 3453 input = fopen(path, "r"); 3454 if (input == NULL) { 3455 fprintf(stderr, "NSFOD %s\n", path); 3456 return; 3457 } 3458 fgets(governor_buf, sizeof(governor_buf), input); 3459 fclose(input); 3460 3461 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf); 3462 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf); 3463 3464 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost"); 3465 input = fopen(path, "r"); 3466 if (input != NULL) { 3467 fscanf(input, "%d", &turbo); 3468 fprintf(outf, "cpufreq boost: %d\n", turbo); 3469 fclose(input); 3470 } 3471 3472 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo"); 3473 input = fopen(path, "r"); 3474 if (input != NULL) { 3475 fscanf(input, "%d", &turbo); 3476 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo); 3477 fclose(input); 3478 } 3479 } 3480 3481 3482 /* 3483 * print_epb() 3484 * Decode the ENERGY_PERF_BIAS MSR 3485 */ 3486 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3487 { 3488 unsigned long long msr; 3489 char *epb_string; 3490 int cpu; 3491 3492 if (!has_epb) 3493 return 0; 3494 3495 cpu = t->cpu_id; 3496 3497 /* EPB is per-package */ 3498 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3499 return 0; 3500 3501 if (cpu_migrate(cpu)) { 3502 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3503 return -1; 3504 } 3505 3506 if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr)) 3507 return 0; 3508 3509 switch (msr & 0xF) { 3510 case ENERGY_PERF_BIAS_PERFORMANCE: 3511 epb_string = "performance"; 3512 break; 3513 case ENERGY_PERF_BIAS_NORMAL: 3514 epb_string = "balanced"; 3515 break; 3516 case ENERGY_PERF_BIAS_POWERSAVE: 3517 epb_string = "powersave"; 3518 break; 3519 default: 3520 epb_string = "custom"; 3521 break; 3522 } 3523 fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string); 3524 3525 return 0; 3526 } 3527 /* 3528 * print_hwp() 3529 * Decode the MSR_HWP_CAPABILITIES 3530 */ 3531 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3532 { 3533 unsigned long long msr; 3534 int cpu; 3535 3536 if (!has_hwp) 3537 return 0; 3538 3539 cpu = t->cpu_id; 3540 3541 /* MSR_HWP_CAPABILITIES is per-package */ 3542 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3543 return 0; 3544 3545 if (cpu_migrate(cpu)) { 3546 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3547 return -1; 3548 } 3549 3550 if (get_msr(cpu, MSR_PM_ENABLE, &msr)) 3551 return 0; 3552 3553 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", 3554 cpu, msr, (msr & (1 << 0)) ? "" : "No-"); 3555 3556 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ 3557 if ((msr & (1 << 0)) == 0) 3558 return 0; 3559 3560 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) 3561 return 0; 3562 3563 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " 3564 "(high %d guar %d eff %d low %d)\n", 3565 cpu, msr, 3566 (unsigned int)HWP_HIGHEST_PERF(msr), 3567 (unsigned int)HWP_GUARANTEED_PERF(msr), 3568 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), 3569 (unsigned int)HWP_LOWEST_PERF(msr)); 3570 3571 if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) 3572 return 0; 3573 3574 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " 3575 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n", 3576 cpu, msr, 3577 (unsigned int)(((msr) >> 0) & 0xff), 3578 (unsigned int)(((msr) >> 8) & 0xff), 3579 (unsigned int)(((msr) >> 16) & 0xff), 3580 (unsigned int)(((msr) >> 24) & 0xff), 3581 (unsigned int)(((msr) >> 32) & 0xff3), 3582 (unsigned int)(((msr) >> 42) & 0x1)); 3583 3584 if (has_hwp_pkg) { 3585 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) 3586 return 0; 3587 3588 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " 3589 "(min %d max %d des %d epp 0x%x window 0x%x)\n", 3590 cpu, msr, 3591 (unsigned int)(((msr) >> 0) & 0xff), 3592 (unsigned int)(((msr) >> 8) & 0xff), 3593 (unsigned int)(((msr) >> 16) & 0xff), 3594 (unsigned int)(((msr) >> 24) & 0xff), 3595 (unsigned int)(((msr) >> 32) & 0xff3)); 3596 } 3597 if (has_hwp_notify) { 3598 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) 3599 return 0; 3600 3601 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " 3602 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", 3603 cpu, msr, 3604 ((msr) & 0x1) ? "EN" : "Dis", 3605 ((msr) & 0x2) ? "EN" : "Dis"); 3606 } 3607 if (get_msr(cpu, MSR_HWP_STATUS, &msr)) 3608 return 0; 3609 3610 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " 3611 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", 3612 cpu, msr, 3613 ((msr) & 0x1) ? "" : "No-", 3614 ((msr) & 0x2) ? "" : "No-"); 3615 3616 return 0; 3617 } 3618 3619 /* 3620 * print_perf_limit() 3621 */ 3622 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3623 { 3624 unsigned long long msr; 3625 int cpu; 3626 3627 cpu = t->cpu_id; 3628 3629 /* per-package */ 3630 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3631 return 0; 3632 3633 if (cpu_migrate(cpu)) { 3634 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3635 return -1; 3636 } 3637 3638 if (do_core_perf_limit_reasons) { 3639 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); 3640 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 3641 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", 3642 (msr & 1 << 15) ? "bit15, " : "", 3643 (msr & 1 << 14) ? "bit14, " : "", 3644 (msr & 1 << 13) ? "Transitions, " : "", 3645 (msr & 1 << 12) ? "MultiCoreTurbo, " : "", 3646 (msr & 1 << 11) ? "PkgPwrL2, " : "", 3647 (msr & 1 << 10) ? "PkgPwrL1, " : "", 3648 (msr & 1 << 9) ? "CorePwr, " : "", 3649 (msr & 1 << 8) ? "Amps, " : "", 3650 (msr & 1 << 6) ? "VR-Therm, " : "", 3651 (msr & 1 << 5) ? "Auto-HWP, " : "", 3652 (msr & 1 << 4) ? "Graphics, " : "", 3653 (msr & 1 << 2) ? "bit2, " : "", 3654 (msr & 1 << 1) ? "ThermStatus, " : "", 3655 (msr & 1 << 0) ? "PROCHOT, " : ""); 3656 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 3657 (msr & 1 << 31) ? "bit31, " : "", 3658 (msr & 1 << 30) ? "bit30, " : "", 3659 (msr & 1 << 29) ? "Transitions, " : "", 3660 (msr & 1 << 28) ? "MultiCoreTurbo, " : "", 3661 (msr & 1 << 27) ? "PkgPwrL2, " : "", 3662 (msr & 1 << 26) ? "PkgPwrL1, " : "", 3663 (msr & 1 << 25) ? "CorePwr, " : "", 3664 (msr & 1 << 24) ? "Amps, " : "", 3665 (msr & 1 << 22) ? "VR-Therm, " : "", 3666 (msr & 1 << 21) ? "Auto-HWP, " : "", 3667 (msr & 1 << 20) ? "Graphics, " : "", 3668 (msr & 1 << 18) ? "bit18, " : "", 3669 (msr & 1 << 17) ? "ThermStatus, " : "", 3670 (msr & 1 << 16) ? "PROCHOT, " : ""); 3671 3672 } 3673 if (do_gfx_perf_limit_reasons) { 3674 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); 3675 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 3676 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", 3677 (msr & 1 << 0) ? "PROCHOT, " : "", 3678 (msr & 1 << 1) ? "ThermStatus, " : "", 3679 (msr & 1 << 4) ? "Graphics, " : "", 3680 (msr & 1 << 6) ? "VR-Therm, " : "", 3681 (msr & 1 << 8) ? "Amps, " : "", 3682 (msr & 1 << 9) ? "GFXPwr, " : "", 3683 (msr & 1 << 10) ? "PkgPwrL1, " : "", 3684 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 3685 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", 3686 (msr & 1 << 16) ? "PROCHOT, " : "", 3687 (msr & 1 << 17) ? "ThermStatus, " : "", 3688 (msr & 1 << 20) ? "Graphics, " : "", 3689 (msr & 1 << 22) ? "VR-Therm, " : "", 3690 (msr & 1 << 24) ? "Amps, " : "", 3691 (msr & 1 << 25) ? "GFXPwr, " : "", 3692 (msr & 1 << 26) ? "PkgPwrL1, " : "", 3693 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 3694 } 3695 if (do_ring_perf_limit_reasons) { 3696 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); 3697 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 3698 fprintf(outf, " (Active: %s%s%s%s%s%s)", 3699 (msr & 1 << 0) ? "PROCHOT, " : "", 3700 (msr & 1 << 1) ? "ThermStatus, " : "", 3701 (msr & 1 << 6) ? "VR-Therm, " : "", 3702 (msr & 1 << 8) ? "Amps, " : "", 3703 (msr & 1 << 10) ? "PkgPwrL1, " : "", 3704 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 3705 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", 3706 (msr & 1 << 16) ? "PROCHOT, " : "", 3707 (msr & 1 << 17) ? "ThermStatus, " : "", 3708 (msr & 1 << 22) ? "VR-Therm, " : "", 3709 (msr & 1 << 24) ? "Amps, " : "", 3710 (msr & 1 << 26) ? "PkgPwrL1, " : "", 3711 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 3712 } 3713 return 0; 3714 } 3715 3716 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ 3717 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ 3718 3719 double get_tdp(unsigned int model) 3720 { 3721 unsigned long long msr; 3722 3723 if (do_rapl & RAPL_PKG_POWER_INFO) 3724 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) 3725 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; 3726 3727 switch (model) { 3728 case INTEL_FAM6_ATOM_SILVERMONT: 3729 case INTEL_FAM6_ATOM_SILVERMONT_X: 3730 return 30.0; 3731 default: 3732 return 135.0; 3733 } 3734 } 3735 3736 /* 3737 * rapl_dram_energy_units_probe() 3738 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR. 3739 */ 3740 static double 3741 rapl_dram_energy_units_probe(int model, double rapl_energy_units) 3742 { 3743 /* only called for genuine_intel, family 6 */ 3744 3745 switch (model) { 3746 case INTEL_FAM6_HASWELL_X: /* HSX */ 3747 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3748 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 3749 return (rapl_dram_energy_units = 15.3 / 1000000); 3750 default: 3751 return (rapl_energy_units); 3752 } 3753 } 3754 3755 3756 /* 3757 * rapl_probe() 3758 * 3759 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units 3760 */ 3761 void rapl_probe(unsigned int family, unsigned int model) 3762 { 3763 unsigned long long msr; 3764 unsigned int time_unit; 3765 double tdp; 3766 3767 if (!genuine_intel) 3768 return; 3769 3770 if (family != 6) 3771 return; 3772 3773 switch (model) { 3774 case INTEL_FAM6_SANDYBRIDGE: 3775 case INTEL_FAM6_IVYBRIDGE: 3776 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3777 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3778 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3779 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3780 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; 3781 if (rapl_joules) { 3782 BIC_PRESENT(BIC_Pkg_J); 3783 BIC_PRESENT(BIC_Cor_J); 3784 BIC_PRESENT(BIC_GFX_J); 3785 } else { 3786 BIC_PRESENT(BIC_PkgWatt); 3787 BIC_PRESENT(BIC_CorWatt); 3788 BIC_PRESENT(BIC_GFXWatt); 3789 } 3790 break; 3791 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3792 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 3793 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; 3794 if (rapl_joules) 3795 BIC_PRESENT(BIC_Pkg_J); 3796 else 3797 BIC_PRESENT(BIC_PkgWatt); 3798 break; 3799 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3800 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 3801 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_GFX | RAPL_PKG_POWER_INFO; 3802 BIC_PRESENT(BIC_PKG__); 3803 BIC_PRESENT(BIC_RAM__); 3804 if (rapl_joules) { 3805 BIC_PRESENT(BIC_Pkg_J); 3806 BIC_PRESENT(BIC_Cor_J); 3807 BIC_PRESENT(BIC_RAM_J); 3808 BIC_PRESENT(BIC_GFX_J); 3809 } else { 3810 BIC_PRESENT(BIC_PkgWatt); 3811 BIC_PRESENT(BIC_CorWatt); 3812 BIC_PRESENT(BIC_RAMWatt); 3813 BIC_PRESENT(BIC_GFXWatt); 3814 } 3815 break; 3816 case INTEL_FAM6_HASWELL_X: /* HSX */ 3817 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3818 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3819 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 3820 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 3821 BIC_PRESENT(BIC_PKG__); 3822 BIC_PRESENT(BIC_RAM__); 3823 if (rapl_joules) { 3824 BIC_PRESENT(BIC_Pkg_J); 3825 BIC_PRESENT(BIC_RAM_J); 3826 } else { 3827 BIC_PRESENT(BIC_PkgWatt); 3828 BIC_PRESENT(BIC_RAMWatt); 3829 } 3830 break; 3831 case INTEL_FAM6_SANDYBRIDGE_X: 3832 case INTEL_FAM6_IVYBRIDGE_X: 3833 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; 3834 BIC_PRESENT(BIC_PKG__); 3835 BIC_PRESENT(BIC_RAM__); 3836 if (rapl_joules) { 3837 BIC_PRESENT(BIC_Pkg_J); 3838 BIC_PRESENT(BIC_Cor_J); 3839 BIC_PRESENT(BIC_RAM_J); 3840 } else { 3841 BIC_PRESENT(BIC_PkgWatt); 3842 BIC_PRESENT(BIC_CorWatt); 3843 BIC_PRESENT(BIC_RAMWatt); 3844 } 3845 break; 3846 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 3847 case INTEL_FAM6_ATOM_SILVERMONT_X: /* AVN */ 3848 do_rapl = RAPL_PKG | RAPL_CORES; 3849 if (rapl_joules) { 3850 BIC_PRESENT(BIC_Pkg_J); 3851 BIC_PRESENT(BIC_Cor_J); 3852 } else { 3853 BIC_PRESENT(BIC_PkgWatt); 3854 BIC_PRESENT(BIC_CorWatt); 3855 } 3856 break; 3857 case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */ 3858 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS; 3859 BIC_PRESENT(BIC_PKG__); 3860 BIC_PRESENT(BIC_RAM__); 3861 if (rapl_joules) { 3862 BIC_PRESENT(BIC_Pkg_J); 3863 BIC_PRESENT(BIC_Cor_J); 3864 BIC_PRESENT(BIC_RAM_J); 3865 } else { 3866 BIC_PRESENT(BIC_PkgWatt); 3867 BIC_PRESENT(BIC_CorWatt); 3868 BIC_PRESENT(BIC_RAMWatt); 3869 } 3870 break; 3871 default: 3872 return; 3873 } 3874 3875 /* units on package 0, verify later other packages match */ 3876 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) 3877 return; 3878 3879 rapl_power_units = 1.0 / (1 << (msr & 0xF)); 3880 if (model == INTEL_FAM6_ATOM_SILVERMONT) 3881 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; 3882 else 3883 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 3884 3885 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units); 3886 3887 time_unit = msr >> 16 & 0xF; 3888 if (time_unit == 0) 3889 time_unit = 0xA; 3890 3891 rapl_time_units = 1.0 / (1 << (time_unit)); 3892 3893 tdp = get_tdp(model); 3894 3895 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 3896 if (!quiet) 3897 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 3898 3899 return; 3900 } 3901 3902 void perf_limit_reasons_probe(unsigned int family, unsigned int model) 3903 { 3904 if (!genuine_intel) 3905 return; 3906 3907 if (family != 6) 3908 return; 3909 3910 switch (model) { 3911 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3912 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3913 do_gfx_perf_limit_reasons = 1; 3914 case INTEL_FAM6_HASWELL_X: /* HSX */ 3915 do_core_perf_limit_reasons = 1; 3916 do_ring_perf_limit_reasons = 1; 3917 default: 3918 return; 3919 } 3920 } 3921 3922 void automatic_cstate_conversion_probe(unsigned int family, unsigned int model) 3923 { 3924 if (is_skx(family, model) || is_bdx(family, model)) 3925 has_automatic_cstate_conversion = 1; 3926 } 3927 3928 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3929 { 3930 unsigned long long msr; 3931 unsigned int dts, dts2; 3932 int cpu; 3933 3934 if (!(do_dts || do_ptm)) 3935 return 0; 3936 3937 cpu = t->cpu_id; 3938 3939 /* DTS is per-core, no need to print for each thread */ 3940 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 3941 return 0; 3942 3943 if (cpu_migrate(cpu)) { 3944 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3945 return -1; 3946 } 3947 3948 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { 3949 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 3950 return 0; 3951 3952 dts = (msr >> 16) & 0x7F; 3953 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", 3954 cpu, msr, tcc_activation_temp - dts); 3955 3956 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) 3957 return 0; 3958 3959 dts = (msr >> 16) & 0x7F; 3960 dts2 = (msr >> 8) & 0x7F; 3961 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 3962 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 3963 } 3964 3965 3966 if (do_dts && debug) { 3967 unsigned int resolution; 3968 3969 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 3970 return 0; 3971 3972 dts = (msr >> 16) & 0x7F; 3973 resolution = (msr >> 27) & 0xF; 3974 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", 3975 cpu, msr, tcc_activation_temp - dts, resolution); 3976 3977 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) 3978 return 0; 3979 3980 dts = (msr >> 16) & 0x7F; 3981 dts2 = (msr >> 8) & 0x7F; 3982 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 3983 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 3984 } 3985 3986 return 0; 3987 } 3988 3989 void print_power_limit_msr(int cpu, unsigned long long msr, char *label) 3990 { 3991 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n", 3992 cpu, label, 3993 ((msr >> 15) & 1) ? "EN" : "DIS", 3994 ((msr >> 0) & 0x7FFF) * rapl_power_units, 3995 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, 3996 (((msr >> 16) & 1) ? "EN" : "DIS")); 3997 3998 return; 3999 } 4000 4001 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4002 { 4003 unsigned long long msr; 4004 int cpu; 4005 4006 if (!do_rapl) 4007 return 0; 4008 4009 /* RAPL counters are per package, so print only for 1st thread/package */ 4010 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4011 return 0; 4012 4013 cpu = t->cpu_id; 4014 if (cpu_migrate(cpu)) { 4015 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 4016 return -1; 4017 } 4018 4019 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) 4020 return -1; 4021 4022 fprintf(outf, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr, 4023 rapl_power_units, rapl_energy_units, rapl_time_units); 4024 4025 if (do_rapl & RAPL_PKG_POWER_INFO) { 4026 4027 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) 4028 return -5; 4029 4030 4031 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4032 cpu, msr, 4033 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4034 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4035 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4036 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4037 4038 } 4039 if (do_rapl & RAPL_PKG) { 4040 4041 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) 4042 return -9; 4043 4044 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", 4045 cpu, msr, (msr >> 63) & 1 ? "" : "UN"); 4046 4047 print_power_limit_msr(cpu, msr, "PKG Limit #1"); 4048 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n", 4049 cpu, 4050 ((msr >> 47) & 1) ? "EN" : "DIS", 4051 ((msr >> 32) & 0x7FFF) * rapl_power_units, 4052 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, 4053 ((msr >> 48) & 1) ? "EN" : "DIS"); 4054 } 4055 4056 if (do_rapl & RAPL_DRAM_POWER_INFO) { 4057 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) 4058 return -6; 4059 4060 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4061 cpu, msr, 4062 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4063 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4064 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4065 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4066 } 4067 if (do_rapl & RAPL_DRAM) { 4068 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) 4069 return -9; 4070 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", 4071 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4072 4073 print_power_limit_msr(cpu, msr, "DRAM Limit"); 4074 } 4075 if (do_rapl & RAPL_CORE_POLICY) { 4076 if (get_msr(cpu, MSR_PP0_POLICY, &msr)) 4077 return -7; 4078 4079 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); 4080 } 4081 if (do_rapl & RAPL_CORES_POWER_LIMIT) { 4082 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) 4083 return -9; 4084 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", 4085 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4086 print_power_limit_msr(cpu, msr, "Cores Limit"); 4087 } 4088 if (do_rapl & RAPL_GFX) { 4089 if (get_msr(cpu, MSR_PP1_POLICY, &msr)) 4090 return -8; 4091 4092 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); 4093 4094 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) 4095 return -9; 4096 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", 4097 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4098 print_power_limit_msr(cpu, msr, "GFX Limit"); 4099 } 4100 return 0; 4101 } 4102 4103 /* 4104 * SNB adds support for additional MSRs: 4105 * 4106 * MSR_PKG_C7_RESIDENCY 0x000003fa 4107 * MSR_CORE_C7_RESIDENCY 0x000003fe 4108 * MSR_PKG_C2_RESIDENCY 0x0000060d 4109 */ 4110 4111 int has_snb_msrs(unsigned int family, unsigned int model) 4112 { 4113 if (!genuine_intel) 4114 return 0; 4115 4116 switch (model) { 4117 case INTEL_FAM6_SANDYBRIDGE: 4118 case INTEL_FAM6_SANDYBRIDGE_X: 4119 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 4120 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 4121 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 4122 case INTEL_FAM6_HASWELL_X: /* HSW */ 4123 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 4124 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 4125 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 4126 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4127 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4128 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 4129 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4130 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4131 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4132 case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */ 4133 return 1; 4134 } 4135 return 0; 4136 } 4137 4138 /* 4139 * HSW adds support for additional MSRs: 4140 * 4141 * MSR_PKG_C8_RESIDENCY 0x00000630 4142 * MSR_PKG_C9_RESIDENCY 0x00000631 4143 * MSR_PKG_C10_RESIDENCY 0x00000632 4144 * 4145 * MSR_PKGC8_IRTL 0x00000633 4146 * MSR_PKGC9_IRTL 0x00000634 4147 * MSR_PKGC10_IRTL 0x00000635 4148 * 4149 */ 4150 int has_hsw_msrs(unsigned int family, unsigned int model) 4151 { 4152 if (!genuine_intel) 4153 return 0; 4154 4155 switch (model) { 4156 case INTEL_FAM6_HASWELL_CORE: 4157 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 4158 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4159 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 4160 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4161 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4162 return 1; 4163 } 4164 return 0; 4165 } 4166 4167 /* 4168 * SKL adds support for additional MSRS: 4169 * 4170 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 4171 * MSR_PKG_ANY_CORE_C0_RES 0x00000659 4172 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 4173 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 4174 */ 4175 int has_skl_msrs(unsigned int family, unsigned int model) 4176 { 4177 if (!genuine_intel) 4178 return 0; 4179 4180 switch (model) { 4181 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4182 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 4183 return 1; 4184 } 4185 return 0; 4186 } 4187 4188 int is_slm(unsigned int family, unsigned int model) 4189 { 4190 if (!genuine_intel) 4191 return 0; 4192 switch (model) { 4193 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 4194 case INTEL_FAM6_ATOM_SILVERMONT_X: /* AVN */ 4195 return 1; 4196 } 4197 return 0; 4198 } 4199 4200 int is_knl(unsigned int family, unsigned int model) 4201 { 4202 if (!genuine_intel) 4203 return 0; 4204 switch (model) { 4205 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4206 return 1; 4207 } 4208 return 0; 4209 } 4210 4211 int is_cnl(unsigned int family, unsigned int model) 4212 { 4213 if (!genuine_intel) 4214 return 0; 4215 4216 switch (model) { 4217 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 4218 return 1; 4219 } 4220 4221 return 0; 4222 } 4223 4224 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model) 4225 { 4226 if (is_knl(family, model)) 4227 return 1024; 4228 return 1; 4229 } 4230 4231 #define SLM_BCLK_FREQS 5 4232 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0}; 4233 4234 double slm_bclk(void) 4235 { 4236 unsigned long long msr = 3; 4237 unsigned int i; 4238 double freq; 4239 4240 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) 4241 fprintf(outf, "SLM BCLK: unknown\n"); 4242 4243 i = msr & 0xf; 4244 if (i >= SLM_BCLK_FREQS) { 4245 fprintf(outf, "SLM BCLK[%d] invalid\n", i); 4246 i = 3; 4247 } 4248 freq = slm_freq_table[i]; 4249 4250 if (!quiet) 4251 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); 4252 4253 return freq; 4254 } 4255 4256 double discover_bclk(unsigned int family, unsigned int model) 4257 { 4258 if (has_snb_msrs(family, model) || is_knl(family, model)) 4259 return 100.00; 4260 else if (is_slm(family, model)) 4261 return slm_bclk(); 4262 else 4263 return 133.33; 4264 } 4265 4266 /* 4267 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where 4268 * the Thermal Control Circuit (TCC) activates. 4269 * This is usually equal to tjMax. 4270 * 4271 * Older processors do not have this MSR, so there we guess, 4272 * but also allow cmdline over-ride with -T. 4273 * 4274 * Several MSR temperature values are in units of degrees-C 4275 * below this value, including the Digital Thermal Sensor (DTS), 4276 * Package Thermal Management Sensor (PTM), and thermal event thresholds. 4277 */ 4278 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4279 { 4280 unsigned long long msr; 4281 unsigned int target_c_local; 4282 int cpu; 4283 4284 /* tcc_activation_temp is used only for dts or ptm */ 4285 if (!(do_dts || do_ptm)) 4286 return 0; 4287 4288 /* this is a per-package concept */ 4289 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4290 return 0; 4291 4292 cpu = t->cpu_id; 4293 if (cpu_migrate(cpu)) { 4294 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 4295 return -1; 4296 } 4297 4298 if (tcc_activation_temp_override != 0) { 4299 tcc_activation_temp = tcc_activation_temp_override; 4300 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", 4301 cpu, tcc_activation_temp); 4302 return 0; 4303 } 4304 4305 /* Temperature Target MSR is Nehalem and newer only */ 4306 if (!do_nhm_platform_info) 4307 goto guess; 4308 4309 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) 4310 goto guess; 4311 4312 target_c_local = (msr >> 16) & 0xFF; 4313 4314 if (!quiet) 4315 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", 4316 cpu, msr, target_c_local); 4317 4318 if (!target_c_local) 4319 goto guess; 4320 4321 tcc_activation_temp = target_c_local; 4322 4323 return 0; 4324 4325 guess: 4326 tcc_activation_temp = TJMAX_DEFAULT; 4327 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", 4328 cpu, tcc_activation_temp); 4329 4330 return 0; 4331 } 4332 4333 void decode_feature_control_msr(void) 4334 { 4335 unsigned long long msr; 4336 4337 if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr)) 4338 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", 4339 base_cpu, msr, 4340 msr & FEATURE_CONTROL_LOCKED ? "" : "UN-", 4341 msr & (1 << 18) ? "SGX" : ""); 4342 } 4343 4344 void decode_misc_enable_msr(void) 4345 { 4346 unsigned long long msr; 4347 4348 if (!genuine_intel) 4349 return; 4350 4351 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) 4352 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n", 4353 base_cpu, msr, 4354 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-", 4355 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-", 4356 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-", 4357 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "", 4358 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : ""); 4359 } 4360 4361 void decode_misc_feature_control(void) 4362 { 4363 unsigned long long msr; 4364 4365 if (!has_misc_feature_control) 4366 return; 4367 4368 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr)) 4369 fprintf(outf, "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n", 4370 base_cpu, msr, 4371 msr & (0 << 0) ? "No-" : "", 4372 msr & (1 << 0) ? "No-" : "", 4373 msr & (2 << 0) ? "No-" : "", 4374 msr & (3 << 0) ? "No-" : ""); 4375 } 4376 /* 4377 * Decode MSR_MISC_PWR_MGMT 4378 * 4379 * Decode the bits according to the Nehalem documentation 4380 * bit[0] seems to continue to have same meaning going forward 4381 * bit[1] less so... 4382 */ 4383 void decode_misc_pwr_mgmt_msr(void) 4384 { 4385 unsigned long long msr; 4386 4387 if (!do_nhm_platform_info) 4388 return; 4389 4390 if (no_MSR_MISC_PWR_MGMT) 4391 return; 4392 4393 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) 4394 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n", 4395 base_cpu, msr, 4396 msr & (1 << 0) ? "DIS" : "EN", 4397 msr & (1 << 1) ? "EN" : "DIS", 4398 msr & (1 << 8) ? "EN" : "DIS"); 4399 } 4400 /* 4401 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG 4402 * 4403 * This MSRs are present on Silvermont processors, 4404 * Intel Atom processor E3000 series (Baytrail), and friends. 4405 */ 4406 void decode_c6_demotion_policy_msr(void) 4407 { 4408 unsigned long long msr; 4409 4410 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr)) 4411 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n", 4412 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 4413 4414 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr)) 4415 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n", 4416 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 4417 } 4418 4419 /* 4420 * When models are the same, for the purpose of turbostat, reuse 4421 */ 4422 unsigned int intel_model_duplicates(unsigned int model) 4423 { 4424 4425 switch(model) { 4426 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ 4427 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 4428 case 0x1F: /* Core i7 and i5 Processor - Nehalem */ 4429 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */ 4430 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */ 4431 return INTEL_FAM6_NEHALEM; 4432 4433 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 4434 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 4435 return INTEL_FAM6_NEHALEM_EX; 4436 4437 case INTEL_FAM6_XEON_PHI_KNM: 4438 return INTEL_FAM6_XEON_PHI_KNL; 4439 4440 case INTEL_FAM6_HASWELL_ULT: 4441 return INTEL_FAM6_HASWELL_CORE; 4442 4443 case INTEL_FAM6_BROADWELL_X: 4444 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 4445 return INTEL_FAM6_BROADWELL_X; 4446 4447 case INTEL_FAM6_SKYLAKE_MOBILE: 4448 case INTEL_FAM6_SKYLAKE_DESKTOP: 4449 case INTEL_FAM6_KABYLAKE_MOBILE: 4450 case INTEL_FAM6_KABYLAKE_DESKTOP: 4451 return INTEL_FAM6_SKYLAKE_MOBILE; 4452 4453 case INTEL_FAM6_ICELAKE_MOBILE: 4454 return INTEL_FAM6_CANNONLAKE_MOBILE; 4455 } 4456 return model; 4457 } 4458 void process_cpuid() 4459 { 4460 unsigned int eax, ebx, ecx, edx; 4461 unsigned int fms, family, model, stepping, ecx_flags, edx_flags; 4462 unsigned int has_turbo; 4463 4464 eax = ebx = ecx = edx = 0; 4465 4466 __cpuid(0, max_level, ebx, ecx, edx); 4467 4468 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69) 4469 genuine_intel = 1; 4470 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) 4471 authentic_amd = 1; 4472 4473 if (!quiet) 4474 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ", 4475 (char *)&ebx, (char *)&edx, (char *)&ecx); 4476 4477 __cpuid(1, fms, ebx, ecx, edx); 4478 family = (fms >> 8) & 0xf; 4479 model = (fms >> 4) & 0xf; 4480 stepping = fms & 0xf; 4481 if (family == 0xf) 4482 family += (fms >> 20) & 0xff; 4483 if (family >= 6) 4484 model += ((fms >> 16) & 0xf) << 4; 4485 ecx_flags = ecx; 4486 edx_flags = edx; 4487 4488 /* 4489 * check max extended function levels of CPUID. 4490 * This is needed to check for invariant TSC. 4491 * This check is valid for both Intel and AMD. 4492 */ 4493 ebx = ecx = edx = 0; 4494 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); 4495 4496 if (!quiet) { 4497 fprintf(outf, "0x%x CPUID levels; 0x%x xlevels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n", 4498 max_level, max_extended_level, family, model, stepping, family, model, stepping); 4499 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n", 4500 ecx_flags & (1 << 0) ? "SSE3" : "-", 4501 ecx_flags & (1 << 3) ? "MONITOR" : "-", 4502 ecx_flags & (1 << 6) ? "SMX" : "-", 4503 ecx_flags & (1 << 7) ? "EIST" : "-", 4504 ecx_flags & (1 << 8) ? "TM2" : "-", 4505 edx_flags & (1 << 4) ? "TSC" : "-", 4506 edx_flags & (1 << 5) ? "MSR" : "-", 4507 edx_flags & (1 << 22) ? "ACPI-TM" : "-", 4508 edx_flags & (1 << 28) ? "HT" : "-", 4509 edx_flags & (1 << 29) ? "TM" : "-"); 4510 } 4511 if (genuine_intel) 4512 model = intel_model_duplicates(model); 4513 4514 if (!(edx_flags & (1 << 5))) 4515 errx(1, "CPUID: no MSR"); 4516 4517 if (max_extended_level >= 0x80000007) { 4518 4519 /* 4520 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 4521 * this check is valid for both Intel and AMD 4522 */ 4523 __cpuid(0x80000007, eax, ebx, ecx, edx); 4524 has_invariant_tsc = edx & (1 << 8); 4525 } 4526 4527 /* 4528 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 4529 * this check is valid for both Intel and AMD 4530 */ 4531 4532 __cpuid(0x6, eax, ebx, ecx, edx); 4533 has_aperf = ecx & (1 << 0); 4534 if (has_aperf) { 4535 BIC_PRESENT(BIC_Avg_MHz); 4536 BIC_PRESENT(BIC_Busy); 4537 BIC_PRESENT(BIC_Bzy_MHz); 4538 } 4539 do_dts = eax & (1 << 0); 4540 if (do_dts) 4541 BIC_PRESENT(BIC_CoreTmp); 4542 has_turbo = eax & (1 << 1); 4543 do_ptm = eax & (1 << 6); 4544 if (do_ptm) 4545 BIC_PRESENT(BIC_PkgTmp); 4546 has_hwp = eax & (1 << 7); 4547 has_hwp_notify = eax & (1 << 8); 4548 has_hwp_activity_window = eax & (1 << 9); 4549 has_hwp_epp = eax & (1 << 10); 4550 has_hwp_pkg = eax & (1 << 11); 4551 has_epb = ecx & (1 << 3); 4552 4553 if (!quiet) 4554 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, " 4555 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", 4556 has_aperf ? "" : "No-", 4557 has_turbo ? "" : "No-", 4558 do_dts ? "" : "No-", 4559 do_ptm ? "" : "No-", 4560 has_hwp ? "" : "No-", 4561 has_hwp_notify ? "" : "No-", 4562 has_hwp_activity_window ? "" : "No-", 4563 has_hwp_epp ? "" : "No-", 4564 has_hwp_pkg ? "" : "No-", 4565 has_epb ? "" : "No-"); 4566 4567 if (!quiet) 4568 decode_misc_enable_msr(); 4569 4570 4571 if (max_level >= 0x7 && !quiet) { 4572 int has_sgx; 4573 4574 ecx = 0; 4575 4576 __cpuid_count(0x7, 0, eax, ebx, ecx, edx); 4577 4578 has_sgx = ebx & (1 << 2); 4579 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-"); 4580 4581 if (has_sgx) 4582 decode_feature_control_msr(); 4583 } 4584 4585 if (max_level >= 0x15) { 4586 unsigned int eax_crystal; 4587 unsigned int ebx_tsc; 4588 4589 /* 4590 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz 4591 */ 4592 eax_crystal = ebx_tsc = crystal_hz = edx = 0; 4593 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); 4594 4595 if (ebx_tsc != 0) { 4596 4597 if (!quiet && (ebx != 0)) 4598 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", 4599 eax_crystal, ebx_tsc, crystal_hz); 4600 4601 if (crystal_hz == 0) 4602 switch(model) { 4603 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4604 crystal_hz = 24000000; /* 24.0 MHz */ 4605 break; 4606 case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */ 4607 crystal_hz = 25000000; /* 25.0 MHz */ 4608 break; 4609 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4610 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4611 crystal_hz = 19200000; /* 19.2 MHz */ 4612 break; 4613 default: 4614 crystal_hz = 0; 4615 } 4616 4617 if (crystal_hz) { 4618 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal; 4619 if (!quiet) 4620 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", 4621 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); 4622 } 4623 } 4624 } 4625 if (max_level >= 0x16) { 4626 unsigned int base_mhz, max_mhz, bus_mhz, edx; 4627 4628 /* 4629 * CPUID 16H Base MHz, Max MHz, Bus MHz 4630 */ 4631 base_mhz = max_mhz = bus_mhz = edx = 0; 4632 4633 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); 4634 if (!quiet) 4635 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", 4636 base_mhz, max_mhz, bus_mhz); 4637 } 4638 4639 if (has_aperf) 4640 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model); 4641 4642 BIC_PRESENT(BIC_IRQ); 4643 BIC_PRESENT(BIC_TSC_MHz); 4644 4645 if (probe_nhm_msrs(family, model)) { 4646 do_nhm_platform_info = 1; 4647 BIC_PRESENT(BIC_CPU_c1); 4648 BIC_PRESENT(BIC_CPU_c3); 4649 BIC_PRESENT(BIC_CPU_c6); 4650 BIC_PRESENT(BIC_SMI); 4651 } 4652 do_snb_cstates = has_snb_msrs(family, model); 4653 4654 if (do_snb_cstates) 4655 BIC_PRESENT(BIC_CPU_c7); 4656 4657 do_irtl_snb = has_snb_msrs(family, model); 4658 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2)) 4659 BIC_PRESENT(BIC_Pkgpc2); 4660 if (pkg_cstate_limit >= PCL__3) 4661 BIC_PRESENT(BIC_Pkgpc3); 4662 if (pkg_cstate_limit >= PCL__6) 4663 BIC_PRESENT(BIC_Pkgpc6); 4664 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7)) 4665 BIC_PRESENT(BIC_Pkgpc7); 4666 if (has_slv_msrs(family, model)) { 4667 BIC_NOT_PRESENT(BIC_Pkgpc2); 4668 BIC_NOT_PRESENT(BIC_Pkgpc3); 4669 BIC_PRESENT(BIC_Pkgpc6); 4670 BIC_NOT_PRESENT(BIC_Pkgpc7); 4671 BIC_PRESENT(BIC_Mod_c6); 4672 use_c1_residency_msr = 1; 4673 } 4674 if (is_dnv(family, model)) { 4675 BIC_PRESENT(BIC_CPU_c1); 4676 BIC_NOT_PRESENT(BIC_CPU_c3); 4677 BIC_NOT_PRESENT(BIC_Pkgpc3); 4678 BIC_NOT_PRESENT(BIC_CPU_c7); 4679 BIC_NOT_PRESENT(BIC_Pkgpc7); 4680 use_c1_residency_msr = 1; 4681 } 4682 if (is_skx(family, model)) { 4683 BIC_NOT_PRESENT(BIC_CPU_c3); 4684 BIC_NOT_PRESENT(BIC_Pkgpc3); 4685 BIC_NOT_PRESENT(BIC_CPU_c7); 4686 BIC_NOT_PRESENT(BIC_Pkgpc7); 4687 } 4688 if (is_bdx(family, model)) { 4689 BIC_NOT_PRESENT(BIC_CPU_c7); 4690 BIC_NOT_PRESENT(BIC_Pkgpc7); 4691 } 4692 if (has_hsw_msrs(family, model)) { 4693 BIC_PRESENT(BIC_Pkgpc8); 4694 BIC_PRESENT(BIC_Pkgpc9); 4695 BIC_PRESENT(BIC_Pkgpc10); 4696 } 4697 do_irtl_hsw = has_hsw_msrs(family, model); 4698 if (has_skl_msrs(family, model)) { 4699 BIC_PRESENT(BIC_Totl_c0); 4700 BIC_PRESENT(BIC_Any_c0); 4701 BIC_PRESENT(BIC_GFX_c0); 4702 BIC_PRESENT(BIC_CPUGFX); 4703 } 4704 do_slm_cstates = is_slm(family, model); 4705 do_knl_cstates = is_knl(family, model); 4706 4707 if (do_slm_cstates || do_knl_cstates || is_cnl(family, model)) 4708 BIC_NOT_PRESENT(BIC_CPU_c3); 4709 4710 if (!quiet) 4711 decode_misc_pwr_mgmt_msr(); 4712 4713 if (!quiet && has_slv_msrs(family, model)) 4714 decode_c6_demotion_policy_msr(); 4715 4716 rapl_probe(family, model); 4717 perf_limit_reasons_probe(family, model); 4718 automatic_cstate_conversion_probe(family, model); 4719 4720 if (!quiet) 4721 dump_cstate_pstate_config_info(family, model); 4722 4723 if (!quiet) 4724 dump_sysfs_cstate_config(); 4725 if (!quiet) 4726 dump_sysfs_pstate_config(); 4727 4728 if (has_skl_msrs(family, model)) 4729 calculate_tsc_tweak(); 4730 4731 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK)) 4732 BIC_PRESENT(BIC_GFX_rc6); 4733 4734 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK)) 4735 BIC_PRESENT(BIC_GFXMHz); 4736 4737 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK)) 4738 BIC_PRESENT(BIC_CPU_LPI); 4739 else 4740 BIC_NOT_PRESENT(BIC_CPU_LPI); 4741 4742 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us", R_OK)) 4743 BIC_PRESENT(BIC_SYS_LPI); 4744 else 4745 BIC_NOT_PRESENT(BIC_SYS_LPI); 4746 4747 if (!quiet) 4748 decode_misc_feature_control(); 4749 4750 return; 4751 } 4752 4753 /* 4754 * in /dev/cpu/ return success for names that are numbers 4755 * ie. filter out ".", "..", "microcode". 4756 */ 4757 int dir_filter(const struct dirent *dirp) 4758 { 4759 if (isdigit(dirp->d_name[0])) 4760 return 1; 4761 else 4762 return 0; 4763 } 4764 4765 int open_dev_cpu_msr(int dummy1) 4766 { 4767 return 0; 4768 } 4769 4770 void topology_probe() 4771 { 4772 int i; 4773 int max_core_id = 0; 4774 int max_package_id = 0; 4775 int max_siblings = 0; 4776 4777 /* Initialize num_cpus, max_cpu_num */ 4778 set_max_cpu_num(); 4779 topo.num_cpus = 0; 4780 for_all_proc_cpus(count_cpus); 4781 if (!summary_only && topo.num_cpus > 1) 4782 BIC_PRESENT(BIC_CPU); 4783 4784 if (debug > 1) 4785 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); 4786 4787 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); 4788 if (cpus == NULL) 4789 err(1, "calloc cpus"); 4790 4791 /* 4792 * Allocate and initialize cpu_present_set 4793 */ 4794 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); 4795 if (cpu_present_set == NULL) 4796 err(3, "CPU_ALLOC"); 4797 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 4798 CPU_ZERO_S(cpu_present_setsize, cpu_present_set); 4799 for_all_proc_cpus(mark_cpu_present); 4800 4801 /* 4802 * Validate that all cpus in cpu_subset are also in cpu_present_set 4803 */ 4804 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) { 4805 if (CPU_ISSET_S(i, cpu_subset_size, cpu_subset)) 4806 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set)) 4807 err(1, "cpu%d not present", i); 4808 } 4809 4810 /* 4811 * Allocate and initialize cpu_affinity_set 4812 */ 4813 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); 4814 if (cpu_affinity_set == NULL) 4815 err(3, "CPU_ALLOC"); 4816 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 4817 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 4818 4819 for_all_proc_cpus(init_thread_id); 4820 4821 /* 4822 * For online cpus 4823 * find max_core_id, max_package_id 4824 */ 4825 for (i = 0; i <= topo.max_cpu_num; ++i) { 4826 int siblings; 4827 4828 if (cpu_is_not_present(i)) { 4829 if (debug > 1) 4830 fprintf(outf, "cpu%d NOT PRESENT\n", i); 4831 continue; 4832 } 4833 4834 cpus[i].logical_cpu_id = i; 4835 4836 /* get package information */ 4837 cpus[i].physical_package_id = get_physical_package_id(i); 4838 if (cpus[i].physical_package_id > max_package_id) 4839 max_package_id = cpus[i].physical_package_id; 4840 4841 /* get numa node information */ 4842 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]); 4843 if (cpus[i].physical_node_id > topo.max_node_num) 4844 topo.max_node_num = cpus[i].physical_node_id; 4845 4846 /* get core information */ 4847 cpus[i].physical_core_id = get_core_id(i); 4848 if (cpus[i].physical_core_id > max_core_id) 4849 max_core_id = cpus[i].physical_core_id; 4850 4851 /* get thread information */ 4852 siblings = get_thread_siblings(&cpus[i]); 4853 if (siblings > max_siblings) 4854 max_siblings = siblings; 4855 if (cpus[i].thread_id == 0) 4856 topo.num_cores++; 4857 } 4858 4859 topo.cores_per_node = max_core_id + 1; 4860 if (debug > 1) 4861 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", 4862 max_core_id, topo.cores_per_node); 4863 if (!summary_only && topo.cores_per_node > 1) 4864 BIC_PRESENT(BIC_Core); 4865 4866 topo.num_packages = max_package_id + 1; 4867 if (debug > 1) 4868 fprintf(outf, "max_package_id %d, sizing for %d packages\n", 4869 max_package_id, topo.num_packages); 4870 if (!summary_only && topo.num_packages > 1) 4871 BIC_PRESENT(BIC_Package); 4872 4873 set_node_data(); 4874 if (debug > 1) 4875 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg); 4876 if (!summary_only && topo.nodes_per_pkg > 1) 4877 BIC_PRESENT(BIC_Node); 4878 4879 topo.threads_per_core = max_siblings; 4880 if (debug > 1) 4881 fprintf(outf, "max_siblings %d\n", max_siblings); 4882 4883 if (debug < 1) 4884 return; 4885 4886 for (i = 0; i <= topo.max_cpu_num; ++i) { 4887 if (cpu_is_not_present(i)) 4888 continue; 4889 fprintf(outf, 4890 "cpu %d pkg %d node %d lnode %d core %d thread %d\n", 4891 i, cpus[i].physical_package_id, 4892 cpus[i].physical_node_id, 4893 cpus[i].logical_node_id, 4894 cpus[i].physical_core_id, 4895 cpus[i].thread_id); 4896 } 4897 4898 } 4899 4900 void 4901 allocate_counters(struct thread_data **t, struct core_data **c, 4902 struct pkg_data **p) 4903 { 4904 int i; 4905 int num_cores = topo.cores_per_node * topo.nodes_per_pkg * 4906 topo.num_packages; 4907 int num_threads = topo.threads_per_core * num_cores; 4908 4909 *t = calloc(num_threads, sizeof(struct thread_data)); 4910 if (*t == NULL) 4911 goto error; 4912 4913 for (i = 0; i < num_threads; i++) 4914 (*t)[i].cpu_id = -1; 4915 4916 *c = calloc(num_cores, sizeof(struct core_data)); 4917 if (*c == NULL) 4918 goto error; 4919 4920 for (i = 0; i < num_cores; i++) 4921 (*c)[i].core_id = -1; 4922 4923 *p = calloc(topo.num_packages, sizeof(struct pkg_data)); 4924 if (*p == NULL) 4925 goto error; 4926 4927 for (i = 0; i < topo.num_packages; i++) 4928 (*p)[i].package_id = i; 4929 4930 return; 4931 error: 4932 err(1, "calloc counters"); 4933 } 4934 /* 4935 * init_counter() 4936 * 4937 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE 4938 */ 4939 void init_counter(struct thread_data *thread_base, struct core_data *core_base, 4940 struct pkg_data *pkg_base, int cpu_id) 4941 { 4942 int pkg_id = cpus[cpu_id].physical_package_id; 4943 int node_id = cpus[cpu_id].logical_node_id; 4944 int core_id = cpus[cpu_id].physical_core_id; 4945 int thread_id = cpus[cpu_id].thread_id; 4946 struct thread_data *t; 4947 struct core_data *c; 4948 struct pkg_data *p; 4949 4950 4951 /* Workaround for systems where physical_node_id==-1 4952 * and logical_node_id==(-1 - topo.num_cpus) 4953 */ 4954 if (node_id < 0) 4955 node_id = 0; 4956 4957 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id); 4958 c = GET_CORE(core_base, core_id, node_id, pkg_id); 4959 p = GET_PKG(pkg_base, pkg_id); 4960 4961 t->cpu_id = cpu_id; 4962 if (thread_id == 0) { 4963 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; 4964 if (cpu_is_first_core_in_package(cpu_id)) 4965 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; 4966 } 4967 4968 c->core_id = core_id; 4969 p->package_id = pkg_id; 4970 } 4971 4972 4973 int initialize_counters(int cpu_id) 4974 { 4975 init_counter(EVEN_COUNTERS, cpu_id); 4976 init_counter(ODD_COUNTERS, cpu_id); 4977 return 0; 4978 } 4979 4980 void allocate_output_buffer() 4981 { 4982 output_buffer = calloc(1, (1 + topo.num_cpus) * 1024); 4983 outp = output_buffer; 4984 if (outp == NULL) 4985 err(-1, "calloc output buffer"); 4986 } 4987 void allocate_fd_percpu(void) 4988 { 4989 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 4990 if (fd_percpu == NULL) 4991 err(-1, "calloc fd_percpu"); 4992 } 4993 void allocate_irq_buffers(void) 4994 { 4995 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); 4996 if (irq_column_2_cpu == NULL) 4997 err(-1, "calloc %d", topo.num_cpus); 4998 4999 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 5000 if (irqs_per_cpu == NULL) 5001 err(-1, "calloc %d", topo.max_cpu_num + 1); 5002 } 5003 void setup_all_buffers(void) 5004 { 5005 topology_probe(); 5006 allocate_irq_buffers(); 5007 allocate_fd_percpu(); 5008 allocate_counters(&thread_even, &core_even, &package_even); 5009 allocate_counters(&thread_odd, &core_odd, &package_odd); 5010 allocate_output_buffer(); 5011 for_all_proc_cpus(initialize_counters); 5012 } 5013 5014 void set_base_cpu(void) 5015 { 5016 base_cpu = sched_getcpu(); 5017 if (base_cpu < 0) 5018 err(-ENODEV, "No valid cpus found"); 5019 5020 if (debug > 1) 5021 fprintf(outf, "base_cpu = %d\n", base_cpu); 5022 } 5023 5024 void turbostat_init() 5025 { 5026 setup_all_buffers(); 5027 set_base_cpu(); 5028 check_dev_msr(); 5029 check_permissions(); 5030 process_cpuid(); 5031 5032 5033 if (!quiet) 5034 for_all_cpus(print_hwp, ODD_COUNTERS); 5035 5036 if (!quiet) 5037 for_all_cpus(print_epb, ODD_COUNTERS); 5038 5039 if (!quiet) 5040 for_all_cpus(print_perf_limit, ODD_COUNTERS); 5041 5042 if (!quiet) 5043 for_all_cpus(print_rapl, ODD_COUNTERS); 5044 5045 for_all_cpus(set_temperature_target, ODD_COUNTERS); 5046 5047 if (!quiet) 5048 for_all_cpus(print_thermal, ODD_COUNTERS); 5049 5050 if (!quiet && do_irtl_snb) 5051 print_irtl(); 5052 } 5053 5054 int fork_it(char **argv) 5055 { 5056 pid_t child_pid; 5057 int status; 5058 5059 snapshot_proc_sysfs_files(); 5060 status = for_all_cpus(get_counters, EVEN_COUNTERS); 5061 first_counter_read = 0; 5062 if (status) 5063 exit(status); 5064 /* clear affinity side-effect of get_counters() */ 5065 sched_setaffinity(0, cpu_present_setsize, cpu_present_set); 5066 gettimeofday(&tv_even, (struct timezone *)NULL); 5067 5068 child_pid = fork(); 5069 if (!child_pid) { 5070 /* child */ 5071 execvp(argv[0], argv); 5072 err(errno, "exec %s", argv[0]); 5073 } else { 5074 5075 /* parent */ 5076 if (child_pid == -1) 5077 err(1, "fork"); 5078 5079 signal(SIGINT, SIG_IGN); 5080 signal(SIGQUIT, SIG_IGN); 5081 if (waitpid(child_pid, &status, 0) == -1) 5082 err(status, "waitpid"); 5083 } 5084 /* 5085 * n.b. fork_it() does not check for errors from for_all_cpus() 5086 * because re-starting is problematic when forking 5087 */ 5088 snapshot_proc_sysfs_files(); 5089 for_all_cpus(get_counters, ODD_COUNTERS); 5090 gettimeofday(&tv_odd, (struct timezone *)NULL); 5091 timersub(&tv_odd, &tv_even, &tv_delta); 5092 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) 5093 fprintf(outf, "%s: Counter reset detected\n", progname); 5094 else { 5095 compute_average(EVEN_COUNTERS); 5096 format_all_counters(EVEN_COUNTERS); 5097 } 5098 5099 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0); 5100 5101 flush_output_stderr(); 5102 5103 return status; 5104 } 5105 5106 int get_and_dump_counters(void) 5107 { 5108 int status; 5109 5110 snapshot_proc_sysfs_files(); 5111 status = for_all_cpus(get_counters, ODD_COUNTERS); 5112 if (status) 5113 return status; 5114 5115 status = for_all_cpus(dump_counters, ODD_COUNTERS); 5116 if (status) 5117 return status; 5118 5119 flush_output_stdout(); 5120 5121 return status; 5122 } 5123 5124 void print_version() { 5125 fprintf(outf, "turbostat version 18.07.27" 5126 " - Len Brown <lenb@kernel.org>\n"); 5127 } 5128 5129 int add_counter(unsigned int msr_num, char *path, char *name, 5130 unsigned int width, enum counter_scope scope, 5131 enum counter_type type, enum counter_format format, int flags) 5132 { 5133 struct msr_counter *msrp; 5134 5135 msrp = calloc(1, sizeof(struct msr_counter)); 5136 if (msrp == NULL) { 5137 perror("calloc"); 5138 exit(1); 5139 } 5140 5141 msrp->msr_num = msr_num; 5142 strncpy(msrp->name, name, NAME_BYTES); 5143 if (path) 5144 strncpy(msrp->path, path, PATH_BYTES); 5145 msrp->width = width; 5146 msrp->type = type; 5147 msrp->format = format; 5148 msrp->flags = flags; 5149 5150 switch (scope) { 5151 5152 case SCOPE_CPU: 5153 msrp->next = sys.tp; 5154 sys.tp = msrp; 5155 sys.added_thread_counters++; 5156 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) { 5157 fprintf(stderr, "exceeded max %d added thread counters\n", 5158 MAX_ADDED_COUNTERS); 5159 exit(-1); 5160 } 5161 break; 5162 5163 case SCOPE_CORE: 5164 msrp->next = sys.cp; 5165 sys.cp = msrp; 5166 sys.added_core_counters++; 5167 if (sys.added_core_counters > MAX_ADDED_COUNTERS) { 5168 fprintf(stderr, "exceeded max %d added core counters\n", 5169 MAX_ADDED_COUNTERS); 5170 exit(-1); 5171 } 5172 break; 5173 5174 case SCOPE_PACKAGE: 5175 msrp->next = sys.pp; 5176 sys.pp = msrp; 5177 sys.added_package_counters++; 5178 if (sys.added_package_counters > MAX_ADDED_COUNTERS) { 5179 fprintf(stderr, "exceeded max %d added package counters\n", 5180 MAX_ADDED_COUNTERS); 5181 exit(-1); 5182 } 5183 break; 5184 } 5185 5186 return 0; 5187 } 5188 5189 void parse_add_command(char *add_command) 5190 { 5191 int msr_num = 0; 5192 char *path = NULL; 5193 char name_buffer[NAME_BYTES] = ""; 5194 int width = 64; 5195 int fail = 0; 5196 enum counter_scope scope = SCOPE_CPU; 5197 enum counter_type type = COUNTER_CYCLES; 5198 enum counter_format format = FORMAT_DELTA; 5199 5200 while (add_command) { 5201 5202 if (sscanf(add_command, "msr0x%x", &msr_num) == 1) 5203 goto next; 5204 5205 if (sscanf(add_command, "msr%d", &msr_num) == 1) 5206 goto next; 5207 5208 if (*add_command == '/') { 5209 path = add_command; 5210 goto next; 5211 } 5212 5213 if (sscanf(add_command, "u%d", &width) == 1) { 5214 if ((width == 32) || (width == 64)) 5215 goto next; 5216 width = 64; 5217 } 5218 if (!strncmp(add_command, "cpu", strlen("cpu"))) { 5219 scope = SCOPE_CPU; 5220 goto next; 5221 } 5222 if (!strncmp(add_command, "core", strlen("core"))) { 5223 scope = SCOPE_CORE; 5224 goto next; 5225 } 5226 if (!strncmp(add_command, "package", strlen("package"))) { 5227 scope = SCOPE_PACKAGE; 5228 goto next; 5229 } 5230 if (!strncmp(add_command, "cycles", strlen("cycles"))) { 5231 type = COUNTER_CYCLES; 5232 goto next; 5233 } 5234 if (!strncmp(add_command, "seconds", strlen("seconds"))) { 5235 type = COUNTER_SECONDS; 5236 goto next; 5237 } 5238 if (!strncmp(add_command, "usec", strlen("usec"))) { 5239 type = COUNTER_USEC; 5240 goto next; 5241 } 5242 if (!strncmp(add_command, "raw", strlen("raw"))) { 5243 format = FORMAT_RAW; 5244 goto next; 5245 } 5246 if (!strncmp(add_command, "delta", strlen("delta"))) { 5247 format = FORMAT_DELTA; 5248 goto next; 5249 } 5250 if (!strncmp(add_command, "percent", strlen("percent"))) { 5251 format = FORMAT_PERCENT; 5252 goto next; 5253 } 5254 5255 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */ 5256 char *eos; 5257 5258 eos = strchr(name_buffer, ','); 5259 if (eos) 5260 *eos = '\0'; 5261 goto next; 5262 } 5263 5264 next: 5265 add_command = strchr(add_command, ','); 5266 if (add_command) { 5267 *add_command = '\0'; 5268 add_command++; 5269 } 5270 5271 } 5272 if ((msr_num == 0) && (path == NULL)) { 5273 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n"); 5274 fail++; 5275 } 5276 5277 /* generate default column header */ 5278 if (*name_buffer == '\0') { 5279 if (width == 32) 5280 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 5281 else 5282 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 5283 } 5284 5285 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0)) 5286 fail++; 5287 5288 if (fail) { 5289 help(); 5290 exit(1); 5291 } 5292 } 5293 5294 int is_deferred_skip(char *name) 5295 { 5296 int i; 5297 5298 for (i = 0; i < deferred_skip_index; ++i) 5299 if (!strcmp(name, deferred_skip_names[i])) 5300 return 1; 5301 return 0; 5302 } 5303 5304 void probe_sysfs(void) 5305 { 5306 char path[64]; 5307 char name_buf[16]; 5308 FILE *input; 5309 int state; 5310 char *sp; 5311 5312 if (!DO_BIC(BIC_sysfs)) 5313 return; 5314 5315 for (state = 10; state >= 0; --state) { 5316 5317 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 5318 base_cpu, state); 5319 input = fopen(path, "r"); 5320 if (input == NULL) 5321 continue; 5322 fgets(name_buf, sizeof(name_buf), input); 5323 5324 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 5325 sp = strchr(name_buf, '-'); 5326 if (!sp) 5327 sp = strchrnul(name_buf, '\n'); 5328 *sp = '%'; 5329 *(sp + 1) = '\0'; 5330 5331 fclose(input); 5332 5333 sprintf(path, "cpuidle/state%d/time", state); 5334 5335 if (is_deferred_skip(name_buf)) 5336 continue; 5337 5338 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC, 5339 FORMAT_PERCENT, SYSFS_PERCPU); 5340 } 5341 5342 for (state = 10; state >= 0; --state) { 5343 5344 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 5345 base_cpu, state); 5346 input = fopen(path, "r"); 5347 if (input == NULL) 5348 continue; 5349 fgets(name_buf, sizeof(name_buf), input); 5350 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 5351 sp = strchr(name_buf, '-'); 5352 if (!sp) 5353 sp = strchrnul(name_buf, '\n'); 5354 *sp = '\0'; 5355 fclose(input); 5356 5357 sprintf(path, "cpuidle/state%d/usage", state); 5358 5359 if (is_deferred_skip(name_buf)) 5360 continue; 5361 5362 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS, 5363 FORMAT_DELTA, SYSFS_PERCPU); 5364 } 5365 5366 } 5367 5368 5369 /* 5370 * parse cpuset with following syntax 5371 * 1,2,4..6,8-10 and set bits in cpu_subset 5372 */ 5373 void parse_cpu_command(char *optarg) 5374 { 5375 unsigned int start, end; 5376 char *next; 5377 5378 if (!strcmp(optarg, "core")) { 5379 if (cpu_subset) 5380 goto error; 5381 show_core_only++; 5382 return; 5383 } 5384 if (!strcmp(optarg, "package")) { 5385 if (cpu_subset) 5386 goto error; 5387 show_pkg_only++; 5388 return; 5389 } 5390 if (show_core_only || show_pkg_only) 5391 goto error; 5392 5393 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS); 5394 if (cpu_subset == NULL) 5395 err(3, "CPU_ALLOC"); 5396 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS); 5397 5398 CPU_ZERO_S(cpu_subset_size, cpu_subset); 5399 5400 next = optarg; 5401 5402 while (next && *next) { 5403 5404 if (*next == '-') /* no negative cpu numbers */ 5405 goto error; 5406 5407 start = strtoul(next, &next, 10); 5408 5409 if (start >= CPU_SUBSET_MAXCPUS) 5410 goto error; 5411 CPU_SET_S(start, cpu_subset_size, cpu_subset); 5412 5413 if (*next == '\0') 5414 break; 5415 5416 if (*next == ',') { 5417 next += 1; 5418 continue; 5419 } 5420 5421 if (*next == '-') { 5422 next += 1; /* start range */ 5423 } else if (*next == '.') { 5424 next += 1; 5425 if (*next == '.') 5426 next += 1; /* start range */ 5427 else 5428 goto error; 5429 } 5430 5431 end = strtoul(next, &next, 10); 5432 if (end <= start) 5433 goto error; 5434 5435 while (++start <= end) { 5436 if (start >= CPU_SUBSET_MAXCPUS) 5437 goto error; 5438 CPU_SET_S(start, cpu_subset_size, cpu_subset); 5439 } 5440 5441 if (*next == ',') 5442 next += 1; 5443 else if (*next != '\0') 5444 goto error; 5445 } 5446 5447 return; 5448 5449 error: 5450 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg); 5451 help(); 5452 exit(-1); 5453 } 5454 5455 5456 void cmdline(int argc, char **argv) 5457 { 5458 int opt; 5459 int option_index = 0; 5460 static struct option long_options[] = { 5461 {"add", required_argument, 0, 'a'}, 5462 {"cpu", required_argument, 0, 'c'}, 5463 {"Dump", no_argument, 0, 'D'}, 5464 {"debug", no_argument, 0, 'd'}, /* internal, not documented */ 5465 {"enable", required_argument, 0, 'e'}, 5466 {"interval", required_argument, 0, 'i'}, 5467 {"num_iterations", required_argument, 0, 'n'}, 5468 {"help", no_argument, 0, 'h'}, 5469 {"hide", required_argument, 0, 'H'}, // meh, -h taken by --help 5470 {"Joules", no_argument, 0, 'J'}, 5471 {"list", no_argument, 0, 'l'}, 5472 {"out", required_argument, 0, 'o'}, 5473 {"quiet", no_argument, 0, 'q'}, 5474 {"show", required_argument, 0, 's'}, 5475 {"Summary", no_argument, 0, 'S'}, 5476 {"TCC", required_argument, 0, 'T'}, 5477 {"version", no_argument, 0, 'v' }, 5478 {0, 0, 0, 0 } 5479 }; 5480 5481 progname = argv[0]; 5482 5483 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v", 5484 long_options, &option_index)) != -1) { 5485 switch (opt) { 5486 case 'a': 5487 parse_add_command(optarg); 5488 break; 5489 case 'c': 5490 parse_cpu_command(optarg); 5491 break; 5492 case 'D': 5493 dump_only++; 5494 break; 5495 case 'e': 5496 /* --enable specified counter */ 5497 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST); 5498 break; 5499 case 'd': 5500 debug++; 5501 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 5502 break; 5503 case 'H': 5504 /* 5505 * --hide: do not show those specified 5506 * multiple invocations simply clear more bits in enabled mask 5507 */ 5508 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST); 5509 break; 5510 case 'h': 5511 default: 5512 help(); 5513 exit(1); 5514 case 'i': 5515 { 5516 double interval = strtod(optarg, NULL); 5517 5518 if (interval < 0.001) { 5519 fprintf(outf, "interval %f seconds is too small\n", 5520 interval); 5521 exit(2); 5522 } 5523 5524 interval_tv.tv_sec = interval_ts.tv_sec = interval; 5525 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000; 5526 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; 5527 } 5528 break; 5529 case 'J': 5530 rapl_joules++; 5531 break; 5532 case 'l': 5533 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 5534 list_header_only++; 5535 quiet++; 5536 break; 5537 case 'o': 5538 outf = fopen_or_die(optarg, "w"); 5539 break; 5540 case 'q': 5541 quiet = 1; 5542 break; 5543 case 'n': 5544 num_iterations = strtod(optarg, NULL); 5545 5546 if (num_iterations <= 0) { 5547 fprintf(outf, "iterations %d should be positive number\n", 5548 num_iterations); 5549 exit(2); 5550 } 5551 break; 5552 case 's': 5553 /* 5554 * --show: show only those specified 5555 * The 1st invocation will clear and replace the enabled mask 5556 * subsequent invocations can add to it. 5557 */ 5558 if (shown == 0) 5559 bic_enabled = bic_lookup(optarg, SHOW_LIST); 5560 else 5561 bic_enabled |= bic_lookup(optarg, SHOW_LIST); 5562 shown = 1; 5563 break; 5564 case 'S': 5565 summary_only++; 5566 break; 5567 case 'T': 5568 tcc_activation_temp_override = atoi(optarg); 5569 break; 5570 case 'v': 5571 print_version(); 5572 exit(0); 5573 break; 5574 } 5575 } 5576 } 5577 5578 int main(int argc, char **argv) 5579 { 5580 outf = stderr; 5581 cmdline(argc, argv); 5582 5583 if (!quiet) 5584 print_version(); 5585 5586 probe_sysfs(); 5587 5588 turbostat_init(); 5589 5590 /* dump counters and exit */ 5591 if (dump_only) 5592 return get_and_dump_counters(); 5593 5594 /* list header and exit */ 5595 if (list_header_only) { 5596 print_header(","); 5597 flush_output_stdout(); 5598 return 0; 5599 } 5600 5601 /* 5602 * if any params left, it must be a command to fork 5603 */ 5604 if (argc - optind) 5605 return fork_it(argv + optind); 5606 else 5607 turbostat_loop(); 5608 5609 return 0; 5610 } 5611