1 /* 2 * turbostat -- show CPU frequency and C-state residency 3 * on modern Intel and AMD processors. 4 * 5 * Copyright (c) 2013 Intel Corporation. 6 * Len Brown <len.brown@intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 20 */ 21 22 #define _GNU_SOURCE 23 #include MSRHEADER 24 #include INTEL_FAMILY_HEADER 25 #include <stdarg.h> 26 #include <stdio.h> 27 #include <err.h> 28 #include <unistd.h> 29 #include <sys/types.h> 30 #include <sys/wait.h> 31 #include <sys/stat.h> 32 #include <sys/select.h> 33 #include <sys/resource.h> 34 #include <fcntl.h> 35 #include <signal.h> 36 #include <sys/time.h> 37 #include <stdlib.h> 38 #include <getopt.h> 39 #include <dirent.h> 40 #include <string.h> 41 #include <ctype.h> 42 #include <sched.h> 43 #include <time.h> 44 #include <cpuid.h> 45 #include <linux/capability.h> 46 #include <errno.h> 47 #include <math.h> 48 49 char *proc_stat = "/proc/stat"; 50 FILE *outf; 51 int *fd_percpu; 52 struct timeval interval_tv = {5, 0}; 53 struct timespec interval_ts = {5, 0}; 54 struct timespec one_msec = {0, 1000000}; 55 unsigned int num_iterations; 56 unsigned int debug; 57 unsigned int quiet; 58 unsigned int shown; 59 unsigned int sums_need_wide_columns; 60 unsigned int rapl_joules; 61 unsigned int summary_only; 62 unsigned int list_header_only; 63 unsigned int dump_only; 64 unsigned int do_snb_cstates; 65 unsigned int do_knl_cstates; 66 unsigned int do_slm_cstates; 67 unsigned int use_c1_residency_msr; 68 unsigned int has_aperf; 69 unsigned int has_epb; 70 unsigned int do_irtl_snb; 71 unsigned int do_irtl_hsw; 72 unsigned int units = 1000000; /* MHz etc */ 73 unsigned int genuine_intel; 74 unsigned int authentic_amd; 75 unsigned int max_level, max_extended_level; 76 unsigned int has_invariant_tsc; 77 unsigned int do_nhm_platform_info; 78 unsigned int no_MSR_MISC_PWR_MGMT; 79 unsigned int aperf_mperf_multiplier = 1; 80 double bclk; 81 double base_hz; 82 unsigned int has_base_hz; 83 double tsc_tweak = 1.0; 84 unsigned int show_pkg_only; 85 unsigned int show_core_only; 86 char *output_buffer, *outp; 87 unsigned int do_rapl; 88 unsigned int do_dts; 89 unsigned int do_ptm; 90 unsigned long long gfx_cur_rc6_ms; 91 unsigned long long cpuidle_cur_cpu_lpi_us; 92 unsigned long long cpuidle_cur_sys_lpi_us; 93 unsigned int gfx_cur_mhz; 94 unsigned int tcc_activation_temp; 95 unsigned int tcc_activation_temp_override; 96 double rapl_power_units, rapl_time_units; 97 double rapl_dram_energy_units, rapl_energy_units; 98 double rapl_joule_counter_range; 99 unsigned int do_core_perf_limit_reasons; 100 unsigned int has_automatic_cstate_conversion; 101 unsigned int do_gfx_perf_limit_reasons; 102 unsigned int do_ring_perf_limit_reasons; 103 unsigned int crystal_hz; 104 unsigned long long tsc_hz; 105 int base_cpu; 106 double discover_bclk(unsigned int family, unsigned int model); 107 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ 108 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ 109 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ 110 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ 111 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ 112 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ 113 unsigned int has_misc_feature_control; 114 unsigned int first_counter_read = 1; 115 116 #define RAPL_PKG (1 << 0) 117 /* 0x610 MSR_PKG_POWER_LIMIT */ 118 /* 0x611 MSR_PKG_ENERGY_STATUS */ 119 #define RAPL_PKG_PERF_STATUS (1 << 1) 120 /* 0x613 MSR_PKG_PERF_STATUS */ 121 #define RAPL_PKG_POWER_INFO (1 << 2) 122 /* 0x614 MSR_PKG_POWER_INFO */ 123 124 #define RAPL_DRAM (1 << 3) 125 /* 0x618 MSR_DRAM_POWER_LIMIT */ 126 /* 0x619 MSR_DRAM_ENERGY_STATUS */ 127 #define RAPL_DRAM_PERF_STATUS (1 << 4) 128 /* 0x61b MSR_DRAM_PERF_STATUS */ 129 #define RAPL_DRAM_POWER_INFO (1 << 5) 130 /* 0x61c MSR_DRAM_POWER_INFO */ 131 132 #define RAPL_CORES_POWER_LIMIT (1 << 6) 133 /* 0x638 MSR_PP0_POWER_LIMIT */ 134 #define RAPL_CORE_POLICY (1 << 7) 135 /* 0x63a MSR_PP0_POLICY */ 136 137 #define RAPL_GFX (1 << 8) 138 /* 0x640 MSR_PP1_POWER_LIMIT */ 139 /* 0x641 MSR_PP1_ENERGY_STATUS */ 140 /* 0x642 MSR_PP1_POLICY */ 141 142 #define RAPL_CORES_ENERGY_STATUS (1 << 9) 143 /* 0x639 MSR_PP0_ENERGY_STATUS */ 144 #define RAPL_PER_CORE_ENERGY (1 << 10) 145 /* Indicates cores energy collection is per-core, 146 * not per-package. */ 147 #define RAPL_AMD_F17H (1 << 11) 148 /* 0xc0010299 MSR_RAPL_PWR_UNIT */ 149 /* 0xc001029a MSR_CORE_ENERGY_STAT */ 150 /* 0xc001029b MSR_PKG_ENERGY_STAT */ 151 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT) 152 #define TJMAX_DEFAULT 100 153 154 /* MSRs that are not yet in the kernel-provided header. */ 155 #define MSR_RAPL_PWR_UNIT 0xc0010299 156 #define MSR_CORE_ENERGY_STAT 0xc001029a 157 #define MSR_PKG_ENERGY_STAT 0xc001029b 158 159 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 160 161 /* 162 * buffer size used by sscanf() for added column names 163 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters 164 */ 165 #define NAME_BYTES 20 166 #define PATH_BYTES 128 167 168 int backwards_count; 169 char *progname; 170 171 #define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */ 172 cpu_set_t *cpu_present_set, *cpu_affinity_set, *cpu_subset; 173 size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size; 174 #define MAX_ADDED_COUNTERS 8 175 #define MAX_ADDED_THREAD_COUNTERS 24 176 #define BITMASK_SIZE 32 177 178 struct thread_data { 179 struct timeval tv_begin; 180 struct timeval tv_end; 181 unsigned long long tsc; 182 unsigned long long aperf; 183 unsigned long long mperf; 184 unsigned long long c1; 185 unsigned long long irq_count; 186 unsigned int smi_count; 187 unsigned int cpu_id; 188 unsigned int apic_id; 189 unsigned int x2apic_id; 190 unsigned int flags; 191 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2 192 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 193 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS]; 194 } *thread_even, *thread_odd; 195 196 struct core_data { 197 unsigned long long c3; 198 unsigned long long c6; 199 unsigned long long c7; 200 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */ 201 unsigned int core_temp_c; 202 unsigned int core_energy; /* MSR_CORE_ENERGY_STAT */ 203 unsigned int core_id; 204 unsigned long long counter[MAX_ADDED_COUNTERS]; 205 } *core_even, *core_odd; 206 207 struct pkg_data { 208 unsigned long long pc2; 209 unsigned long long pc3; 210 unsigned long long pc6; 211 unsigned long long pc7; 212 unsigned long long pc8; 213 unsigned long long pc9; 214 unsigned long long pc10; 215 unsigned long long cpu_lpi; 216 unsigned long long sys_lpi; 217 unsigned long long pkg_wtd_core_c0; 218 unsigned long long pkg_any_core_c0; 219 unsigned long long pkg_any_gfxe_c0; 220 unsigned long long pkg_both_core_gfxe_c0; 221 long long gfx_rc6_ms; 222 unsigned int gfx_mhz; 223 unsigned int package_id; 224 unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */ 225 unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */ 226 unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */ 227 unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */ 228 unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ 229 unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ 230 unsigned int pkg_temp_c; 231 unsigned long long counter[MAX_ADDED_COUNTERS]; 232 } *package_even, *package_odd; 233 234 #define ODD_COUNTERS thread_odd, core_odd, package_odd 235 #define EVEN_COUNTERS thread_even, core_even, package_even 236 237 #define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \ 238 ((thread_base) + \ 239 ((pkg_no) * \ 240 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \ 241 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \ 242 ((core_no) * topo.threads_per_core) + \ 243 (thread_no)) 244 245 #define GET_CORE(core_base, core_no, node_no, pkg_no) \ 246 ((core_base) + \ 247 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \ 248 ((node_no) * topo.cores_per_node) + \ 249 (core_no)) 250 251 252 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) 253 254 enum counter_scope {SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE}; 255 enum counter_type {COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC}; 256 enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT}; 257 258 struct msr_counter { 259 unsigned int msr_num; 260 char name[NAME_BYTES]; 261 char path[PATH_BYTES]; 262 unsigned int width; 263 enum counter_type type; 264 enum counter_format format; 265 struct msr_counter *next; 266 unsigned int flags; 267 #define FLAGS_HIDE (1 << 0) 268 #define FLAGS_SHOW (1 << 1) 269 #define SYSFS_PERCPU (1 << 1) 270 }; 271 272 struct sys_counters { 273 unsigned int added_thread_counters; 274 unsigned int added_core_counters; 275 unsigned int added_package_counters; 276 struct msr_counter *tp; 277 struct msr_counter *cp; 278 struct msr_counter *pp; 279 } sys; 280 281 struct system_summary { 282 struct thread_data threads; 283 struct core_data cores; 284 struct pkg_data packages; 285 } average; 286 287 struct cpu_topology { 288 int physical_package_id; 289 int die_id; 290 int logical_cpu_id; 291 int physical_node_id; 292 int logical_node_id; /* 0-based count within the package */ 293 int physical_core_id; 294 int thread_id; 295 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */ 296 } *cpus; 297 298 struct topo_params { 299 int num_packages; 300 int num_die; 301 int num_cpus; 302 int num_cores; 303 int max_cpu_num; 304 int max_node_num; 305 int nodes_per_pkg; 306 int cores_per_node; 307 int threads_per_core; 308 } topo; 309 310 struct timeval tv_even, tv_odd, tv_delta; 311 312 int *irq_column_2_cpu; /* /proc/interrupts column numbers */ 313 int *irqs_per_cpu; /* indexed by cpu_num */ 314 315 void setup_all_buffers(void); 316 317 int cpu_is_not_present(int cpu) 318 { 319 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); 320 } 321 /* 322 * run func(thread, core, package) in topology order 323 * skip non-present cpus 324 */ 325 326 int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *), 327 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) 328 { 329 int retval, pkg_no, core_no, thread_no, node_no; 330 331 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 332 for (node_no = 0; node_no < topo.nodes_per_pkg; node_no++) { 333 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) { 334 for (thread_no = 0; thread_no < 335 topo.threads_per_core; ++thread_no) { 336 struct thread_data *t; 337 struct core_data *c; 338 struct pkg_data *p; 339 340 t = GET_THREAD(thread_base, thread_no, 341 core_no, node_no, 342 pkg_no); 343 344 if (cpu_is_not_present(t->cpu_id)) 345 continue; 346 347 c = GET_CORE(core_base, core_no, 348 node_no, pkg_no); 349 p = GET_PKG(pkg_base, pkg_no); 350 351 retval = func(t, c, p); 352 if (retval) 353 return retval; 354 } 355 } 356 } 357 } 358 return 0; 359 } 360 361 int cpu_migrate(int cpu) 362 { 363 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 364 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); 365 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) 366 return -1; 367 else 368 return 0; 369 } 370 int get_msr_fd(int cpu) 371 { 372 char pathname[32]; 373 int fd; 374 375 fd = fd_percpu[cpu]; 376 377 if (fd) 378 return fd; 379 380 sprintf(pathname, "/dev/cpu/%d/msr", cpu); 381 fd = open(pathname, O_RDONLY); 382 if (fd < 0) 383 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); 384 385 fd_percpu[cpu] = fd; 386 387 return fd; 388 } 389 390 int get_msr(int cpu, off_t offset, unsigned long long *msr) 391 { 392 ssize_t retval; 393 394 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); 395 396 if (retval != sizeof *msr) 397 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset); 398 399 return 0; 400 } 401 402 /* 403 * This list matches the column headers, except 404 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time 405 * 2. Core and CPU are moved to the end, we can't have strings that contain them 406 * matching on them for --show and --hide. 407 */ 408 struct msr_counter bic[] = { 409 { 0x0, "usec" }, 410 { 0x0, "Time_Of_Day_Seconds" }, 411 { 0x0, "Package" }, 412 { 0x0, "Node" }, 413 { 0x0, "Avg_MHz" }, 414 { 0x0, "Busy%" }, 415 { 0x0, "Bzy_MHz" }, 416 { 0x0, "TSC_MHz" }, 417 { 0x0, "IRQ" }, 418 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL}, 419 { 0x0, "sysfs" }, 420 { 0x0, "CPU%c1" }, 421 { 0x0, "CPU%c3" }, 422 { 0x0, "CPU%c6" }, 423 { 0x0, "CPU%c7" }, 424 { 0x0, "ThreadC" }, 425 { 0x0, "CoreTmp" }, 426 { 0x0, "CoreCnt" }, 427 { 0x0, "PkgTmp" }, 428 { 0x0, "GFX%rc6" }, 429 { 0x0, "GFXMHz" }, 430 { 0x0, "Pkg%pc2" }, 431 { 0x0, "Pkg%pc3" }, 432 { 0x0, "Pkg%pc6" }, 433 { 0x0, "Pkg%pc7" }, 434 { 0x0, "Pkg%pc8" }, 435 { 0x0, "Pkg%pc9" }, 436 { 0x0, "Pk%pc10" }, 437 { 0x0, "CPU%LPI" }, 438 { 0x0, "SYS%LPI" }, 439 { 0x0, "PkgWatt" }, 440 { 0x0, "CorWatt" }, 441 { 0x0, "GFXWatt" }, 442 { 0x0, "PkgCnt" }, 443 { 0x0, "RAMWatt" }, 444 { 0x0, "PKG_%" }, 445 { 0x0, "RAM_%" }, 446 { 0x0, "Pkg_J" }, 447 { 0x0, "Cor_J" }, 448 { 0x0, "GFX_J" }, 449 { 0x0, "RAM_J" }, 450 { 0x0, "Mod%c6" }, 451 { 0x0, "Totl%C0" }, 452 { 0x0, "Any%C0" }, 453 { 0x0, "GFX%C0" }, 454 { 0x0, "CPUGFX%" }, 455 { 0x0, "Core" }, 456 { 0x0, "CPU" }, 457 { 0x0, "APIC" }, 458 { 0x0, "X2APIC" }, 459 { 0x0, "Die" }, 460 }; 461 462 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter)) 463 #define BIC_USEC (1ULL << 0) 464 #define BIC_TOD (1ULL << 1) 465 #define BIC_Package (1ULL << 2) 466 #define BIC_Node (1ULL << 3) 467 #define BIC_Avg_MHz (1ULL << 4) 468 #define BIC_Busy (1ULL << 5) 469 #define BIC_Bzy_MHz (1ULL << 6) 470 #define BIC_TSC_MHz (1ULL << 7) 471 #define BIC_IRQ (1ULL << 8) 472 #define BIC_SMI (1ULL << 9) 473 #define BIC_sysfs (1ULL << 10) 474 #define BIC_CPU_c1 (1ULL << 11) 475 #define BIC_CPU_c3 (1ULL << 12) 476 #define BIC_CPU_c6 (1ULL << 13) 477 #define BIC_CPU_c7 (1ULL << 14) 478 #define BIC_ThreadC (1ULL << 15) 479 #define BIC_CoreTmp (1ULL << 16) 480 #define BIC_CoreCnt (1ULL << 17) 481 #define BIC_PkgTmp (1ULL << 18) 482 #define BIC_GFX_rc6 (1ULL << 19) 483 #define BIC_GFXMHz (1ULL << 20) 484 #define BIC_Pkgpc2 (1ULL << 21) 485 #define BIC_Pkgpc3 (1ULL << 22) 486 #define BIC_Pkgpc6 (1ULL << 23) 487 #define BIC_Pkgpc7 (1ULL << 24) 488 #define BIC_Pkgpc8 (1ULL << 25) 489 #define BIC_Pkgpc9 (1ULL << 26) 490 #define BIC_Pkgpc10 (1ULL << 27) 491 #define BIC_CPU_LPI (1ULL << 28) 492 #define BIC_SYS_LPI (1ULL << 29) 493 #define BIC_PkgWatt (1ULL << 30) 494 #define BIC_CorWatt (1ULL << 31) 495 #define BIC_GFXWatt (1ULL << 32) 496 #define BIC_PkgCnt (1ULL << 33) 497 #define BIC_RAMWatt (1ULL << 34) 498 #define BIC_PKG__ (1ULL << 35) 499 #define BIC_RAM__ (1ULL << 36) 500 #define BIC_Pkg_J (1ULL << 37) 501 #define BIC_Cor_J (1ULL << 38) 502 #define BIC_GFX_J (1ULL << 39) 503 #define BIC_RAM_J (1ULL << 40) 504 #define BIC_Mod_c6 (1ULL << 41) 505 #define BIC_Totl_c0 (1ULL << 42) 506 #define BIC_Any_c0 (1ULL << 43) 507 #define BIC_GFX_c0 (1ULL << 44) 508 #define BIC_CPUGFX (1ULL << 45) 509 #define BIC_Core (1ULL << 46) 510 #define BIC_CPU (1ULL << 47) 511 #define BIC_APIC (1ULL << 48) 512 #define BIC_X2APIC (1ULL << 49) 513 #define BIC_Die (1ULL << 50) 514 515 #define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC) 516 517 unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT); 518 unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC; 519 520 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME) 521 #define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME) 522 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT) 523 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT) 524 525 526 #define MAX_DEFERRED 16 527 char *deferred_skip_names[MAX_DEFERRED]; 528 int deferred_skip_index; 529 530 /* 531 * HIDE_LIST - hide this list of counters, show the rest [default] 532 * SHOW_LIST - show this list of counters, hide the rest 533 */ 534 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST; 535 536 void help(void) 537 { 538 fprintf(outf, 539 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" 540 "\n" 541 "Turbostat forks the specified COMMAND and prints statistics\n" 542 "when COMMAND completes.\n" 543 "If no COMMAND is specified, turbostat wakes every 5-seconds\n" 544 "to print statistics, until interrupted.\n" 545 " -a, --add add a counter\n" 546 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n" 547 " -c, --cpu cpu-set limit output to summary plus cpu-set:\n" 548 " {core | package | j,k,l..m,n-p }\n" 549 " -d, --debug displays usec, Time_Of_Day_Seconds and more debugging\n" 550 " -D, --Dump displays the raw counter values\n" 551 " -e, --enable [all | column]\n" 552 " shows all or the specified disabled column\n" 553 " -H, --hide [column|column,column,...]\n" 554 " hide the specified column(s)\n" 555 " -i, --interval sec.subsec\n" 556 " Override default 5-second measurement interval\n" 557 " -J, --Joules displays energy in Joules instead of Watts\n" 558 " -l, --list list column headers only\n" 559 " -n, --num_iterations num\n" 560 " number of the measurement iterations\n" 561 " -o, --out file\n" 562 " create or truncate \"file\" for all output\n" 563 " -q, --quiet skip decoding system configuration header\n" 564 " -s, --show [column|column,column,...]\n" 565 " show only the specified column(s)\n" 566 " -S, --Summary\n" 567 " limits output to 1-line system summary per interval\n" 568 " -T, --TCC temperature\n" 569 " sets the Thermal Control Circuit temperature in\n" 570 " degrees Celsius\n" 571 " -h, --help print this help message\n" 572 " -v, --version print version information\n" 573 "\n" 574 "For more help, run \"man turbostat\"\n"); 575 } 576 577 /* 578 * bic_lookup 579 * for all the strings in comma separate name_list, 580 * set the approprate bit in return value. 581 */ 582 unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode) 583 { 584 int i; 585 unsigned long long retval = 0; 586 587 while (name_list) { 588 char *comma; 589 590 comma = strchr(name_list, ','); 591 592 if (comma) 593 *comma = '\0'; 594 595 if (!strcmp(name_list, "all")) 596 return ~0; 597 598 for (i = 0; i < MAX_BIC; ++i) { 599 if (!strcmp(name_list, bic[i].name)) { 600 retval |= (1ULL << i); 601 break; 602 } 603 } 604 if (i == MAX_BIC) { 605 if (mode == SHOW_LIST) { 606 fprintf(stderr, "Invalid counter name: %s\n", name_list); 607 exit(-1); 608 } 609 deferred_skip_names[deferred_skip_index++] = name_list; 610 if (debug) 611 fprintf(stderr, "deferred \"%s\"\n", name_list); 612 if (deferred_skip_index >= MAX_DEFERRED) { 613 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n", 614 MAX_DEFERRED, name_list); 615 help(); 616 exit(1); 617 } 618 } 619 620 name_list = comma; 621 if (name_list) 622 name_list++; 623 624 } 625 return retval; 626 } 627 628 629 void print_header(char *delim) 630 { 631 struct msr_counter *mp; 632 int printed = 0; 633 634 if (DO_BIC(BIC_USEC)) 635 outp += sprintf(outp, "%susec", (printed++ ? delim : "")); 636 if (DO_BIC(BIC_TOD)) 637 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : "")); 638 if (DO_BIC(BIC_Package)) 639 outp += sprintf(outp, "%sPackage", (printed++ ? delim : "")); 640 if (DO_BIC(BIC_Die)) 641 outp += sprintf(outp, "%sDie", (printed++ ? delim : "")); 642 if (DO_BIC(BIC_Node)) 643 outp += sprintf(outp, "%sNode", (printed++ ? delim : "")); 644 if (DO_BIC(BIC_Core)) 645 outp += sprintf(outp, "%sCore", (printed++ ? delim : "")); 646 if (DO_BIC(BIC_CPU)) 647 outp += sprintf(outp, "%sCPU", (printed++ ? delim : "")); 648 if (DO_BIC(BIC_APIC)) 649 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : "")); 650 if (DO_BIC(BIC_X2APIC)) 651 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : "")); 652 if (DO_BIC(BIC_Avg_MHz)) 653 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : "")); 654 if (DO_BIC(BIC_Busy)) 655 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : "")); 656 if (DO_BIC(BIC_Bzy_MHz)) 657 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : "")); 658 if (DO_BIC(BIC_TSC_MHz)) 659 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : "")); 660 661 if (DO_BIC(BIC_IRQ)) { 662 if (sums_need_wide_columns) 663 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : "")); 664 else 665 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : "")); 666 } 667 668 if (DO_BIC(BIC_SMI)) 669 outp += sprintf(outp, "%sSMI", (printed++ ? delim : "")); 670 671 for (mp = sys.tp; mp; mp = mp->next) { 672 673 if (mp->format == FORMAT_RAW) { 674 if (mp->width == 64) 675 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name); 676 else 677 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name); 678 } else { 679 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 680 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name); 681 else 682 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name); 683 } 684 } 685 686 if (DO_BIC(BIC_CPU_c1)) 687 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : "")); 688 if (DO_BIC(BIC_CPU_c3)) 689 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : "")); 690 if (DO_BIC(BIC_CPU_c6)) 691 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : "")); 692 if (DO_BIC(BIC_CPU_c7)) 693 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : "")); 694 695 if (DO_BIC(BIC_Mod_c6)) 696 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : "")); 697 698 if (DO_BIC(BIC_CoreTmp)) 699 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : "")); 700 701 if (do_rapl && !rapl_joules) { 702 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY)) 703 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 704 } else if (do_rapl && rapl_joules) { 705 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY)) 706 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 707 } 708 709 for (mp = sys.cp; mp; mp = mp->next) { 710 if (mp->format == FORMAT_RAW) { 711 if (mp->width == 64) 712 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 713 else 714 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 715 } else { 716 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 717 outp += sprintf(outp, "%s%8s", delim, mp->name); 718 else 719 outp += sprintf(outp, "%s%s", delim, mp->name); 720 } 721 } 722 723 if (DO_BIC(BIC_PkgTmp)) 724 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : "")); 725 726 if (DO_BIC(BIC_GFX_rc6)) 727 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : "")); 728 729 if (DO_BIC(BIC_GFXMHz)) 730 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : "")); 731 732 if (DO_BIC(BIC_Totl_c0)) 733 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : "")); 734 if (DO_BIC(BIC_Any_c0)) 735 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : "")); 736 if (DO_BIC(BIC_GFX_c0)) 737 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : "")); 738 if (DO_BIC(BIC_CPUGFX)) 739 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : "")); 740 741 if (DO_BIC(BIC_Pkgpc2)) 742 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : "")); 743 if (DO_BIC(BIC_Pkgpc3)) 744 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : "")); 745 if (DO_BIC(BIC_Pkgpc6)) 746 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : "")); 747 if (DO_BIC(BIC_Pkgpc7)) 748 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : "")); 749 if (DO_BIC(BIC_Pkgpc8)) 750 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : "")); 751 if (DO_BIC(BIC_Pkgpc9)) 752 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : "")); 753 if (DO_BIC(BIC_Pkgpc10)) 754 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : "")); 755 if (DO_BIC(BIC_CPU_LPI)) 756 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : "")); 757 if (DO_BIC(BIC_SYS_LPI)) 758 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : "")); 759 760 if (do_rapl && !rapl_joules) { 761 if (DO_BIC(BIC_PkgWatt)) 762 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : "")); 763 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 764 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 765 if (DO_BIC(BIC_GFXWatt)) 766 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : "")); 767 if (DO_BIC(BIC_RAMWatt)) 768 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : "")); 769 if (DO_BIC(BIC_PKG__)) 770 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 771 if (DO_BIC(BIC_RAM__)) 772 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 773 } else if (do_rapl && rapl_joules) { 774 if (DO_BIC(BIC_Pkg_J)) 775 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : "")); 776 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 777 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 778 if (DO_BIC(BIC_GFX_J)) 779 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : "")); 780 if (DO_BIC(BIC_RAM_J)) 781 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : "")); 782 if (DO_BIC(BIC_PKG__)) 783 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 784 if (DO_BIC(BIC_RAM__)) 785 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 786 } 787 for (mp = sys.pp; mp; mp = mp->next) { 788 if (mp->format == FORMAT_RAW) { 789 if (mp->width == 64) 790 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 791 else 792 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 793 } else { 794 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 795 outp += sprintf(outp, "%s%8s", delim, mp->name); 796 else 797 outp += sprintf(outp, "%s%s", delim, mp->name); 798 } 799 } 800 801 outp += sprintf(outp, "\n"); 802 } 803 804 int dump_counters(struct thread_data *t, struct core_data *c, 805 struct pkg_data *p) 806 { 807 int i; 808 struct msr_counter *mp; 809 810 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); 811 812 if (t) { 813 outp += sprintf(outp, "CPU: %d flags 0x%x\n", 814 t->cpu_id, t->flags); 815 outp += sprintf(outp, "TSC: %016llX\n", t->tsc); 816 outp += sprintf(outp, "aperf: %016llX\n", t->aperf); 817 outp += sprintf(outp, "mperf: %016llX\n", t->mperf); 818 outp += sprintf(outp, "c1: %016llX\n", t->c1); 819 820 if (DO_BIC(BIC_IRQ)) 821 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count); 822 if (DO_BIC(BIC_SMI)) 823 outp += sprintf(outp, "SMI: %d\n", t->smi_count); 824 825 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 826 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", 827 i, mp->msr_num, t->counter[i]); 828 } 829 } 830 831 if (c) { 832 outp += sprintf(outp, "core: %d\n", c->core_id); 833 outp += sprintf(outp, "c3: %016llX\n", c->c3); 834 outp += sprintf(outp, "c6: %016llX\n", c->c6); 835 outp += sprintf(outp, "c7: %016llX\n", c->c7); 836 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); 837 outp += sprintf(outp, "Joules: %0X\n", c->core_energy); 838 839 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 840 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", 841 i, mp->msr_num, c->counter[i]); 842 } 843 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us); 844 } 845 846 if (p) { 847 outp += sprintf(outp, "package: %d\n", p->package_id); 848 849 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); 850 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); 851 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); 852 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); 853 854 outp += sprintf(outp, "pc2: %016llX\n", p->pc2); 855 if (DO_BIC(BIC_Pkgpc3)) 856 outp += sprintf(outp, "pc3: %016llX\n", p->pc3); 857 if (DO_BIC(BIC_Pkgpc6)) 858 outp += sprintf(outp, "pc6: %016llX\n", p->pc6); 859 if (DO_BIC(BIC_Pkgpc7)) 860 outp += sprintf(outp, "pc7: %016llX\n", p->pc7); 861 outp += sprintf(outp, "pc8: %016llX\n", p->pc8); 862 outp += sprintf(outp, "pc9: %016llX\n", p->pc9); 863 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 864 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 865 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi); 866 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi); 867 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg); 868 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores); 869 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx); 870 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram); 871 outp += sprintf(outp, "Throttle PKG: %0X\n", 872 p->rapl_pkg_perf_status); 873 outp += sprintf(outp, "Throttle RAM: %0X\n", 874 p->rapl_dram_perf_status); 875 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); 876 877 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 878 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", 879 i, mp->msr_num, p->counter[i]); 880 } 881 } 882 883 outp += sprintf(outp, "\n"); 884 885 return 0; 886 } 887 888 /* 889 * column formatting convention & formats 890 */ 891 int format_counters(struct thread_data *t, struct core_data *c, 892 struct pkg_data *p) 893 { 894 double interval_float, tsc; 895 char *fmt8; 896 int i; 897 struct msr_counter *mp; 898 char *delim = "\t"; 899 int printed = 0; 900 901 /* if showing only 1st thread in core and this isn't one, bail out */ 902 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 903 return 0; 904 905 /* if showing only 1st thread in pkg and this isn't one, bail out */ 906 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 907 return 0; 908 909 /*if not summary line and --cpu is used */ 910 if ((t != &average.threads) && 911 (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset))) 912 return 0; 913 914 if (DO_BIC(BIC_USEC)) { 915 /* on each row, print how many usec each timestamp took to gather */ 916 struct timeval tv; 917 918 timersub(&t->tv_end, &t->tv_begin, &tv); 919 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec); 920 } 921 922 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */ 923 if (DO_BIC(BIC_TOD)) 924 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec); 925 926 interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0; 927 928 tsc = t->tsc * tsc_tweak; 929 930 /* topo columns, print blanks on 1st (average) line */ 931 if (t == &average.threads) { 932 if (DO_BIC(BIC_Package)) 933 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 934 if (DO_BIC(BIC_Die)) 935 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 936 if (DO_BIC(BIC_Node)) 937 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 938 if (DO_BIC(BIC_Core)) 939 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 940 if (DO_BIC(BIC_CPU)) 941 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 942 if (DO_BIC(BIC_APIC)) 943 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 944 if (DO_BIC(BIC_X2APIC)) 945 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 946 } else { 947 if (DO_BIC(BIC_Package)) { 948 if (p) 949 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id); 950 else 951 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 952 } 953 if (DO_BIC(BIC_Die)) { 954 if (c) 955 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), cpus[t->cpu_id].die_id); 956 else 957 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 958 } 959 if (DO_BIC(BIC_Node)) { 960 if (t) 961 outp += sprintf(outp, "%s%d", 962 (printed++ ? delim : ""), 963 cpus[t->cpu_id].physical_node_id); 964 else 965 outp += sprintf(outp, "%s-", 966 (printed++ ? delim : "")); 967 } 968 if (DO_BIC(BIC_Core)) { 969 if (c) 970 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id); 971 else 972 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 973 } 974 if (DO_BIC(BIC_CPU)) 975 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id); 976 if (DO_BIC(BIC_APIC)) 977 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id); 978 if (DO_BIC(BIC_X2APIC)) 979 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id); 980 } 981 982 if (DO_BIC(BIC_Avg_MHz)) 983 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 984 1.0 / units * t->aperf / interval_float); 985 986 if (DO_BIC(BIC_Busy)) 987 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf/tsc); 988 989 if (DO_BIC(BIC_Bzy_MHz)) { 990 if (has_base_hz) 991 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf); 992 else 993 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 994 tsc / units * t->aperf / t->mperf / interval_float); 995 } 996 997 if (DO_BIC(BIC_TSC_MHz)) 998 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc/units/interval_float); 999 1000 /* IRQ */ 1001 if (DO_BIC(BIC_IRQ)) { 1002 if (sums_need_wide_columns) 1003 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count); 1004 else 1005 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count); 1006 } 1007 1008 /* SMI */ 1009 if (DO_BIC(BIC_SMI)) 1010 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count); 1011 1012 /* Added counters */ 1013 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1014 if (mp->format == FORMAT_RAW) { 1015 if (mp->width == 32) 1016 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) t->counter[i]); 1017 else 1018 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]); 1019 } else if (mp->format == FORMAT_DELTA) { 1020 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1021 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]); 1022 else 1023 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]); 1024 } else if (mp->format == FORMAT_PERCENT) { 1025 if (mp->type == COUNTER_USEC) 1026 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), t->counter[i]/interval_float/10000); 1027 else 1028 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i]/tsc); 1029 } 1030 } 1031 1032 /* C1 */ 1033 if (DO_BIC(BIC_CPU_c1)) 1034 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1/tsc); 1035 1036 1037 /* print per-core data only for 1st thread in core */ 1038 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1039 goto done; 1040 1041 if (DO_BIC(BIC_CPU_c3)) 1042 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3/tsc); 1043 if (DO_BIC(BIC_CPU_c6)) 1044 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6/tsc); 1045 if (DO_BIC(BIC_CPU_c7)) 1046 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7/tsc); 1047 1048 /* Mod%c6 */ 1049 if (DO_BIC(BIC_Mod_c6)) 1050 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc); 1051 1052 if (DO_BIC(BIC_CoreTmp)) 1053 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c); 1054 1055 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1056 if (mp->format == FORMAT_RAW) { 1057 if (mp->width == 32) 1058 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) c->counter[i]); 1059 else 1060 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]); 1061 } else if (mp->format == FORMAT_DELTA) { 1062 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1063 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]); 1064 else 1065 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]); 1066 } else if (mp->format == FORMAT_PERCENT) { 1067 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i]/tsc); 1068 } 1069 } 1070 1071 /* 1072 * If measurement interval exceeds minimum RAPL Joule Counter range, 1073 * indicate that results are suspect by printing "**" in fraction place. 1074 */ 1075 if (interval_float < rapl_joule_counter_range) 1076 fmt8 = "%s%.2f"; 1077 else 1078 fmt8 = "%6.0f**"; 1079 1080 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY)) 1081 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units / interval_float); 1082 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY)) 1083 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units); 1084 1085 /* print per-package data only for 1st core in package */ 1086 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1087 goto done; 1088 1089 /* PkgTmp */ 1090 if (DO_BIC(BIC_PkgTmp)) 1091 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c); 1092 1093 /* GFXrc6 */ 1094 if (DO_BIC(BIC_GFX_rc6)) { 1095 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */ 1096 outp += sprintf(outp, "%s**.**", (printed++ ? delim : "")); 1097 } else { 1098 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1099 p->gfx_rc6_ms / 10.0 / interval_float); 1100 } 1101 } 1102 1103 /* GFXMHz */ 1104 if (DO_BIC(BIC_GFXMHz)) 1105 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz); 1106 1107 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ 1108 if (DO_BIC(BIC_Totl_c0)) 1109 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0/tsc); 1110 if (DO_BIC(BIC_Any_c0)) 1111 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0/tsc); 1112 if (DO_BIC(BIC_GFX_c0)) 1113 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0/tsc); 1114 if (DO_BIC(BIC_CPUGFX)) 1115 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0/tsc); 1116 1117 if (DO_BIC(BIC_Pkgpc2)) 1118 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2/tsc); 1119 if (DO_BIC(BIC_Pkgpc3)) 1120 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3/tsc); 1121 if (DO_BIC(BIC_Pkgpc6)) 1122 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6/tsc); 1123 if (DO_BIC(BIC_Pkgpc7)) 1124 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7/tsc); 1125 if (DO_BIC(BIC_Pkgpc8)) 1126 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8/tsc); 1127 if (DO_BIC(BIC_Pkgpc9)) 1128 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9/tsc); 1129 if (DO_BIC(BIC_Pkgpc10)) 1130 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10/tsc); 1131 1132 if (DO_BIC(BIC_CPU_LPI)) 1133 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float); 1134 if (DO_BIC(BIC_SYS_LPI)) 1135 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float); 1136 1137 if (DO_BIC(BIC_PkgWatt)) 1138 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float); 1139 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 1140 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float); 1141 if (DO_BIC(BIC_GFXWatt)) 1142 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float); 1143 if (DO_BIC(BIC_RAMWatt)) 1144 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units / interval_float); 1145 if (DO_BIC(BIC_Pkg_J)) 1146 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units); 1147 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY)) 1148 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units); 1149 if (DO_BIC(BIC_GFX_J)) 1150 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units); 1151 if (DO_BIC(BIC_RAM_J)) 1152 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units); 1153 if (DO_BIC(BIC_PKG__)) 1154 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 1155 if (DO_BIC(BIC_RAM__)) 1156 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 1157 1158 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1159 if (mp->format == FORMAT_RAW) { 1160 if (mp->width == 32) 1161 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) p->counter[i]); 1162 else 1163 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]); 1164 } else if (mp->format == FORMAT_DELTA) { 1165 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1166 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]); 1167 else 1168 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]); 1169 } else if (mp->format == FORMAT_PERCENT) { 1170 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i]/tsc); 1171 } 1172 } 1173 1174 done: 1175 if (*(outp - 1) != '\n') 1176 outp += sprintf(outp, "\n"); 1177 1178 return 0; 1179 } 1180 1181 void flush_output_stdout(void) 1182 { 1183 FILE *filep; 1184 1185 if (outf == stderr) 1186 filep = stdout; 1187 else 1188 filep = outf; 1189 1190 fputs(output_buffer, filep); 1191 fflush(filep); 1192 1193 outp = output_buffer; 1194 } 1195 void flush_output_stderr(void) 1196 { 1197 fputs(output_buffer, outf); 1198 fflush(outf); 1199 outp = output_buffer; 1200 } 1201 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1202 { 1203 static int printed; 1204 1205 if (!printed || !summary_only) 1206 print_header("\t"); 1207 1208 format_counters(&average.threads, &average.cores, &average.packages); 1209 1210 printed = 1; 1211 1212 if (summary_only) 1213 return; 1214 1215 for_all_cpus(format_counters, t, c, p); 1216 } 1217 1218 #define DELTA_WRAP32(new, old) \ 1219 if (new > old) { \ 1220 old = new - old; \ 1221 } else { \ 1222 old = 0x100000000 + new - old; \ 1223 } 1224 1225 int 1226 delta_package(struct pkg_data *new, struct pkg_data *old) 1227 { 1228 int i; 1229 struct msr_counter *mp; 1230 1231 1232 if (DO_BIC(BIC_Totl_c0)) 1233 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; 1234 if (DO_BIC(BIC_Any_c0)) 1235 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; 1236 if (DO_BIC(BIC_GFX_c0)) 1237 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; 1238 if (DO_BIC(BIC_CPUGFX)) 1239 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; 1240 1241 old->pc2 = new->pc2 - old->pc2; 1242 if (DO_BIC(BIC_Pkgpc3)) 1243 old->pc3 = new->pc3 - old->pc3; 1244 if (DO_BIC(BIC_Pkgpc6)) 1245 old->pc6 = new->pc6 - old->pc6; 1246 if (DO_BIC(BIC_Pkgpc7)) 1247 old->pc7 = new->pc7 - old->pc7; 1248 old->pc8 = new->pc8 - old->pc8; 1249 old->pc9 = new->pc9 - old->pc9; 1250 old->pc10 = new->pc10 - old->pc10; 1251 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi; 1252 old->sys_lpi = new->sys_lpi - old->sys_lpi; 1253 old->pkg_temp_c = new->pkg_temp_c; 1254 1255 /* flag an error when rc6 counter resets/wraps */ 1256 if (old->gfx_rc6_ms > new->gfx_rc6_ms) 1257 old->gfx_rc6_ms = -1; 1258 else 1259 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; 1260 1261 old->gfx_mhz = new->gfx_mhz; 1262 1263 DELTA_WRAP32(new->energy_pkg, old->energy_pkg); 1264 DELTA_WRAP32(new->energy_cores, old->energy_cores); 1265 DELTA_WRAP32(new->energy_gfx, old->energy_gfx); 1266 DELTA_WRAP32(new->energy_dram, old->energy_dram); 1267 DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status); 1268 DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status); 1269 1270 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1271 if (mp->format == FORMAT_RAW) 1272 old->counter[i] = new->counter[i]; 1273 else 1274 old->counter[i] = new->counter[i] - old->counter[i]; 1275 } 1276 1277 return 0; 1278 } 1279 1280 void 1281 delta_core(struct core_data *new, struct core_data *old) 1282 { 1283 int i; 1284 struct msr_counter *mp; 1285 1286 old->c3 = new->c3 - old->c3; 1287 old->c6 = new->c6 - old->c6; 1288 old->c7 = new->c7 - old->c7; 1289 old->core_temp_c = new->core_temp_c; 1290 old->mc6_us = new->mc6_us - old->mc6_us; 1291 1292 DELTA_WRAP32(new->core_energy, old->core_energy); 1293 1294 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1295 if (mp->format == FORMAT_RAW) 1296 old->counter[i] = new->counter[i]; 1297 else 1298 old->counter[i] = new->counter[i] - old->counter[i]; 1299 } 1300 } 1301 1302 /* 1303 * old = new - old 1304 */ 1305 int 1306 delta_thread(struct thread_data *new, struct thread_data *old, 1307 struct core_data *core_delta) 1308 { 1309 int i; 1310 struct msr_counter *mp; 1311 1312 /* we run cpuid just the 1st time, copy the results */ 1313 if (DO_BIC(BIC_APIC)) 1314 new->apic_id = old->apic_id; 1315 if (DO_BIC(BIC_X2APIC)) 1316 new->x2apic_id = old->x2apic_id; 1317 1318 /* 1319 * the timestamps from start of measurement interval are in "old" 1320 * the timestamp from end of measurement interval are in "new" 1321 * over-write old w/ new so we can print end of interval values 1322 */ 1323 1324 old->tv_begin = new->tv_begin; 1325 old->tv_end = new->tv_end; 1326 1327 old->tsc = new->tsc - old->tsc; 1328 1329 /* check for TSC < 1 Mcycles over interval */ 1330 if (old->tsc < (1000 * 1000)) 1331 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" 1332 "You can disable all c-states by booting with \"idle=poll\"\n" 1333 "or just the deep ones with \"processor.max_cstate=1\""); 1334 1335 old->c1 = new->c1 - old->c1; 1336 1337 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) { 1338 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { 1339 old->aperf = new->aperf - old->aperf; 1340 old->mperf = new->mperf - old->mperf; 1341 } else { 1342 return -1; 1343 } 1344 } 1345 1346 1347 if (use_c1_residency_msr) { 1348 /* 1349 * Some models have a dedicated C1 residency MSR, 1350 * which should be more accurate than the derivation below. 1351 */ 1352 } else { 1353 /* 1354 * As counter collection is not atomic, 1355 * it is possible for mperf's non-halted cycles + idle states 1356 * to exceed TSC's all cycles: show c1 = 0% in that case. 1357 */ 1358 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak)) 1359 old->c1 = 0; 1360 else { 1361 /* normal case, derive c1 */ 1362 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3 1363 - core_delta->c6 - core_delta->c7; 1364 } 1365 } 1366 1367 if (old->mperf == 0) { 1368 if (debug > 1) 1369 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); 1370 old->mperf = 1; /* divide by 0 protection */ 1371 } 1372 1373 if (DO_BIC(BIC_IRQ)) 1374 old->irq_count = new->irq_count - old->irq_count; 1375 1376 if (DO_BIC(BIC_SMI)) 1377 old->smi_count = new->smi_count - old->smi_count; 1378 1379 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1380 if (mp->format == FORMAT_RAW) 1381 old->counter[i] = new->counter[i]; 1382 else 1383 old->counter[i] = new->counter[i] - old->counter[i]; 1384 } 1385 return 0; 1386 } 1387 1388 int delta_cpu(struct thread_data *t, struct core_data *c, 1389 struct pkg_data *p, struct thread_data *t2, 1390 struct core_data *c2, struct pkg_data *p2) 1391 { 1392 int retval = 0; 1393 1394 /* calculate core delta only for 1st thread in core */ 1395 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) 1396 delta_core(c, c2); 1397 1398 /* always calculate thread delta */ 1399 retval = delta_thread(t, t2, c2); /* c2 is core delta */ 1400 if (retval) 1401 return retval; 1402 1403 /* calculate package delta only for 1st core in package */ 1404 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) 1405 retval = delta_package(p, p2); 1406 1407 return retval; 1408 } 1409 1410 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1411 { 1412 int i; 1413 struct msr_counter *mp; 1414 1415 t->tv_begin.tv_sec = 0; 1416 t->tv_begin.tv_usec = 0; 1417 t->tv_end.tv_sec = 0; 1418 t->tv_end.tv_usec = 0; 1419 1420 t->tsc = 0; 1421 t->aperf = 0; 1422 t->mperf = 0; 1423 t->c1 = 0; 1424 1425 t->irq_count = 0; 1426 t->smi_count = 0; 1427 1428 /* tells format_counters to dump all fields from this set */ 1429 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; 1430 1431 c->c3 = 0; 1432 c->c6 = 0; 1433 c->c7 = 0; 1434 c->mc6_us = 0; 1435 c->core_temp_c = 0; 1436 c->core_energy = 0; 1437 1438 p->pkg_wtd_core_c0 = 0; 1439 p->pkg_any_core_c0 = 0; 1440 p->pkg_any_gfxe_c0 = 0; 1441 p->pkg_both_core_gfxe_c0 = 0; 1442 1443 p->pc2 = 0; 1444 if (DO_BIC(BIC_Pkgpc3)) 1445 p->pc3 = 0; 1446 if (DO_BIC(BIC_Pkgpc6)) 1447 p->pc6 = 0; 1448 if (DO_BIC(BIC_Pkgpc7)) 1449 p->pc7 = 0; 1450 p->pc8 = 0; 1451 p->pc9 = 0; 1452 p->pc10 = 0; 1453 p->cpu_lpi = 0; 1454 p->sys_lpi = 0; 1455 1456 p->energy_pkg = 0; 1457 p->energy_dram = 0; 1458 p->energy_cores = 0; 1459 p->energy_gfx = 0; 1460 p->rapl_pkg_perf_status = 0; 1461 p->rapl_dram_perf_status = 0; 1462 p->pkg_temp_c = 0; 1463 1464 p->gfx_rc6_ms = 0; 1465 p->gfx_mhz = 0; 1466 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) 1467 t->counter[i] = 0; 1468 1469 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) 1470 c->counter[i] = 0; 1471 1472 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) 1473 p->counter[i] = 0; 1474 } 1475 int sum_counters(struct thread_data *t, struct core_data *c, 1476 struct pkg_data *p) 1477 { 1478 int i; 1479 struct msr_counter *mp; 1480 1481 /* copy un-changing apic_id's */ 1482 if (DO_BIC(BIC_APIC)) 1483 average.threads.apic_id = t->apic_id; 1484 if (DO_BIC(BIC_X2APIC)) 1485 average.threads.x2apic_id = t->x2apic_id; 1486 1487 /* remember first tv_begin */ 1488 if (average.threads.tv_begin.tv_sec == 0) 1489 average.threads.tv_begin = t->tv_begin; 1490 1491 /* remember last tv_end */ 1492 average.threads.tv_end = t->tv_end; 1493 1494 average.threads.tsc += t->tsc; 1495 average.threads.aperf += t->aperf; 1496 average.threads.mperf += t->mperf; 1497 average.threads.c1 += t->c1; 1498 1499 average.threads.irq_count += t->irq_count; 1500 average.threads.smi_count += t->smi_count; 1501 1502 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1503 if (mp->format == FORMAT_RAW) 1504 continue; 1505 average.threads.counter[i] += t->counter[i]; 1506 } 1507 1508 /* sum per-core values only for 1st thread in core */ 1509 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1510 return 0; 1511 1512 average.cores.c3 += c->c3; 1513 average.cores.c6 += c->c6; 1514 average.cores.c7 += c->c7; 1515 average.cores.mc6_us += c->mc6_us; 1516 1517 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); 1518 1519 average.cores.core_energy += c->core_energy; 1520 1521 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1522 if (mp->format == FORMAT_RAW) 1523 continue; 1524 average.cores.counter[i] += c->counter[i]; 1525 } 1526 1527 /* sum per-pkg values only for 1st core in pkg */ 1528 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1529 return 0; 1530 1531 if (DO_BIC(BIC_Totl_c0)) 1532 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; 1533 if (DO_BIC(BIC_Any_c0)) 1534 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; 1535 if (DO_BIC(BIC_GFX_c0)) 1536 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; 1537 if (DO_BIC(BIC_CPUGFX)) 1538 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; 1539 1540 average.packages.pc2 += p->pc2; 1541 if (DO_BIC(BIC_Pkgpc3)) 1542 average.packages.pc3 += p->pc3; 1543 if (DO_BIC(BIC_Pkgpc6)) 1544 average.packages.pc6 += p->pc6; 1545 if (DO_BIC(BIC_Pkgpc7)) 1546 average.packages.pc7 += p->pc7; 1547 average.packages.pc8 += p->pc8; 1548 average.packages.pc9 += p->pc9; 1549 average.packages.pc10 += p->pc10; 1550 1551 average.packages.cpu_lpi = p->cpu_lpi; 1552 average.packages.sys_lpi = p->sys_lpi; 1553 1554 average.packages.energy_pkg += p->energy_pkg; 1555 average.packages.energy_dram += p->energy_dram; 1556 average.packages.energy_cores += p->energy_cores; 1557 average.packages.energy_gfx += p->energy_gfx; 1558 1559 average.packages.gfx_rc6_ms = p->gfx_rc6_ms; 1560 average.packages.gfx_mhz = p->gfx_mhz; 1561 1562 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); 1563 1564 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; 1565 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; 1566 1567 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1568 if (mp->format == FORMAT_RAW) 1569 continue; 1570 average.packages.counter[i] += p->counter[i]; 1571 } 1572 return 0; 1573 } 1574 /* 1575 * sum the counters for all cpus in the system 1576 * compute the weighted average 1577 */ 1578 void compute_average(struct thread_data *t, struct core_data *c, 1579 struct pkg_data *p) 1580 { 1581 int i; 1582 struct msr_counter *mp; 1583 1584 clear_counters(&average.threads, &average.cores, &average.packages); 1585 1586 for_all_cpus(sum_counters, t, c, p); 1587 1588 average.threads.tsc /= topo.num_cpus; 1589 average.threads.aperf /= topo.num_cpus; 1590 average.threads.mperf /= topo.num_cpus; 1591 average.threads.c1 /= topo.num_cpus; 1592 1593 if (average.threads.irq_count > 9999999) 1594 sums_need_wide_columns = 1; 1595 1596 average.cores.c3 /= topo.num_cores; 1597 average.cores.c6 /= topo.num_cores; 1598 average.cores.c7 /= topo.num_cores; 1599 average.cores.mc6_us /= topo.num_cores; 1600 1601 if (DO_BIC(BIC_Totl_c0)) 1602 average.packages.pkg_wtd_core_c0 /= topo.num_packages; 1603 if (DO_BIC(BIC_Any_c0)) 1604 average.packages.pkg_any_core_c0 /= topo.num_packages; 1605 if (DO_BIC(BIC_GFX_c0)) 1606 average.packages.pkg_any_gfxe_c0 /= topo.num_packages; 1607 if (DO_BIC(BIC_CPUGFX)) 1608 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages; 1609 1610 average.packages.pc2 /= topo.num_packages; 1611 if (DO_BIC(BIC_Pkgpc3)) 1612 average.packages.pc3 /= topo.num_packages; 1613 if (DO_BIC(BIC_Pkgpc6)) 1614 average.packages.pc6 /= topo.num_packages; 1615 if (DO_BIC(BIC_Pkgpc7)) 1616 average.packages.pc7 /= topo.num_packages; 1617 1618 average.packages.pc8 /= topo.num_packages; 1619 average.packages.pc9 /= topo.num_packages; 1620 average.packages.pc10 /= topo.num_packages; 1621 1622 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1623 if (mp->format == FORMAT_RAW) 1624 continue; 1625 if (mp->type == COUNTER_ITEMS) { 1626 if (average.threads.counter[i] > 9999999) 1627 sums_need_wide_columns = 1; 1628 continue; 1629 } 1630 average.threads.counter[i] /= topo.num_cpus; 1631 } 1632 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1633 if (mp->format == FORMAT_RAW) 1634 continue; 1635 if (mp->type == COUNTER_ITEMS) { 1636 if (average.cores.counter[i] > 9999999) 1637 sums_need_wide_columns = 1; 1638 } 1639 average.cores.counter[i] /= topo.num_cores; 1640 } 1641 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1642 if (mp->format == FORMAT_RAW) 1643 continue; 1644 if (mp->type == COUNTER_ITEMS) { 1645 if (average.packages.counter[i] > 9999999) 1646 sums_need_wide_columns = 1; 1647 } 1648 average.packages.counter[i] /= topo.num_packages; 1649 } 1650 } 1651 1652 static unsigned long long rdtsc(void) 1653 { 1654 unsigned int low, high; 1655 1656 asm volatile("rdtsc" : "=a" (low), "=d" (high)); 1657 1658 return low | ((unsigned long long)high) << 32; 1659 } 1660 1661 /* 1662 * Open a file, and exit on failure 1663 */ 1664 FILE *fopen_or_die(const char *path, const char *mode) 1665 { 1666 FILE *filep = fopen(path, mode); 1667 1668 if (!filep) 1669 err(1, "%s: open failed", path); 1670 return filep; 1671 } 1672 /* 1673 * snapshot_sysfs_counter() 1674 * 1675 * return snapshot of given counter 1676 */ 1677 unsigned long long snapshot_sysfs_counter(char *path) 1678 { 1679 FILE *fp; 1680 int retval; 1681 unsigned long long counter; 1682 1683 fp = fopen_or_die(path, "r"); 1684 1685 retval = fscanf(fp, "%lld", &counter); 1686 if (retval != 1) 1687 err(1, "snapshot_sysfs_counter(%s)", path); 1688 1689 fclose(fp); 1690 1691 return counter; 1692 } 1693 1694 int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp) 1695 { 1696 if (mp->msr_num != 0) { 1697 if (get_msr(cpu, mp->msr_num, counterp)) 1698 return -1; 1699 } else { 1700 char path[128 + PATH_BYTES]; 1701 1702 if (mp->flags & SYSFS_PERCPU) { 1703 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s", 1704 cpu, mp->path); 1705 1706 *counterp = snapshot_sysfs_counter(path); 1707 } else { 1708 *counterp = snapshot_sysfs_counter(mp->path); 1709 } 1710 } 1711 1712 return 0; 1713 } 1714 1715 void get_apic_id(struct thread_data *t) 1716 { 1717 unsigned int eax, ebx, ecx, edx; 1718 1719 if (DO_BIC(BIC_APIC)) { 1720 eax = ebx = ecx = edx = 0; 1721 __cpuid(1, eax, ebx, ecx, edx); 1722 1723 t->apic_id = (ebx >> 24) & 0xff; 1724 } 1725 1726 if (!DO_BIC(BIC_X2APIC)) 1727 return; 1728 1729 if (authentic_amd) { 1730 unsigned int topology_extensions; 1731 1732 if (max_extended_level < 0x8000001e) 1733 return; 1734 1735 eax = ebx = ecx = edx = 0; 1736 __cpuid(0x80000001, eax, ebx, ecx, edx); 1737 topology_extensions = ecx & (1 << 22); 1738 1739 if (topology_extensions == 0) 1740 return; 1741 1742 eax = ebx = ecx = edx = 0; 1743 __cpuid(0x8000001e, eax, ebx, ecx, edx); 1744 1745 t->x2apic_id = eax; 1746 return; 1747 } 1748 1749 if (!genuine_intel) 1750 return; 1751 1752 if (max_level < 0xb) 1753 return; 1754 1755 ecx = 0; 1756 __cpuid(0xb, eax, ebx, ecx, edx); 1757 t->x2apic_id = edx; 1758 1759 if (debug && (t->apic_id != (t->x2apic_id & 0xff))) 1760 fprintf(outf, "cpu%d: BIOS BUG: apic 0x%x x2apic 0x%x\n", 1761 t->cpu_id, t->apic_id, t->x2apic_id); 1762 } 1763 1764 /* 1765 * get_counters(...) 1766 * migrate to cpu 1767 * acquire and record local counters for that cpu 1768 */ 1769 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1770 { 1771 int cpu = t->cpu_id; 1772 unsigned long long msr; 1773 int aperf_mperf_retry_count = 0; 1774 struct msr_counter *mp; 1775 int i; 1776 1777 gettimeofday(&t->tv_begin, (struct timezone *)NULL); 1778 1779 if (cpu_migrate(cpu)) { 1780 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 1781 return -1; 1782 } 1783 1784 if (first_counter_read) 1785 get_apic_id(t); 1786 retry: 1787 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 1788 1789 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) { 1790 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; 1791 1792 /* 1793 * The TSC, APERF and MPERF must be read together for 1794 * APERF/MPERF and MPERF/TSC to give accurate results. 1795 * 1796 * Unfortunately, APERF and MPERF are read by 1797 * individual system call, so delays may occur 1798 * between them. If the time to read them 1799 * varies by a large amount, we re-read them. 1800 */ 1801 1802 /* 1803 * This initial dummy APERF read has been seen to 1804 * reduce jitter in the subsequent reads. 1805 */ 1806 1807 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1808 return -3; 1809 1810 t->tsc = rdtsc(); /* re-read close to APERF */ 1811 1812 tsc_before = t->tsc; 1813 1814 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1815 return -3; 1816 1817 tsc_between = rdtsc(); 1818 1819 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) 1820 return -4; 1821 1822 tsc_after = rdtsc(); 1823 1824 aperf_time = tsc_between - tsc_before; 1825 mperf_time = tsc_after - tsc_between; 1826 1827 /* 1828 * If the system call latency to read APERF and MPERF 1829 * differ by more than 2x, then try again. 1830 */ 1831 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { 1832 aperf_mperf_retry_count++; 1833 if (aperf_mperf_retry_count < 5) 1834 goto retry; 1835 else 1836 warnx("cpu%d jitter %lld %lld", 1837 cpu, aperf_time, mperf_time); 1838 } 1839 aperf_mperf_retry_count = 0; 1840 1841 t->aperf = t->aperf * aperf_mperf_multiplier; 1842 t->mperf = t->mperf * aperf_mperf_multiplier; 1843 } 1844 1845 if (DO_BIC(BIC_IRQ)) 1846 t->irq_count = irqs_per_cpu[cpu]; 1847 if (DO_BIC(BIC_SMI)) { 1848 if (get_msr(cpu, MSR_SMI_COUNT, &msr)) 1849 return -5; 1850 t->smi_count = msr & 0xFFFFFFFF; 1851 } 1852 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) { 1853 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) 1854 return -6; 1855 } 1856 1857 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1858 if (get_mp(cpu, mp, &t->counter[i])) 1859 return -10; 1860 } 1861 1862 /* collect core counters only for 1st thread in core */ 1863 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1864 goto done; 1865 1866 if (DO_BIC(BIC_CPU_c3)) { 1867 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) 1868 return -6; 1869 } 1870 1871 if (DO_BIC(BIC_CPU_c6) && !do_knl_cstates) { 1872 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) 1873 return -7; 1874 } else if (do_knl_cstates) { 1875 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) 1876 return -7; 1877 } 1878 1879 if (DO_BIC(BIC_CPU_c7)) 1880 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 1881 return -8; 1882 1883 if (DO_BIC(BIC_Mod_c6)) 1884 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us)) 1885 return -8; 1886 1887 if (DO_BIC(BIC_CoreTmp)) { 1888 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 1889 return -9; 1890 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1891 } 1892 1893 if (do_rapl & RAPL_AMD_F17H) { 1894 if (get_msr(cpu, MSR_CORE_ENERGY_STAT, &msr)) 1895 return -14; 1896 c->core_energy = msr & 0xFFFFFFFF; 1897 } 1898 1899 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1900 if (get_mp(cpu, mp, &c->counter[i])) 1901 return -10; 1902 } 1903 1904 /* collect package counters only for 1st core in package */ 1905 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1906 goto done; 1907 1908 if (DO_BIC(BIC_Totl_c0)) { 1909 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) 1910 return -10; 1911 } 1912 if (DO_BIC(BIC_Any_c0)) { 1913 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) 1914 return -11; 1915 } 1916 if (DO_BIC(BIC_GFX_c0)) { 1917 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) 1918 return -12; 1919 } 1920 if (DO_BIC(BIC_CPUGFX)) { 1921 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) 1922 return -13; 1923 } 1924 if (DO_BIC(BIC_Pkgpc3)) 1925 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) 1926 return -9; 1927 if (DO_BIC(BIC_Pkgpc6)) { 1928 if (do_slm_cstates) { 1929 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6)) 1930 return -10; 1931 } else { 1932 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) 1933 return -10; 1934 } 1935 } 1936 1937 if (DO_BIC(BIC_Pkgpc2)) 1938 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) 1939 return -11; 1940 if (DO_BIC(BIC_Pkgpc7)) 1941 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) 1942 return -12; 1943 if (DO_BIC(BIC_Pkgpc8)) 1944 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) 1945 return -13; 1946 if (DO_BIC(BIC_Pkgpc9)) 1947 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) 1948 return -13; 1949 if (DO_BIC(BIC_Pkgpc10)) 1950 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) 1951 return -13; 1952 1953 if (DO_BIC(BIC_CPU_LPI)) 1954 p->cpu_lpi = cpuidle_cur_cpu_lpi_us; 1955 if (DO_BIC(BIC_SYS_LPI)) 1956 p->sys_lpi = cpuidle_cur_sys_lpi_us; 1957 1958 if (do_rapl & RAPL_PKG) { 1959 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr)) 1960 return -13; 1961 p->energy_pkg = msr & 0xFFFFFFFF; 1962 } 1963 if (do_rapl & RAPL_CORES_ENERGY_STATUS) { 1964 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr)) 1965 return -14; 1966 p->energy_cores = msr & 0xFFFFFFFF; 1967 } 1968 if (do_rapl & RAPL_DRAM) { 1969 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) 1970 return -15; 1971 p->energy_dram = msr & 0xFFFFFFFF; 1972 } 1973 if (do_rapl & RAPL_GFX) { 1974 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr)) 1975 return -16; 1976 p->energy_gfx = msr & 0xFFFFFFFF; 1977 } 1978 if (do_rapl & RAPL_PKG_PERF_STATUS) { 1979 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr)) 1980 return -16; 1981 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF; 1982 } 1983 if (do_rapl & RAPL_DRAM_PERF_STATUS) { 1984 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr)) 1985 return -16; 1986 p->rapl_dram_perf_status = msr & 0xFFFFFFFF; 1987 } 1988 if (do_rapl & RAPL_AMD_F17H) { 1989 if (get_msr(cpu, MSR_PKG_ENERGY_STAT, &msr)) 1990 return -13; 1991 p->energy_pkg = msr & 0xFFFFFFFF; 1992 } 1993 if (DO_BIC(BIC_PkgTmp)) { 1994 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 1995 return -17; 1996 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1997 } 1998 1999 if (DO_BIC(BIC_GFX_rc6)) 2000 p->gfx_rc6_ms = gfx_cur_rc6_ms; 2001 2002 if (DO_BIC(BIC_GFXMHz)) 2003 p->gfx_mhz = gfx_cur_mhz; 2004 2005 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 2006 if (get_mp(cpu, mp, &p->counter[i])) 2007 return -10; 2008 } 2009 done: 2010 gettimeofday(&t->tv_end, (struct timezone *)NULL); 2011 2012 return 0; 2013 } 2014 2015 /* 2016 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: 2017 * If you change the values, note they are used both in comparisons 2018 * (>= PCL__7) and to index pkg_cstate_limit_strings[]. 2019 */ 2020 2021 #define PCLUKN 0 /* Unknown */ 2022 #define PCLRSV 1 /* Reserved */ 2023 #define PCL__0 2 /* PC0 */ 2024 #define PCL__1 3 /* PC1 */ 2025 #define PCL__2 4 /* PC2 */ 2026 #define PCL__3 5 /* PC3 */ 2027 #define PCL__4 6 /* PC4 */ 2028 #define PCL__6 7 /* PC6 */ 2029 #define PCL_6N 8 /* PC6 No Retention */ 2030 #define PCL_6R 9 /* PC6 Retention */ 2031 #define PCL__7 10 /* PC7 */ 2032 #define PCL_7S 11 /* PC7 Shrink */ 2033 #define PCL__8 12 /* PC8 */ 2034 #define PCL__9 13 /* PC9 */ 2035 #define PCL_10 14 /* PC10 */ 2036 #define PCLUNL 15 /* Unlimited */ 2037 2038 int pkg_cstate_limit = PCLUKN; 2039 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", 2040 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "pc10", "unlimited"}; 2041 2042 int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2043 int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2044 int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2045 int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7}; 2046 int amt_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2047 int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2048 int glm_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCL_10, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2049 int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 2050 2051 2052 static void 2053 calculate_tsc_tweak() 2054 { 2055 tsc_tweak = base_hz / tsc_hz; 2056 } 2057 2058 static void 2059 dump_nhm_platform_info(void) 2060 { 2061 unsigned long long msr; 2062 unsigned int ratio; 2063 2064 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 2065 2066 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 2067 2068 ratio = (msr >> 40) & 0xFF; 2069 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", 2070 ratio, bclk, ratio * bclk); 2071 2072 ratio = (msr >> 8) & 0xFF; 2073 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", 2074 ratio, bclk, ratio * bclk); 2075 2076 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); 2077 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", 2078 base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); 2079 2080 return; 2081 } 2082 2083 static void 2084 dump_hsw_turbo_ratio_limits(void) 2085 { 2086 unsigned long long msr; 2087 unsigned int ratio; 2088 2089 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); 2090 2091 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); 2092 2093 ratio = (msr >> 8) & 0xFF; 2094 if (ratio) 2095 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", 2096 ratio, bclk, ratio * bclk); 2097 2098 ratio = (msr >> 0) & 0xFF; 2099 if (ratio) 2100 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", 2101 ratio, bclk, ratio * bclk); 2102 return; 2103 } 2104 2105 static void 2106 dump_ivt_turbo_ratio_limits(void) 2107 { 2108 unsigned long long msr; 2109 unsigned int ratio; 2110 2111 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); 2112 2113 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); 2114 2115 ratio = (msr >> 56) & 0xFF; 2116 if (ratio) 2117 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", 2118 ratio, bclk, ratio * bclk); 2119 2120 ratio = (msr >> 48) & 0xFF; 2121 if (ratio) 2122 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", 2123 ratio, bclk, ratio * bclk); 2124 2125 ratio = (msr >> 40) & 0xFF; 2126 if (ratio) 2127 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", 2128 ratio, bclk, ratio * bclk); 2129 2130 ratio = (msr >> 32) & 0xFF; 2131 if (ratio) 2132 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", 2133 ratio, bclk, ratio * bclk); 2134 2135 ratio = (msr >> 24) & 0xFF; 2136 if (ratio) 2137 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", 2138 ratio, bclk, ratio * bclk); 2139 2140 ratio = (msr >> 16) & 0xFF; 2141 if (ratio) 2142 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", 2143 ratio, bclk, ratio * bclk); 2144 2145 ratio = (msr >> 8) & 0xFF; 2146 if (ratio) 2147 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", 2148 ratio, bclk, ratio * bclk); 2149 2150 ratio = (msr >> 0) & 0xFF; 2151 if (ratio) 2152 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", 2153 ratio, bclk, ratio * bclk); 2154 return; 2155 } 2156 int has_turbo_ratio_group_limits(int family, int model) 2157 { 2158 2159 if (!genuine_intel) 2160 return 0; 2161 2162 switch (model) { 2163 case INTEL_FAM6_ATOM_GOLDMONT: 2164 case INTEL_FAM6_SKYLAKE_X: 2165 case INTEL_FAM6_ATOM_GOLDMONT_X: 2166 return 1; 2167 } 2168 return 0; 2169 } 2170 2171 static void 2172 dump_turbo_ratio_limits(int family, int model) 2173 { 2174 unsigned long long msr, core_counts; 2175 unsigned int ratio, group_size; 2176 2177 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2178 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 2179 2180 if (has_turbo_ratio_group_limits(family, model)) { 2181 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts); 2182 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts); 2183 } else { 2184 core_counts = 0x0807060504030201; 2185 } 2186 2187 ratio = (msr >> 56) & 0xFF; 2188 group_size = (core_counts >> 56) & 0xFF; 2189 if (ratio) 2190 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2191 ratio, bclk, ratio * bclk, group_size); 2192 2193 ratio = (msr >> 48) & 0xFF; 2194 group_size = (core_counts >> 48) & 0xFF; 2195 if (ratio) 2196 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2197 ratio, bclk, ratio * bclk, group_size); 2198 2199 ratio = (msr >> 40) & 0xFF; 2200 group_size = (core_counts >> 40) & 0xFF; 2201 if (ratio) 2202 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2203 ratio, bclk, ratio * bclk, group_size); 2204 2205 ratio = (msr >> 32) & 0xFF; 2206 group_size = (core_counts >> 32) & 0xFF; 2207 if (ratio) 2208 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2209 ratio, bclk, ratio * bclk, group_size); 2210 2211 ratio = (msr >> 24) & 0xFF; 2212 group_size = (core_counts >> 24) & 0xFF; 2213 if (ratio) 2214 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2215 ratio, bclk, ratio * bclk, group_size); 2216 2217 ratio = (msr >> 16) & 0xFF; 2218 group_size = (core_counts >> 16) & 0xFF; 2219 if (ratio) 2220 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2221 ratio, bclk, ratio * bclk, group_size); 2222 2223 ratio = (msr >> 8) & 0xFF; 2224 group_size = (core_counts >> 8) & 0xFF; 2225 if (ratio) 2226 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2227 ratio, bclk, ratio * bclk, group_size); 2228 2229 ratio = (msr >> 0) & 0xFF; 2230 group_size = (core_counts >> 0) & 0xFF; 2231 if (ratio) 2232 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2233 ratio, bclk, ratio * bclk, group_size); 2234 return; 2235 } 2236 2237 static void 2238 dump_atom_turbo_ratio_limits(void) 2239 { 2240 unsigned long long msr; 2241 unsigned int ratio; 2242 2243 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr); 2244 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2245 2246 ratio = (msr >> 0) & 0x3F; 2247 if (ratio) 2248 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", 2249 ratio, bclk, ratio * bclk); 2250 2251 ratio = (msr >> 8) & 0x3F; 2252 if (ratio) 2253 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", 2254 ratio, bclk, ratio * bclk); 2255 2256 ratio = (msr >> 16) & 0x3F; 2257 if (ratio) 2258 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", 2259 ratio, bclk, ratio * bclk); 2260 2261 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr); 2262 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2263 2264 ratio = (msr >> 24) & 0x3F; 2265 if (ratio) 2266 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", 2267 ratio, bclk, ratio * bclk); 2268 2269 ratio = (msr >> 16) & 0x3F; 2270 if (ratio) 2271 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", 2272 ratio, bclk, ratio * bclk); 2273 2274 ratio = (msr >> 8) & 0x3F; 2275 if (ratio) 2276 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", 2277 ratio, bclk, ratio * bclk); 2278 2279 ratio = (msr >> 0) & 0x3F; 2280 if (ratio) 2281 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", 2282 ratio, bclk, ratio * bclk); 2283 } 2284 2285 static void 2286 dump_knl_turbo_ratio_limits(void) 2287 { 2288 const unsigned int buckets_no = 7; 2289 2290 unsigned long long msr; 2291 int delta_cores, delta_ratio; 2292 int i, b_nr; 2293 unsigned int cores[buckets_no]; 2294 unsigned int ratio[buckets_no]; 2295 2296 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2297 2298 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", 2299 base_cpu, msr); 2300 2301 /** 2302 * Turbo encoding in KNL is as follows: 2303 * [0] -- Reserved 2304 * [7:1] -- Base value of number of active cores of bucket 1. 2305 * [15:8] -- Base value of freq ratio of bucket 1. 2306 * [20:16] -- +ve delta of number of active cores of bucket 2. 2307 * i.e. active cores of bucket 2 = 2308 * active cores of bucket 1 + delta 2309 * [23:21] -- Negative delta of freq ratio of bucket 2. 2310 * i.e. freq ratio of bucket 2 = 2311 * freq ratio of bucket 1 - delta 2312 * [28:24]-- +ve delta of number of active cores of bucket 3. 2313 * [31:29]-- -ve delta of freq ratio of bucket 3. 2314 * [36:32]-- +ve delta of number of active cores of bucket 4. 2315 * [39:37]-- -ve delta of freq ratio of bucket 4. 2316 * [44:40]-- +ve delta of number of active cores of bucket 5. 2317 * [47:45]-- -ve delta of freq ratio of bucket 5. 2318 * [52:48]-- +ve delta of number of active cores of bucket 6. 2319 * [55:53]-- -ve delta of freq ratio of bucket 6. 2320 * [60:56]-- +ve delta of number of active cores of bucket 7. 2321 * [63:61]-- -ve delta of freq ratio of bucket 7. 2322 */ 2323 2324 b_nr = 0; 2325 cores[b_nr] = (msr & 0xFF) >> 1; 2326 ratio[b_nr] = (msr >> 8) & 0xFF; 2327 2328 for (i = 16; i < 64; i += 8) { 2329 delta_cores = (msr >> i) & 0x1F; 2330 delta_ratio = (msr >> (i + 5)) & 0x7; 2331 2332 cores[b_nr + 1] = cores[b_nr] + delta_cores; 2333 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; 2334 b_nr++; 2335 } 2336 2337 for (i = buckets_no - 1; i >= 0; i--) 2338 if (i > 0 ? ratio[i] != ratio[i - 1] : 1) 2339 fprintf(outf, 2340 "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2341 ratio[i], bclk, ratio[i] * bclk, cores[i]); 2342 } 2343 2344 static void 2345 dump_nhm_cst_cfg(void) 2346 { 2347 unsigned long long msr; 2348 2349 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 2350 2351 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr); 2352 2353 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)", 2354 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", 2355 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", 2356 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", 2357 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", 2358 (msr & (1 << 15)) ? "" : "UN", 2359 (unsigned int)msr & 0xF, 2360 pkg_cstate_limit_strings[pkg_cstate_limit]); 2361 2362 #define AUTOMATIC_CSTATE_CONVERSION (1UL << 16) 2363 if (has_automatic_cstate_conversion) { 2364 fprintf(outf, ", automatic c-state conversion=%s", 2365 (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off"); 2366 } 2367 2368 fprintf(outf, ")\n"); 2369 2370 return; 2371 } 2372 2373 static void 2374 dump_config_tdp(void) 2375 { 2376 unsigned long long msr; 2377 2378 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); 2379 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); 2380 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); 2381 2382 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); 2383 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); 2384 if (msr) { 2385 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2386 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2387 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2388 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); 2389 } 2390 fprintf(outf, ")\n"); 2391 2392 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); 2393 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); 2394 if (msr) { 2395 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2396 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2397 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2398 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); 2399 } 2400 fprintf(outf, ")\n"); 2401 2402 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); 2403 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); 2404 if ((msr) & 0x3) 2405 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); 2406 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2407 fprintf(outf, ")\n"); 2408 2409 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); 2410 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); 2411 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); 2412 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2413 fprintf(outf, ")\n"); 2414 } 2415 2416 unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; 2417 2418 void print_irtl(void) 2419 { 2420 unsigned long long msr; 2421 2422 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr); 2423 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr); 2424 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2425 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2426 2427 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr); 2428 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr); 2429 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2430 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2431 2432 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr); 2433 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr); 2434 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2435 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2436 2437 if (!do_irtl_hsw) 2438 return; 2439 2440 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr); 2441 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr); 2442 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2443 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2444 2445 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr); 2446 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr); 2447 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2448 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2449 2450 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr); 2451 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr); 2452 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2453 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2454 2455 } 2456 void free_fd_percpu(void) 2457 { 2458 int i; 2459 2460 for (i = 0; i < topo.max_cpu_num + 1; ++i) { 2461 if (fd_percpu[i] != 0) 2462 close(fd_percpu[i]); 2463 } 2464 2465 free(fd_percpu); 2466 } 2467 2468 void free_all_buffers(void) 2469 { 2470 int i; 2471 2472 CPU_FREE(cpu_present_set); 2473 cpu_present_set = NULL; 2474 cpu_present_setsize = 0; 2475 2476 CPU_FREE(cpu_affinity_set); 2477 cpu_affinity_set = NULL; 2478 cpu_affinity_setsize = 0; 2479 2480 free(thread_even); 2481 free(core_even); 2482 free(package_even); 2483 2484 thread_even = NULL; 2485 core_even = NULL; 2486 package_even = NULL; 2487 2488 free(thread_odd); 2489 free(core_odd); 2490 free(package_odd); 2491 2492 thread_odd = NULL; 2493 core_odd = NULL; 2494 package_odd = NULL; 2495 2496 free(output_buffer); 2497 output_buffer = NULL; 2498 outp = NULL; 2499 2500 free_fd_percpu(); 2501 2502 free(irq_column_2_cpu); 2503 free(irqs_per_cpu); 2504 2505 for (i = 0; i <= topo.max_cpu_num; ++i) { 2506 if (cpus[i].put_ids) 2507 CPU_FREE(cpus[i].put_ids); 2508 } 2509 free(cpus); 2510 } 2511 2512 2513 /* 2514 * Parse a file containing a single int. 2515 * Return 0 if file can not be opened 2516 * Exit if file can be opened, but can not be parsed 2517 */ 2518 int parse_int_file(const char *fmt, ...) 2519 { 2520 va_list args; 2521 char path[PATH_MAX]; 2522 FILE *filep; 2523 int value; 2524 2525 va_start(args, fmt); 2526 vsnprintf(path, sizeof(path), fmt, args); 2527 va_end(args); 2528 filep = fopen(path, "r"); 2529 if (!filep) 2530 return 0; 2531 if (fscanf(filep, "%d", &value) != 1) 2532 err(1, "%s: failed to parse number from file", path); 2533 fclose(filep); 2534 return value; 2535 } 2536 2537 /* 2538 * cpu_is_first_core_in_package(cpu) 2539 * return 1 if given CPU is 1st core in package 2540 */ 2541 int cpu_is_first_core_in_package(int cpu) 2542 { 2543 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); 2544 } 2545 2546 int get_physical_package_id(int cpu) 2547 { 2548 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); 2549 } 2550 2551 int get_die_id(int cpu) 2552 { 2553 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/die_id", cpu); 2554 } 2555 2556 int get_core_id(int cpu) 2557 { 2558 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); 2559 } 2560 2561 void set_node_data(void) 2562 { 2563 int pkg, node, lnode, cpu, cpux; 2564 int cpu_count; 2565 2566 /* initialize logical_node_id */ 2567 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) 2568 cpus[cpu].logical_node_id = -1; 2569 2570 cpu_count = 0; 2571 for (pkg = 0; pkg < topo.num_packages; pkg++) { 2572 lnode = 0; 2573 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) { 2574 if (cpus[cpu].physical_package_id != pkg) 2575 continue; 2576 /* find a cpu with an unset logical_node_id */ 2577 if (cpus[cpu].logical_node_id != -1) 2578 continue; 2579 cpus[cpu].logical_node_id = lnode; 2580 node = cpus[cpu].physical_node_id; 2581 cpu_count++; 2582 /* 2583 * find all matching cpus on this pkg and set 2584 * the logical_node_id 2585 */ 2586 for (cpux = cpu; cpux <= topo.max_cpu_num; cpux++) { 2587 if ((cpus[cpux].physical_package_id == pkg) && 2588 (cpus[cpux].physical_node_id == node)) { 2589 cpus[cpux].logical_node_id = lnode; 2590 cpu_count++; 2591 } 2592 } 2593 lnode++; 2594 if (lnode > topo.nodes_per_pkg) 2595 topo.nodes_per_pkg = lnode; 2596 } 2597 if (cpu_count >= topo.max_cpu_num) 2598 break; 2599 } 2600 } 2601 2602 int get_physical_node_id(struct cpu_topology *thiscpu) 2603 { 2604 char path[80]; 2605 FILE *filep; 2606 int i; 2607 int cpu = thiscpu->logical_cpu_id; 2608 2609 for (i = 0; i <= topo.max_cpu_num; i++) { 2610 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist", 2611 cpu, i); 2612 filep = fopen(path, "r"); 2613 if (!filep) 2614 continue; 2615 fclose(filep); 2616 return i; 2617 } 2618 return -1; 2619 } 2620 2621 int get_thread_siblings(struct cpu_topology *thiscpu) 2622 { 2623 char path[80], character; 2624 FILE *filep; 2625 unsigned long map; 2626 int so, shift, sib_core; 2627 int cpu = thiscpu->logical_cpu_id; 2628 int offset = topo.max_cpu_num + 1; 2629 size_t size; 2630 int thread_id = 0; 2631 2632 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1)); 2633 if (thiscpu->thread_id < 0) 2634 thiscpu->thread_id = thread_id++; 2635 if (!thiscpu->put_ids) 2636 return -1; 2637 2638 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 2639 CPU_ZERO_S(size, thiscpu->put_ids); 2640 2641 sprintf(path, 2642 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu); 2643 filep = fopen_or_die(path, "r"); 2644 do { 2645 offset -= BITMASK_SIZE; 2646 if (fscanf(filep, "%lx%c", &map, &character) != 2) 2647 err(1, "%s: failed to parse file", path); 2648 for (shift = 0; shift < BITMASK_SIZE; shift++) { 2649 if ((map >> shift) & 0x1) { 2650 so = shift + offset; 2651 sib_core = get_core_id(so); 2652 if (sib_core == thiscpu->physical_core_id) { 2653 CPU_SET_S(so, size, thiscpu->put_ids); 2654 if ((so != cpu) && 2655 (cpus[so].thread_id < 0)) 2656 cpus[so].thread_id = 2657 thread_id++; 2658 } 2659 } 2660 } 2661 } while (!strncmp(&character, ",", 1)); 2662 fclose(filep); 2663 2664 return CPU_COUNT_S(size, thiscpu->put_ids); 2665 } 2666 2667 /* 2668 * run func(thread, core, package) in topology order 2669 * skip non-present cpus 2670 */ 2671 2672 int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *, 2673 struct pkg_data *, struct thread_data *, struct core_data *, 2674 struct pkg_data *), struct thread_data *thread_base, 2675 struct core_data *core_base, struct pkg_data *pkg_base, 2676 struct thread_data *thread_base2, struct core_data *core_base2, 2677 struct pkg_data *pkg_base2) 2678 { 2679 int retval, pkg_no, node_no, core_no, thread_no; 2680 2681 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 2682 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) { 2683 for (core_no = 0; core_no < topo.cores_per_node; 2684 ++core_no) { 2685 for (thread_no = 0; thread_no < 2686 topo.threads_per_core; ++thread_no) { 2687 struct thread_data *t, *t2; 2688 struct core_data *c, *c2; 2689 struct pkg_data *p, *p2; 2690 2691 t = GET_THREAD(thread_base, thread_no, 2692 core_no, node_no, 2693 pkg_no); 2694 2695 if (cpu_is_not_present(t->cpu_id)) 2696 continue; 2697 2698 t2 = GET_THREAD(thread_base2, thread_no, 2699 core_no, node_no, 2700 pkg_no); 2701 2702 c = GET_CORE(core_base, core_no, 2703 node_no, pkg_no); 2704 c2 = GET_CORE(core_base2, core_no, 2705 node_no, 2706 pkg_no); 2707 2708 p = GET_PKG(pkg_base, pkg_no); 2709 p2 = GET_PKG(pkg_base2, pkg_no); 2710 2711 retval = func(t, c, p, t2, c2, p2); 2712 if (retval) 2713 return retval; 2714 } 2715 } 2716 } 2717 } 2718 return 0; 2719 } 2720 2721 /* 2722 * run func(cpu) on every cpu in /proc/stat 2723 * return max_cpu number 2724 */ 2725 int for_all_proc_cpus(int (func)(int)) 2726 { 2727 FILE *fp; 2728 int cpu_num; 2729 int retval; 2730 2731 fp = fopen_or_die(proc_stat, "r"); 2732 2733 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); 2734 if (retval != 0) 2735 err(1, "%s: failed to parse format", proc_stat); 2736 2737 while (1) { 2738 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); 2739 if (retval != 1) 2740 break; 2741 2742 retval = func(cpu_num); 2743 if (retval) { 2744 fclose(fp); 2745 return(retval); 2746 } 2747 } 2748 fclose(fp); 2749 return 0; 2750 } 2751 2752 void re_initialize(void) 2753 { 2754 free_all_buffers(); 2755 setup_all_buffers(); 2756 printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); 2757 } 2758 2759 void set_max_cpu_num(void) 2760 { 2761 FILE *filep; 2762 unsigned long dummy; 2763 2764 topo.max_cpu_num = 0; 2765 filep = fopen_or_die( 2766 "/sys/devices/system/cpu/cpu0/topology/thread_siblings", 2767 "r"); 2768 while (fscanf(filep, "%lx,", &dummy) == 1) 2769 topo.max_cpu_num += BITMASK_SIZE; 2770 fclose(filep); 2771 topo.max_cpu_num--; /* 0 based */ 2772 } 2773 2774 /* 2775 * count_cpus() 2776 * remember the last one seen, it will be the max 2777 */ 2778 int count_cpus(int cpu) 2779 { 2780 topo.num_cpus++; 2781 return 0; 2782 } 2783 int mark_cpu_present(int cpu) 2784 { 2785 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); 2786 return 0; 2787 } 2788 2789 int init_thread_id(int cpu) 2790 { 2791 cpus[cpu].thread_id = -1; 2792 return 0; 2793 } 2794 2795 /* 2796 * snapshot_proc_interrupts() 2797 * 2798 * read and record summary of /proc/interrupts 2799 * 2800 * return 1 if config change requires a restart, else return 0 2801 */ 2802 int snapshot_proc_interrupts(void) 2803 { 2804 static FILE *fp; 2805 int column, retval; 2806 2807 if (fp == NULL) 2808 fp = fopen_or_die("/proc/interrupts", "r"); 2809 else 2810 rewind(fp); 2811 2812 /* read 1st line of /proc/interrupts to get cpu* name for each column */ 2813 for (column = 0; column < topo.num_cpus; ++column) { 2814 int cpu_number; 2815 2816 retval = fscanf(fp, " CPU%d", &cpu_number); 2817 if (retval != 1) 2818 break; 2819 2820 if (cpu_number > topo.max_cpu_num) { 2821 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); 2822 return 1; 2823 } 2824 2825 irq_column_2_cpu[column] = cpu_number; 2826 irqs_per_cpu[cpu_number] = 0; 2827 } 2828 2829 /* read /proc/interrupt count lines and sum up irqs per cpu */ 2830 while (1) { 2831 int column; 2832 char buf[64]; 2833 2834 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ 2835 if (retval != 1) 2836 break; 2837 2838 /* read the count per cpu */ 2839 for (column = 0; column < topo.num_cpus; ++column) { 2840 2841 int cpu_number, irq_count; 2842 2843 retval = fscanf(fp, " %d", &irq_count); 2844 if (retval != 1) 2845 break; 2846 2847 cpu_number = irq_column_2_cpu[column]; 2848 irqs_per_cpu[cpu_number] += irq_count; 2849 2850 } 2851 2852 while (getc(fp) != '\n') 2853 ; /* flush interrupt description */ 2854 2855 } 2856 return 0; 2857 } 2858 /* 2859 * snapshot_gfx_rc6_ms() 2860 * 2861 * record snapshot of 2862 * /sys/class/drm/card0/power/rc6_residency_ms 2863 * 2864 * return 1 if config change requires a restart, else return 0 2865 */ 2866 int snapshot_gfx_rc6_ms(void) 2867 { 2868 FILE *fp; 2869 int retval; 2870 2871 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); 2872 2873 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); 2874 if (retval != 1) 2875 err(1, "GFX rc6"); 2876 2877 fclose(fp); 2878 2879 return 0; 2880 } 2881 /* 2882 * snapshot_gfx_mhz() 2883 * 2884 * record snapshot of 2885 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz 2886 * 2887 * return 1 if config change requires a restart, else return 0 2888 */ 2889 int snapshot_gfx_mhz(void) 2890 { 2891 static FILE *fp; 2892 int retval; 2893 2894 if (fp == NULL) 2895 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); 2896 else { 2897 rewind(fp); 2898 fflush(fp); 2899 } 2900 2901 retval = fscanf(fp, "%d", &gfx_cur_mhz); 2902 if (retval != 1) 2903 err(1, "GFX MHz"); 2904 2905 return 0; 2906 } 2907 2908 /* 2909 * snapshot_cpu_lpi() 2910 * 2911 * record snapshot of 2912 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us 2913 * 2914 * return 1 if config change requires a restart, else return 0 2915 */ 2916 int snapshot_cpu_lpi_us(void) 2917 { 2918 FILE *fp; 2919 int retval; 2920 2921 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r"); 2922 2923 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us); 2924 if (retval != 1) 2925 err(1, "CPU LPI"); 2926 2927 fclose(fp); 2928 2929 return 0; 2930 } 2931 /* 2932 * snapshot_sys_lpi() 2933 * 2934 * record snapshot of 2935 * /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us 2936 * 2937 * return 1 if config change requires a restart, else return 0 2938 */ 2939 int snapshot_sys_lpi_us(void) 2940 { 2941 FILE *fp; 2942 int retval; 2943 2944 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us", "r"); 2945 2946 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us); 2947 if (retval != 1) 2948 err(1, "SYS LPI"); 2949 2950 fclose(fp); 2951 2952 return 0; 2953 } 2954 /* 2955 * snapshot /proc and /sys files 2956 * 2957 * return 1 if configuration restart needed, else return 0 2958 */ 2959 int snapshot_proc_sysfs_files(void) 2960 { 2961 if (DO_BIC(BIC_IRQ)) 2962 if (snapshot_proc_interrupts()) 2963 return 1; 2964 2965 if (DO_BIC(BIC_GFX_rc6)) 2966 snapshot_gfx_rc6_ms(); 2967 2968 if (DO_BIC(BIC_GFXMHz)) 2969 snapshot_gfx_mhz(); 2970 2971 if (DO_BIC(BIC_CPU_LPI)) 2972 snapshot_cpu_lpi_us(); 2973 2974 if (DO_BIC(BIC_SYS_LPI)) 2975 snapshot_sys_lpi_us(); 2976 2977 return 0; 2978 } 2979 2980 int exit_requested; 2981 2982 static void signal_handler (int signal) 2983 { 2984 switch (signal) { 2985 case SIGINT: 2986 exit_requested = 1; 2987 if (debug) 2988 fprintf(stderr, " SIGINT\n"); 2989 break; 2990 case SIGUSR1: 2991 if (debug > 1) 2992 fprintf(stderr, "SIGUSR1\n"); 2993 break; 2994 } 2995 /* make sure this manually-invoked interval is at least 1ms long */ 2996 nanosleep(&one_msec, NULL); 2997 } 2998 2999 void setup_signal_handler(void) 3000 { 3001 struct sigaction sa; 3002 3003 memset(&sa, 0, sizeof(sa)); 3004 3005 sa.sa_handler = &signal_handler; 3006 3007 if (sigaction(SIGINT, &sa, NULL) < 0) 3008 err(1, "sigaction SIGINT"); 3009 if (sigaction(SIGUSR1, &sa, NULL) < 0) 3010 err(1, "sigaction SIGUSR1"); 3011 } 3012 3013 void do_sleep(void) 3014 { 3015 struct timeval select_timeout; 3016 fd_set readfds; 3017 int retval; 3018 3019 FD_ZERO(&readfds); 3020 FD_SET(0, &readfds); 3021 3022 if (!isatty(fileno(stdin))) { 3023 nanosleep(&interval_ts, NULL); 3024 return; 3025 } 3026 3027 select_timeout = interval_tv; 3028 retval = select(1, &readfds, NULL, NULL, &select_timeout); 3029 3030 if (retval == 1) { 3031 switch (getc(stdin)) { 3032 case 'q': 3033 exit_requested = 1; 3034 break; 3035 } 3036 /* make sure this manually-invoked interval is at least 1ms long */ 3037 nanosleep(&one_msec, NULL); 3038 } 3039 } 3040 3041 3042 void turbostat_loop() 3043 { 3044 int retval; 3045 int restarted = 0; 3046 int done_iters = 0; 3047 3048 setup_signal_handler(); 3049 3050 restart: 3051 restarted++; 3052 3053 snapshot_proc_sysfs_files(); 3054 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3055 first_counter_read = 0; 3056 if (retval < -1) { 3057 exit(retval); 3058 } else if (retval == -1) { 3059 if (restarted > 1) { 3060 exit(retval); 3061 } 3062 re_initialize(); 3063 goto restart; 3064 } 3065 restarted = 0; 3066 done_iters = 0; 3067 gettimeofday(&tv_even, (struct timezone *)NULL); 3068 3069 while (1) { 3070 if (for_all_proc_cpus(cpu_is_not_present)) { 3071 re_initialize(); 3072 goto restart; 3073 } 3074 do_sleep(); 3075 if (snapshot_proc_sysfs_files()) 3076 goto restart; 3077 retval = for_all_cpus(get_counters, ODD_COUNTERS); 3078 if (retval < -1) { 3079 exit(retval); 3080 } else if (retval == -1) { 3081 re_initialize(); 3082 goto restart; 3083 } 3084 gettimeofday(&tv_odd, (struct timezone *)NULL); 3085 timersub(&tv_odd, &tv_even, &tv_delta); 3086 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) { 3087 re_initialize(); 3088 goto restart; 3089 } 3090 compute_average(EVEN_COUNTERS); 3091 format_all_counters(EVEN_COUNTERS); 3092 flush_output_stdout(); 3093 if (exit_requested) 3094 break; 3095 if (num_iterations && ++done_iters >= num_iterations) 3096 break; 3097 do_sleep(); 3098 if (snapshot_proc_sysfs_files()) 3099 goto restart; 3100 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3101 if (retval < -1) { 3102 exit(retval); 3103 } else if (retval == -1) { 3104 re_initialize(); 3105 goto restart; 3106 } 3107 gettimeofday(&tv_even, (struct timezone *)NULL); 3108 timersub(&tv_even, &tv_odd, &tv_delta); 3109 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) { 3110 re_initialize(); 3111 goto restart; 3112 } 3113 compute_average(ODD_COUNTERS); 3114 format_all_counters(ODD_COUNTERS); 3115 flush_output_stdout(); 3116 if (exit_requested) 3117 break; 3118 if (num_iterations && ++done_iters >= num_iterations) 3119 break; 3120 } 3121 } 3122 3123 void check_dev_msr() 3124 { 3125 struct stat sb; 3126 char pathname[32]; 3127 3128 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3129 if (stat(pathname, &sb)) 3130 if (system("/sbin/modprobe msr > /dev/null 2>&1")) 3131 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); 3132 } 3133 3134 void check_permissions() 3135 { 3136 struct __user_cap_header_struct cap_header_data; 3137 cap_user_header_t cap_header = &cap_header_data; 3138 struct __user_cap_data_struct cap_data_data; 3139 cap_user_data_t cap_data = &cap_data_data; 3140 extern int capget(cap_user_header_t hdrp, cap_user_data_t datap); 3141 int do_exit = 0; 3142 char pathname[32]; 3143 3144 /* check for CAP_SYS_RAWIO */ 3145 cap_header->pid = getpid(); 3146 cap_header->version = _LINUX_CAPABILITY_VERSION; 3147 if (capget(cap_header, cap_data) < 0) 3148 err(-6, "capget(2) failed"); 3149 3150 if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) { 3151 do_exit++; 3152 warnx("capget(CAP_SYS_RAWIO) failed," 3153 " try \"# setcap cap_sys_rawio=ep %s\"", progname); 3154 } 3155 3156 /* test file permissions */ 3157 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3158 if (euidaccess(pathname, R_OK)) { 3159 do_exit++; 3160 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); 3161 } 3162 3163 /* if all else fails, thell them to be root */ 3164 if (do_exit) 3165 if (getuid() != 0) 3166 warnx("... or simply run as root"); 3167 3168 if (do_exit) 3169 exit(-6); 3170 } 3171 3172 /* 3173 * NHM adds support for additional MSRs: 3174 * 3175 * MSR_SMI_COUNT 0x00000034 3176 * 3177 * MSR_PLATFORM_INFO 0x000000ce 3178 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 3179 * 3180 * MSR_MISC_PWR_MGMT 0x000001aa 3181 * 3182 * MSR_PKG_C3_RESIDENCY 0x000003f8 3183 * MSR_PKG_C6_RESIDENCY 0x000003f9 3184 * MSR_CORE_C3_RESIDENCY 0x000003fc 3185 * MSR_CORE_C6_RESIDENCY 0x000003fd 3186 * 3187 * Side effect: 3188 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL 3189 * sets has_misc_feature_control 3190 */ 3191 int probe_nhm_msrs(unsigned int family, unsigned int model) 3192 { 3193 unsigned long long msr; 3194 unsigned int base_ratio; 3195 int *pkg_cstate_limits; 3196 3197 if (!genuine_intel) 3198 return 0; 3199 3200 if (family != 6) 3201 return 0; 3202 3203 bclk = discover_bclk(family, model); 3204 3205 switch (model) { 3206 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 3207 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3208 pkg_cstate_limits = nhm_pkg_cstate_limits; 3209 break; 3210 case INTEL_FAM6_SANDYBRIDGE: /* SNB */ 3211 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */ 3212 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3213 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3214 pkg_cstate_limits = snb_pkg_cstate_limits; 3215 has_misc_feature_control = 1; 3216 break; 3217 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3218 case INTEL_FAM6_HASWELL_X: /* HSX */ 3219 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3220 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3221 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3222 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3223 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3224 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 3225 pkg_cstate_limits = hsw_pkg_cstate_limits; 3226 has_misc_feature_control = 1; 3227 break; 3228 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3229 pkg_cstate_limits = skx_pkg_cstate_limits; 3230 has_misc_feature_control = 1; 3231 break; 3232 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 3233 no_MSR_MISC_PWR_MGMT = 1; 3234 case INTEL_FAM6_ATOM_SILVERMONT_X: /* AVN */ 3235 pkg_cstate_limits = slv_pkg_cstate_limits; 3236 break; 3237 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */ 3238 pkg_cstate_limits = amt_pkg_cstate_limits; 3239 no_MSR_MISC_PWR_MGMT = 1; 3240 break; 3241 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */ 3242 pkg_cstate_limits = phi_pkg_cstate_limits; 3243 break; 3244 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3245 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 3246 case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */ 3247 pkg_cstate_limits = glm_pkg_cstate_limits; 3248 break; 3249 default: 3250 return 0; 3251 } 3252 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 3253 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; 3254 3255 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 3256 base_ratio = (msr >> 8) & 0xFF; 3257 3258 base_hz = base_ratio * bclk * 1000000; 3259 has_base_hz = 1; 3260 return 1; 3261 } 3262 /* 3263 * SLV client has support for unique MSRs: 3264 * 3265 * MSR_CC6_DEMOTION_POLICY_CONFIG 3266 * MSR_MC6_DEMOTION_POLICY_CONFIG 3267 */ 3268 3269 int has_slv_msrs(unsigned int family, unsigned int model) 3270 { 3271 if (!genuine_intel) 3272 return 0; 3273 3274 switch (model) { 3275 case INTEL_FAM6_ATOM_SILVERMONT: 3276 case INTEL_FAM6_ATOM_SILVERMONT_MID: 3277 case INTEL_FAM6_ATOM_AIRMONT_MID: 3278 return 1; 3279 } 3280 return 0; 3281 } 3282 int is_dnv(unsigned int family, unsigned int model) 3283 { 3284 3285 if (!genuine_intel) 3286 return 0; 3287 3288 switch (model) { 3289 case INTEL_FAM6_ATOM_GOLDMONT_X: 3290 return 1; 3291 } 3292 return 0; 3293 } 3294 int is_bdx(unsigned int family, unsigned int model) 3295 { 3296 3297 if (!genuine_intel) 3298 return 0; 3299 3300 switch (model) { 3301 case INTEL_FAM6_BROADWELL_X: 3302 return 1; 3303 } 3304 return 0; 3305 } 3306 int is_skx(unsigned int family, unsigned int model) 3307 { 3308 3309 if (!genuine_intel) 3310 return 0; 3311 3312 switch (model) { 3313 case INTEL_FAM6_SKYLAKE_X: 3314 return 1; 3315 } 3316 return 0; 3317 } 3318 3319 int has_turbo_ratio_limit(unsigned int family, unsigned int model) 3320 { 3321 if (has_slv_msrs(family, model)) 3322 return 0; 3323 3324 switch (model) { 3325 /* Nehalem compatible, but do not include turbo-ratio limit support */ 3326 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3327 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */ 3328 return 0; 3329 default: 3330 return 1; 3331 } 3332 } 3333 int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model) 3334 { 3335 if (has_slv_msrs(family, model)) 3336 return 1; 3337 3338 return 0; 3339 } 3340 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) 3341 { 3342 if (!genuine_intel) 3343 return 0; 3344 3345 if (family != 6) 3346 return 0; 3347 3348 switch (model) { 3349 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3350 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3351 return 1; 3352 default: 3353 return 0; 3354 } 3355 } 3356 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) 3357 { 3358 if (!genuine_intel) 3359 return 0; 3360 3361 if (family != 6) 3362 return 0; 3363 3364 switch (model) { 3365 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3366 return 1; 3367 default: 3368 return 0; 3369 } 3370 } 3371 3372 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) 3373 { 3374 if (!genuine_intel) 3375 return 0; 3376 3377 if (family != 6) 3378 return 0; 3379 3380 switch (model) { 3381 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 3382 return 1; 3383 default: 3384 return 0; 3385 } 3386 } 3387 int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model) 3388 { 3389 if (!genuine_intel) 3390 return 0; 3391 3392 if (family != 6) 3393 return 0; 3394 3395 switch (model) { 3396 case INTEL_FAM6_ATOM_GOLDMONT: 3397 case INTEL_FAM6_SKYLAKE_X: 3398 return 1; 3399 default: 3400 return 0; 3401 } 3402 } 3403 int has_config_tdp(unsigned int family, unsigned int model) 3404 { 3405 if (!genuine_intel) 3406 return 0; 3407 3408 if (family != 6) 3409 return 0; 3410 3411 switch (model) { 3412 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3413 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3414 case INTEL_FAM6_HASWELL_X: /* HSX */ 3415 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3416 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3417 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3418 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3419 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3420 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 3421 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3422 3423 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 3424 return 1; 3425 default: 3426 return 0; 3427 } 3428 } 3429 3430 static void 3431 dump_cstate_pstate_config_info(unsigned int family, unsigned int model) 3432 { 3433 if (!do_nhm_platform_info) 3434 return; 3435 3436 dump_nhm_platform_info(); 3437 3438 if (has_hsw_turbo_ratio_limit(family, model)) 3439 dump_hsw_turbo_ratio_limits(); 3440 3441 if (has_ivt_turbo_ratio_limit(family, model)) 3442 dump_ivt_turbo_ratio_limits(); 3443 3444 if (has_turbo_ratio_limit(family, model)) 3445 dump_turbo_ratio_limits(family, model); 3446 3447 if (has_atom_turbo_ratio_limit(family, model)) 3448 dump_atom_turbo_ratio_limits(); 3449 3450 if (has_knl_turbo_ratio_limit(family, model)) 3451 dump_knl_turbo_ratio_limits(); 3452 3453 if (has_config_tdp(family, model)) 3454 dump_config_tdp(); 3455 3456 dump_nhm_cst_cfg(); 3457 } 3458 3459 static void 3460 dump_sysfs_cstate_config(void) 3461 { 3462 char path[64]; 3463 char name_buf[16]; 3464 char desc[64]; 3465 FILE *input; 3466 int state; 3467 char *sp; 3468 3469 if (!DO_BIC(BIC_sysfs)) 3470 return; 3471 3472 for (state = 0; state < 10; ++state) { 3473 3474 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 3475 base_cpu, state); 3476 input = fopen(path, "r"); 3477 if (input == NULL) 3478 continue; 3479 if (!fgets(name_buf, sizeof(name_buf), input)) 3480 err(1, "%s: failed to read file", path); 3481 3482 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 3483 sp = strchr(name_buf, '-'); 3484 if (!sp) 3485 sp = strchrnul(name_buf, '\n'); 3486 *sp = '\0'; 3487 fclose(input); 3488 3489 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc", 3490 base_cpu, state); 3491 input = fopen(path, "r"); 3492 if (input == NULL) 3493 continue; 3494 if (!fgets(desc, sizeof(desc), input)) 3495 err(1, "%s: failed to read file", path); 3496 3497 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc); 3498 fclose(input); 3499 } 3500 } 3501 static void 3502 dump_sysfs_pstate_config(void) 3503 { 3504 char path[64]; 3505 char driver_buf[64]; 3506 char governor_buf[64]; 3507 FILE *input; 3508 int turbo; 3509 3510 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver", 3511 base_cpu); 3512 input = fopen(path, "r"); 3513 if (input == NULL) { 3514 fprintf(outf, "NSFOD %s\n", path); 3515 return; 3516 } 3517 if (!fgets(driver_buf, sizeof(driver_buf), input)) 3518 err(1, "%s: failed to read file", path); 3519 fclose(input); 3520 3521 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor", 3522 base_cpu); 3523 input = fopen(path, "r"); 3524 if (input == NULL) { 3525 fprintf(outf, "NSFOD %s\n", path); 3526 return; 3527 } 3528 if (!fgets(governor_buf, sizeof(governor_buf), input)) 3529 err(1, "%s: failed to read file", path); 3530 fclose(input); 3531 3532 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf); 3533 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf); 3534 3535 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost"); 3536 input = fopen(path, "r"); 3537 if (input != NULL) { 3538 if (fscanf(input, "%d", &turbo) != 1) 3539 err(1, "%s: failed to parse number from file", path); 3540 fprintf(outf, "cpufreq boost: %d\n", turbo); 3541 fclose(input); 3542 } 3543 3544 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo"); 3545 input = fopen(path, "r"); 3546 if (input != NULL) { 3547 if (fscanf(input, "%d", &turbo) != 1) 3548 err(1, "%s: failed to parse number from file", path); 3549 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo); 3550 fclose(input); 3551 } 3552 } 3553 3554 3555 /* 3556 * print_epb() 3557 * Decode the ENERGY_PERF_BIAS MSR 3558 */ 3559 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3560 { 3561 unsigned long long msr; 3562 char *epb_string; 3563 int cpu; 3564 3565 if (!has_epb) 3566 return 0; 3567 3568 cpu = t->cpu_id; 3569 3570 /* EPB is per-package */ 3571 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3572 return 0; 3573 3574 if (cpu_migrate(cpu)) { 3575 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3576 return -1; 3577 } 3578 3579 if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr)) 3580 return 0; 3581 3582 switch (msr & 0xF) { 3583 case ENERGY_PERF_BIAS_PERFORMANCE: 3584 epb_string = "performance"; 3585 break; 3586 case ENERGY_PERF_BIAS_NORMAL: 3587 epb_string = "balanced"; 3588 break; 3589 case ENERGY_PERF_BIAS_POWERSAVE: 3590 epb_string = "powersave"; 3591 break; 3592 default: 3593 epb_string = "custom"; 3594 break; 3595 } 3596 fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string); 3597 3598 return 0; 3599 } 3600 /* 3601 * print_hwp() 3602 * Decode the MSR_HWP_CAPABILITIES 3603 */ 3604 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3605 { 3606 unsigned long long msr; 3607 int cpu; 3608 3609 if (!has_hwp) 3610 return 0; 3611 3612 cpu = t->cpu_id; 3613 3614 /* MSR_HWP_CAPABILITIES is per-package */ 3615 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3616 return 0; 3617 3618 if (cpu_migrate(cpu)) { 3619 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3620 return -1; 3621 } 3622 3623 if (get_msr(cpu, MSR_PM_ENABLE, &msr)) 3624 return 0; 3625 3626 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", 3627 cpu, msr, (msr & (1 << 0)) ? "" : "No-"); 3628 3629 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ 3630 if ((msr & (1 << 0)) == 0) 3631 return 0; 3632 3633 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) 3634 return 0; 3635 3636 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " 3637 "(high %d guar %d eff %d low %d)\n", 3638 cpu, msr, 3639 (unsigned int)HWP_HIGHEST_PERF(msr), 3640 (unsigned int)HWP_GUARANTEED_PERF(msr), 3641 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), 3642 (unsigned int)HWP_LOWEST_PERF(msr)); 3643 3644 if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) 3645 return 0; 3646 3647 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " 3648 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n", 3649 cpu, msr, 3650 (unsigned int)(((msr) >> 0) & 0xff), 3651 (unsigned int)(((msr) >> 8) & 0xff), 3652 (unsigned int)(((msr) >> 16) & 0xff), 3653 (unsigned int)(((msr) >> 24) & 0xff), 3654 (unsigned int)(((msr) >> 32) & 0xff3), 3655 (unsigned int)(((msr) >> 42) & 0x1)); 3656 3657 if (has_hwp_pkg) { 3658 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) 3659 return 0; 3660 3661 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " 3662 "(min %d max %d des %d epp 0x%x window 0x%x)\n", 3663 cpu, msr, 3664 (unsigned int)(((msr) >> 0) & 0xff), 3665 (unsigned int)(((msr) >> 8) & 0xff), 3666 (unsigned int)(((msr) >> 16) & 0xff), 3667 (unsigned int)(((msr) >> 24) & 0xff), 3668 (unsigned int)(((msr) >> 32) & 0xff3)); 3669 } 3670 if (has_hwp_notify) { 3671 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) 3672 return 0; 3673 3674 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " 3675 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", 3676 cpu, msr, 3677 ((msr) & 0x1) ? "EN" : "Dis", 3678 ((msr) & 0x2) ? "EN" : "Dis"); 3679 } 3680 if (get_msr(cpu, MSR_HWP_STATUS, &msr)) 3681 return 0; 3682 3683 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " 3684 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", 3685 cpu, msr, 3686 ((msr) & 0x1) ? "" : "No-", 3687 ((msr) & 0x2) ? "" : "No-"); 3688 3689 return 0; 3690 } 3691 3692 /* 3693 * print_perf_limit() 3694 */ 3695 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3696 { 3697 unsigned long long msr; 3698 int cpu; 3699 3700 cpu = t->cpu_id; 3701 3702 /* per-package */ 3703 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3704 return 0; 3705 3706 if (cpu_migrate(cpu)) { 3707 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3708 return -1; 3709 } 3710 3711 if (do_core_perf_limit_reasons) { 3712 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); 3713 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 3714 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", 3715 (msr & 1 << 15) ? "bit15, " : "", 3716 (msr & 1 << 14) ? "bit14, " : "", 3717 (msr & 1 << 13) ? "Transitions, " : "", 3718 (msr & 1 << 12) ? "MultiCoreTurbo, " : "", 3719 (msr & 1 << 11) ? "PkgPwrL2, " : "", 3720 (msr & 1 << 10) ? "PkgPwrL1, " : "", 3721 (msr & 1 << 9) ? "CorePwr, " : "", 3722 (msr & 1 << 8) ? "Amps, " : "", 3723 (msr & 1 << 6) ? "VR-Therm, " : "", 3724 (msr & 1 << 5) ? "Auto-HWP, " : "", 3725 (msr & 1 << 4) ? "Graphics, " : "", 3726 (msr & 1 << 2) ? "bit2, " : "", 3727 (msr & 1 << 1) ? "ThermStatus, " : "", 3728 (msr & 1 << 0) ? "PROCHOT, " : ""); 3729 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 3730 (msr & 1 << 31) ? "bit31, " : "", 3731 (msr & 1 << 30) ? "bit30, " : "", 3732 (msr & 1 << 29) ? "Transitions, " : "", 3733 (msr & 1 << 28) ? "MultiCoreTurbo, " : "", 3734 (msr & 1 << 27) ? "PkgPwrL2, " : "", 3735 (msr & 1 << 26) ? "PkgPwrL1, " : "", 3736 (msr & 1 << 25) ? "CorePwr, " : "", 3737 (msr & 1 << 24) ? "Amps, " : "", 3738 (msr & 1 << 22) ? "VR-Therm, " : "", 3739 (msr & 1 << 21) ? "Auto-HWP, " : "", 3740 (msr & 1 << 20) ? "Graphics, " : "", 3741 (msr & 1 << 18) ? "bit18, " : "", 3742 (msr & 1 << 17) ? "ThermStatus, " : "", 3743 (msr & 1 << 16) ? "PROCHOT, " : ""); 3744 3745 } 3746 if (do_gfx_perf_limit_reasons) { 3747 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); 3748 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 3749 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", 3750 (msr & 1 << 0) ? "PROCHOT, " : "", 3751 (msr & 1 << 1) ? "ThermStatus, " : "", 3752 (msr & 1 << 4) ? "Graphics, " : "", 3753 (msr & 1 << 6) ? "VR-Therm, " : "", 3754 (msr & 1 << 8) ? "Amps, " : "", 3755 (msr & 1 << 9) ? "GFXPwr, " : "", 3756 (msr & 1 << 10) ? "PkgPwrL1, " : "", 3757 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 3758 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", 3759 (msr & 1 << 16) ? "PROCHOT, " : "", 3760 (msr & 1 << 17) ? "ThermStatus, " : "", 3761 (msr & 1 << 20) ? "Graphics, " : "", 3762 (msr & 1 << 22) ? "VR-Therm, " : "", 3763 (msr & 1 << 24) ? "Amps, " : "", 3764 (msr & 1 << 25) ? "GFXPwr, " : "", 3765 (msr & 1 << 26) ? "PkgPwrL1, " : "", 3766 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 3767 } 3768 if (do_ring_perf_limit_reasons) { 3769 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); 3770 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 3771 fprintf(outf, " (Active: %s%s%s%s%s%s)", 3772 (msr & 1 << 0) ? "PROCHOT, " : "", 3773 (msr & 1 << 1) ? "ThermStatus, " : "", 3774 (msr & 1 << 6) ? "VR-Therm, " : "", 3775 (msr & 1 << 8) ? "Amps, " : "", 3776 (msr & 1 << 10) ? "PkgPwrL1, " : "", 3777 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 3778 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", 3779 (msr & 1 << 16) ? "PROCHOT, " : "", 3780 (msr & 1 << 17) ? "ThermStatus, " : "", 3781 (msr & 1 << 22) ? "VR-Therm, " : "", 3782 (msr & 1 << 24) ? "Amps, " : "", 3783 (msr & 1 << 26) ? "PkgPwrL1, " : "", 3784 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 3785 } 3786 return 0; 3787 } 3788 3789 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ 3790 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ 3791 3792 double get_tdp_intel(unsigned int model) 3793 { 3794 unsigned long long msr; 3795 3796 if (do_rapl & RAPL_PKG_POWER_INFO) 3797 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) 3798 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; 3799 3800 switch (model) { 3801 case INTEL_FAM6_ATOM_SILVERMONT: 3802 case INTEL_FAM6_ATOM_SILVERMONT_X: 3803 return 30.0; 3804 default: 3805 return 135.0; 3806 } 3807 } 3808 3809 double get_tdp_amd(unsigned int family) 3810 { 3811 switch (family) { 3812 case 0x17: 3813 default: 3814 /* This is the max stock TDP of HEDT/Server Fam17h chips */ 3815 return 250.0; 3816 } 3817 } 3818 3819 /* 3820 * rapl_dram_energy_units_probe() 3821 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR. 3822 */ 3823 static double 3824 rapl_dram_energy_units_probe(int model, double rapl_energy_units) 3825 { 3826 /* only called for genuine_intel, family 6 */ 3827 3828 switch (model) { 3829 case INTEL_FAM6_HASWELL_X: /* HSX */ 3830 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3831 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 3832 return (rapl_dram_energy_units = 15.3 / 1000000); 3833 default: 3834 return (rapl_energy_units); 3835 } 3836 } 3837 3838 void rapl_probe_intel(unsigned int family, unsigned int model) 3839 { 3840 unsigned long long msr; 3841 unsigned int time_unit; 3842 double tdp; 3843 3844 if (family != 6) 3845 return; 3846 3847 switch (model) { 3848 case INTEL_FAM6_SANDYBRIDGE: 3849 case INTEL_FAM6_IVYBRIDGE: 3850 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3851 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3852 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3853 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3854 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; 3855 if (rapl_joules) { 3856 BIC_PRESENT(BIC_Pkg_J); 3857 BIC_PRESENT(BIC_Cor_J); 3858 BIC_PRESENT(BIC_GFX_J); 3859 } else { 3860 BIC_PRESENT(BIC_PkgWatt); 3861 BIC_PRESENT(BIC_CorWatt); 3862 BIC_PRESENT(BIC_GFXWatt); 3863 } 3864 break; 3865 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3866 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 3867 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; 3868 if (rapl_joules) 3869 BIC_PRESENT(BIC_Pkg_J); 3870 else 3871 BIC_PRESENT(BIC_PkgWatt); 3872 break; 3873 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3874 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 3875 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_GFX | RAPL_PKG_POWER_INFO; 3876 BIC_PRESENT(BIC_PKG__); 3877 BIC_PRESENT(BIC_RAM__); 3878 if (rapl_joules) { 3879 BIC_PRESENT(BIC_Pkg_J); 3880 BIC_PRESENT(BIC_Cor_J); 3881 BIC_PRESENT(BIC_RAM_J); 3882 BIC_PRESENT(BIC_GFX_J); 3883 } else { 3884 BIC_PRESENT(BIC_PkgWatt); 3885 BIC_PRESENT(BIC_CorWatt); 3886 BIC_PRESENT(BIC_RAMWatt); 3887 BIC_PRESENT(BIC_GFXWatt); 3888 } 3889 break; 3890 case INTEL_FAM6_HASWELL_X: /* HSX */ 3891 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3892 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3893 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 3894 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 3895 BIC_PRESENT(BIC_PKG__); 3896 BIC_PRESENT(BIC_RAM__); 3897 if (rapl_joules) { 3898 BIC_PRESENT(BIC_Pkg_J); 3899 BIC_PRESENT(BIC_RAM_J); 3900 } else { 3901 BIC_PRESENT(BIC_PkgWatt); 3902 BIC_PRESENT(BIC_RAMWatt); 3903 } 3904 break; 3905 case INTEL_FAM6_SANDYBRIDGE_X: 3906 case INTEL_FAM6_IVYBRIDGE_X: 3907 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; 3908 BIC_PRESENT(BIC_PKG__); 3909 BIC_PRESENT(BIC_RAM__); 3910 if (rapl_joules) { 3911 BIC_PRESENT(BIC_Pkg_J); 3912 BIC_PRESENT(BIC_Cor_J); 3913 BIC_PRESENT(BIC_RAM_J); 3914 } else { 3915 BIC_PRESENT(BIC_PkgWatt); 3916 BIC_PRESENT(BIC_CorWatt); 3917 BIC_PRESENT(BIC_RAMWatt); 3918 } 3919 break; 3920 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 3921 case INTEL_FAM6_ATOM_SILVERMONT_X: /* AVN */ 3922 do_rapl = RAPL_PKG | RAPL_CORES; 3923 if (rapl_joules) { 3924 BIC_PRESENT(BIC_Pkg_J); 3925 BIC_PRESENT(BIC_Cor_J); 3926 } else { 3927 BIC_PRESENT(BIC_PkgWatt); 3928 BIC_PRESENT(BIC_CorWatt); 3929 } 3930 break; 3931 case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */ 3932 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS; 3933 BIC_PRESENT(BIC_PKG__); 3934 BIC_PRESENT(BIC_RAM__); 3935 if (rapl_joules) { 3936 BIC_PRESENT(BIC_Pkg_J); 3937 BIC_PRESENT(BIC_Cor_J); 3938 BIC_PRESENT(BIC_RAM_J); 3939 } else { 3940 BIC_PRESENT(BIC_PkgWatt); 3941 BIC_PRESENT(BIC_CorWatt); 3942 BIC_PRESENT(BIC_RAMWatt); 3943 } 3944 break; 3945 default: 3946 return; 3947 } 3948 3949 /* units on package 0, verify later other packages match */ 3950 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) 3951 return; 3952 3953 rapl_power_units = 1.0 / (1 << (msr & 0xF)); 3954 if (model == INTEL_FAM6_ATOM_SILVERMONT) 3955 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; 3956 else 3957 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 3958 3959 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units); 3960 3961 time_unit = msr >> 16 & 0xF; 3962 if (time_unit == 0) 3963 time_unit = 0xA; 3964 3965 rapl_time_units = 1.0 / (1 << (time_unit)); 3966 3967 tdp = get_tdp_intel(model); 3968 3969 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 3970 if (!quiet) 3971 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 3972 } 3973 3974 void rapl_probe_amd(unsigned int family, unsigned int model) 3975 { 3976 unsigned long long msr; 3977 unsigned int eax, ebx, ecx, edx; 3978 unsigned int has_rapl = 0; 3979 double tdp; 3980 3981 if (max_extended_level >= 0x80000007) { 3982 __cpuid(0x80000007, eax, ebx, ecx, edx); 3983 /* RAPL (Fam 17h) */ 3984 has_rapl = edx & (1 << 14); 3985 } 3986 3987 if (!has_rapl) 3988 return; 3989 3990 switch (family) { 3991 case 0x17: /* Zen, Zen+ */ 3992 do_rapl = RAPL_AMD_F17H | RAPL_PER_CORE_ENERGY; 3993 if (rapl_joules) { 3994 BIC_PRESENT(BIC_Pkg_J); 3995 BIC_PRESENT(BIC_Cor_J); 3996 } else { 3997 BIC_PRESENT(BIC_PkgWatt); 3998 BIC_PRESENT(BIC_CorWatt); 3999 } 4000 break; 4001 default: 4002 return; 4003 } 4004 4005 if (get_msr(base_cpu, MSR_RAPL_PWR_UNIT, &msr)) 4006 return; 4007 4008 rapl_time_units = ldexp(1.0, -(msr >> 16 & 0xf)); 4009 rapl_energy_units = ldexp(1.0, -(msr >> 8 & 0x1f)); 4010 rapl_power_units = ldexp(1.0, -(msr & 0xf)); 4011 4012 tdp = get_tdp_amd(model); 4013 4014 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 4015 if (!quiet) 4016 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 4017 } 4018 4019 /* 4020 * rapl_probe() 4021 * 4022 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units 4023 */ 4024 void rapl_probe(unsigned int family, unsigned int model) 4025 { 4026 if (genuine_intel) 4027 rapl_probe_intel(family, model); 4028 if (authentic_amd) 4029 rapl_probe_amd(family, model); 4030 } 4031 4032 void perf_limit_reasons_probe(unsigned int family, unsigned int model) 4033 { 4034 if (!genuine_intel) 4035 return; 4036 4037 if (family != 6) 4038 return; 4039 4040 switch (model) { 4041 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 4042 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 4043 do_gfx_perf_limit_reasons = 1; 4044 case INTEL_FAM6_HASWELL_X: /* HSX */ 4045 do_core_perf_limit_reasons = 1; 4046 do_ring_perf_limit_reasons = 1; 4047 default: 4048 return; 4049 } 4050 } 4051 4052 void automatic_cstate_conversion_probe(unsigned int family, unsigned int model) 4053 { 4054 if (is_skx(family, model) || is_bdx(family, model)) 4055 has_automatic_cstate_conversion = 1; 4056 } 4057 4058 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4059 { 4060 unsigned long long msr; 4061 unsigned int dts, dts2; 4062 int cpu; 4063 4064 if (!(do_dts || do_ptm)) 4065 return 0; 4066 4067 cpu = t->cpu_id; 4068 4069 /* DTS is per-core, no need to print for each thread */ 4070 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 4071 return 0; 4072 4073 if (cpu_migrate(cpu)) { 4074 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 4075 return -1; 4076 } 4077 4078 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { 4079 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 4080 return 0; 4081 4082 dts = (msr >> 16) & 0x7F; 4083 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", 4084 cpu, msr, tcc_activation_temp - dts); 4085 4086 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) 4087 return 0; 4088 4089 dts = (msr >> 16) & 0x7F; 4090 dts2 = (msr >> 8) & 0x7F; 4091 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 4092 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 4093 } 4094 4095 4096 if (do_dts && debug) { 4097 unsigned int resolution; 4098 4099 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 4100 return 0; 4101 4102 dts = (msr >> 16) & 0x7F; 4103 resolution = (msr >> 27) & 0xF; 4104 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", 4105 cpu, msr, tcc_activation_temp - dts, resolution); 4106 4107 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) 4108 return 0; 4109 4110 dts = (msr >> 16) & 0x7F; 4111 dts2 = (msr >> 8) & 0x7F; 4112 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 4113 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 4114 } 4115 4116 return 0; 4117 } 4118 4119 void print_power_limit_msr(int cpu, unsigned long long msr, char *label) 4120 { 4121 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n", 4122 cpu, label, 4123 ((msr >> 15) & 1) ? "EN" : "DIS", 4124 ((msr >> 0) & 0x7FFF) * rapl_power_units, 4125 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, 4126 (((msr >> 16) & 1) ? "EN" : "DIS")); 4127 4128 return; 4129 } 4130 4131 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4132 { 4133 unsigned long long msr; 4134 const char *msr_name; 4135 int cpu; 4136 4137 if (!do_rapl) 4138 return 0; 4139 4140 /* RAPL counters are per package, so print only for 1st thread/package */ 4141 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4142 return 0; 4143 4144 cpu = t->cpu_id; 4145 if (cpu_migrate(cpu)) { 4146 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 4147 return -1; 4148 } 4149 4150 if (do_rapl & RAPL_AMD_F17H) { 4151 msr_name = "MSR_RAPL_PWR_UNIT"; 4152 if (get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr)) 4153 return -1; 4154 } else { 4155 msr_name = "MSR_RAPL_POWER_UNIT"; 4156 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) 4157 return -1; 4158 } 4159 4160 fprintf(outf, "cpu%d: %s: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr_name, msr, 4161 rapl_power_units, rapl_energy_units, rapl_time_units); 4162 4163 if (do_rapl & RAPL_PKG_POWER_INFO) { 4164 4165 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) 4166 return -5; 4167 4168 4169 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4170 cpu, msr, 4171 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4172 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4173 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4174 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4175 4176 } 4177 if (do_rapl & RAPL_PKG) { 4178 4179 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) 4180 return -9; 4181 4182 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", 4183 cpu, msr, (msr >> 63) & 1 ? "" : "UN"); 4184 4185 print_power_limit_msr(cpu, msr, "PKG Limit #1"); 4186 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n", 4187 cpu, 4188 ((msr >> 47) & 1) ? "EN" : "DIS", 4189 ((msr >> 32) & 0x7FFF) * rapl_power_units, 4190 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, 4191 ((msr >> 48) & 1) ? "EN" : "DIS"); 4192 } 4193 4194 if (do_rapl & RAPL_DRAM_POWER_INFO) { 4195 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) 4196 return -6; 4197 4198 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4199 cpu, msr, 4200 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4201 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4202 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4203 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4204 } 4205 if (do_rapl & RAPL_DRAM) { 4206 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) 4207 return -9; 4208 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", 4209 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4210 4211 print_power_limit_msr(cpu, msr, "DRAM Limit"); 4212 } 4213 if (do_rapl & RAPL_CORE_POLICY) { 4214 if (get_msr(cpu, MSR_PP0_POLICY, &msr)) 4215 return -7; 4216 4217 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); 4218 } 4219 if (do_rapl & RAPL_CORES_POWER_LIMIT) { 4220 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) 4221 return -9; 4222 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", 4223 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4224 print_power_limit_msr(cpu, msr, "Cores Limit"); 4225 } 4226 if (do_rapl & RAPL_GFX) { 4227 if (get_msr(cpu, MSR_PP1_POLICY, &msr)) 4228 return -8; 4229 4230 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); 4231 4232 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) 4233 return -9; 4234 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", 4235 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4236 print_power_limit_msr(cpu, msr, "GFX Limit"); 4237 } 4238 return 0; 4239 } 4240 4241 /* 4242 * SNB adds support for additional MSRs: 4243 * 4244 * MSR_PKG_C7_RESIDENCY 0x000003fa 4245 * MSR_CORE_C7_RESIDENCY 0x000003fe 4246 * MSR_PKG_C2_RESIDENCY 0x0000060d 4247 */ 4248 4249 int has_snb_msrs(unsigned int family, unsigned int model) 4250 { 4251 if (!genuine_intel) 4252 return 0; 4253 4254 switch (model) { 4255 case INTEL_FAM6_SANDYBRIDGE: 4256 case INTEL_FAM6_SANDYBRIDGE_X: 4257 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 4258 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 4259 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 4260 case INTEL_FAM6_HASWELL_X: /* HSW */ 4261 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 4262 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 4263 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 4264 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4265 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4266 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 4267 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4268 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4269 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4270 case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */ 4271 return 1; 4272 } 4273 return 0; 4274 } 4275 4276 /* 4277 * HSW adds support for additional MSRs: 4278 * 4279 * MSR_PKG_C8_RESIDENCY 0x00000630 4280 * MSR_PKG_C9_RESIDENCY 0x00000631 4281 * MSR_PKG_C10_RESIDENCY 0x00000632 4282 * 4283 * MSR_PKGC8_IRTL 0x00000633 4284 * MSR_PKGC9_IRTL 0x00000634 4285 * MSR_PKGC10_IRTL 0x00000635 4286 * 4287 */ 4288 int has_hsw_msrs(unsigned int family, unsigned int model) 4289 { 4290 if (!genuine_intel) 4291 return 0; 4292 4293 switch (model) { 4294 case INTEL_FAM6_HASWELL_CORE: 4295 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 4296 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4297 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 4298 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4299 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4300 return 1; 4301 } 4302 return 0; 4303 } 4304 4305 /* 4306 * SKL adds support for additional MSRS: 4307 * 4308 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 4309 * MSR_PKG_ANY_CORE_C0_RES 0x00000659 4310 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 4311 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 4312 */ 4313 int has_skl_msrs(unsigned int family, unsigned int model) 4314 { 4315 if (!genuine_intel) 4316 return 0; 4317 4318 switch (model) { 4319 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4320 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 4321 return 1; 4322 } 4323 return 0; 4324 } 4325 4326 int is_slm(unsigned int family, unsigned int model) 4327 { 4328 if (!genuine_intel) 4329 return 0; 4330 switch (model) { 4331 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */ 4332 case INTEL_FAM6_ATOM_SILVERMONT_X: /* AVN */ 4333 return 1; 4334 } 4335 return 0; 4336 } 4337 4338 int is_knl(unsigned int family, unsigned int model) 4339 { 4340 if (!genuine_intel) 4341 return 0; 4342 switch (model) { 4343 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4344 return 1; 4345 } 4346 return 0; 4347 } 4348 4349 int is_cnl(unsigned int family, unsigned int model) 4350 { 4351 if (!genuine_intel) 4352 return 0; 4353 4354 switch (model) { 4355 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 4356 return 1; 4357 } 4358 4359 return 0; 4360 } 4361 4362 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model) 4363 { 4364 if (is_knl(family, model)) 4365 return 1024; 4366 return 1; 4367 } 4368 4369 #define SLM_BCLK_FREQS 5 4370 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0}; 4371 4372 double slm_bclk(void) 4373 { 4374 unsigned long long msr = 3; 4375 unsigned int i; 4376 double freq; 4377 4378 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) 4379 fprintf(outf, "SLM BCLK: unknown\n"); 4380 4381 i = msr & 0xf; 4382 if (i >= SLM_BCLK_FREQS) { 4383 fprintf(outf, "SLM BCLK[%d] invalid\n", i); 4384 i = 3; 4385 } 4386 freq = slm_freq_table[i]; 4387 4388 if (!quiet) 4389 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); 4390 4391 return freq; 4392 } 4393 4394 double discover_bclk(unsigned int family, unsigned int model) 4395 { 4396 if (has_snb_msrs(family, model) || is_knl(family, model)) 4397 return 100.00; 4398 else if (is_slm(family, model)) 4399 return slm_bclk(); 4400 else 4401 return 133.33; 4402 } 4403 4404 /* 4405 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where 4406 * the Thermal Control Circuit (TCC) activates. 4407 * This is usually equal to tjMax. 4408 * 4409 * Older processors do not have this MSR, so there we guess, 4410 * but also allow cmdline over-ride with -T. 4411 * 4412 * Several MSR temperature values are in units of degrees-C 4413 * below this value, including the Digital Thermal Sensor (DTS), 4414 * Package Thermal Management Sensor (PTM), and thermal event thresholds. 4415 */ 4416 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4417 { 4418 unsigned long long msr; 4419 unsigned int target_c_local; 4420 int cpu; 4421 4422 /* tcc_activation_temp is used only for dts or ptm */ 4423 if (!(do_dts || do_ptm)) 4424 return 0; 4425 4426 /* this is a per-package concept */ 4427 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4428 return 0; 4429 4430 cpu = t->cpu_id; 4431 if (cpu_migrate(cpu)) { 4432 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 4433 return -1; 4434 } 4435 4436 if (tcc_activation_temp_override != 0) { 4437 tcc_activation_temp = tcc_activation_temp_override; 4438 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", 4439 cpu, tcc_activation_temp); 4440 return 0; 4441 } 4442 4443 /* Temperature Target MSR is Nehalem and newer only */ 4444 if (!do_nhm_platform_info) 4445 goto guess; 4446 4447 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) 4448 goto guess; 4449 4450 target_c_local = (msr >> 16) & 0xFF; 4451 4452 if (!quiet) 4453 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", 4454 cpu, msr, target_c_local); 4455 4456 if (!target_c_local) 4457 goto guess; 4458 4459 tcc_activation_temp = target_c_local; 4460 4461 return 0; 4462 4463 guess: 4464 tcc_activation_temp = TJMAX_DEFAULT; 4465 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", 4466 cpu, tcc_activation_temp); 4467 4468 return 0; 4469 } 4470 4471 void decode_feature_control_msr(void) 4472 { 4473 unsigned long long msr; 4474 4475 if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr)) 4476 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", 4477 base_cpu, msr, 4478 msr & FEATURE_CONTROL_LOCKED ? "" : "UN-", 4479 msr & (1 << 18) ? "SGX" : ""); 4480 } 4481 4482 void decode_misc_enable_msr(void) 4483 { 4484 unsigned long long msr; 4485 4486 if (!genuine_intel) 4487 return; 4488 4489 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) 4490 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n", 4491 base_cpu, msr, 4492 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-", 4493 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-", 4494 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-", 4495 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "", 4496 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : ""); 4497 } 4498 4499 void decode_misc_feature_control(void) 4500 { 4501 unsigned long long msr; 4502 4503 if (!has_misc_feature_control) 4504 return; 4505 4506 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr)) 4507 fprintf(outf, "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n", 4508 base_cpu, msr, 4509 msr & (0 << 0) ? "No-" : "", 4510 msr & (1 << 0) ? "No-" : "", 4511 msr & (2 << 0) ? "No-" : "", 4512 msr & (3 << 0) ? "No-" : ""); 4513 } 4514 /* 4515 * Decode MSR_MISC_PWR_MGMT 4516 * 4517 * Decode the bits according to the Nehalem documentation 4518 * bit[0] seems to continue to have same meaning going forward 4519 * bit[1] less so... 4520 */ 4521 void decode_misc_pwr_mgmt_msr(void) 4522 { 4523 unsigned long long msr; 4524 4525 if (!do_nhm_platform_info) 4526 return; 4527 4528 if (no_MSR_MISC_PWR_MGMT) 4529 return; 4530 4531 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) 4532 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n", 4533 base_cpu, msr, 4534 msr & (1 << 0) ? "DIS" : "EN", 4535 msr & (1 << 1) ? "EN" : "DIS", 4536 msr & (1 << 8) ? "EN" : "DIS"); 4537 } 4538 /* 4539 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG 4540 * 4541 * This MSRs are present on Silvermont processors, 4542 * Intel Atom processor E3000 series (Baytrail), and friends. 4543 */ 4544 void decode_c6_demotion_policy_msr(void) 4545 { 4546 unsigned long long msr; 4547 4548 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr)) 4549 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n", 4550 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 4551 4552 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr)) 4553 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n", 4554 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 4555 } 4556 4557 /* 4558 * When models are the same, for the purpose of turbostat, reuse 4559 */ 4560 unsigned int intel_model_duplicates(unsigned int model) 4561 { 4562 4563 switch(model) { 4564 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ 4565 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 4566 case 0x1F: /* Core i7 and i5 Processor - Nehalem */ 4567 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */ 4568 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */ 4569 return INTEL_FAM6_NEHALEM; 4570 4571 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 4572 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 4573 return INTEL_FAM6_NEHALEM_EX; 4574 4575 case INTEL_FAM6_XEON_PHI_KNM: 4576 return INTEL_FAM6_XEON_PHI_KNL; 4577 4578 case INTEL_FAM6_HASWELL_ULT: 4579 return INTEL_FAM6_HASWELL_CORE; 4580 4581 case INTEL_FAM6_BROADWELL_X: 4582 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 4583 return INTEL_FAM6_BROADWELL_X; 4584 4585 case INTEL_FAM6_SKYLAKE_MOBILE: 4586 case INTEL_FAM6_SKYLAKE_DESKTOP: 4587 case INTEL_FAM6_KABYLAKE_MOBILE: 4588 case INTEL_FAM6_KABYLAKE_DESKTOP: 4589 return INTEL_FAM6_SKYLAKE_MOBILE; 4590 4591 case INTEL_FAM6_ICELAKE_MOBILE: 4592 return INTEL_FAM6_CANNONLAKE_MOBILE; 4593 } 4594 return model; 4595 } 4596 void process_cpuid() 4597 { 4598 unsigned int eax, ebx, ecx, edx; 4599 unsigned int fms, family, model, stepping, ecx_flags, edx_flags; 4600 unsigned int has_turbo; 4601 4602 eax = ebx = ecx = edx = 0; 4603 4604 __cpuid(0, max_level, ebx, ecx, edx); 4605 4606 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69) 4607 genuine_intel = 1; 4608 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) 4609 authentic_amd = 1; 4610 4611 if (!quiet) 4612 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ", 4613 (char *)&ebx, (char *)&edx, (char *)&ecx); 4614 4615 __cpuid(1, fms, ebx, ecx, edx); 4616 family = (fms >> 8) & 0xf; 4617 model = (fms >> 4) & 0xf; 4618 stepping = fms & 0xf; 4619 if (family == 0xf) 4620 family += (fms >> 20) & 0xff; 4621 if (family >= 6) 4622 model += ((fms >> 16) & 0xf) << 4; 4623 ecx_flags = ecx; 4624 edx_flags = edx; 4625 4626 /* 4627 * check max extended function levels of CPUID. 4628 * This is needed to check for invariant TSC. 4629 * This check is valid for both Intel and AMD. 4630 */ 4631 ebx = ecx = edx = 0; 4632 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); 4633 4634 if (!quiet) { 4635 fprintf(outf, "0x%x CPUID levels; 0x%x xlevels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n", 4636 max_level, max_extended_level, family, model, stepping, family, model, stepping); 4637 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n", 4638 ecx_flags & (1 << 0) ? "SSE3" : "-", 4639 ecx_flags & (1 << 3) ? "MONITOR" : "-", 4640 ecx_flags & (1 << 6) ? "SMX" : "-", 4641 ecx_flags & (1 << 7) ? "EIST" : "-", 4642 ecx_flags & (1 << 8) ? "TM2" : "-", 4643 edx_flags & (1 << 4) ? "TSC" : "-", 4644 edx_flags & (1 << 5) ? "MSR" : "-", 4645 edx_flags & (1 << 22) ? "ACPI-TM" : "-", 4646 edx_flags & (1 << 28) ? "HT" : "-", 4647 edx_flags & (1 << 29) ? "TM" : "-"); 4648 } 4649 if (genuine_intel) 4650 model = intel_model_duplicates(model); 4651 4652 if (!(edx_flags & (1 << 5))) 4653 errx(1, "CPUID: no MSR"); 4654 4655 if (max_extended_level >= 0x80000007) { 4656 4657 /* 4658 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 4659 * this check is valid for both Intel and AMD 4660 */ 4661 __cpuid(0x80000007, eax, ebx, ecx, edx); 4662 has_invariant_tsc = edx & (1 << 8); 4663 } 4664 4665 /* 4666 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 4667 * this check is valid for both Intel and AMD 4668 */ 4669 4670 __cpuid(0x6, eax, ebx, ecx, edx); 4671 has_aperf = ecx & (1 << 0); 4672 if (has_aperf) { 4673 BIC_PRESENT(BIC_Avg_MHz); 4674 BIC_PRESENT(BIC_Busy); 4675 BIC_PRESENT(BIC_Bzy_MHz); 4676 } 4677 do_dts = eax & (1 << 0); 4678 if (do_dts) 4679 BIC_PRESENT(BIC_CoreTmp); 4680 has_turbo = eax & (1 << 1); 4681 do_ptm = eax & (1 << 6); 4682 if (do_ptm) 4683 BIC_PRESENT(BIC_PkgTmp); 4684 has_hwp = eax & (1 << 7); 4685 has_hwp_notify = eax & (1 << 8); 4686 has_hwp_activity_window = eax & (1 << 9); 4687 has_hwp_epp = eax & (1 << 10); 4688 has_hwp_pkg = eax & (1 << 11); 4689 has_epb = ecx & (1 << 3); 4690 4691 if (!quiet) 4692 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, " 4693 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", 4694 has_aperf ? "" : "No-", 4695 has_turbo ? "" : "No-", 4696 do_dts ? "" : "No-", 4697 do_ptm ? "" : "No-", 4698 has_hwp ? "" : "No-", 4699 has_hwp_notify ? "" : "No-", 4700 has_hwp_activity_window ? "" : "No-", 4701 has_hwp_epp ? "" : "No-", 4702 has_hwp_pkg ? "" : "No-", 4703 has_epb ? "" : "No-"); 4704 4705 if (!quiet) 4706 decode_misc_enable_msr(); 4707 4708 4709 if (max_level >= 0x7 && !quiet) { 4710 int has_sgx; 4711 4712 ecx = 0; 4713 4714 __cpuid_count(0x7, 0, eax, ebx, ecx, edx); 4715 4716 has_sgx = ebx & (1 << 2); 4717 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-"); 4718 4719 if (has_sgx) 4720 decode_feature_control_msr(); 4721 } 4722 4723 if (max_level >= 0x15) { 4724 unsigned int eax_crystal; 4725 unsigned int ebx_tsc; 4726 4727 /* 4728 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz 4729 */ 4730 eax_crystal = ebx_tsc = crystal_hz = edx = 0; 4731 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); 4732 4733 if (ebx_tsc != 0) { 4734 4735 if (!quiet && (ebx != 0)) 4736 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", 4737 eax_crystal, ebx_tsc, crystal_hz); 4738 4739 if (crystal_hz == 0) 4740 switch(model) { 4741 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4742 crystal_hz = 24000000; /* 24.0 MHz */ 4743 break; 4744 case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */ 4745 crystal_hz = 25000000; /* 25.0 MHz */ 4746 break; 4747 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4748 case INTEL_FAM6_ATOM_GOLDMONT_PLUS: 4749 crystal_hz = 19200000; /* 19.2 MHz */ 4750 break; 4751 default: 4752 crystal_hz = 0; 4753 } 4754 4755 if (crystal_hz) { 4756 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal; 4757 if (!quiet) 4758 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", 4759 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); 4760 } 4761 } 4762 } 4763 if (max_level >= 0x16) { 4764 unsigned int base_mhz, max_mhz, bus_mhz, edx; 4765 4766 /* 4767 * CPUID 16H Base MHz, Max MHz, Bus MHz 4768 */ 4769 base_mhz = max_mhz = bus_mhz = edx = 0; 4770 4771 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); 4772 if (!quiet) 4773 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", 4774 base_mhz, max_mhz, bus_mhz); 4775 } 4776 4777 if (has_aperf) 4778 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model); 4779 4780 BIC_PRESENT(BIC_IRQ); 4781 BIC_PRESENT(BIC_TSC_MHz); 4782 4783 if (probe_nhm_msrs(family, model)) { 4784 do_nhm_platform_info = 1; 4785 BIC_PRESENT(BIC_CPU_c1); 4786 BIC_PRESENT(BIC_CPU_c3); 4787 BIC_PRESENT(BIC_CPU_c6); 4788 BIC_PRESENT(BIC_SMI); 4789 } 4790 do_snb_cstates = has_snb_msrs(family, model); 4791 4792 if (do_snb_cstates) 4793 BIC_PRESENT(BIC_CPU_c7); 4794 4795 do_irtl_snb = has_snb_msrs(family, model); 4796 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2)) 4797 BIC_PRESENT(BIC_Pkgpc2); 4798 if (pkg_cstate_limit >= PCL__3) 4799 BIC_PRESENT(BIC_Pkgpc3); 4800 if (pkg_cstate_limit >= PCL__6) 4801 BIC_PRESENT(BIC_Pkgpc6); 4802 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7)) 4803 BIC_PRESENT(BIC_Pkgpc7); 4804 if (has_slv_msrs(family, model)) { 4805 BIC_NOT_PRESENT(BIC_Pkgpc2); 4806 BIC_NOT_PRESENT(BIC_Pkgpc3); 4807 BIC_PRESENT(BIC_Pkgpc6); 4808 BIC_NOT_PRESENT(BIC_Pkgpc7); 4809 BIC_PRESENT(BIC_Mod_c6); 4810 use_c1_residency_msr = 1; 4811 } 4812 if (is_dnv(family, model)) { 4813 BIC_PRESENT(BIC_CPU_c1); 4814 BIC_NOT_PRESENT(BIC_CPU_c3); 4815 BIC_NOT_PRESENT(BIC_Pkgpc3); 4816 BIC_NOT_PRESENT(BIC_CPU_c7); 4817 BIC_NOT_PRESENT(BIC_Pkgpc7); 4818 use_c1_residency_msr = 1; 4819 } 4820 if (is_skx(family, model)) { 4821 BIC_NOT_PRESENT(BIC_CPU_c3); 4822 BIC_NOT_PRESENT(BIC_Pkgpc3); 4823 BIC_NOT_PRESENT(BIC_CPU_c7); 4824 BIC_NOT_PRESENT(BIC_Pkgpc7); 4825 } 4826 if (is_bdx(family, model)) { 4827 BIC_NOT_PRESENT(BIC_CPU_c7); 4828 BIC_NOT_PRESENT(BIC_Pkgpc7); 4829 } 4830 if (has_hsw_msrs(family, model)) { 4831 BIC_PRESENT(BIC_Pkgpc8); 4832 BIC_PRESENT(BIC_Pkgpc9); 4833 BIC_PRESENT(BIC_Pkgpc10); 4834 } 4835 do_irtl_hsw = has_hsw_msrs(family, model); 4836 if (has_skl_msrs(family, model)) { 4837 BIC_PRESENT(BIC_Totl_c0); 4838 BIC_PRESENT(BIC_Any_c0); 4839 BIC_PRESENT(BIC_GFX_c0); 4840 BIC_PRESENT(BIC_CPUGFX); 4841 } 4842 do_slm_cstates = is_slm(family, model); 4843 do_knl_cstates = is_knl(family, model); 4844 4845 if (do_slm_cstates || do_knl_cstates || is_cnl(family, model)) 4846 BIC_NOT_PRESENT(BIC_CPU_c3); 4847 4848 if (!quiet) 4849 decode_misc_pwr_mgmt_msr(); 4850 4851 if (!quiet && has_slv_msrs(family, model)) 4852 decode_c6_demotion_policy_msr(); 4853 4854 rapl_probe(family, model); 4855 perf_limit_reasons_probe(family, model); 4856 automatic_cstate_conversion_probe(family, model); 4857 4858 if (!quiet) 4859 dump_cstate_pstate_config_info(family, model); 4860 4861 if (!quiet) 4862 dump_sysfs_cstate_config(); 4863 if (!quiet) 4864 dump_sysfs_pstate_config(); 4865 4866 if (has_skl_msrs(family, model)) 4867 calculate_tsc_tweak(); 4868 4869 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK)) 4870 BIC_PRESENT(BIC_GFX_rc6); 4871 4872 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK)) 4873 BIC_PRESENT(BIC_GFXMHz); 4874 4875 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK)) 4876 BIC_PRESENT(BIC_CPU_LPI); 4877 else 4878 BIC_NOT_PRESENT(BIC_CPU_LPI); 4879 4880 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us", R_OK)) 4881 BIC_PRESENT(BIC_SYS_LPI); 4882 else 4883 BIC_NOT_PRESENT(BIC_SYS_LPI); 4884 4885 if (!quiet) 4886 decode_misc_feature_control(); 4887 4888 return; 4889 } 4890 4891 /* 4892 * in /dev/cpu/ return success for names that are numbers 4893 * ie. filter out ".", "..", "microcode". 4894 */ 4895 int dir_filter(const struct dirent *dirp) 4896 { 4897 if (isdigit(dirp->d_name[0])) 4898 return 1; 4899 else 4900 return 0; 4901 } 4902 4903 int open_dev_cpu_msr(int dummy1) 4904 { 4905 return 0; 4906 } 4907 4908 void topology_probe() 4909 { 4910 int i; 4911 int max_core_id = 0; 4912 int max_package_id = 0; 4913 int max_die_id = 0; 4914 int max_siblings = 0; 4915 4916 /* Initialize num_cpus, max_cpu_num */ 4917 set_max_cpu_num(); 4918 topo.num_cpus = 0; 4919 for_all_proc_cpus(count_cpus); 4920 if (!summary_only && topo.num_cpus > 1) 4921 BIC_PRESENT(BIC_CPU); 4922 4923 if (debug > 1) 4924 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); 4925 4926 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); 4927 if (cpus == NULL) 4928 err(1, "calloc cpus"); 4929 4930 /* 4931 * Allocate and initialize cpu_present_set 4932 */ 4933 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); 4934 if (cpu_present_set == NULL) 4935 err(3, "CPU_ALLOC"); 4936 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 4937 CPU_ZERO_S(cpu_present_setsize, cpu_present_set); 4938 for_all_proc_cpus(mark_cpu_present); 4939 4940 /* 4941 * Validate that all cpus in cpu_subset are also in cpu_present_set 4942 */ 4943 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) { 4944 if (CPU_ISSET_S(i, cpu_subset_size, cpu_subset)) 4945 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set)) 4946 err(1, "cpu%d not present", i); 4947 } 4948 4949 /* 4950 * Allocate and initialize cpu_affinity_set 4951 */ 4952 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); 4953 if (cpu_affinity_set == NULL) 4954 err(3, "CPU_ALLOC"); 4955 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 4956 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 4957 4958 for_all_proc_cpus(init_thread_id); 4959 4960 /* 4961 * For online cpus 4962 * find max_core_id, max_package_id 4963 */ 4964 for (i = 0; i <= topo.max_cpu_num; ++i) { 4965 int siblings; 4966 4967 if (cpu_is_not_present(i)) { 4968 if (debug > 1) 4969 fprintf(outf, "cpu%d NOT PRESENT\n", i); 4970 continue; 4971 } 4972 4973 cpus[i].logical_cpu_id = i; 4974 4975 /* get package information */ 4976 cpus[i].physical_package_id = get_physical_package_id(i); 4977 if (cpus[i].physical_package_id > max_package_id) 4978 max_package_id = cpus[i].physical_package_id; 4979 4980 /* get die information */ 4981 cpus[i].die_id = get_die_id(i); 4982 if (cpus[i].die_id > max_die_id) 4983 max_die_id = cpus[i].die_id; 4984 4985 /* get numa node information */ 4986 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]); 4987 if (cpus[i].physical_node_id > topo.max_node_num) 4988 topo.max_node_num = cpus[i].physical_node_id; 4989 4990 /* get core information */ 4991 cpus[i].physical_core_id = get_core_id(i); 4992 if (cpus[i].physical_core_id > max_core_id) 4993 max_core_id = cpus[i].physical_core_id; 4994 4995 /* get thread information */ 4996 siblings = get_thread_siblings(&cpus[i]); 4997 if (siblings > max_siblings) 4998 max_siblings = siblings; 4999 if (cpus[i].thread_id == 0) 5000 topo.num_cores++; 5001 } 5002 5003 topo.cores_per_node = max_core_id + 1; 5004 if (debug > 1) 5005 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", 5006 max_core_id, topo.cores_per_node); 5007 if (!summary_only && topo.cores_per_node > 1) 5008 BIC_PRESENT(BIC_Core); 5009 5010 topo.num_die = max_die_id + 1; 5011 if (debug > 1) 5012 fprintf(outf, "max_die_id %d, sizing for %d die\n", 5013 max_die_id, topo.num_die); 5014 if (!summary_only && topo.num_die > 1) 5015 BIC_PRESENT(BIC_Die); 5016 5017 topo.num_packages = max_package_id + 1; 5018 if (debug > 1) 5019 fprintf(outf, "max_package_id %d, sizing for %d packages\n", 5020 max_package_id, topo.num_packages); 5021 if (!summary_only && topo.num_packages > 1) 5022 BIC_PRESENT(BIC_Package); 5023 5024 set_node_data(); 5025 if (debug > 1) 5026 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg); 5027 if (!summary_only && topo.nodes_per_pkg > 1) 5028 BIC_PRESENT(BIC_Node); 5029 5030 topo.threads_per_core = max_siblings; 5031 if (debug > 1) 5032 fprintf(outf, "max_siblings %d\n", max_siblings); 5033 5034 if (debug < 1) 5035 return; 5036 5037 for (i = 0; i <= topo.max_cpu_num; ++i) { 5038 if (cpu_is_not_present(i)) 5039 continue; 5040 fprintf(outf, 5041 "cpu %d pkg %d die %d node %d lnode %d core %d thread %d\n", 5042 i, cpus[i].physical_package_id, cpus[i].die_id, 5043 cpus[i].physical_node_id, 5044 cpus[i].logical_node_id, 5045 cpus[i].physical_core_id, 5046 cpus[i].thread_id); 5047 } 5048 5049 } 5050 5051 void 5052 allocate_counters(struct thread_data **t, struct core_data **c, 5053 struct pkg_data **p) 5054 { 5055 int i; 5056 int num_cores = topo.cores_per_node * topo.nodes_per_pkg * 5057 topo.num_packages; 5058 int num_threads = topo.threads_per_core * num_cores; 5059 5060 *t = calloc(num_threads, sizeof(struct thread_data)); 5061 if (*t == NULL) 5062 goto error; 5063 5064 for (i = 0; i < num_threads; i++) 5065 (*t)[i].cpu_id = -1; 5066 5067 *c = calloc(num_cores, sizeof(struct core_data)); 5068 if (*c == NULL) 5069 goto error; 5070 5071 for (i = 0; i < num_cores; i++) 5072 (*c)[i].core_id = -1; 5073 5074 *p = calloc(topo.num_packages, sizeof(struct pkg_data)); 5075 if (*p == NULL) 5076 goto error; 5077 5078 for (i = 0; i < topo.num_packages; i++) 5079 (*p)[i].package_id = i; 5080 5081 return; 5082 error: 5083 err(1, "calloc counters"); 5084 } 5085 /* 5086 * init_counter() 5087 * 5088 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE 5089 */ 5090 void init_counter(struct thread_data *thread_base, struct core_data *core_base, 5091 struct pkg_data *pkg_base, int cpu_id) 5092 { 5093 int pkg_id = cpus[cpu_id].physical_package_id; 5094 int node_id = cpus[cpu_id].logical_node_id; 5095 int core_id = cpus[cpu_id].physical_core_id; 5096 int thread_id = cpus[cpu_id].thread_id; 5097 struct thread_data *t; 5098 struct core_data *c; 5099 struct pkg_data *p; 5100 5101 5102 /* Workaround for systems where physical_node_id==-1 5103 * and logical_node_id==(-1 - topo.num_cpus) 5104 */ 5105 if (node_id < 0) 5106 node_id = 0; 5107 5108 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id); 5109 c = GET_CORE(core_base, core_id, node_id, pkg_id); 5110 p = GET_PKG(pkg_base, pkg_id); 5111 5112 t->cpu_id = cpu_id; 5113 if (thread_id == 0) { 5114 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; 5115 if (cpu_is_first_core_in_package(cpu_id)) 5116 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; 5117 } 5118 5119 c->core_id = core_id; 5120 p->package_id = pkg_id; 5121 } 5122 5123 5124 int initialize_counters(int cpu_id) 5125 { 5126 init_counter(EVEN_COUNTERS, cpu_id); 5127 init_counter(ODD_COUNTERS, cpu_id); 5128 return 0; 5129 } 5130 5131 void allocate_output_buffer() 5132 { 5133 output_buffer = calloc(1, (1 + topo.num_cpus) * 1024); 5134 outp = output_buffer; 5135 if (outp == NULL) 5136 err(-1, "calloc output buffer"); 5137 } 5138 void allocate_fd_percpu(void) 5139 { 5140 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 5141 if (fd_percpu == NULL) 5142 err(-1, "calloc fd_percpu"); 5143 } 5144 void allocate_irq_buffers(void) 5145 { 5146 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); 5147 if (irq_column_2_cpu == NULL) 5148 err(-1, "calloc %d", topo.num_cpus); 5149 5150 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 5151 if (irqs_per_cpu == NULL) 5152 err(-1, "calloc %d", topo.max_cpu_num + 1); 5153 } 5154 void setup_all_buffers(void) 5155 { 5156 topology_probe(); 5157 allocate_irq_buffers(); 5158 allocate_fd_percpu(); 5159 allocate_counters(&thread_even, &core_even, &package_even); 5160 allocate_counters(&thread_odd, &core_odd, &package_odd); 5161 allocate_output_buffer(); 5162 for_all_proc_cpus(initialize_counters); 5163 } 5164 5165 void set_base_cpu(void) 5166 { 5167 base_cpu = sched_getcpu(); 5168 if (base_cpu < 0) 5169 err(-ENODEV, "No valid cpus found"); 5170 5171 if (debug > 1) 5172 fprintf(outf, "base_cpu = %d\n", base_cpu); 5173 } 5174 5175 void turbostat_init() 5176 { 5177 setup_all_buffers(); 5178 set_base_cpu(); 5179 check_dev_msr(); 5180 check_permissions(); 5181 process_cpuid(); 5182 5183 5184 if (!quiet) 5185 for_all_cpus(print_hwp, ODD_COUNTERS); 5186 5187 if (!quiet) 5188 for_all_cpus(print_epb, ODD_COUNTERS); 5189 5190 if (!quiet) 5191 for_all_cpus(print_perf_limit, ODD_COUNTERS); 5192 5193 if (!quiet) 5194 for_all_cpus(print_rapl, ODD_COUNTERS); 5195 5196 for_all_cpus(set_temperature_target, ODD_COUNTERS); 5197 5198 if (!quiet) 5199 for_all_cpus(print_thermal, ODD_COUNTERS); 5200 5201 if (!quiet && do_irtl_snb) 5202 print_irtl(); 5203 } 5204 5205 int fork_it(char **argv) 5206 { 5207 pid_t child_pid; 5208 int status; 5209 5210 snapshot_proc_sysfs_files(); 5211 status = for_all_cpus(get_counters, EVEN_COUNTERS); 5212 first_counter_read = 0; 5213 if (status) 5214 exit(status); 5215 /* clear affinity side-effect of get_counters() */ 5216 sched_setaffinity(0, cpu_present_setsize, cpu_present_set); 5217 gettimeofday(&tv_even, (struct timezone *)NULL); 5218 5219 child_pid = fork(); 5220 if (!child_pid) { 5221 /* child */ 5222 execvp(argv[0], argv); 5223 err(errno, "exec %s", argv[0]); 5224 } else { 5225 5226 /* parent */ 5227 if (child_pid == -1) 5228 err(1, "fork"); 5229 5230 signal(SIGINT, SIG_IGN); 5231 signal(SIGQUIT, SIG_IGN); 5232 if (waitpid(child_pid, &status, 0) == -1) 5233 err(status, "waitpid"); 5234 } 5235 /* 5236 * n.b. fork_it() does not check for errors from for_all_cpus() 5237 * because re-starting is problematic when forking 5238 */ 5239 snapshot_proc_sysfs_files(); 5240 for_all_cpus(get_counters, ODD_COUNTERS); 5241 gettimeofday(&tv_odd, (struct timezone *)NULL); 5242 timersub(&tv_odd, &tv_even, &tv_delta); 5243 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) 5244 fprintf(outf, "%s: Counter reset detected\n", progname); 5245 else { 5246 compute_average(EVEN_COUNTERS); 5247 format_all_counters(EVEN_COUNTERS); 5248 } 5249 5250 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0); 5251 5252 flush_output_stderr(); 5253 5254 return status; 5255 } 5256 5257 int get_and_dump_counters(void) 5258 { 5259 int status; 5260 5261 snapshot_proc_sysfs_files(); 5262 status = for_all_cpus(get_counters, ODD_COUNTERS); 5263 if (status) 5264 return status; 5265 5266 status = for_all_cpus(dump_counters, ODD_COUNTERS); 5267 if (status) 5268 return status; 5269 5270 flush_output_stdout(); 5271 5272 return status; 5273 } 5274 5275 void print_version() { 5276 fprintf(outf, "turbostat version 18.07.27" 5277 " - Len Brown <lenb@kernel.org>\n"); 5278 } 5279 5280 int add_counter(unsigned int msr_num, char *path, char *name, 5281 unsigned int width, enum counter_scope scope, 5282 enum counter_type type, enum counter_format format, int flags) 5283 { 5284 struct msr_counter *msrp; 5285 5286 msrp = calloc(1, sizeof(struct msr_counter)); 5287 if (msrp == NULL) { 5288 perror("calloc"); 5289 exit(1); 5290 } 5291 5292 msrp->msr_num = msr_num; 5293 strncpy(msrp->name, name, NAME_BYTES); 5294 if (path) 5295 strncpy(msrp->path, path, PATH_BYTES); 5296 msrp->width = width; 5297 msrp->type = type; 5298 msrp->format = format; 5299 msrp->flags = flags; 5300 5301 switch (scope) { 5302 5303 case SCOPE_CPU: 5304 msrp->next = sys.tp; 5305 sys.tp = msrp; 5306 sys.added_thread_counters++; 5307 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) { 5308 fprintf(stderr, "exceeded max %d added thread counters\n", 5309 MAX_ADDED_COUNTERS); 5310 exit(-1); 5311 } 5312 break; 5313 5314 case SCOPE_CORE: 5315 msrp->next = sys.cp; 5316 sys.cp = msrp; 5317 sys.added_core_counters++; 5318 if (sys.added_core_counters > MAX_ADDED_COUNTERS) { 5319 fprintf(stderr, "exceeded max %d added core counters\n", 5320 MAX_ADDED_COUNTERS); 5321 exit(-1); 5322 } 5323 break; 5324 5325 case SCOPE_PACKAGE: 5326 msrp->next = sys.pp; 5327 sys.pp = msrp; 5328 sys.added_package_counters++; 5329 if (sys.added_package_counters > MAX_ADDED_COUNTERS) { 5330 fprintf(stderr, "exceeded max %d added package counters\n", 5331 MAX_ADDED_COUNTERS); 5332 exit(-1); 5333 } 5334 break; 5335 } 5336 5337 return 0; 5338 } 5339 5340 void parse_add_command(char *add_command) 5341 { 5342 int msr_num = 0; 5343 char *path = NULL; 5344 char name_buffer[NAME_BYTES] = ""; 5345 int width = 64; 5346 int fail = 0; 5347 enum counter_scope scope = SCOPE_CPU; 5348 enum counter_type type = COUNTER_CYCLES; 5349 enum counter_format format = FORMAT_DELTA; 5350 5351 while (add_command) { 5352 5353 if (sscanf(add_command, "msr0x%x", &msr_num) == 1) 5354 goto next; 5355 5356 if (sscanf(add_command, "msr%d", &msr_num) == 1) 5357 goto next; 5358 5359 if (*add_command == '/') { 5360 path = add_command; 5361 goto next; 5362 } 5363 5364 if (sscanf(add_command, "u%d", &width) == 1) { 5365 if ((width == 32) || (width == 64)) 5366 goto next; 5367 width = 64; 5368 } 5369 if (!strncmp(add_command, "cpu", strlen("cpu"))) { 5370 scope = SCOPE_CPU; 5371 goto next; 5372 } 5373 if (!strncmp(add_command, "core", strlen("core"))) { 5374 scope = SCOPE_CORE; 5375 goto next; 5376 } 5377 if (!strncmp(add_command, "package", strlen("package"))) { 5378 scope = SCOPE_PACKAGE; 5379 goto next; 5380 } 5381 if (!strncmp(add_command, "cycles", strlen("cycles"))) { 5382 type = COUNTER_CYCLES; 5383 goto next; 5384 } 5385 if (!strncmp(add_command, "seconds", strlen("seconds"))) { 5386 type = COUNTER_SECONDS; 5387 goto next; 5388 } 5389 if (!strncmp(add_command, "usec", strlen("usec"))) { 5390 type = COUNTER_USEC; 5391 goto next; 5392 } 5393 if (!strncmp(add_command, "raw", strlen("raw"))) { 5394 format = FORMAT_RAW; 5395 goto next; 5396 } 5397 if (!strncmp(add_command, "delta", strlen("delta"))) { 5398 format = FORMAT_DELTA; 5399 goto next; 5400 } 5401 if (!strncmp(add_command, "percent", strlen("percent"))) { 5402 format = FORMAT_PERCENT; 5403 goto next; 5404 } 5405 5406 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */ 5407 char *eos; 5408 5409 eos = strchr(name_buffer, ','); 5410 if (eos) 5411 *eos = '\0'; 5412 goto next; 5413 } 5414 5415 next: 5416 add_command = strchr(add_command, ','); 5417 if (add_command) { 5418 *add_command = '\0'; 5419 add_command++; 5420 } 5421 5422 } 5423 if ((msr_num == 0) && (path == NULL)) { 5424 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n"); 5425 fail++; 5426 } 5427 5428 /* generate default column header */ 5429 if (*name_buffer == '\0') { 5430 if (width == 32) 5431 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 5432 else 5433 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 5434 } 5435 5436 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0)) 5437 fail++; 5438 5439 if (fail) { 5440 help(); 5441 exit(1); 5442 } 5443 } 5444 5445 int is_deferred_skip(char *name) 5446 { 5447 int i; 5448 5449 for (i = 0; i < deferred_skip_index; ++i) 5450 if (!strcmp(name, deferred_skip_names[i])) 5451 return 1; 5452 return 0; 5453 } 5454 5455 void probe_sysfs(void) 5456 { 5457 char path[64]; 5458 char name_buf[16]; 5459 FILE *input; 5460 int state; 5461 char *sp; 5462 5463 if (!DO_BIC(BIC_sysfs)) 5464 return; 5465 5466 for (state = 10; state >= 0; --state) { 5467 5468 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 5469 base_cpu, state); 5470 input = fopen(path, "r"); 5471 if (input == NULL) 5472 continue; 5473 if (!fgets(name_buf, sizeof(name_buf), input)) 5474 err(1, "%s: failed to read file", path); 5475 5476 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 5477 sp = strchr(name_buf, '-'); 5478 if (!sp) 5479 sp = strchrnul(name_buf, '\n'); 5480 *sp = '%'; 5481 *(sp + 1) = '\0'; 5482 5483 fclose(input); 5484 5485 sprintf(path, "cpuidle/state%d/time", state); 5486 5487 if (is_deferred_skip(name_buf)) 5488 continue; 5489 5490 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC, 5491 FORMAT_PERCENT, SYSFS_PERCPU); 5492 } 5493 5494 for (state = 10; state >= 0; --state) { 5495 5496 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 5497 base_cpu, state); 5498 input = fopen(path, "r"); 5499 if (input == NULL) 5500 continue; 5501 if (!fgets(name_buf, sizeof(name_buf), input)) 5502 err(1, "%s: failed to read file", path); 5503 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 5504 sp = strchr(name_buf, '-'); 5505 if (!sp) 5506 sp = strchrnul(name_buf, '\n'); 5507 *sp = '\0'; 5508 fclose(input); 5509 5510 sprintf(path, "cpuidle/state%d/usage", state); 5511 5512 if (is_deferred_skip(name_buf)) 5513 continue; 5514 5515 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS, 5516 FORMAT_DELTA, SYSFS_PERCPU); 5517 } 5518 5519 } 5520 5521 5522 /* 5523 * parse cpuset with following syntax 5524 * 1,2,4..6,8-10 and set bits in cpu_subset 5525 */ 5526 void parse_cpu_command(char *optarg) 5527 { 5528 unsigned int start, end; 5529 char *next; 5530 5531 if (!strcmp(optarg, "core")) { 5532 if (cpu_subset) 5533 goto error; 5534 show_core_only++; 5535 return; 5536 } 5537 if (!strcmp(optarg, "package")) { 5538 if (cpu_subset) 5539 goto error; 5540 show_pkg_only++; 5541 return; 5542 } 5543 if (show_core_only || show_pkg_only) 5544 goto error; 5545 5546 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS); 5547 if (cpu_subset == NULL) 5548 err(3, "CPU_ALLOC"); 5549 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS); 5550 5551 CPU_ZERO_S(cpu_subset_size, cpu_subset); 5552 5553 next = optarg; 5554 5555 while (next && *next) { 5556 5557 if (*next == '-') /* no negative cpu numbers */ 5558 goto error; 5559 5560 start = strtoul(next, &next, 10); 5561 5562 if (start >= CPU_SUBSET_MAXCPUS) 5563 goto error; 5564 CPU_SET_S(start, cpu_subset_size, cpu_subset); 5565 5566 if (*next == '\0') 5567 break; 5568 5569 if (*next == ',') { 5570 next += 1; 5571 continue; 5572 } 5573 5574 if (*next == '-') { 5575 next += 1; /* start range */ 5576 } else if (*next == '.') { 5577 next += 1; 5578 if (*next == '.') 5579 next += 1; /* start range */ 5580 else 5581 goto error; 5582 } 5583 5584 end = strtoul(next, &next, 10); 5585 if (end <= start) 5586 goto error; 5587 5588 while (++start <= end) { 5589 if (start >= CPU_SUBSET_MAXCPUS) 5590 goto error; 5591 CPU_SET_S(start, cpu_subset_size, cpu_subset); 5592 } 5593 5594 if (*next == ',') 5595 next += 1; 5596 else if (*next != '\0') 5597 goto error; 5598 } 5599 5600 return; 5601 5602 error: 5603 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg); 5604 help(); 5605 exit(-1); 5606 } 5607 5608 5609 void cmdline(int argc, char **argv) 5610 { 5611 int opt; 5612 int option_index = 0; 5613 static struct option long_options[] = { 5614 {"add", required_argument, 0, 'a'}, 5615 {"cpu", required_argument, 0, 'c'}, 5616 {"Dump", no_argument, 0, 'D'}, 5617 {"debug", no_argument, 0, 'd'}, /* internal, not documented */ 5618 {"enable", required_argument, 0, 'e'}, 5619 {"interval", required_argument, 0, 'i'}, 5620 {"num_iterations", required_argument, 0, 'n'}, 5621 {"help", no_argument, 0, 'h'}, 5622 {"hide", required_argument, 0, 'H'}, // meh, -h taken by --help 5623 {"Joules", no_argument, 0, 'J'}, 5624 {"list", no_argument, 0, 'l'}, 5625 {"out", required_argument, 0, 'o'}, 5626 {"quiet", no_argument, 0, 'q'}, 5627 {"show", required_argument, 0, 's'}, 5628 {"Summary", no_argument, 0, 'S'}, 5629 {"TCC", required_argument, 0, 'T'}, 5630 {"version", no_argument, 0, 'v' }, 5631 {0, 0, 0, 0 } 5632 }; 5633 5634 progname = argv[0]; 5635 5636 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v", 5637 long_options, &option_index)) != -1) { 5638 switch (opt) { 5639 case 'a': 5640 parse_add_command(optarg); 5641 break; 5642 case 'c': 5643 parse_cpu_command(optarg); 5644 break; 5645 case 'D': 5646 dump_only++; 5647 break; 5648 case 'e': 5649 /* --enable specified counter */ 5650 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST); 5651 break; 5652 case 'd': 5653 debug++; 5654 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 5655 break; 5656 case 'H': 5657 /* 5658 * --hide: do not show those specified 5659 * multiple invocations simply clear more bits in enabled mask 5660 */ 5661 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST); 5662 break; 5663 case 'h': 5664 default: 5665 help(); 5666 exit(1); 5667 case 'i': 5668 { 5669 double interval = strtod(optarg, NULL); 5670 5671 if (interval < 0.001) { 5672 fprintf(outf, "interval %f seconds is too small\n", 5673 interval); 5674 exit(2); 5675 } 5676 5677 interval_tv.tv_sec = interval_ts.tv_sec = interval; 5678 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000; 5679 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; 5680 } 5681 break; 5682 case 'J': 5683 rapl_joules++; 5684 break; 5685 case 'l': 5686 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 5687 list_header_only++; 5688 quiet++; 5689 break; 5690 case 'o': 5691 outf = fopen_or_die(optarg, "w"); 5692 break; 5693 case 'q': 5694 quiet = 1; 5695 break; 5696 case 'n': 5697 num_iterations = strtod(optarg, NULL); 5698 5699 if (num_iterations <= 0) { 5700 fprintf(outf, "iterations %d should be positive number\n", 5701 num_iterations); 5702 exit(2); 5703 } 5704 break; 5705 case 's': 5706 /* 5707 * --show: show only those specified 5708 * The 1st invocation will clear and replace the enabled mask 5709 * subsequent invocations can add to it. 5710 */ 5711 if (shown == 0) 5712 bic_enabled = bic_lookup(optarg, SHOW_LIST); 5713 else 5714 bic_enabled |= bic_lookup(optarg, SHOW_LIST); 5715 shown = 1; 5716 break; 5717 case 'S': 5718 summary_only++; 5719 break; 5720 case 'T': 5721 tcc_activation_temp_override = atoi(optarg); 5722 break; 5723 case 'v': 5724 print_version(); 5725 exit(0); 5726 break; 5727 } 5728 } 5729 } 5730 5731 int main(int argc, char **argv) 5732 { 5733 outf = stderr; 5734 cmdline(argc, argv); 5735 5736 if (!quiet) 5737 print_version(); 5738 5739 probe_sysfs(); 5740 5741 turbostat_init(); 5742 5743 /* dump counters and exit */ 5744 if (dump_only) 5745 return get_and_dump_counters(); 5746 5747 /* list header and exit */ 5748 if (list_header_only) { 5749 print_header(","); 5750 flush_output_stdout(); 5751 return 0; 5752 } 5753 5754 /* 5755 * if any params left, it must be a command to fork 5756 */ 5757 if (argc - optind) 5758 return fork_it(argv + optind); 5759 else 5760 turbostat_loop(); 5761 5762 return 0; 5763 } 5764