1 /* 2 * turbostat -- show CPU frequency and C-state residency 3 * on modern Intel turbo-capable processors. 4 * 5 * Copyright (c) 2013 Intel Corporation. 6 * Len Brown <len.brown@intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 20 */ 21 22 #define _GNU_SOURCE 23 #include MSRHEADER 24 #include INTEL_FAMILY_HEADER 25 #include <stdarg.h> 26 #include <stdio.h> 27 #include <err.h> 28 #include <unistd.h> 29 #include <sys/types.h> 30 #include <sys/wait.h> 31 #include <sys/stat.h> 32 #include <sys/resource.h> 33 #include <fcntl.h> 34 #include <signal.h> 35 #include <sys/time.h> 36 #include <stdlib.h> 37 #include <getopt.h> 38 #include <dirent.h> 39 #include <string.h> 40 #include <ctype.h> 41 #include <sched.h> 42 #include <time.h> 43 #include <cpuid.h> 44 #include <linux/capability.h> 45 #include <errno.h> 46 47 char *proc_stat = "/proc/stat"; 48 FILE *outf; 49 int *fd_percpu; 50 struct timespec interval_ts = {5, 0}; 51 unsigned int debug; 52 unsigned int rapl_joules; 53 unsigned int summary_only; 54 unsigned int dump_only; 55 unsigned int do_nhm_cstates; 56 unsigned int do_snb_cstates; 57 unsigned int do_knl_cstates; 58 unsigned int do_pc2; 59 unsigned int do_pc3; 60 unsigned int do_pc6; 61 unsigned int do_pc7; 62 unsigned int do_c8_c9_c10; 63 unsigned int do_skl_residency; 64 unsigned int do_slm_cstates; 65 unsigned int use_c1_residency_msr; 66 unsigned int has_aperf; 67 unsigned int has_epb; 68 unsigned int do_irtl_snb; 69 unsigned int do_irtl_hsw; 70 unsigned int units = 1000000; /* MHz etc */ 71 unsigned int genuine_intel; 72 unsigned int has_invariant_tsc; 73 unsigned int do_nhm_platform_info; 74 unsigned int aperf_mperf_multiplier = 1; 75 int do_irq = 1; 76 int do_smi; 77 double bclk; 78 double base_hz; 79 unsigned int has_base_hz; 80 double tsc_tweak = 1.0; 81 unsigned int show_pkg; 82 unsigned int show_core; 83 unsigned int show_cpu; 84 unsigned int show_pkg_only; 85 unsigned int show_core_only; 86 char *output_buffer, *outp; 87 unsigned int do_rapl; 88 unsigned int do_dts; 89 unsigned int do_ptm; 90 unsigned int do_gfx_rc6_ms; 91 unsigned long long gfx_cur_rc6_ms; 92 unsigned int do_gfx_mhz; 93 unsigned int gfx_cur_mhz; 94 unsigned int tcc_activation_temp; 95 unsigned int tcc_activation_temp_override; 96 double rapl_power_units, rapl_time_units; 97 double rapl_dram_energy_units, rapl_energy_units; 98 double rapl_joule_counter_range; 99 unsigned int do_core_perf_limit_reasons; 100 unsigned int do_gfx_perf_limit_reasons; 101 unsigned int do_ring_perf_limit_reasons; 102 unsigned int crystal_hz; 103 unsigned long long tsc_hz; 104 int base_cpu; 105 double discover_bclk(unsigned int family, unsigned int model); 106 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ 107 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ 108 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ 109 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ 110 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ 111 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ 112 113 #define RAPL_PKG (1 << 0) 114 /* 0x610 MSR_PKG_POWER_LIMIT */ 115 /* 0x611 MSR_PKG_ENERGY_STATUS */ 116 #define RAPL_PKG_PERF_STATUS (1 << 1) 117 /* 0x613 MSR_PKG_PERF_STATUS */ 118 #define RAPL_PKG_POWER_INFO (1 << 2) 119 /* 0x614 MSR_PKG_POWER_INFO */ 120 121 #define RAPL_DRAM (1 << 3) 122 /* 0x618 MSR_DRAM_POWER_LIMIT */ 123 /* 0x619 MSR_DRAM_ENERGY_STATUS */ 124 #define RAPL_DRAM_PERF_STATUS (1 << 4) 125 /* 0x61b MSR_DRAM_PERF_STATUS */ 126 #define RAPL_DRAM_POWER_INFO (1 << 5) 127 /* 0x61c MSR_DRAM_POWER_INFO */ 128 129 #define RAPL_CORES_POWER_LIMIT (1 << 6) 130 /* 0x638 MSR_PP0_POWER_LIMIT */ 131 #define RAPL_CORE_POLICY (1 << 7) 132 /* 0x63a MSR_PP0_POLICY */ 133 134 #define RAPL_GFX (1 << 8) 135 /* 0x640 MSR_PP1_POWER_LIMIT */ 136 /* 0x641 MSR_PP1_ENERGY_STATUS */ 137 /* 0x642 MSR_PP1_POLICY */ 138 139 #define RAPL_CORES_ENERGY_STATUS (1 << 9) 140 /* 0x639 MSR_PP0_ENERGY_STATUS */ 141 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT) 142 #define TJMAX_DEFAULT 100 143 144 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 145 146 /* 147 * buffer size used by sscanf() for added column names 148 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters 149 */ 150 #define NAME_BYTES 20 151 152 int backwards_count; 153 char *progname; 154 155 cpu_set_t *cpu_present_set, *cpu_affinity_set; 156 size_t cpu_present_setsize, cpu_affinity_setsize; 157 #define MAX_ADDED_COUNTERS 16 158 159 struct thread_data { 160 unsigned long long tsc; 161 unsigned long long aperf; 162 unsigned long long mperf; 163 unsigned long long c1; 164 unsigned int irq_count; 165 unsigned int smi_count; 166 unsigned int cpu_id; 167 unsigned int flags; 168 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2 169 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 170 unsigned long long counter[MAX_ADDED_COUNTERS]; 171 } *thread_even, *thread_odd; 172 173 struct core_data { 174 unsigned long long c3; 175 unsigned long long c6; 176 unsigned long long c7; 177 unsigned int core_temp_c; 178 unsigned int core_id; 179 unsigned long long counter[MAX_ADDED_COUNTERS]; 180 } *core_even, *core_odd; 181 182 struct pkg_data { 183 unsigned long long pc2; 184 unsigned long long pc3; 185 unsigned long long pc6; 186 unsigned long long pc7; 187 unsigned long long pc8; 188 unsigned long long pc9; 189 unsigned long long pc10; 190 unsigned long long pkg_wtd_core_c0; 191 unsigned long long pkg_any_core_c0; 192 unsigned long long pkg_any_gfxe_c0; 193 unsigned long long pkg_both_core_gfxe_c0; 194 long long gfx_rc6_ms; 195 unsigned int gfx_mhz; 196 unsigned int package_id; 197 unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */ 198 unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */ 199 unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */ 200 unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */ 201 unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ 202 unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ 203 unsigned int pkg_temp_c; 204 unsigned long long counter[MAX_ADDED_COUNTERS]; 205 } *package_even, *package_odd; 206 207 #define ODD_COUNTERS thread_odd, core_odd, package_odd 208 #define EVEN_COUNTERS thread_even, core_even, package_even 209 210 #define GET_THREAD(thread_base, thread_no, core_no, pkg_no) \ 211 (thread_base + (pkg_no) * topo.num_cores_per_pkg * \ 212 topo.num_threads_per_core + \ 213 (core_no) * topo.num_threads_per_core + (thread_no)) 214 #define GET_CORE(core_base, core_no, pkg_no) \ 215 (core_base + (pkg_no) * topo.num_cores_per_pkg + (core_no)) 216 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) 217 218 enum counter_scope {SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE}; 219 enum counter_type {COUNTER_CYCLES, COUNTER_SECONDS}; 220 enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT}; 221 222 struct msr_counter { 223 unsigned int msr_num; 224 char name[NAME_BYTES]; 225 unsigned int width; 226 enum counter_type type; 227 enum counter_format format; 228 struct msr_counter *next; 229 }; 230 231 struct sys_counters { 232 unsigned int added_thread_counters; 233 unsigned int added_core_counters; 234 unsigned int added_package_counters; 235 struct msr_counter *tp; 236 struct msr_counter *cp; 237 struct msr_counter *pp; 238 } sys; 239 240 struct system_summary { 241 struct thread_data threads; 242 struct core_data cores; 243 struct pkg_data packages; 244 } average; 245 246 247 struct topo_params { 248 int num_packages; 249 int num_cpus; 250 int num_cores; 251 int max_cpu_num; 252 int num_cores_per_pkg; 253 int num_threads_per_core; 254 } topo; 255 256 struct timeval tv_even, tv_odd, tv_delta; 257 258 int *irq_column_2_cpu; /* /proc/interrupts column numbers */ 259 int *irqs_per_cpu; /* indexed by cpu_num */ 260 261 void setup_all_buffers(void); 262 263 int cpu_is_not_present(int cpu) 264 { 265 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); 266 } 267 /* 268 * run func(thread, core, package) in topology order 269 * skip non-present cpus 270 */ 271 272 int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *), 273 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) 274 { 275 int retval, pkg_no, core_no, thread_no; 276 277 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 278 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) { 279 for (thread_no = 0; thread_no < 280 topo.num_threads_per_core; ++thread_no) { 281 struct thread_data *t; 282 struct core_data *c; 283 struct pkg_data *p; 284 285 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no); 286 287 if (cpu_is_not_present(t->cpu_id)) 288 continue; 289 290 c = GET_CORE(core_base, core_no, pkg_no); 291 p = GET_PKG(pkg_base, pkg_no); 292 293 retval = func(t, c, p); 294 if (retval) 295 return retval; 296 } 297 } 298 } 299 return 0; 300 } 301 302 int cpu_migrate(int cpu) 303 { 304 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 305 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); 306 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) 307 return -1; 308 else 309 return 0; 310 } 311 int get_msr_fd(int cpu) 312 { 313 char pathname[32]; 314 int fd; 315 316 fd = fd_percpu[cpu]; 317 318 if (fd) 319 return fd; 320 321 sprintf(pathname, "/dev/cpu/%d/msr", cpu); 322 fd = open(pathname, O_RDONLY); 323 if (fd < 0) 324 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); 325 326 fd_percpu[cpu] = fd; 327 328 return fd; 329 } 330 331 int get_msr(int cpu, off_t offset, unsigned long long *msr) 332 { 333 ssize_t retval; 334 335 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); 336 337 if (retval != sizeof *msr) 338 err(-1, "msr %d offset 0x%llx read failed", cpu, (unsigned long long)offset); 339 340 return 0; 341 } 342 343 /* 344 * Example Format w/ field column widths: 345 * 346 * Package Core CPU Avg_MHz Bzy_MHz TSC_MHz IRQ SMI Busy% CPU_%c1 CPU_%c3 CPU_%c6 CPU_%c7 ThreadC CoreTmp CoreCnt PkgTmp GFXMHz Pkg%pc2 Pkg%pc3 Pkg%pc6 Pkg%pc7 PkgWatt CorWatt GFXWatt PkgCnt 347 * 12345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678 348 */ 349 350 void print_header(void) 351 { 352 struct msr_counter *mp; 353 354 if (show_pkg) 355 outp += sprintf(outp, "\tPackage"); 356 if (show_core) 357 outp += sprintf(outp, "\tCore"); 358 if (show_cpu) 359 outp += sprintf(outp, "\tCPU"); 360 if (has_aperf) 361 outp += sprintf(outp, "\tAvg_MHz"); 362 if (has_aperf) 363 outp += sprintf(outp, "\tBusy%%"); 364 if (has_aperf) 365 outp += sprintf(outp, "\tBzy_MHz"); 366 outp += sprintf(outp, "\tTSC_MHz"); 367 368 if (!debug) 369 goto done; 370 371 if (do_irq) 372 outp += sprintf(outp, "\tIRQ"); 373 if (do_smi) 374 outp += sprintf(outp, "\tSMI"); 375 376 if (do_nhm_cstates) 377 outp += sprintf(outp, "\tCPU%%c1"); 378 379 for (mp = sys.tp; mp; mp = mp->next) { 380 if (mp->format == FORMAT_RAW) { 381 if (mp->width == 64) 382 outp += sprintf(outp, "\t%18.18s", mp->name); 383 else 384 outp += sprintf(outp, "\t%10.10s", mp->name); 385 } else { 386 outp += sprintf(outp, "\t%-7.7s", mp->name); 387 } 388 } 389 390 if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates) 391 outp += sprintf(outp, "\tCPU%%c3"); 392 if (do_nhm_cstates) 393 outp += sprintf(outp, "\tCPU%%c6"); 394 if (do_snb_cstates) 395 outp += sprintf(outp, "\tCPU%%c7"); 396 397 398 if (do_dts) 399 outp += sprintf(outp, "\tCoreTmp"); 400 401 for (mp = sys.cp; mp; mp = mp->next) { 402 if (mp->format == FORMAT_RAW) { 403 if (mp->width == 64) 404 outp += sprintf(outp, "\t%18.18s", mp->name); 405 else 406 outp += sprintf(outp, "\t%10.10s", mp->name); 407 } else { 408 outp += sprintf(outp, "\t%-7.7s", mp->name); 409 } 410 } 411 412 if (do_ptm) 413 outp += sprintf(outp, "\tPkgTmp"); 414 415 if (do_gfx_rc6_ms) 416 outp += sprintf(outp, "\tGFX%%rc6"); 417 418 if (do_gfx_mhz) 419 outp += sprintf(outp, "\tGFXMHz"); 420 421 if (do_skl_residency) { 422 outp += sprintf(outp, "\tTotl%%C0"); 423 outp += sprintf(outp, "\tAny%%C0"); 424 outp += sprintf(outp, "\tGFX%%C0"); 425 outp += sprintf(outp, "\tCPUGFX%%"); 426 } 427 428 if (do_pc2) 429 outp += sprintf(outp, "\tPkg%%pc2"); 430 if (do_pc3) 431 outp += sprintf(outp, "\tPkg%%pc3"); 432 if (do_pc6) 433 outp += sprintf(outp, "\tPkg%%pc6"); 434 if (do_pc7) 435 outp += sprintf(outp, "\tPkg%%pc7"); 436 if (do_c8_c9_c10) { 437 outp += sprintf(outp, "\tPkg%%pc8"); 438 outp += sprintf(outp, "\tPkg%%pc9"); 439 outp += sprintf(outp, "\tPk%%pc10"); 440 } 441 442 if (do_rapl && !rapl_joules) { 443 if (do_rapl & RAPL_PKG) 444 outp += sprintf(outp, "\tPkgWatt"); 445 if (do_rapl & RAPL_CORES_ENERGY_STATUS) 446 outp += sprintf(outp, "\tCorWatt"); 447 if (do_rapl & RAPL_GFX) 448 outp += sprintf(outp, "\tGFXWatt"); 449 if (do_rapl & RAPL_DRAM) 450 outp += sprintf(outp, "\tRAMWatt"); 451 if (do_rapl & RAPL_PKG_PERF_STATUS) 452 outp += sprintf(outp, "\tPKG_%%"); 453 if (do_rapl & RAPL_DRAM_PERF_STATUS) 454 outp += sprintf(outp, "\tRAM_%%"); 455 } else if (do_rapl && rapl_joules) { 456 if (do_rapl & RAPL_PKG) 457 outp += sprintf(outp, "\tPkg_J"); 458 if (do_rapl & RAPL_CORES_ENERGY_STATUS) 459 outp += sprintf(outp, "\tCor_J"); 460 if (do_rapl & RAPL_GFX) 461 outp += sprintf(outp, "\tGFX_J"); 462 if (do_rapl & RAPL_DRAM) 463 outp += sprintf(outp, "\tRAM_J"); 464 if (do_rapl & RAPL_PKG_PERF_STATUS) 465 outp += sprintf(outp, "\tPKG_%%"); 466 if (do_rapl & RAPL_DRAM_PERF_STATUS) 467 outp += sprintf(outp, "\tRAM_%%"); 468 } 469 for (mp = sys.pp; mp; mp = mp->next) { 470 if (mp->format == FORMAT_RAW) { 471 if (mp->width == 64) 472 outp += sprintf(outp, "\t%18.18s", mp->name); 473 else 474 outp += sprintf(outp, "\t%10.10s", mp->name); 475 } else { 476 outp += sprintf(outp, "\t%-7.7s", mp->name); 477 } 478 } 479 480 done: 481 outp += sprintf(outp, "\n"); 482 } 483 484 int dump_counters(struct thread_data *t, struct core_data *c, 485 struct pkg_data *p) 486 { 487 int i; 488 struct msr_counter *mp; 489 490 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); 491 492 if (t) { 493 outp += sprintf(outp, "CPU: %d flags 0x%x\n", 494 t->cpu_id, t->flags); 495 outp += sprintf(outp, "TSC: %016llX\n", t->tsc); 496 outp += sprintf(outp, "aperf: %016llX\n", t->aperf); 497 outp += sprintf(outp, "mperf: %016llX\n", t->mperf); 498 outp += sprintf(outp, "c1: %016llX\n", t->c1); 499 500 if (do_irq) 501 outp += sprintf(outp, "IRQ: %08X\n", t->irq_count); 502 if (do_smi) 503 outp += sprintf(outp, "SMI: %08X\n", t->smi_count); 504 505 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 506 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", 507 i, mp->msr_num, t->counter[i]); 508 } 509 } 510 511 if (c) { 512 outp += sprintf(outp, "core: %d\n", c->core_id); 513 outp += sprintf(outp, "c3: %016llX\n", c->c3); 514 outp += sprintf(outp, "c6: %016llX\n", c->c6); 515 outp += sprintf(outp, "c7: %016llX\n", c->c7); 516 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); 517 518 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 519 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", 520 i, mp->msr_num, c->counter[i]); 521 } 522 } 523 524 if (p) { 525 outp += sprintf(outp, "package: %d\n", p->package_id); 526 527 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); 528 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); 529 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); 530 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); 531 532 outp += sprintf(outp, "pc2: %016llX\n", p->pc2); 533 if (do_pc3) 534 outp += sprintf(outp, "pc3: %016llX\n", p->pc3); 535 if (do_pc6) 536 outp += sprintf(outp, "pc6: %016llX\n", p->pc6); 537 if (do_pc7) 538 outp += sprintf(outp, "pc7: %016llX\n", p->pc7); 539 outp += sprintf(outp, "pc8: %016llX\n", p->pc8); 540 outp += sprintf(outp, "pc9: %016llX\n", p->pc9); 541 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 542 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg); 543 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores); 544 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx); 545 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram); 546 outp += sprintf(outp, "Throttle PKG: %0X\n", 547 p->rapl_pkg_perf_status); 548 outp += sprintf(outp, "Throttle RAM: %0X\n", 549 p->rapl_dram_perf_status); 550 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); 551 552 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 553 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", 554 i, mp->msr_num, p->counter[i]); 555 } 556 } 557 558 outp += sprintf(outp, "\n"); 559 560 return 0; 561 } 562 563 /* 564 * column formatting convention & formats 565 */ 566 int format_counters(struct thread_data *t, struct core_data *c, 567 struct pkg_data *p) 568 { 569 double interval_float; 570 char *fmt8; 571 int i; 572 struct msr_counter *mp; 573 574 /* if showing only 1st thread in core and this isn't one, bail out */ 575 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 576 return 0; 577 578 /* if showing only 1st thread in pkg and this isn't one, bail out */ 579 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 580 return 0; 581 582 interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0; 583 584 /* topo columns, print blanks on 1st (average) line */ 585 if (t == &average.threads) { 586 if (show_pkg) 587 outp += sprintf(outp, "\t-"); 588 if (show_core) 589 outp += sprintf(outp, "\t-"); 590 if (show_cpu) 591 outp += sprintf(outp, "\t-"); 592 } else { 593 if (show_pkg) { 594 if (p) 595 outp += sprintf(outp, "\t%d", p->package_id); 596 else 597 outp += sprintf(outp, "\t-"); 598 } 599 if (show_core) { 600 if (c) 601 outp += sprintf(outp, "\t%d", c->core_id); 602 else 603 outp += sprintf(outp, "\t-"); 604 } 605 if (show_cpu) 606 outp += sprintf(outp, "\t%d", t->cpu_id); 607 } 608 609 /* Avg_MHz */ 610 if (has_aperf) 611 outp += sprintf(outp, "\t%.0f", 612 1.0 / units * t->aperf / interval_float); 613 614 /* Busy% */ 615 if (has_aperf) 616 outp += sprintf(outp, "\t%.2f", 100.0 * t->mperf/t->tsc/tsc_tweak); 617 618 /* Bzy_MHz */ 619 if (has_aperf) { 620 if (has_base_hz) 621 outp += sprintf(outp, "\t%.0f", base_hz / units * t->aperf / t->mperf); 622 else 623 outp += sprintf(outp, "\t%.0f", 624 1.0 * t->tsc / units * t->aperf / t->mperf / interval_float); 625 } 626 627 /* TSC_MHz */ 628 outp += sprintf(outp, "\t%.0f", 1.0 * t->tsc/units/interval_float); 629 630 if (!debug) 631 goto done; 632 633 /* IRQ */ 634 if (do_irq) 635 outp += sprintf(outp, "\t%d", t->irq_count); 636 637 /* SMI */ 638 if (do_smi) 639 outp += sprintf(outp, "\t%d", t->smi_count); 640 641 /* C1 */ 642 if (do_nhm_cstates) 643 outp += sprintf(outp, "\t%.2f", 100.0 * t->c1/t->tsc); 644 645 /* Added counters */ 646 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 647 if (mp->format == FORMAT_RAW) { 648 if (mp->width == 32) 649 outp += sprintf(outp, "\t0x%08lx", (unsigned long) t->counter[i]); 650 else 651 outp += sprintf(outp, "\t0x%016llx", t->counter[i]); 652 } else if (mp->format == FORMAT_DELTA) { 653 outp += sprintf(outp, "\t%lld", t->counter[i]); 654 } else if (mp->format == FORMAT_PERCENT) { 655 outp += sprintf(outp, "\t%.2f", 100.0 * t->counter[i]/t->tsc); 656 } 657 } 658 659 /* print per-core data only for 1st thread in core */ 660 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 661 goto done; 662 663 if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates) 664 outp += sprintf(outp, "\t%.2f", 100.0 * c->c3/t->tsc); 665 if (do_nhm_cstates) 666 outp += sprintf(outp, "\t%.2f", 100.0 * c->c6/t->tsc); 667 if (do_snb_cstates) 668 outp += sprintf(outp, "\t%.2f", 100.0 * c->c7/t->tsc); 669 670 671 if (do_dts) 672 outp += sprintf(outp, "\t%d", c->core_temp_c); 673 674 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 675 if (mp->format == FORMAT_RAW) { 676 if (mp->width == 32) 677 outp += sprintf(outp, "\t0x%08lx", (unsigned long) c->counter[i]); 678 else 679 outp += sprintf(outp, "\t0x%016llx", c->counter[i]); 680 } else if (mp->format == FORMAT_DELTA) { 681 outp += sprintf(outp, "\t%lld", c->counter[i]); 682 } else if (mp->format == FORMAT_PERCENT) { 683 outp += sprintf(outp, "\t%.2f", 100.0 * c->counter[i]/t->tsc); 684 } 685 } 686 687 /* print per-package data only for 1st core in package */ 688 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 689 goto done; 690 691 /* PkgTmp */ 692 if (do_ptm) 693 outp += sprintf(outp, "\t%d", p->pkg_temp_c); 694 695 /* GFXrc6 */ 696 if (do_gfx_rc6_ms) { 697 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */ 698 outp += sprintf(outp, "\t**.**"); 699 } else { 700 outp += sprintf(outp, "\t%.2f", 701 p->gfx_rc6_ms / 10.0 / interval_float); 702 } 703 } 704 705 /* GFXMHz */ 706 if (do_gfx_mhz) 707 outp += sprintf(outp, "\t%d", p->gfx_mhz); 708 709 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ 710 if (do_skl_residency) { 711 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_wtd_core_c0/t->tsc); 712 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_core_c0/t->tsc); 713 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_gfxe_c0/t->tsc); 714 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_both_core_gfxe_c0/t->tsc); 715 } 716 717 if (do_pc2) 718 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc2/t->tsc); 719 if (do_pc3) 720 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc3/t->tsc); 721 if (do_pc6) 722 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc6/t->tsc); 723 if (do_pc7) 724 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc7/t->tsc); 725 if (do_c8_c9_c10) { 726 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc8/t->tsc); 727 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc9/t->tsc); 728 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc10/t->tsc); 729 } 730 731 /* 732 * If measurement interval exceeds minimum RAPL Joule Counter range, 733 * indicate that results are suspect by printing "**" in fraction place. 734 */ 735 if (interval_float < rapl_joule_counter_range) 736 fmt8 = "\t%.2f"; 737 else 738 fmt8 = "%6.0f**"; 739 740 if (do_rapl && !rapl_joules) { 741 if (do_rapl & RAPL_PKG) 742 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float); 743 if (do_rapl & RAPL_CORES_ENERGY_STATUS) 744 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float); 745 if (do_rapl & RAPL_GFX) 746 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float); 747 if (do_rapl & RAPL_DRAM) 748 outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units / interval_float); 749 if (do_rapl & RAPL_PKG_PERF_STATUS) 750 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 751 if (do_rapl & RAPL_DRAM_PERF_STATUS) 752 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 753 } else if (do_rapl && rapl_joules) { 754 if (do_rapl & RAPL_PKG) 755 outp += sprintf(outp, fmt8, 756 p->energy_pkg * rapl_energy_units); 757 if (do_rapl & RAPL_CORES) 758 outp += sprintf(outp, fmt8, 759 p->energy_cores * rapl_energy_units); 760 if (do_rapl & RAPL_GFX) 761 outp += sprintf(outp, fmt8, 762 p->energy_gfx * rapl_energy_units); 763 if (do_rapl & RAPL_DRAM) 764 outp += sprintf(outp, fmt8, 765 p->energy_dram * rapl_dram_energy_units); 766 if (do_rapl & RAPL_PKG_PERF_STATUS) 767 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 768 if (do_rapl & RAPL_DRAM_PERF_STATUS) 769 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 770 } 771 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 772 if (mp->format == FORMAT_RAW) { 773 if (mp->width == 32) 774 outp += sprintf(outp, "\t0x%08lx", (unsigned long) p->counter[i]); 775 else 776 outp += sprintf(outp, "\t0x%016llx", p->counter[i]); 777 } else if (mp->format == FORMAT_DELTA) { 778 outp += sprintf(outp, "\t%lld", p->counter[i]); 779 } else if (mp->format == FORMAT_PERCENT) { 780 outp += sprintf(outp, "\t%.2f", 100.0 * p->counter[i]/t->tsc); 781 } 782 } 783 784 done: 785 outp += sprintf(outp, "\n"); 786 787 return 0; 788 } 789 790 void flush_output_stdout(void) 791 { 792 FILE *filep; 793 794 if (outf == stderr) 795 filep = stdout; 796 else 797 filep = outf; 798 799 fputs(output_buffer, filep); 800 fflush(filep); 801 802 outp = output_buffer; 803 } 804 void flush_output_stderr(void) 805 { 806 fputs(output_buffer, outf); 807 fflush(outf); 808 outp = output_buffer; 809 } 810 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 811 { 812 static int printed; 813 814 if (!printed || !summary_only) 815 print_header(); 816 817 if (topo.num_cpus > 1) 818 format_counters(&average.threads, &average.cores, 819 &average.packages); 820 821 printed = 1; 822 823 if (summary_only) 824 return; 825 826 for_all_cpus(format_counters, t, c, p); 827 } 828 829 #define DELTA_WRAP32(new, old) \ 830 if (new > old) { \ 831 old = new - old; \ 832 } else { \ 833 old = 0x100000000 + new - old; \ 834 } 835 836 int 837 delta_package(struct pkg_data *new, struct pkg_data *old) 838 { 839 int i; 840 struct msr_counter *mp; 841 842 if (do_skl_residency) { 843 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; 844 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; 845 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; 846 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; 847 } 848 old->pc2 = new->pc2 - old->pc2; 849 if (do_pc3) 850 old->pc3 = new->pc3 - old->pc3; 851 if (do_pc6) 852 old->pc6 = new->pc6 - old->pc6; 853 if (do_pc7) 854 old->pc7 = new->pc7 - old->pc7; 855 old->pc8 = new->pc8 - old->pc8; 856 old->pc9 = new->pc9 - old->pc9; 857 old->pc10 = new->pc10 - old->pc10; 858 old->pkg_temp_c = new->pkg_temp_c; 859 860 /* flag an error when rc6 counter resets/wraps */ 861 if (old->gfx_rc6_ms > new->gfx_rc6_ms) 862 old->gfx_rc6_ms = -1; 863 else 864 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; 865 866 old->gfx_mhz = new->gfx_mhz; 867 868 DELTA_WRAP32(new->energy_pkg, old->energy_pkg); 869 DELTA_WRAP32(new->energy_cores, old->energy_cores); 870 DELTA_WRAP32(new->energy_gfx, old->energy_gfx); 871 DELTA_WRAP32(new->energy_dram, old->energy_dram); 872 DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status); 873 DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status); 874 875 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 876 if (mp->format == FORMAT_RAW) 877 old->counter[i] = new->counter[i]; 878 else 879 old->counter[i] = new->counter[i] - old->counter[i]; 880 } 881 882 return 0; 883 } 884 885 void 886 delta_core(struct core_data *new, struct core_data *old) 887 { 888 int i; 889 struct msr_counter *mp; 890 891 old->c3 = new->c3 - old->c3; 892 old->c6 = new->c6 - old->c6; 893 old->c7 = new->c7 - old->c7; 894 old->core_temp_c = new->core_temp_c; 895 896 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 897 if (mp->format == FORMAT_RAW) 898 old->counter[i] = new->counter[i]; 899 else 900 old->counter[i] = new->counter[i] - old->counter[i]; 901 } 902 } 903 904 /* 905 * old = new - old 906 */ 907 int 908 delta_thread(struct thread_data *new, struct thread_data *old, 909 struct core_data *core_delta) 910 { 911 int i; 912 struct msr_counter *mp; 913 914 old->tsc = new->tsc - old->tsc; 915 916 /* check for TSC < 1 Mcycles over interval */ 917 if (old->tsc < (1000 * 1000)) 918 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" 919 "You can disable all c-states by booting with \"idle=poll\"\n" 920 "or just the deep ones with \"processor.max_cstate=1\""); 921 922 old->c1 = new->c1 - old->c1; 923 924 if (has_aperf) { 925 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { 926 old->aperf = new->aperf - old->aperf; 927 old->mperf = new->mperf - old->mperf; 928 } else { 929 return -1; 930 } 931 } 932 933 934 if (use_c1_residency_msr) { 935 /* 936 * Some models have a dedicated C1 residency MSR, 937 * which should be more accurate than the derivation below. 938 */ 939 } else { 940 /* 941 * As counter collection is not atomic, 942 * it is possible for mperf's non-halted cycles + idle states 943 * to exceed TSC's all cycles: show c1 = 0% in that case. 944 */ 945 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > old->tsc) 946 old->c1 = 0; 947 else { 948 /* normal case, derive c1 */ 949 old->c1 = old->tsc - old->mperf - core_delta->c3 950 - core_delta->c6 - core_delta->c7; 951 } 952 } 953 954 if (old->mperf == 0) { 955 if (debug > 1) 956 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); 957 old->mperf = 1; /* divide by 0 protection */ 958 } 959 960 if (do_irq) 961 old->irq_count = new->irq_count - old->irq_count; 962 963 if (do_smi) 964 old->smi_count = new->smi_count - old->smi_count; 965 966 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 967 if (mp->format == FORMAT_RAW) 968 old->counter[i] = new->counter[i]; 969 else 970 old->counter[i] = new->counter[i] - old->counter[i]; 971 } 972 return 0; 973 } 974 975 int delta_cpu(struct thread_data *t, struct core_data *c, 976 struct pkg_data *p, struct thread_data *t2, 977 struct core_data *c2, struct pkg_data *p2) 978 { 979 int retval = 0; 980 981 /* calculate core delta only for 1st thread in core */ 982 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) 983 delta_core(c, c2); 984 985 /* always calculate thread delta */ 986 retval = delta_thread(t, t2, c2); /* c2 is core delta */ 987 if (retval) 988 return retval; 989 990 /* calculate package delta only for 1st core in package */ 991 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) 992 retval = delta_package(p, p2); 993 994 return retval; 995 } 996 997 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 998 { 999 int i; 1000 struct msr_counter *mp; 1001 1002 t->tsc = 0; 1003 t->aperf = 0; 1004 t->mperf = 0; 1005 t->c1 = 0; 1006 1007 t->irq_count = 0; 1008 t->smi_count = 0; 1009 1010 /* tells format_counters to dump all fields from this set */ 1011 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; 1012 1013 c->c3 = 0; 1014 c->c6 = 0; 1015 c->c7 = 0; 1016 c->core_temp_c = 0; 1017 1018 p->pkg_wtd_core_c0 = 0; 1019 p->pkg_any_core_c0 = 0; 1020 p->pkg_any_gfxe_c0 = 0; 1021 p->pkg_both_core_gfxe_c0 = 0; 1022 1023 p->pc2 = 0; 1024 if (do_pc3) 1025 p->pc3 = 0; 1026 if (do_pc6) 1027 p->pc6 = 0; 1028 if (do_pc7) 1029 p->pc7 = 0; 1030 p->pc8 = 0; 1031 p->pc9 = 0; 1032 p->pc10 = 0; 1033 1034 p->energy_pkg = 0; 1035 p->energy_dram = 0; 1036 p->energy_cores = 0; 1037 p->energy_gfx = 0; 1038 p->rapl_pkg_perf_status = 0; 1039 p->rapl_dram_perf_status = 0; 1040 p->pkg_temp_c = 0; 1041 1042 p->gfx_rc6_ms = 0; 1043 p->gfx_mhz = 0; 1044 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) 1045 t->counter[i] = 0; 1046 1047 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) 1048 c->counter[i] = 0; 1049 1050 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) 1051 p->counter[i] = 0; 1052 } 1053 int sum_counters(struct thread_data *t, struct core_data *c, 1054 struct pkg_data *p) 1055 { 1056 int i; 1057 struct msr_counter *mp; 1058 1059 average.threads.tsc += t->tsc; 1060 average.threads.aperf += t->aperf; 1061 average.threads.mperf += t->mperf; 1062 average.threads.c1 += t->c1; 1063 1064 average.threads.irq_count += t->irq_count; 1065 average.threads.smi_count += t->smi_count; 1066 1067 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1068 if (mp->format == FORMAT_RAW) 1069 continue; 1070 average.threads.counter[i] += t->counter[i]; 1071 } 1072 1073 /* sum per-core values only for 1st thread in core */ 1074 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1075 return 0; 1076 1077 average.cores.c3 += c->c3; 1078 average.cores.c6 += c->c6; 1079 average.cores.c7 += c->c7; 1080 1081 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); 1082 1083 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1084 if (mp->format == FORMAT_RAW) 1085 continue; 1086 average.cores.counter[i] += c->counter[i]; 1087 } 1088 1089 /* sum per-pkg values only for 1st core in pkg */ 1090 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1091 return 0; 1092 1093 if (do_skl_residency) { 1094 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; 1095 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; 1096 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; 1097 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; 1098 } 1099 1100 average.packages.pc2 += p->pc2; 1101 if (do_pc3) 1102 average.packages.pc3 += p->pc3; 1103 if (do_pc6) 1104 average.packages.pc6 += p->pc6; 1105 if (do_pc7) 1106 average.packages.pc7 += p->pc7; 1107 average.packages.pc8 += p->pc8; 1108 average.packages.pc9 += p->pc9; 1109 average.packages.pc10 += p->pc10; 1110 1111 average.packages.energy_pkg += p->energy_pkg; 1112 average.packages.energy_dram += p->energy_dram; 1113 average.packages.energy_cores += p->energy_cores; 1114 average.packages.energy_gfx += p->energy_gfx; 1115 1116 average.packages.gfx_rc6_ms = p->gfx_rc6_ms; 1117 average.packages.gfx_mhz = p->gfx_mhz; 1118 1119 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); 1120 1121 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; 1122 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; 1123 1124 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1125 if (mp->format == FORMAT_RAW) 1126 continue; 1127 average.packages.counter[i] += p->counter[i]; 1128 } 1129 return 0; 1130 } 1131 /* 1132 * sum the counters for all cpus in the system 1133 * compute the weighted average 1134 */ 1135 void compute_average(struct thread_data *t, struct core_data *c, 1136 struct pkg_data *p) 1137 { 1138 int i; 1139 struct msr_counter *mp; 1140 1141 clear_counters(&average.threads, &average.cores, &average.packages); 1142 1143 for_all_cpus(sum_counters, t, c, p); 1144 1145 average.threads.tsc /= topo.num_cpus; 1146 average.threads.aperf /= topo.num_cpus; 1147 average.threads.mperf /= topo.num_cpus; 1148 average.threads.c1 /= topo.num_cpus; 1149 1150 average.cores.c3 /= topo.num_cores; 1151 average.cores.c6 /= topo.num_cores; 1152 average.cores.c7 /= topo.num_cores; 1153 1154 if (do_skl_residency) { 1155 average.packages.pkg_wtd_core_c0 /= topo.num_packages; 1156 average.packages.pkg_any_core_c0 /= topo.num_packages; 1157 average.packages.pkg_any_gfxe_c0 /= topo.num_packages; 1158 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages; 1159 } 1160 1161 average.packages.pc2 /= topo.num_packages; 1162 if (do_pc3) 1163 average.packages.pc3 /= topo.num_packages; 1164 if (do_pc6) 1165 average.packages.pc6 /= topo.num_packages; 1166 if (do_pc7) 1167 average.packages.pc7 /= topo.num_packages; 1168 1169 average.packages.pc8 /= topo.num_packages; 1170 average.packages.pc9 /= topo.num_packages; 1171 average.packages.pc10 /= topo.num_packages; 1172 1173 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1174 if (mp->format == FORMAT_RAW) 1175 continue; 1176 average.threads.counter[i] /= topo.num_cpus; 1177 } 1178 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1179 if (mp->format == FORMAT_RAW) 1180 continue; 1181 average.cores.counter[i] /= topo.num_cores; 1182 } 1183 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1184 if (mp->format == FORMAT_RAW) 1185 continue; 1186 average.packages.counter[i] /= topo.num_packages; 1187 } 1188 } 1189 1190 static unsigned long long rdtsc(void) 1191 { 1192 unsigned int low, high; 1193 1194 asm volatile("rdtsc" : "=a" (low), "=d" (high)); 1195 1196 return low | ((unsigned long long)high) << 32; 1197 } 1198 1199 /* 1200 * get_counters(...) 1201 * migrate to cpu 1202 * acquire and record local counters for that cpu 1203 */ 1204 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1205 { 1206 int cpu = t->cpu_id; 1207 unsigned long long msr; 1208 int aperf_mperf_retry_count = 0; 1209 struct msr_counter *mp; 1210 int i; 1211 1212 if (cpu_migrate(cpu)) { 1213 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 1214 return -1; 1215 } 1216 1217 retry: 1218 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 1219 1220 if (has_aperf) { 1221 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; 1222 1223 /* 1224 * The TSC, APERF and MPERF must be read together for 1225 * APERF/MPERF and MPERF/TSC to give accurate results. 1226 * 1227 * Unfortunately, APERF and MPERF are read by 1228 * individual system call, so delays may occur 1229 * between them. If the time to read them 1230 * varies by a large amount, we re-read them. 1231 */ 1232 1233 /* 1234 * This initial dummy APERF read has been seen to 1235 * reduce jitter in the subsequent reads. 1236 */ 1237 1238 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1239 return -3; 1240 1241 t->tsc = rdtsc(); /* re-read close to APERF */ 1242 1243 tsc_before = t->tsc; 1244 1245 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1246 return -3; 1247 1248 tsc_between = rdtsc(); 1249 1250 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) 1251 return -4; 1252 1253 tsc_after = rdtsc(); 1254 1255 aperf_time = tsc_between - tsc_before; 1256 mperf_time = tsc_after - tsc_between; 1257 1258 /* 1259 * If the system call latency to read APERF and MPERF 1260 * differ by more than 2x, then try again. 1261 */ 1262 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { 1263 aperf_mperf_retry_count++; 1264 if (aperf_mperf_retry_count < 5) 1265 goto retry; 1266 else 1267 warnx("cpu%d jitter %lld %lld", 1268 cpu, aperf_time, mperf_time); 1269 } 1270 aperf_mperf_retry_count = 0; 1271 1272 t->aperf = t->aperf * aperf_mperf_multiplier; 1273 t->mperf = t->mperf * aperf_mperf_multiplier; 1274 } 1275 1276 if (do_irq) 1277 t->irq_count = irqs_per_cpu[cpu]; 1278 if (do_smi) { 1279 if (get_msr(cpu, MSR_SMI_COUNT, &msr)) 1280 return -5; 1281 t->smi_count = msr & 0xFFFFFFFF; 1282 } 1283 1284 if (use_c1_residency_msr) { 1285 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) 1286 return -6; 1287 } 1288 1289 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1290 if (get_msr(cpu, mp->msr_num, &t->counter[i])) 1291 return -10; 1292 } 1293 1294 1295 /* collect core counters only for 1st thread in core */ 1296 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1297 return 0; 1298 1299 if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates) { 1300 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) 1301 return -6; 1302 } 1303 1304 if (do_nhm_cstates && !do_knl_cstates) { 1305 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) 1306 return -7; 1307 } else if (do_knl_cstates) { 1308 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) 1309 return -7; 1310 } 1311 1312 if (do_snb_cstates) 1313 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 1314 return -8; 1315 1316 if (do_dts) { 1317 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 1318 return -9; 1319 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1320 } 1321 1322 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1323 if (get_msr(cpu, mp->msr_num, &c->counter[i])) 1324 return -10; 1325 } 1326 1327 /* collect package counters only for 1st core in package */ 1328 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1329 return 0; 1330 1331 if (do_skl_residency) { 1332 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) 1333 return -10; 1334 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) 1335 return -11; 1336 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) 1337 return -12; 1338 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) 1339 return -13; 1340 } 1341 if (do_pc3) 1342 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) 1343 return -9; 1344 if (do_pc6) 1345 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) 1346 return -10; 1347 if (do_pc2) 1348 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) 1349 return -11; 1350 if (do_pc7) 1351 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) 1352 return -12; 1353 if (do_c8_c9_c10) { 1354 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) 1355 return -13; 1356 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) 1357 return -13; 1358 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) 1359 return -13; 1360 } 1361 if (do_rapl & RAPL_PKG) { 1362 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr)) 1363 return -13; 1364 p->energy_pkg = msr & 0xFFFFFFFF; 1365 } 1366 if (do_rapl & RAPL_CORES_ENERGY_STATUS) { 1367 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr)) 1368 return -14; 1369 p->energy_cores = msr & 0xFFFFFFFF; 1370 } 1371 if (do_rapl & RAPL_DRAM) { 1372 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) 1373 return -15; 1374 p->energy_dram = msr & 0xFFFFFFFF; 1375 } 1376 if (do_rapl & RAPL_GFX) { 1377 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr)) 1378 return -16; 1379 p->energy_gfx = msr & 0xFFFFFFFF; 1380 } 1381 if (do_rapl & RAPL_PKG_PERF_STATUS) { 1382 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr)) 1383 return -16; 1384 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF; 1385 } 1386 if (do_rapl & RAPL_DRAM_PERF_STATUS) { 1387 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr)) 1388 return -16; 1389 p->rapl_dram_perf_status = msr & 0xFFFFFFFF; 1390 } 1391 if (do_ptm) { 1392 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 1393 return -17; 1394 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1395 } 1396 1397 if (do_gfx_rc6_ms) 1398 p->gfx_rc6_ms = gfx_cur_rc6_ms; 1399 1400 if (do_gfx_mhz) 1401 p->gfx_mhz = gfx_cur_mhz; 1402 1403 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1404 if (get_msr(cpu, mp->msr_num, &p->counter[i])) 1405 return -10; 1406 } 1407 1408 return 0; 1409 } 1410 1411 /* 1412 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: 1413 * If you change the values, note they are used both in comparisons 1414 * (>= PCL__7) and to index pkg_cstate_limit_strings[]. 1415 */ 1416 1417 #define PCLUKN 0 /* Unknown */ 1418 #define PCLRSV 1 /* Reserved */ 1419 #define PCL__0 2 /* PC0 */ 1420 #define PCL__1 3 /* PC1 */ 1421 #define PCL__2 4 /* PC2 */ 1422 #define PCL__3 5 /* PC3 */ 1423 #define PCL__4 6 /* PC4 */ 1424 #define PCL__6 7 /* PC6 */ 1425 #define PCL_6N 8 /* PC6 No Retention */ 1426 #define PCL_6R 9 /* PC6 Retention */ 1427 #define PCL__7 10 /* PC7 */ 1428 #define PCL_7S 11 /* PC7 Shrink */ 1429 #define PCL__8 12 /* PC8 */ 1430 #define PCL__9 13 /* PC9 */ 1431 #define PCLUNL 14 /* Unlimited */ 1432 1433 int pkg_cstate_limit = PCLUKN; 1434 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", 1435 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"}; 1436 1437 int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1438 int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1439 int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1440 int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1441 int amt_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1442 int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1443 int bxt_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1444 int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1445 1446 1447 static void 1448 calculate_tsc_tweak() 1449 { 1450 tsc_tweak = base_hz / tsc_hz; 1451 } 1452 1453 static void 1454 dump_nhm_platform_info(void) 1455 { 1456 unsigned long long msr; 1457 unsigned int ratio; 1458 1459 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 1460 1461 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 1462 1463 ratio = (msr >> 40) & 0xFF; 1464 fprintf(outf, "%d * %.0f = %.0f MHz max efficiency frequency\n", 1465 ratio, bclk, ratio * bclk); 1466 1467 ratio = (msr >> 8) & 0xFF; 1468 fprintf(outf, "%d * %.0f = %.0f MHz base frequency\n", 1469 ratio, bclk, ratio * bclk); 1470 1471 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); 1472 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", 1473 base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); 1474 1475 return; 1476 } 1477 1478 static void 1479 dump_hsw_turbo_ratio_limits(void) 1480 { 1481 unsigned long long msr; 1482 unsigned int ratio; 1483 1484 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); 1485 1486 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); 1487 1488 ratio = (msr >> 8) & 0xFF; 1489 if (ratio) 1490 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 18 active cores\n", 1491 ratio, bclk, ratio * bclk); 1492 1493 ratio = (msr >> 0) & 0xFF; 1494 if (ratio) 1495 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 17 active cores\n", 1496 ratio, bclk, ratio * bclk); 1497 return; 1498 } 1499 1500 static void 1501 dump_ivt_turbo_ratio_limits(void) 1502 { 1503 unsigned long long msr; 1504 unsigned int ratio; 1505 1506 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); 1507 1508 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); 1509 1510 ratio = (msr >> 56) & 0xFF; 1511 if (ratio) 1512 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 16 active cores\n", 1513 ratio, bclk, ratio * bclk); 1514 1515 ratio = (msr >> 48) & 0xFF; 1516 if (ratio) 1517 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 15 active cores\n", 1518 ratio, bclk, ratio * bclk); 1519 1520 ratio = (msr >> 40) & 0xFF; 1521 if (ratio) 1522 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 14 active cores\n", 1523 ratio, bclk, ratio * bclk); 1524 1525 ratio = (msr >> 32) & 0xFF; 1526 if (ratio) 1527 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 13 active cores\n", 1528 ratio, bclk, ratio * bclk); 1529 1530 ratio = (msr >> 24) & 0xFF; 1531 if (ratio) 1532 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 12 active cores\n", 1533 ratio, bclk, ratio * bclk); 1534 1535 ratio = (msr >> 16) & 0xFF; 1536 if (ratio) 1537 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 11 active cores\n", 1538 ratio, bclk, ratio * bclk); 1539 1540 ratio = (msr >> 8) & 0xFF; 1541 if (ratio) 1542 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 10 active cores\n", 1543 ratio, bclk, ratio * bclk); 1544 1545 ratio = (msr >> 0) & 0xFF; 1546 if (ratio) 1547 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 9 active cores\n", 1548 ratio, bclk, ratio * bclk); 1549 return; 1550 } 1551 1552 static void 1553 dump_nhm_turbo_ratio_limits(void) 1554 { 1555 unsigned long long msr; 1556 unsigned int ratio; 1557 1558 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 1559 1560 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 1561 1562 ratio = (msr >> 56) & 0xFF; 1563 if (ratio) 1564 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 8 active cores\n", 1565 ratio, bclk, ratio * bclk); 1566 1567 ratio = (msr >> 48) & 0xFF; 1568 if (ratio) 1569 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 7 active cores\n", 1570 ratio, bclk, ratio * bclk); 1571 1572 ratio = (msr >> 40) & 0xFF; 1573 if (ratio) 1574 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 6 active cores\n", 1575 ratio, bclk, ratio * bclk); 1576 1577 ratio = (msr >> 32) & 0xFF; 1578 if (ratio) 1579 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 5 active cores\n", 1580 ratio, bclk, ratio * bclk); 1581 1582 ratio = (msr >> 24) & 0xFF; 1583 if (ratio) 1584 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 4 active cores\n", 1585 ratio, bclk, ratio * bclk); 1586 1587 ratio = (msr >> 16) & 0xFF; 1588 if (ratio) 1589 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 3 active cores\n", 1590 ratio, bclk, ratio * bclk); 1591 1592 ratio = (msr >> 8) & 0xFF; 1593 if (ratio) 1594 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 2 active cores\n", 1595 ratio, bclk, ratio * bclk); 1596 1597 ratio = (msr >> 0) & 0xFF; 1598 if (ratio) 1599 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 1 active cores\n", 1600 ratio, bclk, ratio * bclk); 1601 return; 1602 } 1603 1604 static void 1605 dump_knl_turbo_ratio_limits(void) 1606 { 1607 const unsigned int buckets_no = 7; 1608 1609 unsigned long long msr; 1610 int delta_cores, delta_ratio; 1611 int i, b_nr; 1612 unsigned int cores[buckets_no]; 1613 unsigned int ratio[buckets_no]; 1614 1615 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 1616 1617 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", 1618 base_cpu, msr); 1619 1620 /** 1621 * Turbo encoding in KNL is as follows: 1622 * [0] -- Reserved 1623 * [7:1] -- Base value of number of active cores of bucket 1. 1624 * [15:8] -- Base value of freq ratio of bucket 1. 1625 * [20:16] -- +ve delta of number of active cores of bucket 2. 1626 * i.e. active cores of bucket 2 = 1627 * active cores of bucket 1 + delta 1628 * [23:21] -- Negative delta of freq ratio of bucket 2. 1629 * i.e. freq ratio of bucket 2 = 1630 * freq ratio of bucket 1 - delta 1631 * [28:24]-- +ve delta of number of active cores of bucket 3. 1632 * [31:29]-- -ve delta of freq ratio of bucket 3. 1633 * [36:32]-- +ve delta of number of active cores of bucket 4. 1634 * [39:37]-- -ve delta of freq ratio of bucket 4. 1635 * [44:40]-- +ve delta of number of active cores of bucket 5. 1636 * [47:45]-- -ve delta of freq ratio of bucket 5. 1637 * [52:48]-- +ve delta of number of active cores of bucket 6. 1638 * [55:53]-- -ve delta of freq ratio of bucket 6. 1639 * [60:56]-- +ve delta of number of active cores of bucket 7. 1640 * [63:61]-- -ve delta of freq ratio of bucket 7. 1641 */ 1642 1643 b_nr = 0; 1644 cores[b_nr] = (msr & 0xFF) >> 1; 1645 ratio[b_nr] = (msr >> 8) & 0xFF; 1646 1647 for (i = 16; i < 64; i += 8) { 1648 delta_cores = (msr >> i) & 0x1F; 1649 delta_ratio = (msr >> (i + 5)) & 0x7; 1650 1651 cores[b_nr + 1] = cores[b_nr] + delta_cores; 1652 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; 1653 b_nr++; 1654 } 1655 1656 for (i = buckets_no - 1; i >= 0; i--) 1657 if (i > 0 ? ratio[i] != ratio[i - 1] : 1) 1658 fprintf(outf, 1659 "%d * %.0f = %.0f MHz max turbo %d active cores\n", 1660 ratio[i], bclk, ratio[i] * bclk, cores[i]); 1661 } 1662 1663 static void 1664 dump_nhm_cst_cfg(void) 1665 { 1666 unsigned long long msr; 1667 1668 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr); 1669 1670 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 1671 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 1672 1673 fprintf(outf, "cpu%d: MSR_NHM_SNB_PKG_CST_CFG_CTL: 0x%08llx", base_cpu, msr); 1674 1675 fprintf(outf, " (%s%s%s%s%slocked: pkg-cstate-limit=%d: %s)\n", 1676 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", 1677 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", 1678 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", 1679 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", 1680 (msr & (1 << 15)) ? "" : "UN", 1681 (unsigned int)msr & 0xF, 1682 pkg_cstate_limit_strings[pkg_cstate_limit]); 1683 return; 1684 } 1685 1686 static void 1687 dump_config_tdp(void) 1688 { 1689 unsigned long long msr; 1690 1691 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); 1692 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); 1693 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); 1694 1695 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); 1696 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); 1697 if (msr) { 1698 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 1699 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 1700 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 1701 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); 1702 } 1703 fprintf(outf, ")\n"); 1704 1705 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); 1706 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); 1707 if (msr) { 1708 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 1709 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 1710 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 1711 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); 1712 } 1713 fprintf(outf, ")\n"); 1714 1715 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); 1716 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); 1717 if ((msr) & 0x3) 1718 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); 1719 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 1720 fprintf(outf, ")\n"); 1721 1722 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); 1723 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); 1724 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); 1725 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 1726 fprintf(outf, ")\n"); 1727 } 1728 1729 unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; 1730 1731 void print_irtl(void) 1732 { 1733 unsigned long long msr; 1734 1735 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr); 1736 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr); 1737 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1738 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1739 1740 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr); 1741 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr); 1742 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1743 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1744 1745 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr); 1746 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr); 1747 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1748 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1749 1750 if (!do_irtl_hsw) 1751 return; 1752 1753 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr); 1754 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr); 1755 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1756 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1757 1758 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr); 1759 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr); 1760 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1761 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1762 1763 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr); 1764 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr); 1765 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 1766 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 1767 1768 } 1769 void free_fd_percpu(void) 1770 { 1771 int i; 1772 1773 for (i = 0; i < topo.max_cpu_num + 1; ++i) { 1774 if (fd_percpu[i] != 0) 1775 close(fd_percpu[i]); 1776 } 1777 1778 free(fd_percpu); 1779 } 1780 1781 void free_all_buffers(void) 1782 { 1783 CPU_FREE(cpu_present_set); 1784 cpu_present_set = NULL; 1785 cpu_present_setsize = 0; 1786 1787 CPU_FREE(cpu_affinity_set); 1788 cpu_affinity_set = NULL; 1789 cpu_affinity_setsize = 0; 1790 1791 free(thread_even); 1792 free(core_even); 1793 free(package_even); 1794 1795 thread_even = NULL; 1796 core_even = NULL; 1797 package_even = NULL; 1798 1799 free(thread_odd); 1800 free(core_odd); 1801 free(package_odd); 1802 1803 thread_odd = NULL; 1804 core_odd = NULL; 1805 package_odd = NULL; 1806 1807 free(output_buffer); 1808 output_buffer = NULL; 1809 outp = NULL; 1810 1811 free_fd_percpu(); 1812 1813 free(irq_column_2_cpu); 1814 free(irqs_per_cpu); 1815 } 1816 1817 /* 1818 * Open a file, and exit on failure 1819 */ 1820 FILE *fopen_or_die(const char *path, const char *mode) 1821 { 1822 FILE *filep = fopen(path, mode); 1823 if (!filep) 1824 err(1, "%s: open failed", path); 1825 return filep; 1826 } 1827 1828 /* 1829 * Parse a file containing a single int. 1830 */ 1831 int parse_int_file(const char *fmt, ...) 1832 { 1833 va_list args; 1834 char path[PATH_MAX]; 1835 FILE *filep; 1836 int value; 1837 1838 va_start(args, fmt); 1839 vsnprintf(path, sizeof(path), fmt, args); 1840 va_end(args); 1841 filep = fopen_or_die(path, "r"); 1842 if (fscanf(filep, "%d", &value) != 1) 1843 err(1, "%s: failed to parse number from file", path); 1844 fclose(filep); 1845 return value; 1846 } 1847 1848 /* 1849 * get_cpu_position_in_core(cpu) 1850 * return the position of the CPU among its HT siblings in the core 1851 * return -1 if the sibling is not in list 1852 */ 1853 int get_cpu_position_in_core(int cpu) 1854 { 1855 char path[64]; 1856 FILE *filep; 1857 int this_cpu; 1858 char character; 1859 int i; 1860 1861 sprintf(path, 1862 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", 1863 cpu); 1864 filep = fopen(path, "r"); 1865 if (filep == NULL) { 1866 perror(path); 1867 exit(1); 1868 } 1869 1870 for (i = 0; i < topo.num_threads_per_core; i++) { 1871 fscanf(filep, "%d", &this_cpu); 1872 if (this_cpu == cpu) { 1873 fclose(filep); 1874 return i; 1875 } 1876 1877 /* Account for no separator after last thread*/ 1878 if (i != (topo.num_threads_per_core - 1)) 1879 fscanf(filep, "%c", &character); 1880 } 1881 1882 fclose(filep); 1883 return -1; 1884 } 1885 1886 /* 1887 * cpu_is_first_core_in_package(cpu) 1888 * return 1 if given CPU is 1st core in package 1889 */ 1890 int cpu_is_first_core_in_package(int cpu) 1891 { 1892 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); 1893 } 1894 1895 int get_physical_package_id(int cpu) 1896 { 1897 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); 1898 } 1899 1900 int get_core_id(int cpu) 1901 { 1902 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); 1903 } 1904 1905 int get_num_ht_siblings(int cpu) 1906 { 1907 char path[80]; 1908 FILE *filep; 1909 int sib1; 1910 int matches = 0; 1911 char character; 1912 char str[100]; 1913 char *ch; 1914 1915 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", cpu); 1916 filep = fopen_or_die(path, "r"); 1917 1918 /* 1919 * file format: 1920 * A ',' separated or '-' separated set of numbers 1921 * (eg 1-2 or 1,3,4,5) 1922 */ 1923 fscanf(filep, "%d%c\n", &sib1, &character); 1924 fseek(filep, 0, SEEK_SET); 1925 fgets(str, 100, filep); 1926 ch = strchr(str, character); 1927 while (ch != NULL) { 1928 matches++; 1929 ch = strchr(ch+1, character); 1930 } 1931 1932 fclose(filep); 1933 return matches+1; 1934 } 1935 1936 /* 1937 * run func(thread, core, package) in topology order 1938 * skip non-present cpus 1939 */ 1940 1941 int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *, 1942 struct pkg_data *, struct thread_data *, struct core_data *, 1943 struct pkg_data *), struct thread_data *thread_base, 1944 struct core_data *core_base, struct pkg_data *pkg_base, 1945 struct thread_data *thread_base2, struct core_data *core_base2, 1946 struct pkg_data *pkg_base2) 1947 { 1948 int retval, pkg_no, core_no, thread_no; 1949 1950 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 1951 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) { 1952 for (thread_no = 0; thread_no < 1953 topo.num_threads_per_core; ++thread_no) { 1954 struct thread_data *t, *t2; 1955 struct core_data *c, *c2; 1956 struct pkg_data *p, *p2; 1957 1958 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no); 1959 1960 if (cpu_is_not_present(t->cpu_id)) 1961 continue; 1962 1963 t2 = GET_THREAD(thread_base2, thread_no, core_no, pkg_no); 1964 1965 c = GET_CORE(core_base, core_no, pkg_no); 1966 c2 = GET_CORE(core_base2, core_no, pkg_no); 1967 1968 p = GET_PKG(pkg_base, pkg_no); 1969 p2 = GET_PKG(pkg_base2, pkg_no); 1970 1971 retval = func(t, c, p, t2, c2, p2); 1972 if (retval) 1973 return retval; 1974 } 1975 } 1976 } 1977 return 0; 1978 } 1979 1980 /* 1981 * run func(cpu) on every cpu in /proc/stat 1982 * return max_cpu number 1983 */ 1984 int for_all_proc_cpus(int (func)(int)) 1985 { 1986 FILE *fp; 1987 int cpu_num; 1988 int retval; 1989 1990 fp = fopen_or_die(proc_stat, "r"); 1991 1992 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); 1993 if (retval != 0) 1994 err(1, "%s: failed to parse format", proc_stat); 1995 1996 while (1) { 1997 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); 1998 if (retval != 1) 1999 break; 2000 2001 retval = func(cpu_num); 2002 if (retval) { 2003 fclose(fp); 2004 return(retval); 2005 } 2006 } 2007 fclose(fp); 2008 return 0; 2009 } 2010 2011 void re_initialize(void) 2012 { 2013 free_all_buffers(); 2014 setup_all_buffers(); 2015 printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); 2016 } 2017 2018 2019 /* 2020 * count_cpus() 2021 * remember the last one seen, it will be the max 2022 */ 2023 int count_cpus(int cpu) 2024 { 2025 if (topo.max_cpu_num < cpu) 2026 topo.max_cpu_num = cpu; 2027 2028 topo.num_cpus += 1; 2029 return 0; 2030 } 2031 int mark_cpu_present(int cpu) 2032 { 2033 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); 2034 return 0; 2035 } 2036 2037 /* 2038 * snapshot_proc_interrupts() 2039 * 2040 * read and record summary of /proc/interrupts 2041 * 2042 * return 1 if config change requires a restart, else return 0 2043 */ 2044 int snapshot_proc_interrupts(void) 2045 { 2046 static FILE *fp; 2047 int column, retval; 2048 2049 if (fp == NULL) 2050 fp = fopen_or_die("/proc/interrupts", "r"); 2051 else 2052 rewind(fp); 2053 2054 /* read 1st line of /proc/interrupts to get cpu* name for each column */ 2055 for (column = 0; column < topo.num_cpus; ++column) { 2056 int cpu_number; 2057 2058 retval = fscanf(fp, " CPU%d", &cpu_number); 2059 if (retval != 1) 2060 break; 2061 2062 if (cpu_number > topo.max_cpu_num) { 2063 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); 2064 return 1; 2065 } 2066 2067 irq_column_2_cpu[column] = cpu_number; 2068 irqs_per_cpu[cpu_number] = 0; 2069 } 2070 2071 /* read /proc/interrupt count lines and sum up irqs per cpu */ 2072 while (1) { 2073 int column; 2074 char buf[64]; 2075 2076 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ 2077 if (retval != 1) 2078 break; 2079 2080 /* read the count per cpu */ 2081 for (column = 0; column < topo.num_cpus; ++column) { 2082 2083 int cpu_number, irq_count; 2084 2085 retval = fscanf(fp, " %d", &irq_count); 2086 if (retval != 1) 2087 break; 2088 2089 cpu_number = irq_column_2_cpu[column]; 2090 irqs_per_cpu[cpu_number] += irq_count; 2091 2092 } 2093 2094 while (getc(fp) != '\n') 2095 ; /* flush interrupt description */ 2096 2097 } 2098 return 0; 2099 } 2100 /* 2101 * snapshot_gfx_rc6_ms() 2102 * 2103 * record snapshot of 2104 * /sys/class/drm/card0/power/rc6_residency_ms 2105 * 2106 * return 1 if config change requires a restart, else return 0 2107 */ 2108 int snapshot_gfx_rc6_ms(void) 2109 { 2110 FILE *fp; 2111 int retval; 2112 2113 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); 2114 2115 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); 2116 if (retval != 1) 2117 err(1, "GFX rc6"); 2118 2119 fclose(fp); 2120 2121 return 0; 2122 } 2123 /* 2124 * snapshot_gfx_mhz() 2125 * 2126 * record snapshot of 2127 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz 2128 * 2129 * return 1 if config change requires a restart, else return 0 2130 */ 2131 int snapshot_gfx_mhz(void) 2132 { 2133 static FILE *fp; 2134 int retval; 2135 2136 if (fp == NULL) 2137 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); 2138 else 2139 rewind(fp); 2140 2141 retval = fscanf(fp, "%d", &gfx_cur_mhz); 2142 if (retval != 1) 2143 err(1, "GFX MHz"); 2144 2145 return 0; 2146 } 2147 2148 /* 2149 * snapshot /proc and /sys files 2150 * 2151 * return 1 if configuration restart needed, else return 0 2152 */ 2153 int snapshot_proc_sysfs_files(void) 2154 { 2155 if (snapshot_proc_interrupts()) 2156 return 1; 2157 2158 if (do_gfx_rc6_ms) 2159 snapshot_gfx_rc6_ms(); 2160 2161 if (do_gfx_mhz) 2162 snapshot_gfx_mhz(); 2163 2164 return 0; 2165 } 2166 2167 void turbostat_loop() 2168 { 2169 int retval; 2170 int restarted = 0; 2171 2172 restart: 2173 restarted++; 2174 2175 snapshot_proc_sysfs_files(); 2176 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 2177 if (retval < -1) { 2178 exit(retval); 2179 } else if (retval == -1) { 2180 if (restarted > 1) { 2181 exit(retval); 2182 } 2183 re_initialize(); 2184 goto restart; 2185 } 2186 restarted = 0; 2187 gettimeofday(&tv_even, (struct timezone *)NULL); 2188 2189 while (1) { 2190 if (for_all_proc_cpus(cpu_is_not_present)) { 2191 re_initialize(); 2192 goto restart; 2193 } 2194 nanosleep(&interval_ts, NULL); 2195 if (snapshot_proc_sysfs_files()) 2196 goto restart; 2197 retval = for_all_cpus(get_counters, ODD_COUNTERS); 2198 if (retval < -1) { 2199 exit(retval); 2200 } else if (retval == -1) { 2201 re_initialize(); 2202 goto restart; 2203 } 2204 gettimeofday(&tv_odd, (struct timezone *)NULL); 2205 timersub(&tv_odd, &tv_even, &tv_delta); 2206 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) { 2207 re_initialize(); 2208 goto restart; 2209 } 2210 compute_average(EVEN_COUNTERS); 2211 format_all_counters(EVEN_COUNTERS); 2212 flush_output_stdout(); 2213 nanosleep(&interval_ts, NULL); 2214 if (snapshot_proc_sysfs_files()) 2215 goto restart; 2216 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 2217 if (retval < -1) { 2218 exit(retval); 2219 } else if (retval == -1) { 2220 re_initialize(); 2221 goto restart; 2222 } 2223 gettimeofday(&tv_even, (struct timezone *)NULL); 2224 timersub(&tv_even, &tv_odd, &tv_delta); 2225 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) { 2226 re_initialize(); 2227 goto restart; 2228 } 2229 compute_average(ODD_COUNTERS); 2230 format_all_counters(ODD_COUNTERS); 2231 flush_output_stdout(); 2232 } 2233 } 2234 2235 void check_dev_msr() 2236 { 2237 struct stat sb; 2238 char pathname[32]; 2239 2240 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 2241 if (stat(pathname, &sb)) 2242 if (system("/sbin/modprobe msr > /dev/null 2>&1")) 2243 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); 2244 } 2245 2246 void check_permissions() 2247 { 2248 struct __user_cap_header_struct cap_header_data; 2249 cap_user_header_t cap_header = &cap_header_data; 2250 struct __user_cap_data_struct cap_data_data; 2251 cap_user_data_t cap_data = &cap_data_data; 2252 extern int capget(cap_user_header_t hdrp, cap_user_data_t datap); 2253 int do_exit = 0; 2254 char pathname[32]; 2255 2256 /* check for CAP_SYS_RAWIO */ 2257 cap_header->pid = getpid(); 2258 cap_header->version = _LINUX_CAPABILITY_VERSION; 2259 if (capget(cap_header, cap_data) < 0) 2260 err(-6, "capget(2) failed"); 2261 2262 if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) { 2263 do_exit++; 2264 warnx("capget(CAP_SYS_RAWIO) failed," 2265 " try \"# setcap cap_sys_rawio=ep %s\"", progname); 2266 } 2267 2268 /* test file permissions */ 2269 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 2270 if (euidaccess(pathname, R_OK)) { 2271 do_exit++; 2272 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); 2273 } 2274 2275 /* if all else fails, thell them to be root */ 2276 if (do_exit) 2277 if (getuid() != 0) 2278 warnx("... or simply run as root"); 2279 2280 if (do_exit) 2281 exit(-6); 2282 } 2283 2284 /* 2285 * NHM adds support for additional MSRs: 2286 * 2287 * MSR_SMI_COUNT 0x00000034 2288 * 2289 * MSR_PLATFORM_INFO 0x000000ce 2290 * MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 2291 * 2292 * MSR_PKG_C3_RESIDENCY 0x000003f8 2293 * MSR_PKG_C6_RESIDENCY 0x000003f9 2294 * MSR_CORE_C3_RESIDENCY 0x000003fc 2295 * MSR_CORE_C6_RESIDENCY 0x000003fd 2296 * 2297 * Side effect: 2298 * sets global pkg_cstate_limit to decode MSR_NHM_SNB_PKG_CST_CFG_CTL 2299 */ 2300 int probe_nhm_msrs(unsigned int family, unsigned int model) 2301 { 2302 unsigned long long msr; 2303 unsigned int base_ratio; 2304 int *pkg_cstate_limits; 2305 2306 if (!genuine_intel) 2307 return 0; 2308 2309 if (family != 6) 2310 return 0; 2311 2312 bclk = discover_bclk(family, model); 2313 2314 switch (model) { 2315 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ 2316 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 2317 case 0x1F: /* Core i7 and i5 Processor - Nehalem */ 2318 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */ 2319 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */ 2320 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 2321 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 2322 pkg_cstate_limits = nhm_pkg_cstate_limits; 2323 break; 2324 case INTEL_FAM6_SANDYBRIDGE: /* SNB */ 2325 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */ 2326 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 2327 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 2328 pkg_cstate_limits = snb_pkg_cstate_limits; 2329 break; 2330 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 2331 case INTEL_FAM6_HASWELL_X: /* HSX */ 2332 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 2333 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 2334 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 2335 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 2336 case INTEL_FAM6_BROADWELL_X: /* BDX */ 2337 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 2338 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 2339 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 2340 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 2341 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 2342 pkg_cstate_limits = hsw_pkg_cstate_limits; 2343 break; 2344 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 2345 pkg_cstate_limits = skx_pkg_cstate_limits; 2346 break; 2347 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ 2348 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ 2349 pkg_cstate_limits = slv_pkg_cstate_limits; 2350 break; 2351 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */ 2352 pkg_cstate_limits = amt_pkg_cstate_limits; 2353 break; 2354 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */ 2355 case INTEL_FAM6_XEON_PHI_KNM: 2356 pkg_cstate_limits = phi_pkg_cstate_limits; 2357 break; 2358 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 2359 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 2360 pkg_cstate_limits = bxt_pkg_cstate_limits; 2361 break; 2362 default: 2363 return 0; 2364 } 2365 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr); 2366 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; 2367 2368 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 2369 base_ratio = (msr >> 8) & 0xFF; 2370 2371 base_hz = base_ratio * bclk * 1000000; 2372 has_base_hz = 1; 2373 return 1; 2374 } 2375 int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model) 2376 { 2377 switch (model) { 2378 /* Nehalem compatible, but do not include turbo-ratio limit support */ 2379 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 2380 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 2381 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */ 2382 case INTEL_FAM6_XEON_PHI_KNM: 2383 return 0; 2384 default: 2385 return 1; 2386 } 2387 } 2388 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) 2389 { 2390 if (!genuine_intel) 2391 return 0; 2392 2393 if (family != 6) 2394 return 0; 2395 2396 switch (model) { 2397 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 2398 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 2399 return 1; 2400 default: 2401 return 0; 2402 } 2403 } 2404 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) 2405 { 2406 if (!genuine_intel) 2407 return 0; 2408 2409 if (family != 6) 2410 return 0; 2411 2412 switch (model) { 2413 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 2414 return 1; 2415 default: 2416 return 0; 2417 } 2418 } 2419 2420 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) 2421 { 2422 if (!genuine_intel) 2423 return 0; 2424 2425 if (family != 6) 2426 return 0; 2427 2428 switch (model) { 2429 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 2430 case INTEL_FAM6_XEON_PHI_KNM: 2431 return 1; 2432 default: 2433 return 0; 2434 } 2435 } 2436 int has_config_tdp(unsigned int family, unsigned int model) 2437 { 2438 if (!genuine_intel) 2439 return 0; 2440 2441 if (family != 6) 2442 return 0; 2443 2444 switch (model) { 2445 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 2446 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 2447 case INTEL_FAM6_HASWELL_X: /* HSX */ 2448 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 2449 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 2450 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 2451 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 2452 case INTEL_FAM6_BROADWELL_X: /* BDX */ 2453 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 2454 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 2455 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 2456 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 2457 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 2458 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 2459 2460 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 2461 case INTEL_FAM6_XEON_PHI_KNM: 2462 return 1; 2463 default: 2464 return 0; 2465 } 2466 } 2467 2468 static void 2469 dump_cstate_pstate_config_info(unsigned int family, unsigned int model) 2470 { 2471 if (!do_nhm_platform_info) 2472 return; 2473 2474 dump_nhm_platform_info(); 2475 2476 if (has_hsw_turbo_ratio_limit(family, model)) 2477 dump_hsw_turbo_ratio_limits(); 2478 2479 if (has_ivt_turbo_ratio_limit(family, model)) 2480 dump_ivt_turbo_ratio_limits(); 2481 2482 if (has_nhm_turbo_ratio_limit(family, model)) 2483 dump_nhm_turbo_ratio_limits(); 2484 2485 if (has_knl_turbo_ratio_limit(family, model)) 2486 dump_knl_turbo_ratio_limits(); 2487 2488 if (has_config_tdp(family, model)) 2489 dump_config_tdp(); 2490 2491 dump_nhm_cst_cfg(); 2492 } 2493 2494 2495 /* 2496 * print_epb() 2497 * Decode the ENERGY_PERF_BIAS MSR 2498 */ 2499 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2500 { 2501 unsigned long long msr; 2502 char *epb_string; 2503 int cpu; 2504 2505 if (!has_epb) 2506 return 0; 2507 2508 cpu = t->cpu_id; 2509 2510 /* EPB is per-package */ 2511 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2512 return 0; 2513 2514 if (cpu_migrate(cpu)) { 2515 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2516 return -1; 2517 } 2518 2519 if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr)) 2520 return 0; 2521 2522 switch (msr & 0xF) { 2523 case ENERGY_PERF_BIAS_PERFORMANCE: 2524 epb_string = "performance"; 2525 break; 2526 case ENERGY_PERF_BIAS_NORMAL: 2527 epb_string = "balanced"; 2528 break; 2529 case ENERGY_PERF_BIAS_POWERSAVE: 2530 epb_string = "powersave"; 2531 break; 2532 default: 2533 epb_string = "custom"; 2534 break; 2535 } 2536 fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string); 2537 2538 return 0; 2539 } 2540 /* 2541 * print_hwp() 2542 * Decode the MSR_HWP_CAPABILITIES 2543 */ 2544 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2545 { 2546 unsigned long long msr; 2547 int cpu; 2548 2549 if (!has_hwp) 2550 return 0; 2551 2552 cpu = t->cpu_id; 2553 2554 /* MSR_HWP_CAPABILITIES is per-package */ 2555 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2556 return 0; 2557 2558 if (cpu_migrate(cpu)) { 2559 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2560 return -1; 2561 } 2562 2563 if (get_msr(cpu, MSR_PM_ENABLE, &msr)) 2564 return 0; 2565 2566 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", 2567 cpu, msr, (msr & (1 << 0)) ? "" : "No-"); 2568 2569 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ 2570 if ((msr & (1 << 0)) == 0) 2571 return 0; 2572 2573 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) 2574 return 0; 2575 2576 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " 2577 "(high 0x%x guar 0x%x eff 0x%x low 0x%x)\n", 2578 cpu, msr, 2579 (unsigned int)HWP_HIGHEST_PERF(msr), 2580 (unsigned int)HWP_GUARANTEED_PERF(msr), 2581 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), 2582 (unsigned int)HWP_LOWEST_PERF(msr)); 2583 2584 if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) 2585 return 0; 2586 2587 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " 2588 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x pkg 0x%x)\n", 2589 cpu, msr, 2590 (unsigned int)(((msr) >> 0) & 0xff), 2591 (unsigned int)(((msr) >> 8) & 0xff), 2592 (unsigned int)(((msr) >> 16) & 0xff), 2593 (unsigned int)(((msr) >> 24) & 0xff), 2594 (unsigned int)(((msr) >> 32) & 0xff3), 2595 (unsigned int)(((msr) >> 42) & 0x1)); 2596 2597 if (has_hwp_pkg) { 2598 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) 2599 return 0; 2600 2601 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " 2602 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x)\n", 2603 cpu, msr, 2604 (unsigned int)(((msr) >> 0) & 0xff), 2605 (unsigned int)(((msr) >> 8) & 0xff), 2606 (unsigned int)(((msr) >> 16) & 0xff), 2607 (unsigned int)(((msr) >> 24) & 0xff), 2608 (unsigned int)(((msr) >> 32) & 0xff3)); 2609 } 2610 if (has_hwp_notify) { 2611 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) 2612 return 0; 2613 2614 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " 2615 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", 2616 cpu, msr, 2617 ((msr) & 0x1) ? "EN" : "Dis", 2618 ((msr) & 0x2) ? "EN" : "Dis"); 2619 } 2620 if (get_msr(cpu, MSR_HWP_STATUS, &msr)) 2621 return 0; 2622 2623 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " 2624 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", 2625 cpu, msr, 2626 ((msr) & 0x1) ? "" : "No-", 2627 ((msr) & 0x2) ? "" : "No-"); 2628 2629 return 0; 2630 } 2631 2632 /* 2633 * print_perf_limit() 2634 */ 2635 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2636 { 2637 unsigned long long msr; 2638 int cpu; 2639 2640 cpu = t->cpu_id; 2641 2642 /* per-package */ 2643 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2644 return 0; 2645 2646 if (cpu_migrate(cpu)) { 2647 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2648 return -1; 2649 } 2650 2651 if (do_core_perf_limit_reasons) { 2652 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); 2653 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 2654 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", 2655 (msr & 1 << 15) ? "bit15, " : "", 2656 (msr & 1 << 14) ? "bit14, " : "", 2657 (msr & 1 << 13) ? "Transitions, " : "", 2658 (msr & 1 << 12) ? "MultiCoreTurbo, " : "", 2659 (msr & 1 << 11) ? "PkgPwrL2, " : "", 2660 (msr & 1 << 10) ? "PkgPwrL1, " : "", 2661 (msr & 1 << 9) ? "CorePwr, " : "", 2662 (msr & 1 << 8) ? "Amps, " : "", 2663 (msr & 1 << 6) ? "VR-Therm, " : "", 2664 (msr & 1 << 5) ? "Auto-HWP, " : "", 2665 (msr & 1 << 4) ? "Graphics, " : "", 2666 (msr & 1 << 2) ? "bit2, " : "", 2667 (msr & 1 << 1) ? "ThermStatus, " : "", 2668 (msr & 1 << 0) ? "PROCHOT, " : ""); 2669 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 2670 (msr & 1 << 31) ? "bit31, " : "", 2671 (msr & 1 << 30) ? "bit30, " : "", 2672 (msr & 1 << 29) ? "Transitions, " : "", 2673 (msr & 1 << 28) ? "MultiCoreTurbo, " : "", 2674 (msr & 1 << 27) ? "PkgPwrL2, " : "", 2675 (msr & 1 << 26) ? "PkgPwrL1, " : "", 2676 (msr & 1 << 25) ? "CorePwr, " : "", 2677 (msr & 1 << 24) ? "Amps, " : "", 2678 (msr & 1 << 22) ? "VR-Therm, " : "", 2679 (msr & 1 << 21) ? "Auto-HWP, " : "", 2680 (msr & 1 << 20) ? "Graphics, " : "", 2681 (msr & 1 << 18) ? "bit18, " : "", 2682 (msr & 1 << 17) ? "ThermStatus, " : "", 2683 (msr & 1 << 16) ? "PROCHOT, " : ""); 2684 2685 } 2686 if (do_gfx_perf_limit_reasons) { 2687 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); 2688 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 2689 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", 2690 (msr & 1 << 0) ? "PROCHOT, " : "", 2691 (msr & 1 << 1) ? "ThermStatus, " : "", 2692 (msr & 1 << 4) ? "Graphics, " : "", 2693 (msr & 1 << 6) ? "VR-Therm, " : "", 2694 (msr & 1 << 8) ? "Amps, " : "", 2695 (msr & 1 << 9) ? "GFXPwr, " : "", 2696 (msr & 1 << 10) ? "PkgPwrL1, " : "", 2697 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 2698 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", 2699 (msr & 1 << 16) ? "PROCHOT, " : "", 2700 (msr & 1 << 17) ? "ThermStatus, " : "", 2701 (msr & 1 << 20) ? "Graphics, " : "", 2702 (msr & 1 << 22) ? "VR-Therm, " : "", 2703 (msr & 1 << 24) ? "Amps, " : "", 2704 (msr & 1 << 25) ? "GFXPwr, " : "", 2705 (msr & 1 << 26) ? "PkgPwrL1, " : "", 2706 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 2707 } 2708 if (do_ring_perf_limit_reasons) { 2709 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); 2710 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 2711 fprintf(outf, " (Active: %s%s%s%s%s%s)", 2712 (msr & 1 << 0) ? "PROCHOT, " : "", 2713 (msr & 1 << 1) ? "ThermStatus, " : "", 2714 (msr & 1 << 6) ? "VR-Therm, " : "", 2715 (msr & 1 << 8) ? "Amps, " : "", 2716 (msr & 1 << 10) ? "PkgPwrL1, " : "", 2717 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 2718 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", 2719 (msr & 1 << 16) ? "PROCHOT, " : "", 2720 (msr & 1 << 17) ? "ThermStatus, " : "", 2721 (msr & 1 << 22) ? "VR-Therm, " : "", 2722 (msr & 1 << 24) ? "Amps, " : "", 2723 (msr & 1 << 26) ? "PkgPwrL1, " : "", 2724 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 2725 } 2726 return 0; 2727 } 2728 2729 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ 2730 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ 2731 2732 double get_tdp(unsigned int model) 2733 { 2734 unsigned long long msr; 2735 2736 if (do_rapl & RAPL_PKG_POWER_INFO) 2737 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) 2738 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; 2739 2740 switch (model) { 2741 case INTEL_FAM6_ATOM_SILVERMONT1: 2742 case INTEL_FAM6_ATOM_SILVERMONT2: 2743 return 30.0; 2744 default: 2745 return 135.0; 2746 } 2747 } 2748 2749 /* 2750 * rapl_dram_energy_units_probe() 2751 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR. 2752 */ 2753 static double 2754 rapl_dram_energy_units_probe(int model, double rapl_energy_units) 2755 { 2756 /* only called for genuine_intel, family 6 */ 2757 2758 switch (model) { 2759 case INTEL_FAM6_HASWELL_X: /* HSX */ 2760 case INTEL_FAM6_BROADWELL_X: /* BDX */ 2761 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 2762 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 2763 case INTEL_FAM6_XEON_PHI_KNM: 2764 return (rapl_dram_energy_units = 15.3 / 1000000); 2765 default: 2766 return (rapl_energy_units); 2767 } 2768 } 2769 2770 2771 /* 2772 * rapl_probe() 2773 * 2774 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units 2775 */ 2776 void rapl_probe(unsigned int family, unsigned int model) 2777 { 2778 unsigned long long msr; 2779 unsigned int time_unit; 2780 double tdp; 2781 2782 if (!genuine_intel) 2783 return; 2784 2785 if (family != 6) 2786 return; 2787 2788 switch (model) { 2789 case INTEL_FAM6_SANDYBRIDGE: 2790 case INTEL_FAM6_IVYBRIDGE: 2791 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 2792 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 2793 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 2794 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 2795 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 2796 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; 2797 break; 2798 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 2799 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; 2800 break; 2801 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 2802 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 2803 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 2804 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 2805 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 2806 break; 2807 case INTEL_FAM6_HASWELL_X: /* HSX */ 2808 case INTEL_FAM6_BROADWELL_X: /* BDX */ 2809 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 2810 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 2811 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 2812 case INTEL_FAM6_XEON_PHI_KNM: 2813 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 2814 break; 2815 case INTEL_FAM6_SANDYBRIDGE_X: 2816 case INTEL_FAM6_IVYBRIDGE_X: 2817 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; 2818 break; 2819 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ 2820 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ 2821 do_rapl = RAPL_PKG | RAPL_CORES; 2822 break; 2823 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 2824 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS; 2825 break; 2826 default: 2827 return; 2828 } 2829 2830 /* units on package 0, verify later other packages match */ 2831 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) 2832 return; 2833 2834 rapl_power_units = 1.0 / (1 << (msr & 0xF)); 2835 if (model == INTEL_FAM6_ATOM_SILVERMONT1) 2836 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; 2837 else 2838 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 2839 2840 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units); 2841 2842 time_unit = msr >> 16 & 0xF; 2843 if (time_unit == 0) 2844 time_unit = 0xA; 2845 2846 rapl_time_units = 1.0 / (1 << (time_unit)); 2847 2848 tdp = get_tdp(model); 2849 2850 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 2851 if (debug) 2852 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 2853 2854 return; 2855 } 2856 2857 void perf_limit_reasons_probe(unsigned int family, unsigned int model) 2858 { 2859 if (!genuine_intel) 2860 return; 2861 2862 if (family != 6) 2863 return; 2864 2865 switch (model) { 2866 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 2867 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 2868 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 2869 do_gfx_perf_limit_reasons = 1; 2870 case INTEL_FAM6_HASWELL_X: /* HSX */ 2871 do_core_perf_limit_reasons = 1; 2872 do_ring_perf_limit_reasons = 1; 2873 default: 2874 return; 2875 } 2876 } 2877 2878 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2879 { 2880 unsigned long long msr; 2881 unsigned int dts; 2882 int cpu; 2883 2884 if (!(do_dts || do_ptm)) 2885 return 0; 2886 2887 cpu = t->cpu_id; 2888 2889 /* DTS is per-core, no need to print for each thread */ 2890 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 2891 return 0; 2892 2893 if (cpu_migrate(cpu)) { 2894 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2895 return -1; 2896 } 2897 2898 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { 2899 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 2900 return 0; 2901 2902 dts = (msr >> 16) & 0x7F; 2903 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", 2904 cpu, msr, tcc_activation_temp - dts); 2905 2906 #ifdef THERM_DEBUG 2907 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) 2908 return 0; 2909 2910 dts = (msr >> 16) & 0x7F; 2911 dts2 = (msr >> 8) & 0x7F; 2912 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 2913 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 2914 #endif 2915 } 2916 2917 2918 if (do_dts) { 2919 unsigned int resolution; 2920 2921 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 2922 return 0; 2923 2924 dts = (msr >> 16) & 0x7F; 2925 resolution = (msr >> 27) & 0xF; 2926 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", 2927 cpu, msr, tcc_activation_temp - dts, resolution); 2928 2929 #ifdef THERM_DEBUG 2930 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) 2931 return 0; 2932 2933 dts = (msr >> 16) & 0x7F; 2934 dts2 = (msr >> 8) & 0x7F; 2935 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 2936 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 2937 #endif 2938 } 2939 2940 return 0; 2941 } 2942 2943 void print_power_limit_msr(int cpu, unsigned long long msr, char *label) 2944 { 2945 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n", 2946 cpu, label, 2947 ((msr >> 15) & 1) ? "EN" : "DIS", 2948 ((msr >> 0) & 0x7FFF) * rapl_power_units, 2949 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, 2950 (((msr >> 16) & 1) ? "EN" : "DIS")); 2951 2952 return; 2953 } 2954 2955 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 2956 { 2957 unsigned long long msr; 2958 int cpu; 2959 2960 if (!do_rapl) 2961 return 0; 2962 2963 /* RAPL counters are per package, so print only for 1st thread/package */ 2964 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 2965 return 0; 2966 2967 cpu = t->cpu_id; 2968 if (cpu_migrate(cpu)) { 2969 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 2970 return -1; 2971 } 2972 2973 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) 2974 return -1; 2975 2976 if (debug) { 2977 fprintf(outf, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx " 2978 "(%f Watts, %f Joules, %f sec.)\n", cpu, msr, 2979 rapl_power_units, rapl_energy_units, rapl_time_units); 2980 } 2981 if (do_rapl & RAPL_PKG_POWER_INFO) { 2982 2983 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) 2984 return -5; 2985 2986 2987 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 2988 cpu, msr, 2989 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 2990 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 2991 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 2992 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 2993 2994 } 2995 if (do_rapl & RAPL_PKG) { 2996 2997 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) 2998 return -9; 2999 3000 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", 3001 cpu, msr, (msr >> 63) & 1 ? "": "UN"); 3002 3003 print_power_limit_msr(cpu, msr, "PKG Limit #1"); 3004 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n", 3005 cpu, 3006 ((msr >> 47) & 1) ? "EN" : "DIS", 3007 ((msr >> 32) & 0x7FFF) * rapl_power_units, 3008 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, 3009 ((msr >> 48) & 1) ? "EN" : "DIS"); 3010 } 3011 3012 if (do_rapl & RAPL_DRAM_POWER_INFO) { 3013 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) 3014 return -6; 3015 3016 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 3017 cpu, msr, 3018 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3019 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3020 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 3021 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 3022 } 3023 if (do_rapl & RAPL_DRAM) { 3024 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) 3025 return -9; 3026 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", 3027 cpu, msr, (msr >> 31) & 1 ? "": "UN"); 3028 3029 print_power_limit_msr(cpu, msr, "DRAM Limit"); 3030 } 3031 if (do_rapl & RAPL_CORE_POLICY) { 3032 if (debug) { 3033 if (get_msr(cpu, MSR_PP0_POLICY, &msr)) 3034 return -7; 3035 3036 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); 3037 } 3038 } 3039 if (do_rapl & RAPL_CORES_POWER_LIMIT) { 3040 if (debug) { 3041 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) 3042 return -9; 3043 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", 3044 cpu, msr, (msr >> 31) & 1 ? "": "UN"); 3045 print_power_limit_msr(cpu, msr, "Cores Limit"); 3046 } 3047 } 3048 if (do_rapl & RAPL_GFX) { 3049 if (debug) { 3050 if (get_msr(cpu, MSR_PP1_POLICY, &msr)) 3051 return -8; 3052 3053 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); 3054 3055 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) 3056 return -9; 3057 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", 3058 cpu, msr, (msr >> 31) & 1 ? "": "UN"); 3059 print_power_limit_msr(cpu, msr, "GFX Limit"); 3060 } 3061 } 3062 return 0; 3063 } 3064 3065 /* 3066 * SNB adds support for additional MSRs: 3067 * 3068 * MSR_PKG_C7_RESIDENCY 0x000003fa 3069 * MSR_CORE_C7_RESIDENCY 0x000003fe 3070 * MSR_PKG_C2_RESIDENCY 0x0000060d 3071 */ 3072 3073 int has_snb_msrs(unsigned int family, unsigned int model) 3074 { 3075 if (!genuine_intel) 3076 return 0; 3077 3078 switch (model) { 3079 case INTEL_FAM6_SANDYBRIDGE: 3080 case INTEL_FAM6_SANDYBRIDGE_X: 3081 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3082 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3083 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3084 case INTEL_FAM6_HASWELL_X: /* HSW */ 3085 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3086 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3087 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3088 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3089 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3090 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 3091 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3092 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3093 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3094 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3095 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3096 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3097 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 3098 return 1; 3099 } 3100 return 0; 3101 } 3102 3103 /* 3104 * HSW adds support for additional MSRs: 3105 * 3106 * MSR_PKG_C8_RESIDENCY 0x00000630 3107 * MSR_PKG_C9_RESIDENCY 0x00000631 3108 * MSR_PKG_C10_RESIDENCY 0x00000632 3109 * 3110 * MSR_PKGC8_IRTL 0x00000633 3111 * MSR_PKGC9_IRTL 0x00000634 3112 * MSR_PKGC10_IRTL 0x00000635 3113 * 3114 */ 3115 int has_hsw_msrs(unsigned int family, unsigned int model) 3116 { 3117 if (!genuine_intel) 3118 return 0; 3119 3120 switch (model) { 3121 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3122 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3123 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3124 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3125 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3126 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3127 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3128 return 1; 3129 } 3130 return 0; 3131 } 3132 3133 /* 3134 * SKL adds support for additional MSRS: 3135 * 3136 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 3137 * MSR_PKG_ANY_CORE_C0_RES 0x00000659 3138 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 3139 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 3140 */ 3141 int has_skl_msrs(unsigned int family, unsigned int model) 3142 { 3143 if (!genuine_intel) 3144 return 0; 3145 3146 switch (model) { 3147 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3148 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3149 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3150 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3151 return 1; 3152 } 3153 return 0; 3154 } 3155 3156 3157 3158 int is_slm(unsigned int family, unsigned int model) 3159 { 3160 if (!genuine_intel) 3161 return 0; 3162 switch (model) { 3163 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ 3164 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ 3165 return 1; 3166 } 3167 return 0; 3168 } 3169 3170 int is_knl(unsigned int family, unsigned int model) 3171 { 3172 if (!genuine_intel) 3173 return 0; 3174 switch (model) { 3175 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 3176 case INTEL_FAM6_XEON_PHI_KNM: 3177 return 1; 3178 } 3179 return 0; 3180 } 3181 3182 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model) 3183 { 3184 if (is_knl(family, model)) 3185 return 1024; 3186 return 1; 3187 } 3188 3189 #define SLM_BCLK_FREQS 5 3190 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0}; 3191 3192 double slm_bclk(void) 3193 { 3194 unsigned long long msr = 3; 3195 unsigned int i; 3196 double freq; 3197 3198 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) 3199 fprintf(outf, "SLM BCLK: unknown\n"); 3200 3201 i = msr & 0xf; 3202 if (i >= SLM_BCLK_FREQS) { 3203 fprintf(outf, "SLM BCLK[%d] invalid\n", i); 3204 i = 3; 3205 } 3206 freq = slm_freq_table[i]; 3207 3208 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); 3209 3210 return freq; 3211 } 3212 3213 double discover_bclk(unsigned int family, unsigned int model) 3214 { 3215 if (has_snb_msrs(family, model) || is_knl(family, model)) 3216 return 100.00; 3217 else if (is_slm(family, model)) 3218 return slm_bclk(); 3219 else 3220 return 133.33; 3221 } 3222 3223 /* 3224 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where 3225 * the Thermal Control Circuit (TCC) activates. 3226 * This is usually equal to tjMax. 3227 * 3228 * Older processors do not have this MSR, so there we guess, 3229 * but also allow cmdline over-ride with -T. 3230 * 3231 * Several MSR temperature values are in units of degrees-C 3232 * below this value, including the Digital Thermal Sensor (DTS), 3233 * Package Thermal Management Sensor (PTM), and thermal event thresholds. 3234 */ 3235 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3236 { 3237 unsigned long long msr; 3238 unsigned int target_c_local; 3239 int cpu; 3240 3241 /* tcc_activation_temp is used only for dts or ptm */ 3242 if (!(do_dts || do_ptm)) 3243 return 0; 3244 3245 /* this is a per-package concept */ 3246 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3247 return 0; 3248 3249 cpu = t->cpu_id; 3250 if (cpu_migrate(cpu)) { 3251 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3252 return -1; 3253 } 3254 3255 if (tcc_activation_temp_override != 0) { 3256 tcc_activation_temp = tcc_activation_temp_override; 3257 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", 3258 cpu, tcc_activation_temp); 3259 return 0; 3260 } 3261 3262 /* Temperature Target MSR is Nehalem and newer only */ 3263 if (!do_nhm_platform_info) 3264 goto guess; 3265 3266 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) 3267 goto guess; 3268 3269 target_c_local = (msr >> 16) & 0xFF; 3270 3271 if (debug) 3272 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", 3273 cpu, msr, target_c_local); 3274 3275 if (!target_c_local) 3276 goto guess; 3277 3278 tcc_activation_temp = target_c_local; 3279 3280 return 0; 3281 3282 guess: 3283 tcc_activation_temp = TJMAX_DEFAULT; 3284 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", 3285 cpu, tcc_activation_temp); 3286 3287 return 0; 3288 } 3289 3290 void decode_feature_control_msr(void) 3291 { 3292 unsigned long long msr; 3293 3294 if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr)) 3295 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", 3296 base_cpu, msr, 3297 msr & FEATURE_CONTROL_LOCKED ? "" : "UN-", 3298 msr & (1 << 18) ? "SGX" : ""); 3299 } 3300 3301 void decode_misc_enable_msr(void) 3302 { 3303 unsigned long long msr; 3304 3305 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) 3306 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%s %s %s)\n", 3307 base_cpu, msr, 3308 msr & (1 << 3) ? "TCC" : "", 3309 msr & (1 << 16) ? "EIST" : "", 3310 msr & (1 << 18) ? "MONITOR" : ""); 3311 } 3312 3313 /* 3314 * Decode MSR_MISC_PWR_MGMT 3315 * 3316 * Decode the bits according to the Nehalem documentation 3317 * bit[0] seems to continue to have same meaning going forward 3318 * bit[1] less so... 3319 */ 3320 void decode_misc_pwr_mgmt_msr(void) 3321 { 3322 unsigned long long msr; 3323 3324 if (!do_nhm_platform_info) 3325 return; 3326 3327 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) 3328 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n", 3329 base_cpu, msr, 3330 msr & (1 << 0) ? "DIS" : "EN", 3331 msr & (1 << 1) ? "EN" : "DIS", 3332 msr & (1 << 8) ? "EN" : "DIS"); 3333 } 3334 3335 void process_cpuid() 3336 { 3337 unsigned int eax, ebx, ecx, edx, max_level, max_extended_level; 3338 unsigned int fms, family, model, stepping; 3339 3340 eax = ebx = ecx = edx = 0; 3341 3342 __cpuid(0, max_level, ebx, ecx, edx); 3343 3344 if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e) 3345 genuine_intel = 1; 3346 3347 if (debug) 3348 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ", 3349 (char *)&ebx, (char *)&edx, (char *)&ecx); 3350 3351 __cpuid(1, fms, ebx, ecx, edx); 3352 family = (fms >> 8) & 0xf; 3353 model = (fms >> 4) & 0xf; 3354 stepping = fms & 0xf; 3355 if (family == 6 || family == 0xf) 3356 model += ((fms >> 16) & 0xf) << 4; 3357 3358 if (debug) { 3359 fprintf(outf, "%d CPUID levels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n", 3360 max_level, family, model, stepping, family, model, stepping); 3361 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s\n", 3362 ecx & (1 << 0) ? "SSE3" : "-", 3363 ecx & (1 << 3) ? "MONITOR" : "-", 3364 ecx & (1 << 6) ? "SMX" : "-", 3365 ecx & (1 << 7) ? "EIST" : "-", 3366 ecx & (1 << 8) ? "TM2" : "-", 3367 edx & (1 << 4) ? "TSC" : "-", 3368 edx & (1 << 5) ? "MSR" : "-", 3369 edx & (1 << 22) ? "ACPI-TM" : "-", 3370 edx & (1 << 29) ? "TM" : "-"); 3371 } 3372 3373 if (!(edx & (1 << 5))) 3374 errx(1, "CPUID: no MSR"); 3375 3376 /* 3377 * check max extended function levels of CPUID. 3378 * This is needed to check for invariant TSC. 3379 * This check is valid for both Intel and AMD. 3380 */ 3381 ebx = ecx = edx = 0; 3382 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); 3383 3384 if (max_extended_level >= 0x80000007) { 3385 3386 /* 3387 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 3388 * this check is valid for both Intel and AMD 3389 */ 3390 __cpuid(0x80000007, eax, ebx, ecx, edx); 3391 has_invariant_tsc = edx & (1 << 8); 3392 } 3393 3394 /* 3395 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 3396 * this check is valid for both Intel and AMD 3397 */ 3398 3399 __cpuid(0x6, eax, ebx, ecx, edx); 3400 has_aperf = ecx & (1 << 0); 3401 do_dts = eax & (1 << 0); 3402 do_ptm = eax & (1 << 6); 3403 has_hwp = eax & (1 << 7); 3404 has_hwp_notify = eax & (1 << 8); 3405 has_hwp_activity_window = eax & (1 << 9); 3406 has_hwp_epp = eax & (1 << 10); 3407 has_hwp_pkg = eax & (1 << 11); 3408 has_epb = ecx & (1 << 3); 3409 3410 if (debug) 3411 fprintf(outf, "CPUID(6): %sAPERF, %sDTS, %sPTM, %sHWP, " 3412 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", 3413 has_aperf ? "" : "No-", 3414 do_dts ? "" : "No-", 3415 do_ptm ? "" : "No-", 3416 has_hwp ? "" : "No-", 3417 has_hwp_notify ? "" : "No-", 3418 has_hwp_activity_window ? "" : "No-", 3419 has_hwp_epp ? "" : "No-", 3420 has_hwp_pkg ? "" : "No-", 3421 has_epb ? "" : "No-"); 3422 3423 if (debug) 3424 decode_misc_enable_msr(); 3425 3426 if (max_level >= 0x7 && debug) { 3427 int has_sgx; 3428 3429 ecx = 0; 3430 3431 __cpuid_count(0x7, 0, eax, ebx, ecx, edx); 3432 3433 has_sgx = ebx & (1 << 2); 3434 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-"); 3435 3436 if (has_sgx) 3437 decode_feature_control_msr(); 3438 } 3439 3440 if (max_level >= 0x15) { 3441 unsigned int eax_crystal; 3442 unsigned int ebx_tsc; 3443 3444 /* 3445 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz 3446 */ 3447 eax_crystal = ebx_tsc = crystal_hz = edx = 0; 3448 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); 3449 3450 if (ebx_tsc != 0) { 3451 3452 if (debug && (ebx != 0)) 3453 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", 3454 eax_crystal, ebx_tsc, crystal_hz); 3455 3456 if (crystal_hz == 0) 3457 switch(model) { 3458 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3459 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3460 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3461 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3462 crystal_hz = 24000000; /* 24.0 MHz */ 3463 break; 3464 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3465 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 3466 crystal_hz = 25000000; /* 25.0 MHz */ 3467 break; 3468 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3469 crystal_hz = 19200000; /* 19.2 MHz */ 3470 break; 3471 default: 3472 crystal_hz = 0; 3473 } 3474 3475 if (crystal_hz) { 3476 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal; 3477 if (debug) 3478 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", 3479 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); 3480 } 3481 } 3482 } 3483 if (max_level >= 0x16) { 3484 unsigned int base_mhz, max_mhz, bus_mhz, edx; 3485 3486 /* 3487 * CPUID 16H Base MHz, Max MHz, Bus MHz 3488 */ 3489 base_mhz = max_mhz = bus_mhz = edx = 0; 3490 3491 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); 3492 if (debug) 3493 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", 3494 base_mhz, max_mhz, bus_mhz); 3495 } 3496 3497 if (has_aperf) 3498 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model); 3499 3500 do_nhm_platform_info = do_nhm_cstates = do_smi = probe_nhm_msrs(family, model); 3501 do_snb_cstates = has_snb_msrs(family, model); 3502 do_irtl_snb = has_snb_msrs(family, model); 3503 do_pc2 = do_snb_cstates && (pkg_cstate_limit >= PCL__2); 3504 do_pc3 = (pkg_cstate_limit >= PCL__3); 3505 do_pc6 = (pkg_cstate_limit >= PCL__6); 3506 do_pc7 = do_snb_cstates && (pkg_cstate_limit >= PCL__7); 3507 do_c8_c9_c10 = has_hsw_msrs(family, model); 3508 do_irtl_hsw = has_hsw_msrs(family, model); 3509 do_skl_residency = has_skl_msrs(family, model); 3510 do_slm_cstates = is_slm(family, model); 3511 do_knl_cstates = is_knl(family, model); 3512 3513 if (debug) 3514 decode_misc_pwr_mgmt_msr(); 3515 3516 rapl_probe(family, model); 3517 perf_limit_reasons_probe(family, model); 3518 3519 if (debug) 3520 dump_cstate_pstate_config_info(family, model); 3521 3522 if (has_skl_msrs(family, model)) 3523 calculate_tsc_tweak(); 3524 3525 do_gfx_rc6_ms = !access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK); 3526 3527 do_gfx_mhz = !access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK); 3528 3529 return; 3530 } 3531 3532 void help() 3533 { 3534 fprintf(outf, 3535 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" 3536 "\n" 3537 "Turbostat forks the specified COMMAND and prints statistics\n" 3538 "when COMMAND completes.\n" 3539 "If no COMMAND is specified, turbostat wakes every 5-seconds\n" 3540 "to print statistics, until interrupted.\n" 3541 "--add add a counter\n" 3542 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n" 3543 "--debug run in \"debug\" mode\n" 3544 "--interval sec Override default 5-second measurement interval\n" 3545 "--help print this help message\n" 3546 "--out file create or truncate \"file\" for all output\n" 3547 "--version print version information\n" 3548 "\n" 3549 "For more help, run \"man turbostat\"\n"); 3550 } 3551 3552 3553 /* 3554 * in /dev/cpu/ return success for names that are numbers 3555 * ie. filter out ".", "..", "microcode". 3556 */ 3557 int dir_filter(const struct dirent *dirp) 3558 { 3559 if (isdigit(dirp->d_name[0])) 3560 return 1; 3561 else 3562 return 0; 3563 } 3564 3565 int open_dev_cpu_msr(int dummy1) 3566 { 3567 return 0; 3568 } 3569 3570 void topology_probe() 3571 { 3572 int i; 3573 int max_core_id = 0; 3574 int max_package_id = 0; 3575 int max_siblings = 0; 3576 struct cpu_topology { 3577 int core_id; 3578 int physical_package_id; 3579 } *cpus; 3580 3581 /* Initialize num_cpus, max_cpu_num */ 3582 topo.num_cpus = 0; 3583 topo.max_cpu_num = 0; 3584 for_all_proc_cpus(count_cpus); 3585 if (!summary_only && topo.num_cpus > 1) 3586 show_cpu = 1; 3587 3588 if (debug > 1) 3589 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); 3590 3591 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); 3592 if (cpus == NULL) 3593 err(1, "calloc cpus"); 3594 3595 /* 3596 * Allocate and initialize cpu_present_set 3597 */ 3598 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); 3599 if (cpu_present_set == NULL) 3600 err(3, "CPU_ALLOC"); 3601 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 3602 CPU_ZERO_S(cpu_present_setsize, cpu_present_set); 3603 for_all_proc_cpus(mark_cpu_present); 3604 3605 /* 3606 * Allocate and initialize cpu_affinity_set 3607 */ 3608 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); 3609 if (cpu_affinity_set == NULL) 3610 err(3, "CPU_ALLOC"); 3611 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 3612 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 3613 3614 3615 /* 3616 * For online cpus 3617 * find max_core_id, max_package_id 3618 */ 3619 for (i = 0; i <= topo.max_cpu_num; ++i) { 3620 int siblings; 3621 3622 if (cpu_is_not_present(i)) { 3623 if (debug > 1) 3624 fprintf(outf, "cpu%d NOT PRESENT\n", i); 3625 continue; 3626 } 3627 cpus[i].core_id = get_core_id(i); 3628 if (cpus[i].core_id > max_core_id) 3629 max_core_id = cpus[i].core_id; 3630 3631 cpus[i].physical_package_id = get_physical_package_id(i); 3632 if (cpus[i].physical_package_id > max_package_id) 3633 max_package_id = cpus[i].physical_package_id; 3634 3635 siblings = get_num_ht_siblings(i); 3636 if (siblings > max_siblings) 3637 max_siblings = siblings; 3638 if (debug > 1) 3639 fprintf(outf, "cpu %d pkg %d core %d\n", 3640 i, cpus[i].physical_package_id, cpus[i].core_id); 3641 } 3642 topo.num_cores_per_pkg = max_core_id + 1; 3643 if (debug > 1) 3644 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", 3645 max_core_id, topo.num_cores_per_pkg); 3646 if (debug && !summary_only && topo.num_cores_per_pkg > 1) 3647 show_core = 1; 3648 3649 topo.num_packages = max_package_id + 1; 3650 if (debug > 1) 3651 fprintf(outf, "max_package_id %d, sizing for %d packages\n", 3652 max_package_id, topo.num_packages); 3653 if (debug && !summary_only && topo.num_packages > 1) 3654 show_pkg = 1; 3655 3656 topo.num_threads_per_core = max_siblings; 3657 if (debug > 1) 3658 fprintf(outf, "max_siblings %d\n", max_siblings); 3659 3660 free(cpus); 3661 } 3662 3663 void 3664 allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p) 3665 { 3666 int i; 3667 3668 *t = calloc(topo.num_threads_per_core * topo.num_cores_per_pkg * 3669 topo.num_packages, sizeof(struct thread_data)); 3670 if (*t == NULL) 3671 goto error; 3672 3673 for (i = 0; i < topo.num_threads_per_core * 3674 topo.num_cores_per_pkg * topo.num_packages; i++) 3675 (*t)[i].cpu_id = -1; 3676 3677 *c = calloc(topo.num_cores_per_pkg * topo.num_packages, 3678 sizeof(struct core_data)); 3679 if (*c == NULL) 3680 goto error; 3681 3682 for (i = 0; i < topo.num_cores_per_pkg * topo.num_packages; i++) 3683 (*c)[i].core_id = -1; 3684 3685 *p = calloc(topo.num_packages, sizeof(struct pkg_data)); 3686 if (*p == NULL) 3687 goto error; 3688 3689 for (i = 0; i < topo.num_packages; i++) 3690 (*p)[i].package_id = i; 3691 3692 return; 3693 error: 3694 err(1, "calloc counters"); 3695 } 3696 /* 3697 * init_counter() 3698 * 3699 * set cpu_id, core_num, pkg_num 3700 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE 3701 * 3702 * increment topo.num_cores when 1st core in pkg seen 3703 */ 3704 void init_counter(struct thread_data *thread_base, struct core_data *core_base, 3705 struct pkg_data *pkg_base, int thread_num, int core_num, 3706 int pkg_num, int cpu_id) 3707 { 3708 struct thread_data *t; 3709 struct core_data *c; 3710 struct pkg_data *p; 3711 3712 t = GET_THREAD(thread_base, thread_num, core_num, pkg_num); 3713 c = GET_CORE(core_base, core_num, pkg_num); 3714 p = GET_PKG(pkg_base, pkg_num); 3715 3716 t->cpu_id = cpu_id; 3717 if (thread_num == 0) { 3718 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; 3719 if (cpu_is_first_core_in_package(cpu_id)) 3720 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; 3721 } 3722 3723 c->core_id = core_num; 3724 p->package_id = pkg_num; 3725 } 3726 3727 3728 int initialize_counters(int cpu_id) 3729 { 3730 int my_thread_id, my_core_id, my_package_id; 3731 3732 my_package_id = get_physical_package_id(cpu_id); 3733 my_core_id = get_core_id(cpu_id); 3734 my_thread_id = get_cpu_position_in_core(cpu_id); 3735 if (!my_thread_id) 3736 topo.num_cores++; 3737 3738 init_counter(EVEN_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id); 3739 init_counter(ODD_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id); 3740 return 0; 3741 } 3742 3743 void allocate_output_buffer() 3744 { 3745 output_buffer = calloc(1, (1 + topo.num_cpus) * 1024); 3746 outp = output_buffer; 3747 if (outp == NULL) 3748 err(-1, "calloc output buffer"); 3749 } 3750 void allocate_fd_percpu(void) 3751 { 3752 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 3753 if (fd_percpu == NULL) 3754 err(-1, "calloc fd_percpu"); 3755 } 3756 void allocate_irq_buffers(void) 3757 { 3758 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); 3759 if (irq_column_2_cpu == NULL) 3760 err(-1, "calloc %d", topo.num_cpus); 3761 3762 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 3763 if (irqs_per_cpu == NULL) 3764 err(-1, "calloc %d", topo.max_cpu_num + 1); 3765 } 3766 void setup_all_buffers(void) 3767 { 3768 topology_probe(); 3769 allocate_irq_buffers(); 3770 allocate_fd_percpu(); 3771 allocate_counters(&thread_even, &core_even, &package_even); 3772 allocate_counters(&thread_odd, &core_odd, &package_odd); 3773 allocate_output_buffer(); 3774 for_all_proc_cpus(initialize_counters); 3775 } 3776 3777 void set_base_cpu(void) 3778 { 3779 base_cpu = sched_getcpu(); 3780 if (base_cpu < 0) 3781 err(-ENODEV, "No valid cpus found"); 3782 3783 if (debug > 1) 3784 fprintf(outf, "base_cpu = %d\n", base_cpu); 3785 } 3786 3787 void turbostat_init() 3788 { 3789 setup_all_buffers(); 3790 set_base_cpu(); 3791 check_dev_msr(); 3792 check_permissions(); 3793 process_cpuid(); 3794 3795 3796 if (debug) 3797 for_all_cpus(print_hwp, ODD_COUNTERS); 3798 3799 if (debug) 3800 for_all_cpus(print_epb, ODD_COUNTERS); 3801 3802 if (debug) 3803 for_all_cpus(print_perf_limit, ODD_COUNTERS); 3804 3805 if (debug) 3806 for_all_cpus(print_rapl, ODD_COUNTERS); 3807 3808 for_all_cpus(set_temperature_target, ODD_COUNTERS); 3809 3810 if (debug) 3811 for_all_cpus(print_thermal, ODD_COUNTERS); 3812 3813 if (debug && do_irtl_snb) 3814 print_irtl(); 3815 } 3816 3817 int fork_it(char **argv) 3818 { 3819 pid_t child_pid; 3820 int status; 3821 3822 status = for_all_cpus(get_counters, EVEN_COUNTERS); 3823 if (status) 3824 exit(status); 3825 /* clear affinity side-effect of get_counters() */ 3826 sched_setaffinity(0, cpu_present_setsize, cpu_present_set); 3827 gettimeofday(&tv_even, (struct timezone *)NULL); 3828 3829 child_pid = fork(); 3830 if (!child_pid) { 3831 /* child */ 3832 execvp(argv[0], argv); 3833 } else { 3834 3835 /* parent */ 3836 if (child_pid == -1) 3837 err(1, "fork"); 3838 3839 signal(SIGINT, SIG_IGN); 3840 signal(SIGQUIT, SIG_IGN); 3841 if (waitpid(child_pid, &status, 0) == -1) 3842 err(status, "waitpid"); 3843 } 3844 /* 3845 * n.b. fork_it() does not check for errors from for_all_cpus() 3846 * because re-starting is problematic when forking 3847 */ 3848 for_all_cpus(get_counters, ODD_COUNTERS); 3849 gettimeofday(&tv_odd, (struct timezone *)NULL); 3850 timersub(&tv_odd, &tv_even, &tv_delta); 3851 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) 3852 fprintf(outf, "%s: Counter reset detected\n", progname); 3853 else { 3854 compute_average(EVEN_COUNTERS); 3855 format_all_counters(EVEN_COUNTERS); 3856 } 3857 3858 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0); 3859 3860 flush_output_stderr(); 3861 3862 return status; 3863 } 3864 3865 int get_and_dump_counters(void) 3866 { 3867 int status; 3868 3869 status = for_all_cpus(get_counters, ODD_COUNTERS); 3870 if (status) 3871 return status; 3872 3873 status = for_all_cpus(dump_counters, ODD_COUNTERS); 3874 if (status) 3875 return status; 3876 3877 flush_output_stdout(); 3878 3879 return status; 3880 } 3881 3882 void print_version() { 3883 fprintf(outf, "turbostat version 4.16 24 Dec 2016" 3884 " - Len Brown <lenb@kernel.org>\n"); 3885 } 3886 3887 int add_counter(unsigned int msr_num, char *name, unsigned int width, 3888 enum counter_scope scope, enum counter_type type, 3889 enum counter_format format) 3890 { 3891 struct msr_counter *msrp; 3892 3893 msrp = calloc(1, sizeof(struct msr_counter)); 3894 if (msrp == NULL) { 3895 perror("calloc"); 3896 exit(1); 3897 } 3898 3899 msrp->msr_num = msr_num; 3900 strncpy(msrp->name, name, NAME_BYTES); 3901 msrp->width = width; 3902 msrp->type = type; 3903 msrp->format = format; 3904 3905 switch (scope) { 3906 3907 case SCOPE_CPU: 3908 msrp->next = sys.tp; 3909 sys.tp = msrp; 3910 sys.added_thread_counters++; 3911 if (sys.added_thread_counters > MAX_ADDED_COUNTERS) { 3912 fprintf(stderr, "exceeded max %d added thread counters\n", 3913 MAX_ADDED_COUNTERS); 3914 exit(-1); 3915 } 3916 break; 3917 3918 case SCOPE_CORE: 3919 msrp->next = sys.cp; 3920 sys.cp = msrp; 3921 sys.added_core_counters++; 3922 if (sys.added_core_counters > MAX_ADDED_COUNTERS) { 3923 fprintf(stderr, "exceeded max %d added core counters\n", 3924 MAX_ADDED_COUNTERS); 3925 exit(-1); 3926 } 3927 break; 3928 3929 case SCOPE_PACKAGE: 3930 msrp->next = sys.pp; 3931 sys.pp = msrp; 3932 sys.added_package_counters++; 3933 if (sys.added_package_counters > MAX_ADDED_COUNTERS) { 3934 fprintf(stderr, "exceeded max %d added package counters\n", 3935 MAX_ADDED_COUNTERS); 3936 exit(-1); 3937 } 3938 break; 3939 } 3940 3941 return 0; 3942 } 3943 3944 void parse_add_command(char *add_command) 3945 { 3946 int msr_num = 0; 3947 char name_buffer[NAME_BYTES]; 3948 int width = 64; 3949 int fail = 0; 3950 enum counter_scope scope = SCOPE_CPU; 3951 enum counter_type type = COUNTER_CYCLES; 3952 enum counter_format format = FORMAT_DELTA; 3953 3954 while (add_command) { 3955 3956 if (sscanf(add_command, "msr0x%x", &msr_num) == 1) 3957 goto next; 3958 3959 if (sscanf(add_command, "msr%d", &msr_num) == 1) 3960 goto next; 3961 3962 if (sscanf(add_command, "u%d", &width) == 1) { 3963 if ((width == 32) || (width == 64)) 3964 goto next; 3965 width = 64; 3966 } 3967 if (!strncmp(add_command, "cpu", strlen("cpu"))) { 3968 scope = SCOPE_CPU; 3969 goto next; 3970 } 3971 if (!strncmp(add_command, "core", strlen("core"))) { 3972 scope = SCOPE_CORE; 3973 goto next; 3974 } 3975 if (!strncmp(add_command, "package", strlen("package"))) { 3976 scope = SCOPE_PACKAGE; 3977 goto next; 3978 } 3979 if (!strncmp(add_command, "cycles", strlen("cycles"))) { 3980 type = COUNTER_CYCLES; 3981 goto next; 3982 } 3983 if (!strncmp(add_command, "seconds", strlen("seconds"))) { 3984 type = COUNTER_SECONDS; 3985 goto next; 3986 } 3987 if (!strncmp(add_command, "raw", strlen("raw"))) { 3988 format = FORMAT_RAW; 3989 goto next; 3990 } 3991 if (!strncmp(add_command, "delta", strlen("delta"))) { 3992 format = FORMAT_DELTA; 3993 goto next; 3994 } 3995 if (!strncmp(add_command, "percent", strlen("percent"))) { 3996 format = FORMAT_PERCENT; 3997 goto next; 3998 } 3999 4000 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */ 4001 char *eos; 4002 4003 eos = strchr(name_buffer, ','); 4004 if (eos) 4005 *eos = '\0'; 4006 goto next; 4007 } 4008 4009 next: 4010 add_command = strchr(add_command, ','); 4011 if (add_command) 4012 add_command++; 4013 4014 } 4015 if (msr_num == 0) { 4016 fprintf(stderr, "--add: (msrDDD | msr0xXXX) required\n"); 4017 fail++; 4018 } 4019 4020 /* generate default column header */ 4021 if (*name_buffer == '\0') { 4022 if (format == FORMAT_RAW) { 4023 if (width == 32) 4024 sprintf(name_buffer, "msr%d", msr_num); 4025 else 4026 sprintf(name_buffer, "MSR%d", msr_num); 4027 } else if (format == FORMAT_DELTA) { 4028 if (width == 32) 4029 sprintf(name_buffer, "cnt%d", msr_num); 4030 else 4031 sprintf(name_buffer, "CNT%d", msr_num); 4032 } else if (format == FORMAT_PERCENT) { 4033 if (width == 32) 4034 sprintf(name_buffer, "msr%d%%", msr_num); 4035 else 4036 sprintf(name_buffer, "MSR%d%%", msr_num); 4037 } 4038 } 4039 4040 if (add_counter(msr_num, name_buffer, width, scope, type, format)) 4041 fail++; 4042 4043 if (fail) { 4044 help(); 4045 exit(1); 4046 } 4047 } 4048 void cmdline(int argc, char **argv) 4049 { 4050 int opt; 4051 int option_index = 0; 4052 static struct option long_options[] = { 4053 {"add", required_argument, 0, 'a'}, 4054 {"Dump", no_argument, 0, 'D'}, 4055 {"debug", no_argument, 0, 'd'}, 4056 {"interval", required_argument, 0, 'i'}, 4057 {"help", no_argument, 0, 'h'}, 4058 {"Joules", no_argument, 0, 'J'}, 4059 {"out", required_argument, 0, 'o'}, 4060 {"Package", no_argument, 0, 'p'}, 4061 {"processor", no_argument, 0, 'p'}, 4062 {"Summary", no_argument, 0, 'S'}, 4063 {"TCC", required_argument, 0, 'T'}, 4064 {"version", no_argument, 0, 'v' }, 4065 {0, 0, 0, 0 } 4066 }; 4067 4068 progname = argv[0]; 4069 4070 while ((opt = getopt_long_only(argc, argv, "+C:c:Ddhi:JM:m:o:PpST:v", 4071 long_options, &option_index)) != -1) { 4072 switch (opt) { 4073 case 'a': 4074 parse_add_command(optarg); 4075 break; 4076 case 'D': 4077 dump_only++; 4078 break; 4079 case 'd': 4080 debug++; 4081 break; 4082 case 'h': 4083 default: 4084 help(); 4085 exit(1); 4086 case 'i': 4087 { 4088 double interval = strtod(optarg, NULL); 4089 4090 if (interval < 0.001) { 4091 fprintf(outf, "interval %f seconds is too small\n", 4092 interval); 4093 exit(2); 4094 } 4095 4096 interval_ts.tv_sec = interval; 4097 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; 4098 } 4099 break; 4100 case 'J': 4101 rapl_joules++; 4102 break; 4103 case 'o': 4104 outf = fopen_or_die(optarg, "w"); 4105 break; 4106 case 'P': 4107 show_pkg_only++; 4108 break; 4109 case 'p': 4110 show_core_only++; 4111 break; 4112 case 'S': 4113 summary_only++; 4114 break; 4115 case 'T': 4116 tcc_activation_temp_override = atoi(optarg); 4117 break; 4118 case 'v': 4119 print_version(); 4120 exit(0); 4121 break; 4122 } 4123 } 4124 } 4125 4126 int main(int argc, char **argv) 4127 { 4128 outf = stderr; 4129 4130 cmdline(argc, argv); 4131 4132 if (debug) 4133 print_version(); 4134 4135 turbostat_init(); 4136 4137 /* dump counters and exit */ 4138 if (dump_only) 4139 return get_and_dump_counters(); 4140 4141 /* 4142 * if any params left, it must be a command to fork 4143 */ 4144 if (argc - optind) 4145 return fork_it(argv + optind); 4146 else 4147 turbostat_loop(); 4148 4149 return 0; 4150 } 4151