1 /* 2 * turbostat -- show CPU frequency and C-state residency 3 * on modern Intel turbo-capable processors. 4 * 5 * Copyright (c) 2013 Intel Corporation. 6 * Len Brown <len.brown@intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 20 */ 21 22 #define _GNU_SOURCE 23 #include MSRHEADER 24 #include INTEL_FAMILY_HEADER 25 #include <stdarg.h> 26 #include <stdio.h> 27 #include <err.h> 28 #include <unistd.h> 29 #include <sys/types.h> 30 #include <sys/wait.h> 31 #include <sys/stat.h> 32 #include <sys/select.h> 33 #include <sys/resource.h> 34 #include <fcntl.h> 35 #include <signal.h> 36 #include <sys/time.h> 37 #include <stdlib.h> 38 #include <getopt.h> 39 #include <dirent.h> 40 #include <string.h> 41 #include <ctype.h> 42 #include <sched.h> 43 #include <time.h> 44 #include <cpuid.h> 45 #include <linux/capability.h> 46 #include <errno.h> 47 48 char *proc_stat = "/proc/stat"; 49 FILE *outf; 50 int *fd_percpu; 51 struct timeval interval_tv = {5, 0}; 52 struct timespec interval_ts = {5, 0}; 53 struct timespec one_msec = {0, 1000000}; 54 unsigned int num_iterations; 55 unsigned int debug; 56 unsigned int quiet; 57 unsigned int shown; 58 unsigned int sums_need_wide_columns; 59 unsigned int rapl_joules; 60 unsigned int summary_only; 61 unsigned int list_header_only; 62 unsigned int dump_only; 63 unsigned int do_snb_cstates; 64 unsigned int do_knl_cstates; 65 unsigned int do_slm_cstates; 66 unsigned int do_cnl_cstates; 67 unsigned int use_c1_residency_msr; 68 unsigned int has_aperf; 69 unsigned int has_epb; 70 unsigned int do_irtl_snb; 71 unsigned int do_irtl_hsw; 72 unsigned int units = 1000000; /* MHz etc */ 73 unsigned int genuine_intel; 74 unsigned int has_invariant_tsc; 75 unsigned int do_nhm_platform_info; 76 unsigned int no_MSR_MISC_PWR_MGMT; 77 unsigned int aperf_mperf_multiplier = 1; 78 double bclk; 79 double base_hz; 80 unsigned int has_base_hz; 81 double tsc_tweak = 1.0; 82 unsigned int show_pkg_only; 83 unsigned int show_core_only; 84 char *output_buffer, *outp; 85 unsigned int do_rapl; 86 unsigned int do_dts; 87 unsigned int do_ptm; 88 unsigned long long gfx_cur_rc6_ms; 89 unsigned long long cpuidle_cur_cpu_lpi_us; 90 unsigned long long cpuidle_cur_sys_lpi_us; 91 unsigned int gfx_cur_mhz; 92 unsigned int tcc_activation_temp; 93 unsigned int tcc_activation_temp_override; 94 double rapl_power_units, rapl_time_units; 95 double rapl_dram_energy_units, rapl_energy_units; 96 double rapl_joule_counter_range; 97 unsigned int do_core_perf_limit_reasons; 98 unsigned int has_automatic_cstate_conversion; 99 unsigned int do_gfx_perf_limit_reasons; 100 unsigned int do_ring_perf_limit_reasons; 101 unsigned int crystal_hz; 102 unsigned long long tsc_hz; 103 int base_cpu; 104 double discover_bclk(unsigned int family, unsigned int model); 105 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ 106 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ 107 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ 108 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ 109 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ 110 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ 111 unsigned int has_misc_feature_control; 112 unsigned int first_counter_read = 1; 113 114 #define RAPL_PKG (1 << 0) 115 /* 0x610 MSR_PKG_POWER_LIMIT */ 116 /* 0x611 MSR_PKG_ENERGY_STATUS */ 117 #define RAPL_PKG_PERF_STATUS (1 << 1) 118 /* 0x613 MSR_PKG_PERF_STATUS */ 119 #define RAPL_PKG_POWER_INFO (1 << 2) 120 /* 0x614 MSR_PKG_POWER_INFO */ 121 122 #define RAPL_DRAM (1 << 3) 123 /* 0x618 MSR_DRAM_POWER_LIMIT */ 124 /* 0x619 MSR_DRAM_ENERGY_STATUS */ 125 #define RAPL_DRAM_PERF_STATUS (1 << 4) 126 /* 0x61b MSR_DRAM_PERF_STATUS */ 127 #define RAPL_DRAM_POWER_INFO (1 << 5) 128 /* 0x61c MSR_DRAM_POWER_INFO */ 129 130 #define RAPL_CORES_POWER_LIMIT (1 << 6) 131 /* 0x638 MSR_PP0_POWER_LIMIT */ 132 #define RAPL_CORE_POLICY (1 << 7) 133 /* 0x63a MSR_PP0_POLICY */ 134 135 #define RAPL_GFX (1 << 8) 136 /* 0x640 MSR_PP1_POWER_LIMIT */ 137 /* 0x641 MSR_PP1_ENERGY_STATUS */ 138 /* 0x642 MSR_PP1_POLICY */ 139 140 #define RAPL_CORES_ENERGY_STATUS (1 << 9) 141 /* 0x639 MSR_PP0_ENERGY_STATUS */ 142 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT) 143 #define TJMAX_DEFAULT 100 144 145 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 146 147 /* 148 * buffer size used by sscanf() for added column names 149 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters 150 */ 151 #define NAME_BYTES 20 152 #define PATH_BYTES 128 153 154 int backwards_count; 155 char *progname; 156 157 #define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */ 158 cpu_set_t *cpu_present_set, *cpu_affinity_set, *cpu_subset; 159 size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size; 160 #define MAX_ADDED_COUNTERS 8 161 #define MAX_ADDED_THREAD_COUNTERS 24 162 #define BITMASK_SIZE 32 163 164 struct thread_data { 165 struct timeval tv_begin; 166 struct timeval tv_end; 167 unsigned long long tsc; 168 unsigned long long aperf; 169 unsigned long long mperf; 170 unsigned long long c1; 171 unsigned long long irq_count; 172 unsigned int smi_count; 173 unsigned int cpu_id; 174 unsigned int apic_id; 175 unsigned int x2apic_id; 176 unsigned int flags; 177 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2 178 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 179 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS]; 180 } *thread_even, *thread_odd; 181 182 struct core_data { 183 unsigned long long c3; 184 unsigned long long c6; 185 unsigned long long c7; 186 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */ 187 unsigned int core_temp_c; 188 unsigned int core_id; 189 unsigned long long counter[MAX_ADDED_COUNTERS]; 190 } *core_even, *core_odd; 191 192 struct pkg_data { 193 unsigned long long pc2; 194 unsigned long long pc3; 195 unsigned long long pc6; 196 unsigned long long pc7; 197 unsigned long long pc8; 198 unsigned long long pc9; 199 unsigned long long pc10; 200 unsigned long long cpu_lpi; 201 unsigned long long sys_lpi; 202 unsigned long long pkg_wtd_core_c0; 203 unsigned long long pkg_any_core_c0; 204 unsigned long long pkg_any_gfxe_c0; 205 unsigned long long pkg_both_core_gfxe_c0; 206 long long gfx_rc6_ms; 207 unsigned int gfx_mhz; 208 unsigned int package_id; 209 unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */ 210 unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */ 211 unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */ 212 unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */ 213 unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ 214 unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ 215 unsigned int pkg_temp_c; 216 unsigned long long counter[MAX_ADDED_COUNTERS]; 217 } *package_even, *package_odd; 218 219 #define ODD_COUNTERS thread_odd, core_odd, package_odd 220 #define EVEN_COUNTERS thread_even, core_even, package_even 221 222 #define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \ 223 ((thread_base) + \ 224 ((pkg_no) * \ 225 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \ 226 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \ 227 ((core_no) * topo.threads_per_core) + \ 228 (thread_no)) 229 230 #define GET_CORE(core_base, core_no, node_no, pkg_no) \ 231 ((core_base) + \ 232 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \ 233 ((node_no) * topo.cores_per_node) + \ 234 (core_no)) 235 236 237 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) 238 239 enum counter_scope {SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE}; 240 enum counter_type {COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC}; 241 enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT}; 242 243 struct msr_counter { 244 unsigned int msr_num; 245 char name[NAME_BYTES]; 246 char path[PATH_BYTES]; 247 unsigned int width; 248 enum counter_type type; 249 enum counter_format format; 250 struct msr_counter *next; 251 unsigned int flags; 252 #define FLAGS_HIDE (1 << 0) 253 #define FLAGS_SHOW (1 << 1) 254 #define SYSFS_PERCPU (1 << 1) 255 }; 256 257 struct sys_counters { 258 unsigned int added_thread_counters; 259 unsigned int added_core_counters; 260 unsigned int added_package_counters; 261 struct msr_counter *tp; 262 struct msr_counter *cp; 263 struct msr_counter *pp; 264 } sys; 265 266 struct system_summary { 267 struct thread_data threads; 268 struct core_data cores; 269 struct pkg_data packages; 270 } average; 271 272 struct cpu_topology { 273 int physical_package_id; 274 int logical_cpu_id; 275 int physical_node_id; 276 int logical_node_id; /* 0-based count within the package */ 277 int physical_core_id; 278 int thread_id; 279 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */ 280 } *cpus; 281 282 struct topo_params { 283 int num_packages; 284 int num_cpus; 285 int num_cores; 286 int max_cpu_num; 287 int max_node_num; 288 int nodes_per_pkg; 289 int cores_per_node; 290 int threads_per_core; 291 } topo; 292 293 struct timeval tv_even, tv_odd, tv_delta; 294 295 int *irq_column_2_cpu; /* /proc/interrupts column numbers */ 296 int *irqs_per_cpu; /* indexed by cpu_num */ 297 298 void setup_all_buffers(void); 299 300 int cpu_is_not_present(int cpu) 301 { 302 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); 303 } 304 /* 305 * run func(thread, core, package) in topology order 306 * skip non-present cpus 307 */ 308 309 int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *), 310 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) 311 { 312 int retval, pkg_no, core_no, thread_no, node_no; 313 314 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 315 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) { 316 for (node_no = 0; node_no < topo.nodes_per_pkg; 317 node_no++) { 318 for (thread_no = 0; thread_no < 319 topo.threads_per_core; ++thread_no) { 320 struct thread_data *t; 321 struct core_data *c; 322 struct pkg_data *p; 323 324 t = GET_THREAD(thread_base, thread_no, 325 core_no, node_no, 326 pkg_no); 327 328 if (cpu_is_not_present(t->cpu_id)) 329 continue; 330 331 c = GET_CORE(core_base, core_no, 332 node_no, pkg_no); 333 p = GET_PKG(pkg_base, pkg_no); 334 335 retval = func(t, c, p); 336 if (retval) 337 return retval; 338 } 339 } 340 } 341 } 342 return 0; 343 } 344 345 int cpu_migrate(int cpu) 346 { 347 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 348 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); 349 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) 350 return -1; 351 else 352 return 0; 353 } 354 int get_msr_fd(int cpu) 355 { 356 char pathname[32]; 357 int fd; 358 359 fd = fd_percpu[cpu]; 360 361 if (fd) 362 return fd; 363 364 sprintf(pathname, "/dev/cpu/%d/msr", cpu); 365 fd = open(pathname, O_RDONLY); 366 if (fd < 0) 367 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); 368 369 fd_percpu[cpu] = fd; 370 371 return fd; 372 } 373 374 int get_msr(int cpu, off_t offset, unsigned long long *msr) 375 { 376 ssize_t retval; 377 378 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); 379 380 if (retval != sizeof *msr) 381 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset); 382 383 return 0; 384 } 385 386 /* 387 * This list matches the column headers, except 388 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time 389 * 2. Core and CPU are moved to the end, we can't have strings that contain them 390 * matching on them for --show and --hide. 391 */ 392 struct msr_counter bic[] = { 393 { 0x0, "usec" }, 394 { 0x0, "Time_Of_Day_Seconds" }, 395 { 0x0, "Package" }, 396 { 0x0, "Node" }, 397 { 0x0, "Avg_MHz" }, 398 { 0x0, "Busy%" }, 399 { 0x0, "Bzy_MHz" }, 400 { 0x0, "TSC_MHz" }, 401 { 0x0, "IRQ" }, 402 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL}, 403 { 0x0, "sysfs" }, 404 { 0x0, "CPU%c1" }, 405 { 0x0, "CPU%c3" }, 406 { 0x0, "CPU%c6" }, 407 { 0x0, "CPU%c7" }, 408 { 0x0, "ThreadC" }, 409 { 0x0, "CoreTmp" }, 410 { 0x0, "CoreCnt" }, 411 { 0x0, "PkgTmp" }, 412 { 0x0, "GFX%rc6" }, 413 { 0x0, "GFXMHz" }, 414 { 0x0, "Pkg%pc2" }, 415 { 0x0, "Pkg%pc3" }, 416 { 0x0, "Pkg%pc6" }, 417 { 0x0, "Pkg%pc7" }, 418 { 0x0, "Pkg%pc8" }, 419 { 0x0, "Pkg%pc9" }, 420 { 0x0, "Pk%pc10" }, 421 { 0x0, "CPU%LPI" }, 422 { 0x0, "SYS%LPI" }, 423 { 0x0, "PkgWatt" }, 424 { 0x0, "CorWatt" }, 425 { 0x0, "GFXWatt" }, 426 { 0x0, "PkgCnt" }, 427 { 0x0, "RAMWatt" }, 428 { 0x0, "PKG_%" }, 429 { 0x0, "RAM_%" }, 430 { 0x0, "Pkg_J" }, 431 { 0x0, "Cor_J" }, 432 { 0x0, "GFX_J" }, 433 { 0x0, "RAM_J" }, 434 { 0x0, "Mod%c6" }, 435 { 0x0, "Totl%C0" }, 436 { 0x0, "Any%C0" }, 437 { 0x0, "GFX%C0" }, 438 { 0x0, "CPUGFX%" }, 439 { 0x0, "Core" }, 440 { 0x0, "CPU" }, 441 { 0x0, "APIC" }, 442 { 0x0, "X2APIC" }, 443 }; 444 445 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter)) 446 #define BIC_USEC (1ULL << 0) 447 #define BIC_TOD (1ULL << 1) 448 #define BIC_Package (1ULL << 2) 449 #define BIC_Node (1ULL << 3) 450 #define BIC_Avg_MHz (1ULL << 4) 451 #define BIC_Busy (1ULL << 5) 452 #define BIC_Bzy_MHz (1ULL << 6) 453 #define BIC_TSC_MHz (1ULL << 7) 454 #define BIC_IRQ (1ULL << 8) 455 #define BIC_SMI (1ULL << 9) 456 #define BIC_sysfs (1ULL << 10) 457 #define BIC_CPU_c1 (1ULL << 11) 458 #define BIC_CPU_c3 (1ULL << 12) 459 #define BIC_CPU_c6 (1ULL << 13) 460 #define BIC_CPU_c7 (1ULL << 14) 461 #define BIC_ThreadC (1ULL << 15) 462 #define BIC_CoreTmp (1ULL << 16) 463 #define BIC_CoreCnt (1ULL << 17) 464 #define BIC_PkgTmp (1ULL << 18) 465 #define BIC_GFX_rc6 (1ULL << 19) 466 #define BIC_GFXMHz (1ULL << 20) 467 #define BIC_Pkgpc2 (1ULL << 21) 468 #define BIC_Pkgpc3 (1ULL << 22) 469 #define BIC_Pkgpc6 (1ULL << 23) 470 #define BIC_Pkgpc7 (1ULL << 24) 471 #define BIC_Pkgpc8 (1ULL << 25) 472 #define BIC_Pkgpc9 (1ULL << 26) 473 #define BIC_Pkgpc10 (1ULL << 27) 474 #define BIC_CPU_LPI (1ULL << 28) 475 #define BIC_SYS_LPI (1ULL << 29) 476 #define BIC_PkgWatt (1ULL << 30) 477 #define BIC_CorWatt (1ULL << 31) 478 #define BIC_GFXWatt (1ULL << 32) 479 #define BIC_PkgCnt (1ULL << 33) 480 #define BIC_RAMWatt (1ULL << 34) 481 #define BIC_PKG__ (1ULL << 35) 482 #define BIC_RAM__ (1ULL << 36) 483 #define BIC_Pkg_J (1ULL << 37) 484 #define BIC_Cor_J (1ULL << 38) 485 #define BIC_GFX_J (1ULL << 39) 486 #define BIC_RAM_J (1ULL << 40) 487 #define BIC_Mod_c6 (1ULL << 41) 488 #define BIC_Totl_c0 (1ULL << 42) 489 #define BIC_Any_c0 (1ULL << 43) 490 #define BIC_GFX_c0 (1ULL << 44) 491 #define BIC_CPUGFX (1ULL << 45) 492 #define BIC_Core (1ULL << 46) 493 #define BIC_CPU (1ULL << 47) 494 #define BIC_APIC (1ULL << 48) 495 #define BIC_X2APIC (1ULL << 49) 496 497 #define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC) 498 499 unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT); 500 unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC; 501 502 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME) 503 #define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME) 504 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT) 505 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT) 506 507 508 #define MAX_DEFERRED 16 509 char *deferred_skip_names[MAX_DEFERRED]; 510 int deferred_skip_index; 511 512 /* 513 * HIDE_LIST - hide this list of counters, show the rest [default] 514 * SHOW_LIST - show this list of counters, hide the rest 515 */ 516 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST; 517 518 void help(void) 519 { 520 fprintf(outf, 521 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" 522 "\n" 523 "Turbostat forks the specified COMMAND and prints statistics\n" 524 "when COMMAND completes.\n" 525 "If no COMMAND is specified, turbostat wakes every 5-seconds\n" 526 "to print statistics, until interrupted.\n" 527 "--add add a counter\n" 528 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n" 529 "--cpu cpu-set limit output to summary plus cpu-set:\n" 530 " {core | package | j,k,l..m,n-p }\n" 531 "--quiet skip decoding system configuration header\n" 532 "--interval sec.subsec Override default 5-second measurement interval\n" 533 "--help print this help message\n" 534 "--list list column headers only\n" 535 "--num_iterations num number of the measurement iterations\n" 536 "--out file create or truncate \"file\" for all output\n" 537 "--version print version information\n" 538 "\n" 539 "For more help, run \"man turbostat\"\n"); 540 } 541 542 /* 543 * bic_lookup 544 * for all the strings in comma separate name_list, 545 * set the approprate bit in return value. 546 */ 547 unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode) 548 { 549 int i; 550 unsigned long long retval = 0; 551 552 while (name_list) { 553 char *comma; 554 555 comma = strchr(name_list, ','); 556 557 if (comma) 558 *comma = '\0'; 559 560 if (!strcmp(name_list, "all")) 561 return ~0; 562 563 for (i = 0; i < MAX_BIC; ++i) { 564 if (!strcmp(name_list, bic[i].name)) { 565 retval |= (1ULL << i); 566 break; 567 } 568 } 569 if (i == MAX_BIC) { 570 if (mode == SHOW_LIST) { 571 fprintf(stderr, "Invalid counter name: %s\n", name_list); 572 exit(-1); 573 } 574 deferred_skip_names[deferred_skip_index++] = name_list; 575 if (debug) 576 fprintf(stderr, "deferred \"%s\"\n", name_list); 577 if (deferred_skip_index >= MAX_DEFERRED) { 578 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n", 579 MAX_DEFERRED, name_list); 580 help(); 581 exit(1); 582 } 583 } 584 585 name_list = comma; 586 if (name_list) 587 name_list++; 588 589 } 590 return retval; 591 } 592 593 594 void print_header(char *delim) 595 { 596 struct msr_counter *mp; 597 int printed = 0; 598 599 if (DO_BIC(BIC_USEC)) 600 outp += sprintf(outp, "%susec", (printed++ ? delim : "")); 601 if (DO_BIC(BIC_TOD)) 602 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : "")); 603 if (DO_BIC(BIC_Package)) 604 outp += sprintf(outp, "%sPackage", (printed++ ? delim : "")); 605 if (DO_BIC(BIC_Node)) 606 outp += sprintf(outp, "%sNode", (printed++ ? delim : "")); 607 if (DO_BIC(BIC_Core)) 608 outp += sprintf(outp, "%sCore", (printed++ ? delim : "")); 609 if (DO_BIC(BIC_CPU)) 610 outp += sprintf(outp, "%sCPU", (printed++ ? delim : "")); 611 if (DO_BIC(BIC_APIC)) 612 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : "")); 613 if (DO_BIC(BIC_X2APIC)) 614 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : "")); 615 if (DO_BIC(BIC_Avg_MHz)) 616 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : "")); 617 if (DO_BIC(BIC_Busy)) 618 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : "")); 619 if (DO_BIC(BIC_Bzy_MHz)) 620 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : "")); 621 if (DO_BIC(BIC_TSC_MHz)) 622 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : "")); 623 624 if (DO_BIC(BIC_IRQ)) { 625 if (sums_need_wide_columns) 626 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : "")); 627 else 628 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : "")); 629 } 630 631 if (DO_BIC(BIC_SMI)) 632 outp += sprintf(outp, "%sSMI", (printed++ ? delim : "")); 633 634 for (mp = sys.tp; mp; mp = mp->next) { 635 636 if (mp->format == FORMAT_RAW) { 637 if (mp->width == 64) 638 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name); 639 else 640 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name); 641 } else { 642 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 643 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name); 644 else 645 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name); 646 } 647 } 648 649 if (DO_BIC(BIC_CPU_c1)) 650 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : "")); 651 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates && !do_cnl_cstates) 652 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : "")); 653 if (DO_BIC(BIC_CPU_c6)) 654 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : "")); 655 if (DO_BIC(BIC_CPU_c7)) 656 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : "")); 657 658 if (DO_BIC(BIC_Mod_c6)) 659 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : "")); 660 661 if (DO_BIC(BIC_CoreTmp)) 662 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : "")); 663 664 for (mp = sys.cp; mp; mp = mp->next) { 665 if (mp->format == FORMAT_RAW) { 666 if (mp->width == 64) 667 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 668 else 669 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 670 } else { 671 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 672 outp += sprintf(outp, "%s%8s", delim, mp->name); 673 else 674 outp += sprintf(outp, "%s%s", delim, mp->name); 675 } 676 } 677 678 if (DO_BIC(BIC_PkgTmp)) 679 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : "")); 680 681 if (DO_BIC(BIC_GFX_rc6)) 682 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : "")); 683 684 if (DO_BIC(BIC_GFXMHz)) 685 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : "")); 686 687 if (DO_BIC(BIC_Totl_c0)) 688 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : "")); 689 if (DO_BIC(BIC_Any_c0)) 690 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : "")); 691 if (DO_BIC(BIC_GFX_c0)) 692 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : "")); 693 if (DO_BIC(BIC_CPUGFX)) 694 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : "")); 695 696 if (DO_BIC(BIC_Pkgpc2)) 697 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : "")); 698 if (DO_BIC(BIC_Pkgpc3)) 699 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : "")); 700 if (DO_BIC(BIC_Pkgpc6)) 701 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : "")); 702 if (DO_BIC(BIC_Pkgpc7)) 703 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : "")); 704 if (DO_BIC(BIC_Pkgpc8)) 705 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : "")); 706 if (DO_BIC(BIC_Pkgpc9)) 707 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : "")); 708 if (DO_BIC(BIC_Pkgpc10)) 709 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : "")); 710 if (DO_BIC(BIC_CPU_LPI)) 711 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : "")); 712 if (DO_BIC(BIC_SYS_LPI)) 713 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : "")); 714 715 if (do_rapl && !rapl_joules) { 716 if (DO_BIC(BIC_PkgWatt)) 717 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : "")); 718 if (DO_BIC(BIC_CorWatt)) 719 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 720 if (DO_BIC(BIC_GFXWatt)) 721 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : "")); 722 if (DO_BIC(BIC_RAMWatt)) 723 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : "")); 724 if (DO_BIC(BIC_PKG__)) 725 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 726 if (DO_BIC(BIC_RAM__)) 727 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 728 } else if (do_rapl && rapl_joules) { 729 if (DO_BIC(BIC_Pkg_J)) 730 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : "")); 731 if (DO_BIC(BIC_Cor_J)) 732 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 733 if (DO_BIC(BIC_GFX_J)) 734 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : "")); 735 if (DO_BIC(BIC_RAM_J)) 736 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : "")); 737 if (DO_BIC(BIC_PKG__)) 738 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 739 if (DO_BIC(BIC_RAM__)) 740 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 741 } 742 for (mp = sys.pp; mp; mp = mp->next) { 743 if (mp->format == FORMAT_RAW) { 744 if (mp->width == 64) 745 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 746 else 747 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 748 } else { 749 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 750 outp += sprintf(outp, "%s%8s", delim, mp->name); 751 else 752 outp += sprintf(outp, "%s%s", delim, mp->name); 753 } 754 } 755 756 outp += sprintf(outp, "\n"); 757 } 758 759 int dump_counters(struct thread_data *t, struct core_data *c, 760 struct pkg_data *p) 761 { 762 int i; 763 struct msr_counter *mp; 764 765 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); 766 767 if (t) { 768 outp += sprintf(outp, "CPU: %d flags 0x%x\n", 769 t->cpu_id, t->flags); 770 outp += sprintf(outp, "TSC: %016llX\n", t->tsc); 771 outp += sprintf(outp, "aperf: %016llX\n", t->aperf); 772 outp += sprintf(outp, "mperf: %016llX\n", t->mperf); 773 outp += sprintf(outp, "c1: %016llX\n", t->c1); 774 775 if (DO_BIC(BIC_IRQ)) 776 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count); 777 if (DO_BIC(BIC_SMI)) 778 outp += sprintf(outp, "SMI: %d\n", t->smi_count); 779 780 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 781 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", 782 i, mp->msr_num, t->counter[i]); 783 } 784 } 785 786 if (c) { 787 outp += sprintf(outp, "core: %d\n", c->core_id); 788 outp += sprintf(outp, "c3: %016llX\n", c->c3); 789 outp += sprintf(outp, "c6: %016llX\n", c->c6); 790 outp += sprintf(outp, "c7: %016llX\n", c->c7); 791 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); 792 793 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 794 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", 795 i, mp->msr_num, c->counter[i]); 796 } 797 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us); 798 } 799 800 if (p) { 801 outp += sprintf(outp, "package: %d\n", p->package_id); 802 803 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); 804 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); 805 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); 806 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); 807 808 outp += sprintf(outp, "pc2: %016llX\n", p->pc2); 809 if (DO_BIC(BIC_Pkgpc3)) 810 outp += sprintf(outp, "pc3: %016llX\n", p->pc3); 811 if (DO_BIC(BIC_Pkgpc6)) 812 outp += sprintf(outp, "pc6: %016llX\n", p->pc6); 813 if (DO_BIC(BIC_Pkgpc7)) 814 outp += sprintf(outp, "pc7: %016llX\n", p->pc7); 815 outp += sprintf(outp, "pc8: %016llX\n", p->pc8); 816 outp += sprintf(outp, "pc9: %016llX\n", p->pc9); 817 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 818 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 819 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi); 820 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi); 821 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg); 822 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores); 823 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx); 824 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram); 825 outp += sprintf(outp, "Throttle PKG: %0X\n", 826 p->rapl_pkg_perf_status); 827 outp += sprintf(outp, "Throttle RAM: %0X\n", 828 p->rapl_dram_perf_status); 829 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); 830 831 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 832 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", 833 i, mp->msr_num, p->counter[i]); 834 } 835 } 836 837 outp += sprintf(outp, "\n"); 838 839 return 0; 840 } 841 842 /* 843 * column formatting convention & formats 844 */ 845 int format_counters(struct thread_data *t, struct core_data *c, 846 struct pkg_data *p) 847 { 848 double interval_float, tsc; 849 char *fmt8; 850 int i; 851 struct msr_counter *mp; 852 char *delim = "\t"; 853 int printed = 0; 854 855 /* if showing only 1st thread in core and this isn't one, bail out */ 856 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 857 return 0; 858 859 /* if showing only 1st thread in pkg and this isn't one, bail out */ 860 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 861 return 0; 862 863 /*if not summary line and --cpu is used */ 864 if ((t != &average.threads) && 865 (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset))) 866 return 0; 867 868 if (DO_BIC(BIC_USEC)) { 869 /* on each row, print how many usec each timestamp took to gather */ 870 struct timeval tv; 871 872 timersub(&t->tv_end, &t->tv_begin, &tv); 873 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec); 874 } 875 876 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */ 877 if (DO_BIC(BIC_TOD)) 878 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec); 879 880 interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0; 881 882 tsc = t->tsc * tsc_tweak; 883 884 /* topo columns, print blanks on 1st (average) line */ 885 if (t == &average.threads) { 886 if (DO_BIC(BIC_Package)) 887 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 888 if (DO_BIC(BIC_Node)) 889 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 890 if (DO_BIC(BIC_Core)) 891 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 892 if (DO_BIC(BIC_CPU)) 893 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 894 if (DO_BIC(BIC_APIC)) 895 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 896 if (DO_BIC(BIC_X2APIC)) 897 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 898 } else { 899 if (DO_BIC(BIC_Package)) { 900 if (p) 901 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id); 902 else 903 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 904 } 905 if (DO_BIC(BIC_Node)) { 906 if (t) 907 outp += sprintf(outp, "%s%d", 908 (printed++ ? delim : ""), 909 cpus[t->cpu_id].physical_node_id); 910 else 911 outp += sprintf(outp, "%s-", 912 (printed++ ? delim : "")); 913 } 914 if (DO_BIC(BIC_Core)) { 915 if (c) 916 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id); 917 else 918 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 919 } 920 if (DO_BIC(BIC_CPU)) 921 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id); 922 if (DO_BIC(BIC_APIC)) 923 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id); 924 if (DO_BIC(BIC_X2APIC)) 925 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id); 926 } 927 928 if (DO_BIC(BIC_Avg_MHz)) 929 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 930 1.0 / units * t->aperf / interval_float); 931 932 if (DO_BIC(BIC_Busy)) 933 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf/tsc); 934 935 if (DO_BIC(BIC_Bzy_MHz)) { 936 if (has_base_hz) 937 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf); 938 else 939 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 940 tsc / units * t->aperf / t->mperf / interval_float); 941 } 942 943 if (DO_BIC(BIC_TSC_MHz)) 944 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc/units/interval_float); 945 946 /* IRQ */ 947 if (DO_BIC(BIC_IRQ)) { 948 if (sums_need_wide_columns) 949 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count); 950 else 951 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count); 952 } 953 954 /* SMI */ 955 if (DO_BIC(BIC_SMI)) 956 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count); 957 958 /* Added counters */ 959 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 960 if (mp->format == FORMAT_RAW) { 961 if (mp->width == 32) 962 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) t->counter[i]); 963 else 964 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]); 965 } else if (mp->format == FORMAT_DELTA) { 966 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 967 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]); 968 else 969 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]); 970 } else if (mp->format == FORMAT_PERCENT) { 971 if (mp->type == COUNTER_USEC) 972 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), t->counter[i]/interval_float/10000); 973 else 974 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i]/tsc); 975 } 976 } 977 978 /* C1 */ 979 if (DO_BIC(BIC_CPU_c1)) 980 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1/tsc); 981 982 983 /* print per-core data only for 1st thread in core */ 984 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 985 goto done; 986 987 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates && !do_cnl_cstates) 988 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3/tsc); 989 if (DO_BIC(BIC_CPU_c6)) 990 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6/tsc); 991 if (DO_BIC(BIC_CPU_c7)) 992 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7/tsc); 993 994 /* Mod%c6 */ 995 if (DO_BIC(BIC_Mod_c6)) 996 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc); 997 998 if (DO_BIC(BIC_CoreTmp)) 999 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c); 1000 1001 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1002 if (mp->format == FORMAT_RAW) { 1003 if (mp->width == 32) 1004 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) c->counter[i]); 1005 else 1006 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]); 1007 } else if (mp->format == FORMAT_DELTA) { 1008 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1009 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]); 1010 else 1011 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]); 1012 } else if (mp->format == FORMAT_PERCENT) { 1013 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i]/tsc); 1014 } 1015 } 1016 1017 /* print per-package data only for 1st core in package */ 1018 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1019 goto done; 1020 1021 /* PkgTmp */ 1022 if (DO_BIC(BIC_PkgTmp)) 1023 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c); 1024 1025 /* GFXrc6 */ 1026 if (DO_BIC(BIC_GFX_rc6)) { 1027 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */ 1028 outp += sprintf(outp, "%s**.**", (printed++ ? delim : "")); 1029 } else { 1030 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1031 p->gfx_rc6_ms / 10.0 / interval_float); 1032 } 1033 } 1034 1035 /* GFXMHz */ 1036 if (DO_BIC(BIC_GFXMHz)) 1037 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz); 1038 1039 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ 1040 if (DO_BIC(BIC_Totl_c0)) 1041 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0/tsc); 1042 if (DO_BIC(BIC_Any_c0)) 1043 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0/tsc); 1044 if (DO_BIC(BIC_GFX_c0)) 1045 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0/tsc); 1046 if (DO_BIC(BIC_CPUGFX)) 1047 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0/tsc); 1048 1049 if (DO_BIC(BIC_Pkgpc2)) 1050 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2/tsc); 1051 if (DO_BIC(BIC_Pkgpc3)) 1052 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3/tsc); 1053 if (DO_BIC(BIC_Pkgpc6)) 1054 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6/tsc); 1055 if (DO_BIC(BIC_Pkgpc7)) 1056 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7/tsc); 1057 if (DO_BIC(BIC_Pkgpc8)) 1058 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8/tsc); 1059 if (DO_BIC(BIC_Pkgpc9)) 1060 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9/tsc); 1061 if (DO_BIC(BIC_Pkgpc10)) 1062 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10/tsc); 1063 1064 if (DO_BIC(BIC_CPU_LPI)) 1065 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float); 1066 if (DO_BIC(BIC_SYS_LPI)) 1067 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float); 1068 1069 /* 1070 * If measurement interval exceeds minimum RAPL Joule Counter range, 1071 * indicate that results are suspect by printing "**" in fraction place. 1072 */ 1073 if (interval_float < rapl_joule_counter_range) 1074 fmt8 = "%s%.2f"; 1075 else 1076 fmt8 = "%6.0f**"; 1077 1078 if (DO_BIC(BIC_PkgWatt)) 1079 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float); 1080 if (DO_BIC(BIC_CorWatt)) 1081 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float); 1082 if (DO_BIC(BIC_GFXWatt)) 1083 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float); 1084 if (DO_BIC(BIC_RAMWatt)) 1085 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units / interval_float); 1086 if (DO_BIC(BIC_Pkg_J)) 1087 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units); 1088 if (DO_BIC(BIC_Cor_J)) 1089 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units); 1090 if (DO_BIC(BIC_GFX_J)) 1091 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units); 1092 if (DO_BIC(BIC_RAM_J)) 1093 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units); 1094 if (DO_BIC(BIC_PKG__)) 1095 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 1096 if (DO_BIC(BIC_RAM__)) 1097 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 1098 1099 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1100 if (mp->format == FORMAT_RAW) { 1101 if (mp->width == 32) 1102 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) p->counter[i]); 1103 else 1104 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]); 1105 } else if (mp->format == FORMAT_DELTA) { 1106 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1107 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]); 1108 else 1109 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]); 1110 } else if (mp->format == FORMAT_PERCENT) { 1111 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i]/tsc); 1112 } 1113 } 1114 1115 done: 1116 if (*(outp - 1) != '\n') 1117 outp += sprintf(outp, "\n"); 1118 1119 return 0; 1120 } 1121 1122 void flush_output_stdout(void) 1123 { 1124 FILE *filep; 1125 1126 if (outf == stderr) 1127 filep = stdout; 1128 else 1129 filep = outf; 1130 1131 fputs(output_buffer, filep); 1132 fflush(filep); 1133 1134 outp = output_buffer; 1135 } 1136 void flush_output_stderr(void) 1137 { 1138 fputs(output_buffer, outf); 1139 fflush(outf); 1140 outp = output_buffer; 1141 } 1142 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1143 { 1144 static int printed; 1145 1146 if (!printed || !summary_only) 1147 print_header("\t"); 1148 1149 if (topo.num_cpus > 1) 1150 format_counters(&average.threads, &average.cores, 1151 &average.packages); 1152 1153 printed = 1; 1154 1155 if (summary_only) 1156 return; 1157 1158 for_all_cpus(format_counters, t, c, p); 1159 } 1160 1161 #define DELTA_WRAP32(new, old) \ 1162 if (new > old) { \ 1163 old = new - old; \ 1164 } else { \ 1165 old = 0x100000000 + new - old; \ 1166 } 1167 1168 int 1169 delta_package(struct pkg_data *new, struct pkg_data *old) 1170 { 1171 int i; 1172 struct msr_counter *mp; 1173 1174 1175 if (DO_BIC(BIC_Totl_c0)) 1176 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; 1177 if (DO_BIC(BIC_Any_c0)) 1178 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; 1179 if (DO_BIC(BIC_GFX_c0)) 1180 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; 1181 if (DO_BIC(BIC_CPUGFX)) 1182 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; 1183 1184 old->pc2 = new->pc2 - old->pc2; 1185 if (DO_BIC(BIC_Pkgpc3)) 1186 old->pc3 = new->pc3 - old->pc3; 1187 if (DO_BIC(BIC_Pkgpc6)) 1188 old->pc6 = new->pc6 - old->pc6; 1189 if (DO_BIC(BIC_Pkgpc7)) 1190 old->pc7 = new->pc7 - old->pc7; 1191 old->pc8 = new->pc8 - old->pc8; 1192 old->pc9 = new->pc9 - old->pc9; 1193 old->pc10 = new->pc10 - old->pc10; 1194 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi; 1195 old->sys_lpi = new->sys_lpi - old->sys_lpi; 1196 old->pkg_temp_c = new->pkg_temp_c; 1197 1198 /* flag an error when rc6 counter resets/wraps */ 1199 if (old->gfx_rc6_ms > new->gfx_rc6_ms) 1200 old->gfx_rc6_ms = -1; 1201 else 1202 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; 1203 1204 old->gfx_mhz = new->gfx_mhz; 1205 1206 DELTA_WRAP32(new->energy_pkg, old->energy_pkg); 1207 DELTA_WRAP32(new->energy_cores, old->energy_cores); 1208 DELTA_WRAP32(new->energy_gfx, old->energy_gfx); 1209 DELTA_WRAP32(new->energy_dram, old->energy_dram); 1210 DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status); 1211 DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status); 1212 1213 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1214 if (mp->format == FORMAT_RAW) 1215 old->counter[i] = new->counter[i]; 1216 else 1217 old->counter[i] = new->counter[i] - old->counter[i]; 1218 } 1219 1220 return 0; 1221 } 1222 1223 void 1224 delta_core(struct core_data *new, struct core_data *old) 1225 { 1226 int i; 1227 struct msr_counter *mp; 1228 1229 old->c3 = new->c3 - old->c3; 1230 old->c6 = new->c6 - old->c6; 1231 old->c7 = new->c7 - old->c7; 1232 old->core_temp_c = new->core_temp_c; 1233 old->mc6_us = new->mc6_us - old->mc6_us; 1234 1235 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1236 if (mp->format == FORMAT_RAW) 1237 old->counter[i] = new->counter[i]; 1238 else 1239 old->counter[i] = new->counter[i] - old->counter[i]; 1240 } 1241 } 1242 1243 /* 1244 * old = new - old 1245 */ 1246 int 1247 delta_thread(struct thread_data *new, struct thread_data *old, 1248 struct core_data *core_delta) 1249 { 1250 int i; 1251 struct msr_counter *mp; 1252 1253 /* we run cpuid just the 1st time, copy the results */ 1254 if (DO_BIC(BIC_APIC)) 1255 new->apic_id = old->apic_id; 1256 if (DO_BIC(BIC_X2APIC)) 1257 new->x2apic_id = old->x2apic_id; 1258 1259 /* 1260 * the timestamps from start of measurement interval are in "old" 1261 * the timestamp from end of measurement interval are in "new" 1262 * over-write old w/ new so we can print end of interval values 1263 */ 1264 1265 old->tv_begin = new->tv_begin; 1266 old->tv_end = new->tv_end; 1267 1268 old->tsc = new->tsc - old->tsc; 1269 1270 /* check for TSC < 1 Mcycles over interval */ 1271 if (old->tsc < (1000 * 1000)) 1272 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" 1273 "You can disable all c-states by booting with \"idle=poll\"\n" 1274 "or just the deep ones with \"processor.max_cstate=1\""); 1275 1276 old->c1 = new->c1 - old->c1; 1277 1278 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) { 1279 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { 1280 old->aperf = new->aperf - old->aperf; 1281 old->mperf = new->mperf - old->mperf; 1282 } else { 1283 return -1; 1284 } 1285 } 1286 1287 1288 if (use_c1_residency_msr) { 1289 /* 1290 * Some models have a dedicated C1 residency MSR, 1291 * which should be more accurate than the derivation below. 1292 */ 1293 } else { 1294 /* 1295 * As counter collection is not atomic, 1296 * it is possible for mperf's non-halted cycles + idle states 1297 * to exceed TSC's all cycles: show c1 = 0% in that case. 1298 */ 1299 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak)) 1300 old->c1 = 0; 1301 else { 1302 /* normal case, derive c1 */ 1303 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3 1304 - core_delta->c6 - core_delta->c7; 1305 } 1306 } 1307 1308 if (old->mperf == 0) { 1309 if (debug > 1) 1310 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); 1311 old->mperf = 1; /* divide by 0 protection */ 1312 } 1313 1314 if (DO_BIC(BIC_IRQ)) 1315 old->irq_count = new->irq_count - old->irq_count; 1316 1317 if (DO_BIC(BIC_SMI)) 1318 old->smi_count = new->smi_count - old->smi_count; 1319 1320 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1321 if (mp->format == FORMAT_RAW) 1322 old->counter[i] = new->counter[i]; 1323 else 1324 old->counter[i] = new->counter[i] - old->counter[i]; 1325 } 1326 return 0; 1327 } 1328 1329 int delta_cpu(struct thread_data *t, struct core_data *c, 1330 struct pkg_data *p, struct thread_data *t2, 1331 struct core_data *c2, struct pkg_data *p2) 1332 { 1333 int retval = 0; 1334 1335 /* calculate core delta only for 1st thread in core */ 1336 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) 1337 delta_core(c, c2); 1338 1339 /* always calculate thread delta */ 1340 retval = delta_thread(t, t2, c2); /* c2 is core delta */ 1341 if (retval) 1342 return retval; 1343 1344 /* calculate package delta only for 1st core in package */ 1345 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) 1346 retval = delta_package(p, p2); 1347 1348 return retval; 1349 } 1350 1351 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1352 { 1353 int i; 1354 struct msr_counter *mp; 1355 1356 t->tv_begin.tv_sec = 0; 1357 t->tv_begin.tv_usec = 0; 1358 t->tv_end.tv_sec = 0; 1359 t->tv_end.tv_usec = 0; 1360 1361 t->tsc = 0; 1362 t->aperf = 0; 1363 t->mperf = 0; 1364 t->c1 = 0; 1365 1366 t->irq_count = 0; 1367 t->smi_count = 0; 1368 1369 /* tells format_counters to dump all fields from this set */ 1370 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; 1371 1372 c->c3 = 0; 1373 c->c6 = 0; 1374 c->c7 = 0; 1375 c->mc6_us = 0; 1376 c->core_temp_c = 0; 1377 1378 p->pkg_wtd_core_c0 = 0; 1379 p->pkg_any_core_c0 = 0; 1380 p->pkg_any_gfxe_c0 = 0; 1381 p->pkg_both_core_gfxe_c0 = 0; 1382 1383 p->pc2 = 0; 1384 if (DO_BIC(BIC_Pkgpc3)) 1385 p->pc3 = 0; 1386 if (DO_BIC(BIC_Pkgpc6)) 1387 p->pc6 = 0; 1388 if (DO_BIC(BIC_Pkgpc7)) 1389 p->pc7 = 0; 1390 p->pc8 = 0; 1391 p->pc9 = 0; 1392 p->pc10 = 0; 1393 p->cpu_lpi = 0; 1394 p->sys_lpi = 0; 1395 1396 p->energy_pkg = 0; 1397 p->energy_dram = 0; 1398 p->energy_cores = 0; 1399 p->energy_gfx = 0; 1400 p->rapl_pkg_perf_status = 0; 1401 p->rapl_dram_perf_status = 0; 1402 p->pkg_temp_c = 0; 1403 1404 p->gfx_rc6_ms = 0; 1405 p->gfx_mhz = 0; 1406 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) 1407 t->counter[i] = 0; 1408 1409 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) 1410 c->counter[i] = 0; 1411 1412 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) 1413 p->counter[i] = 0; 1414 } 1415 int sum_counters(struct thread_data *t, struct core_data *c, 1416 struct pkg_data *p) 1417 { 1418 int i; 1419 struct msr_counter *mp; 1420 1421 /* copy un-changing apic_id's */ 1422 if (DO_BIC(BIC_APIC)) 1423 average.threads.apic_id = t->apic_id; 1424 if (DO_BIC(BIC_X2APIC)) 1425 average.threads.x2apic_id = t->x2apic_id; 1426 1427 /* remember first tv_begin */ 1428 if (average.threads.tv_begin.tv_sec == 0) 1429 average.threads.tv_begin = t->tv_begin; 1430 1431 /* remember last tv_end */ 1432 average.threads.tv_end = t->tv_end; 1433 1434 average.threads.tsc += t->tsc; 1435 average.threads.aperf += t->aperf; 1436 average.threads.mperf += t->mperf; 1437 average.threads.c1 += t->c1; 1438 1439 average.threads.irq_count += t->irq_count; 1440 average.threads.smi_count += t->smi_count; 1441 1442 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1443 if (mp->format == FORMAT_RAW) 1444 continue; 1445 average.threads.counter[i] += t->counter[i]; 1446 } 1447 1448 /* sum per-core values only for 1st thread in core */ 1449 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1450 return 0; 1451 1452 average.cores.c3 += c->c3; 1453 average.cores.c6 += c->c6; 1454 average.cores.c7 += c->c7; 1455 average.cores.mc6_us += c->mc6_us; 1456 1457 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); 1458 1459 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1460 if (mp->format == FORMAT_RAW) 1461 continue; 1462 average.cores.counter[i] += c->counter[i]; 1463 } 1464 1465 /* sum per-pkg values only for 1st core in pkg */ 1466 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1467 return 0; 1468 1469 if (DO_BIC(BIC_Totl_c0)) 1470 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; 1471 if (DO_BIC(BIC_Any_c0)) 1472 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; 1473 if (DO_BIC(BIC_GFX_c0)) 1474 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; 1475 if (DO_BIC(BIC_CPUGFX)) 1476 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; 1477 1478 average.packages.pc2 += p->pc2; 1479 if (DO_BIC(BIC_Pkgpc3)) 1480 average.packages.pc3 += p->pc3; 1481 if (DO_BIC(BIC_Pkgpc6)) 1482 average.packages.pc6 += p->pc6; 1483 if (DO_BIC(BIC_Pkgpc7)) 1484 average.packages.pc7 += p->pc7; 1485 average.packages.pc8 += p->pc8; 1486 average.packages.pc9 += p->pc9; 1487 average.packages.pc10 += p->pc10; 1488 1489 average.packages.cpu_lpi = p->cpu_lpi; 1490 average.packages.sys_lpi = p->sys_lpi; 1491 1492 average.packages.energy_pkg += p->energy_pkg; 1493 average.packages.energy_dram += p->energy_dram; 1494 average.packages.energy_cores += p->energy_cores; 1495 average.packages.energy_gfx += p->energy_gfx; 1496 1497 average.packages.gfx_rc6_ms = p->gfx_rc6_ms; 1498 average.packages.gfx_mhz = p->gfx_mhz; 1499 1500 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); 1501 1502 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; 1503 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; 1504 1505 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1506 if (mp->format == FORMAT_RAW) 1507 continue; 1508 average.packages.counter[i] += p->counter[i]; 1509 } 1510 return 0; 1511 } 1512 /* 1513 * sum the counters for all cpus in the system 1514 * compute the weighted average 1515 */ 1516 void compute_average(struct thread_data *t, struct core_data *c, 1517 struct pkg_data *p) 1518 { 1519 int i; 1520 struct msr_counter *mp; 1521 1522 clear_counters(&average.threads, &average.cores, &average.packages); 1523 1524 for_all_cpus(sum_counters, t, c, p); 1525 1526 average.threads.tsc /= topo.num_cpus; 1527 average.threads.aperf /= topo.num_cpus; 1528 average.threads.mperf /= topo.num_cpus; 1529 average.threads.c1 /= topo.num_cpus; 1530 1531 if (average.threads.irq_count > 9999999) 1532 sums_need_wide_columns = 1; 1533 1534 average.cores.c3 /= topo.num_cores; 1535 average.cores.c6 /= topo.num_cores; 1536 average.cores.c7 /= topo.num_cores; 1537 average.cores.mc6_us /= topo.num_cores; 1538 1539 if (DO_BIC(BIC_Totl_c0)) 1540 average.packages.pkg_wtd_core_c0 /= topo.num_packages; 1541 if (DO_BIC(BIC_Any_c0)) 1542 average.packages.pkg_any_core_c0 /= topo.num_packages; 1543 if (DO_BIC(BIC_GFX_c0)) 1544 average.packages.pkg_any_gfxe_c0 /= topo.num_packages; 1545 if (DO_BIC(BIC_CPUGFX)) 1546 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages; 1547 1548 average.packages.pc2 /= topo.num_packages; 1549 if (DO_BIC(BIC_Pkgpc3)) 1550 average.packages.pc3 /= topo.num_packages; 1551 if (DO_BIC(BIC_Pkgpc6)) 1552 average.packages.pc6 /= topo.num_packages; 1553 if (DO_BIC(BIC_Pkgpc7)) 1554 average.packages.pc7 /= topo.num_packages; 1555 1556 average.packages.pc8 /= topo.num_packages; 1557 average.packages.pc9 /= topo.num_packages; 1558 average.packages.pc10 /= topo.num_packages; 1559 1560 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1561 if (mp->format == FORMAT_RAW) 1562 continue; 1563 if (mp->type == COUNTER_ITEMS) { 1564 if (average.threads.counter[i] > 9999999) 1565 sums_need_wide_columns = 1; 1566 continue; 1567 } 1568 average.threads.counter[i] /= topo.num_cpus; 1569 } 1570 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1571 if (mp->format == FORMAT_RAW) 1572 continue; 1573 if (mp->type == COUNTER_ITEMS) { 1574 if (average.cores.counter[i] > 9999999) 1575 sums_need_wide_columns = 1; 1576 } 1577 average.cores.counter[i] /= topo.num_cores; 1578 } 1579 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1580 if (mp->format == FORMAT_RAW) 1581 continue; 1582 if (mp->type == COUNTER_ITEMS) { 1583 if (average.packages.counter[i] > 9999999) 1584 sums_need_wide_columns = 1; 1585 } 1586 average.packages.counter[i] /= topo.num_packages; 1587 } 1588 } 1589 1590 static unsigned long long rdtsc(void) 1591 { 1592 unsigned int low, high; 1593 1594 asm volatile("rdtsc" : "=a" (low), "=d" (high)); 1595 1596 return low | ((unsigned long long)high) << 32; 1597 } 1598 1599 /* 1600 * Open a file, and exit on failure 1601 */ 1602 FILE *fopen_or_die(const char *path, const char *mode) 1603 { 1604 FILE *filep = fopen(path, mode); 1605 1606 if (!filep) 1607 err(1, "%s: open failed", path); 1608 return filep; 1609 } 1610 /* 1611 * snapshot_sysfs_counter() 1612 * 1613 * return snapshot of given counter 1614 */ 1615 unsigned long long snapshot_sysfs_counter(char *path) 1616 { 1617 FILE *fp; 1618 int retval; 1619 unsigned long long counter; 1620 1621 fp = fopen_or_die(path, "r"); 1622 1623 retval = fscanf(fp, "%lld", &counter); 1624 if (retval != 1) 1625 err(1, "snapshot_sysfs_counter(%s)", path); 1626 1627 fclose(fp); 1628 1629 return counter; 1630 } 1631 1632 int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp) 1633 { 1634 if (mp->msr_num != 0) { 1635 if (get_msr(cpu, mp->msr_num, counterp)) 1636 return -1; 1637 } else { 1638 char path[128 + PATH_BYTES]; 1639 1640 if (mp->flags & SYSFS_PERCPU) { 1641 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s", 1642 cpu, mp->path); 1643 1644 *counterp = snapshot_sysfs_counter(path); 1645 } else { 1646 *counterp = snapshot_sysfs_counter(mp->path); 1647 } 1648 } 1649 1650 return 0; 1651 } 1652 1653 void get_apic_id(struct thread_data *t) 1654 { 1655 unsigned int eax, ebx, ecx, edx, max_level; 1656 1657 eax = ebx = ecx = edx = 0; 1658 1659 if (!genuine_intel) 1660 return; 1661 1662 __cpuid(0, max_level, ebx, ecx, edx); 1663 1664 __cpuid(1, eax, ebx, ecx, edx); 1665 t->apic_id = (ebx >> 24) & 0xf; 1666 1667 if (max_level < 0xb) 1668 return; 1669 1670 if (!DO_BIC(BIC_X2APIC)) 1671 return; 1672 1673 ecx = 0; 1674 __cpuid(0xb, eax, ebx, ecx, edx); 1675 t->x2apic_id = edx; 1676 1677 if (debug && (t->apic_id != t->x2apic_id)) 1678 fprintf(stderr, "cpu%d: apic 0x%x x2apic 0x%x\n", t->cpu_id, t->apic_id, t->x2apic_id); 1679 } 1680 1681 /* 1682 * get_counters(...) 1683 * migrate to cpu 1684 * acquire and record local counters for that cpu 1685 */ 1686 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1687 { 1688 int cpu = t->cpu_id; 1689 unsigned long long msr; 1690 int aperf_mperf_retry_count = 0; 1691 struct msr_counter *mp; 1692 int i; 1693 1694 gettimeofday(&t->tv_begin, (struct timezone *)NULL); 1695 1696 if (cpu_migrate(cpu)) { 1697 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 1698 return -1; 1699 } 1700 1701 if (first_counter_read) 1702 get_apic_id(t); 1703 retry: 1704 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 1705 1706 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) { 1707 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; 1708 1709 /* 1710 * The TSC, APERF and MPERF must be read together for 1711 * APERF/MPERF and MPERF/TSC to give accurate results. 1712 * 1713 * Unfortunately, APERF and MPERF are read by 1714 * individual system call, so delays may occur 1715 * between them. If the time to read them 1716 * varies by a large amount, we re-read them. 1717 */ 1718 1719 /* 1720 * This initial dummy APERF read has been seen to 1721 * reduce jitter in the subsequent reads. 1722 */ 1723 1724 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1725 return -3; 1726 1727 t->tsc = rdtsc(); /* re-read close to APERF */ 1728 1729 tsc_before = t->tsc; 1730 1731 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1732 return -3; 1733 1734 tsc_between = rdtsc(); 1735 1736 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) 1737 return -4; 1738 1739 tsc_after = rdtsc(); 1740 1741 aperf_time = tsc_between - tsc_before; 1742 mperf_time = tsc_after - tsc_between; 1743 1744 /* 1745 * If the system call latency to read APERF and MPERF 1746 * differ by more than 2x, then try again. 1747 */ 1748 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { 1749 aperf_mperf_retry_count++; 1750 if (aperf_mperf_retry_count < 5) 1751 goto retry; 1752 else 1753 warnx("cpu%d jitter %lld %lld", 1754 cpu, aperf_time, mperf_time); 1755 } 1756 aperf_mperf_retry_count = 0; 1757 1758 t->aperf = t->aperf * aperf_mperf_multiplier; 1759 t->mperf = t->mperf * aperf_mperf_multiplier; 1760 } 1761 1762 if (DO_BIC(BIC_IRQ)) 1763 t->irq_count = irqs_per_cpu[cpu]; 1764 if (DO_BIC(BIC_SMI)) { 1765 if (get_msr(cpu, MSR_SMI_COUNT, &msr)) 1766 return -5; 1767 t->smi_count = msr & 0xFFFFFFFF; 1768 } 1769 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) { 1770 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) 1771 return -6; 1772 } 1773 1774 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1775 if (get_mp(cpu, mp, &t->counter[i])) 1776 return -10; 1777 } 1778 1779 /* collect core counters only for 1st thread in core */ 1780 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1781 goto done; 1782 1783 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates && !do_cnl_cstates) { 1784 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) 1785 return -6; 1786 } 1787 1788 if (DO_BIC(BIC_CPU_c6) && !do_knl_cstates) { 1789 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) 1790 return -7; 1791 } else if (do_knl_cstates) { 1792 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) 1793 return -7; 1794 } 1795 1796 if (DO_BIC(BIC_CPU_c7)) 1797 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 1798 return -8; 1799 1800 if (DO_BIC(BIC_Mod_c6)) 1801 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us)) 1802 return -8; 1803 1804 if (DO_BIC(BIC_CoreTmp)) { 1805 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 1806 return -9; 1807 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1808 } 1809 1810 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1811 if (get_mp(cpu, mp, &c->counter[i])) 1812 return -10; 1813 } 1814 1815 /* collect package counters only for 1st core in package */ 1816 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1817 goto done; 1818 1819 if (DO_BIC(BIC_Totl_c0)) { 1820 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) 1821 return -10; 1822 } 1823 if (DO_BIC(BIC_Any_c0)) { 1824 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) 1825 return -11; 1826 } 1827 if (DO_BIC(BIC_GFX_c0)) { 1828 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) 1829 return -12; 1830 } 1831 if (DO_BIC(BIC_CPUGFX)) { 1832 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) 1833 return -13; 1834 } 1835 if (DO_BIC(BIC_Pkgpc3)) 1836 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) 1837 return -9; 1838 if (DO_BIC(BIC_Pkgpc6)) { 1839 if (do_slm_cstates) { 1840 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6)) 1841 return -10; 1842 } else { 1843 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) 1844 return -10; 1845 } 1846 } 1847 1848 if (DO_BIC(BIC_Pkgpc2)) 1849 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) 1850 return -11; 1851 if (DO_BIC(BIC_Pkgpc7)) 1852 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) 1853 return -12; 1854 if (DO_BIC(BIC_Pkgpc8)) 1855 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) 1856 return -13; 1857 if (DO_BIC(BIC_Pkgpc9)) 1858 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) 1859 return -13; 1860 if (DO_BIC(BIC_Pkgpc10)) 1861 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) 1862 return -13; 1863 1864 if (DO_BIC(BIC_CPU_LPI)) 1865 p->cpu_lpi = cpuidle_cur_cpu_lpi_us; 1866 if (DO_BIC(BIC_SYS_LPI)) 1867 p->sys_lpi = cpuidle_cur_sys_lpi_us; 1868 1869 if (do_rapl & RAPL_PKG) { 1870 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr)) 1871 return -13; 1872 p->energy_pkg = msr & 0xFFFFFFFF; 1873 } 1874 if (do_rapl & RAPL_CORES_ENERGY_STATUS) { 1875 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr)) 1876 return -14; 1877 p->energy_cores = msr & 0xFFFFFFFF; 1878 } 1879 if (do_rapl & RAPL_DRAM) { 1880 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) 1881 return -15; 1882 p->energy_dram = msr & 0xFFFFFFFF; 1883 } 1884 if (do_rapl & RAPL_GFX) { 1885 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr)) 1886 return -16; 1887 p->energy_gfx = msr & 0xFFFFFFFF; 1888 } 1889 if (do_rapl & RAPL_PKG_PERF_STATUS) { 1890 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr)) 1891 return -16; 1892 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF; 1893 } 1894 if (do_rapl & RAPL_DRAM_PERF_STATUS) { 1895 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr)) 1896 return -16; 1897 p->rapl_dram_perf_status = msr & 0xFFFFFFFF; 1898 } 1899 if (DO_BIC(BIC_PkgTmp)) { 1900 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 1901 return -17; 1902 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1903 } 1904 1905 if (DO_BIC(BIC_GFX_rc6)) 1906 p->gfx_rc6_ms = gfx_cur_rc6_ms; 1907 1908 if (DO_BIC(BIC_GFXMHz)) 1909 p->gfx_mhz = gfx_cur_mhz; 1910 1911 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1912 if (get_mp(cpu, mp, &p->counter[i])) 1913 return -10; 1914 } 1915 done: 1916 gettimeofday(&t->tv_end, (struct timezone *)NULL); 1917 1918 return 0; 1919 } 1920 1921 /* 1922 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: 1923 * If you change the values, note they are used both in comparisons 1924 * (>= PCL__7) and to index pkg_cstate_limit_strings[]. 1925 */ 1926 1927 #define PCLUKN 0 /* Unknown */ 1928 #define PCLRSV 1 /* Reserved */ 1929 #define PCL__0 2 /* PC0 */ 1930 #define PCL__1 3 /* PC1 */ 1931 #define PCL__2 4 /* PC2 */ 1932 #define PCL__3 5 /* PC3 */ 1933 #define PCL__4 6 /* PC4 */ 1934 #define PCL__6 7 /* PC6 */ 1935 #define PCL_6N 8 /* PC6 No Retention */ 1936 #define PCL_6R 9 /* PC6 Retention */ 1937 #define PCL__7 10 /* PC7 */ 1938 #define PCL_7S 11 /* PC7 Shrink */ 1939 #define PCL__8 12 /* PC8 */ 1940 #define PCL__9 13 /* PC9 */ 1941 #define PCLUNL 14 /* Unlimited */ 1942 1943 int pkg_cstate_limit = PCLUKN; 1944 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", 1945 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"}; 1946 1947 int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1948 int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1949 int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1950 int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7}; 1951 int amt_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1952 int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1953 int bxt_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1954 int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1955 1956 1957 static void 1958 calculate_tsc_tweak() 1959 { 1960 tsc_tweak = base_hz / tsc_hz; 1961 } 1962 1963 static void 1964 dump_nhm_platform_info(void) 1965 { 1966 unsigned long long msr; 1967 unsigned int ratio; 1968 1969 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 1970 1971 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 1972 1973 ratio = (msr >> 40) & 0xFF; 1974 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", 1975 ratio, bclk, ratio * bclk); 1976 1977 ratio = (msr >> 8) & 0xFF; 1978 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", 1979 ratio, bclk, ratio * bclk); 1980 1981 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); 1982 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", 1983 base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); 1984 1985 return; 1986 } 1987 1988 static void 1989 dump_hsw_turbo_ratio_limits(void) 1990 { 1991 unsigned long long msr; 1992 unsigned int ratio; 1993 1994 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); 1995 1996 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); 1997 1998 ratio = (msr >> 8) & 0xFF; 1999 if (ratio) 2000 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", 2001 ratio, bclk, ratio * bclk); 2002 2003 ratio = (msr >> 0) & 0xFF; 2004 if (ratio) 2005 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", 2006 ratio, bclk, ratio * bclk); 2007 return; 2008 } 2009 2010 static void 2011 dump_ivt_turbo_ratio_limits(void) 2012 { 2013 unsigned long long msr; 2014 unsigned int ratio; 2015 2016 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); 2017 2018 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); 2019 2020 ratio = (msr >> 56) & 0xFF; 2021 if (ratio) 2022 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", 2023 ratio, bclk, ratio * bclk); 2024 2025 ratio = (msr >> 48) & 0xFF; 2026 if (ratio) 2027 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", 2028 ratio, bclk, ratio * bclk); 2029 2030 ratio = (msr >> 40) & 0xFF; 2031 if (ratio) 2032 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", 2033 ratio, bclk, ratio * bclk); 2034 2035 ratio = (msr >> 32) & 0xFF; 2036 if (ratio) 2037 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", 2038 ratio, bclk, ratio * bclk); 2039 2040 ratio = (msr >> 24) & 0xFF; 2041 if (ratio) 2042 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", 2043 ratio, bclk, ratio * bclk); 2044 2045 ratio = (msr >> 16) & 0xFF; 2046 if (ratio) 2047 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", 2048 ratio, bclk, ratio * bclk); 2049 2050 ratio = (msr >> 8) & 0xFF; 2051 if (ratio) 2052 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", 2053 ratio, bclk, ratio * bclk); 2054 2055 ratio = (msr >> 0) & 0xFF; 2056 if (ratio) 2057 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", 2058 ratio, bclk, ratio * bclk); 2059 return; 2060 } 2061 int has_turbo_ratio_group_limits(int family, int model) 2062 { 2063 2064 if (!genuine_intel) 2065 return 0; 2066 2067 switch (model) { 2068 case INTEL_FAM6_ATOM_GOLDMONT: 2069 case INTEL_FAM6_SKYLAKE_X: 2070 case INTEL_FAM6_ATOM_DENVERTON: 2071 return 1; 2072 } 2073 return 0; 2074 } 2075 2076 static void 2077 dump_turbo_ratio_limits(int family, int model) 2078 { 2079 unsigned long long msr, core_counts; 2080 unsigned int ratio, group_size; 2081 2082 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2083 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 2084 2085 if (has_turbo_ratio_group_limits(family, model)) { 2086 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts); 2087 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts); 2088 } else { 2089 core_counts = 0x0807060504030201; 2090 } 2091 2092 ratio = (msr >> 56) & 0xFF; 2093 group_size = (core_counts >> 56) & 0xFF; 2094 if (ratio) 2095 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2096 ratio, bclk, ratio * bclk, group_size); 2097 2098 ratio = (msr >> 48) & 0xFF; 2099 group_size = (core_counts >> 48) & 0xFF; 2100 if (ratio) 2101 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2102 ratio, bclk, ratio * bclk, group_size); 2103 2104 ratio = (msr >> 40) & 0xFF; 2105 group_size = (core_counts >> 40) & 0xFF; 2106 if (ratio) 2107 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2108 ratio, bclk, ratio * bclk, group_size); 2109 2110 ratio = (msr >> 32) & 0xFF; 2111 group_size = (core_counts >> 32) & 0xFF; 2112 if (ratio) 2113 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2114 ratio, bclk, ratio * bclk, group_size); 2115 2116 ratio = (msr >> 24) & 0xFF; 2117 group_size = (core_counts >> 24) & 0xFF; 2118 if (ratio) 2119 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2120 ratio, bclk, ratio * bclk, group_size); 2121 2122 ratio = (msr >> 16) & 0xFF; 2123 group_size = (core_counts >> 16) & 0xFF; 2124 if (ratio) 2125 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2126 ratio, bclk, ratio * bclk, group_size); 2127 2128 ratio = (msr >> 8) & 0xFF; 2129 group_size = (core_counts >> 8) & 0xFF; 2130 if (ratio) 2131 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2132 ratio, bclk, ratio * bclk, group_size); 2133 2134 ratio = (msr >> 0) & 0xFF; 2135 group_size = (core_counts >> 0) & 0xFF; 2136 if (ratio) 2137 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2138 ratio, bclk, ratio * bclk, group_size); 2139 return; 2140 } 2141 2142 static void 2143 dump_atom_turbo_ratio_limits(void) 2144 { 2145 unsigned long long msr; 2146 unsigned int ratio; 2147 2148 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr); 2149 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2150 2151 ratio = (msr >> 0) & 0x3F; 2152 if (ratio) 2153 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", 2154 ratio, bclk, ratio * bclk); 2155 2156 ratio = (msr >> 8) & 0x3F; 2157 if (ratio) 2158 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", 2159 ratio, bclk, ratio * bclk); 2160 2161 ratio = (msr >> 16) & 0x3F; 2162 if (ratio) 2163 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", 2164 ratio, bclk, ratio * bclk); 2165 2166 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr); 2167 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2168 2169 ratio = (msr >> 24) & 0x3F; 2170 if (ratio) 2171 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", 2172 ratio, bclk, ratio * bclk); 2173 2174 ratio = (msr >> 16) & 0x3F; 2175 if (ratio) 2176 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", 2177 ratio, bclk, ratio * bclk); 2178 2179 ratio = (msr >> 8) & 0x3F; 2180 if (ratio) 2181 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", 2182 ratio, bclk, ratio * bclk); 2183 2184 ratio = (msr >> 0) & 0x3F; 2185 if (ratio) 2186 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", 2187 ratio, bclk, ratio * bclk); 2188 } 2189 2190 static void 2191 dump_knl_turbo_ratio_limits(void) 2192 { 2193 const unsigned int buckets_no = 7; 2194 2195 unsigned long long msr; 2196 int delta_cores, delta_ratio; 2197 int i, b_nr; 2198 unsigned int cores[buckets_no]; 2199 unsigned int ratio[buckets_no]; 2200 2201 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2202 2203 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", 2204 base_cpu, msr); 2205 2206 /** 2207 * Turbo encoding in KNL is as follows: 2208 * [0] -- Reserved 2209 * [7:1] -- Base value of number of active cores of bucket 1. 2210 * [15:8] -- Base value of freq ratio of bucket 1. 2211 * [20:16] -- +ve delta of number of active cores of bucket 2. 2212 * i.e. active cores of bucket 2 = 2213 * active cores of bucket 1 + delta 2214 * [23:21] -- Negative delta of freq ratio of bucket 2. 2215 * i.e. freq ratio of bucket 2 = 2216 * freq ratio of bucket 1 - delta 2217 * [28:24]-- +ve delta of number of active cores of bucket 3. 2218 * [31:29]-- -ve delta of freq ratio of bucket 3. 2219 * [36:32]-- +ve delta of number of active cores of bucket 4. 2220 * [39:37]-- -ve delta of freq ratio of bucket 4. 2221 * [44:40]-- +ve delta of number of active cores of bucket 5. 2222 * [47:45]-- -ve delta of freq ratio of bucket 5. 2223 * [52:48]-- +ve delta of number of active cores of bucket 6. 2224 * [55:53]-- -ve delta of freq ratio of bucket 6. 2225 * [60:56]-- +ve delta of number of active cores of bucket 7. 2226 * [63:61]-- -ve delta of freq ratio of bucket 7. 2227 */ 2228 2229 b_nr = 0; 2230 cores[b_nr] = (msr & 0xFF) >> 1; 2231 ratio[b_nr] = (msr >> 8) & 0xFF; 2232 2233 for (i = 16; i < 64; i += 8) { 2234 delta_cores = (msr >> i) & 0x1F; 2235 delta_ratio = (msr >> (i + 5)) & 0x7; 2236 2237 cores[b_nr + 1] = cores[b_nr] + delta_cores; 2238 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; 2239 b_nr++; 2240 } 2241 2242 for (i = buckets_no - 1; i >= 0; i--) 2243 if (i > 0 ? ratio[i] != ratio[i - 1] : 1) 2244 fprintf(outf, 2245 "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2246 ratio[i], bclk, ratio[i] * bclk, cores[i]); 2247 } 2248 2249 static void 2250 dump_nhm_cst_cfg(void) 2251 { 2252 unsigned long long msr; 2253 2254 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 2255 2256 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr); 2257 2258 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)", 2259 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", 2260 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", 2261 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", 2262 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", 2263 (msr & (1 << 15)) ? "" : "UN", 2264 (unsigned int)msr & 0xF, 2265 pkg_cstate_limit_strings[pkg_cstate_limit]); 2266 2267 #define AUTOMATIC_CSTATE_CONVERSION (1UL << 16) 2268 if (has_automatic_cstate_conversion) { 2269 fprintf(outf, ", automatic c-state conversion=%s", 2270 (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off"); 2271 } 2272 2273 fprintf(outf, ")\n"); 2274 2275 return; 2276 } 2277 2278 static void 2279 dump_config_tdp(void) 2280 { 2281 unsigned long long msr; 2282 2283 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); 2284 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); 2285 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); 2286 2287 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); 2288 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); 2289 if (msr) { 2290 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2291 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2292 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2293 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); 2294 } 2295 fprintf(outf, ")\n"); 2296 2297 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); 2298 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); 2299 if (msr) { 2300 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2301 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2302 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2303 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); 2304 } 2305 fprintf(outf, ")\n"); 2306 2307 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); 2308 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); 2309 if ((msr) & 0x3) 2310 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); 2311 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2312 fprintf(outf, ")\n"); 2313 2314 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); 2315 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); 2316 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); 2317 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2318 fprintf(outf, ")\n"); 2319 } 2320 2321 unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; 2322 2323 void print_irtl(void) 2324 { 2325 unsigned long long msr; 2326 2327 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr); 2328 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr); 2329 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2330 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2331 2332 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr); 2333 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr); 2334 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2335 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2336 2337 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr); 2338 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr); 2339 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2340 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2341 2342 if (!do_irtl_hsw) 2343 return; 2344 2345 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr); 2346 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr); 2347 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2348 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2349 2350 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr); 2351 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr); 2352 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2353 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2354 2355 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr); 2356 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr); 2357 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2358 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2359 2360 } 2361 void free_fd_percpu(void) 2362 { 2363 int i; 2364 2365 for (i = 0; i < topo.max_cpu_num + 1; ++i) { 2366 if (fd_percpu[i] != 0) 2367 close(fd_percpu[i]); 2368 } 2369 2370 free(fd_percpu); 2371 } 2372 2373 void free_all_buffers(void) 2374 { 2375 int i; 2376 2377 CPU_FREE(cpu_present_set); 2378 cpu_present_set = NULL; 2379 cpu_present_setsize = 0; 2380 2381 CPU_FREE(cpu_affinity_set); 2382 cpu_affinity_set = NULL; 2383 cpu_affinity_setsize = 0; 2384 2385 free(thread_even); 2386 free(core_even); 2387 free(package_even); 2388 2389 thread_even = NULL; 2390 core_even = NULL; 2391 package_even = NULL; 2392 2393 free(thread_odd); 2394 free(core_odd); 2395 free(package_odd); 2396 2397 thread_odd = NULL; 2398 core_odd = NULL; 2399 package_odd = NULL; 2400 2401 free(output_buffer); 2402 output_buffer = NULL; 2403 outp = NULL; 2404 2405 free_fd_percpu(); 2406 2407 free(irq_column_2_cpu); 2408 free(irqs_per_cpu); 2409 2410 for (i = 0; i <= topo.max_cpu_num; ++i) { 2411 if (cpus[i].put_ids) 2412 CPU_FREE(cpus[i].put_ids); 2413 } 2414 free(cpus); 2415 } 2416 2417 2418 /* 2419 * Parse a file containing a single int. 2420 */ 2421 int parse_int_file(const char *fmt, ...) 2422 { 2423 va_list args; 2424 char path[PATH_MAX]; 2425 FILE *filep; 2426 int value; 2427 2428 va_start(args, fmt); 2429 vsnprintf(path, sizeof(path), fmt, args); 2430 va_end(args); 2431 filep = fopen_or_die(path, "r"); 2432 if (fscanf(filep, "%d", &value) != 1) 2433 err(1, "%s: failed to parse number from file", path); 2434 fclose(filep); 2435 return value; 2436 } 2437 2438 /* 2439 * cpu_is_first_core_in_package(cpu) 2440 * return 1 if given CPU is 1st core in package 2441 */ 2442 int cpu_is_first_core_in_package(int cpu) 2443 { 2444 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); 2445 } 2446 2447 int get_physical_package_id(int cpu) 2448 { 2449 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); 2450 } 2451 2452 int get_core_id(int cpu) 2453 { 2454 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); 2455 } 2456 2457 void set_node_data(void) 2458 { 2459 char path[80]; 2460 FILE *filep; 2461 int pkg, node, cpu; 2462 2463 struct pkg_node_info { 2464 int count; 2465 int min; 2466 } *pni; 2467 2468 pni = calloc(topo.num_packages, sizeof(struct pkg_node_info)); 2469 if (!pni) 2470 err(1, "calloc pkg_node_count"); 2471 2472 for (pkg = 0; pkg < topo.num_packages; pkg++) 2473 pni[pkg].min = topo.num_cpus; 2474 2475 for (node = 0; node <= topo.max_node_num; node++) { 2476 /* find the "first" cpu in the node */ 2477 sprintf(path, "/sys/bus/node/devices/node%d/cpulist", node); 2478 filep = fopen(path, "r"); 2479 if (!filep) 2480 continue; 2481 fscanf(filep, "%d", &cpu); 2482 fclose(filep); 2483 2484 pkg = cpus[cpu].physical_package_id; 2485 pni[pkg].count++; 2486 2487 if (node < pni[pkg].min) 2488 pni[pkg].min = node; 2489 } 2490 2491 for (pkg = 0; pkg < topo.num_packages; pkg++) 2492 if (pni[pkg].count > topo.nodes_per_pkg) 2493 topo.nodes_per_pkg = pni[0].count; 2494 2495 for (cpu = 0; cpu < topo.num_cpus; cpu++) { 2496 pkg = cpus[cpu].physical_package_id; 2497 node = cpus[cpu].physical_node_id; 2498 cpus[cpu].logical_node_id = node - pni[pkg].min; 2499 } 2500 free(pni); 2501 2502 } 2503 2504 int get_physical_node_id(struct cpu_topology *thiscpu) 2505 { 2506 char path[80]; 2507 FILE *filep; 2508 int i; 2509 int cpu = thiscpu->logical_cpu_id; 2510 2511 for (i = 0; i <= topo.max_cpu_num; i++) { 2512 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist", 2513 cpu, i); 2514 filep = fopen(path, "r"); 2515 if (!filep) 2516 continue; 2517 fclose(filep); 2518 return i; 2519 } 2520 return -1; 2521 } 2522 2523 int get_thread_siblings(struct cpu_topology *thiscpu) 2524 { 2525 char path[80], character; 2526 FILE *filep; 2527 unsigned long map; 2528 int so, shift, sib_core; 2529 int cpu = thiscpu->logical_cpu_id; 2530 int offset = topo.max_cpu_num + 1; 2531 size_t size; 2532 int thread_id = 0; 2533 2534 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1)); 2535 if (thiscpu->thread_id < 0) 2536 thiscpu->thread_id = thread_id++; 2537 if (!thiscpu->put_ids) 2538 return -1; 2539 2540 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 2541 CPU_ZERO_S(size, thiscpu->put_ids); 2542 2543 sprintf(path, 2544 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu); 2545 filep = fopen_or_die(path, "r"); 2546 do { 2547 offset -= BITMASK_SIZE; 2548 fscanf(filep, "%lx%c", &map, &character); 2549 for (shift = 0; shift < BITMASK_SIZE; shift++) { 2550 if ((map >> shift) & 0x1) { 2551 so = shift + offset; 2552 sib_core = get_core_id(so); 2553 if (sib_core == thiscpu->physical_core_id) { 2554 CPU_SET_S(so, size, thiscpu->put_ids); 2555 if ((so != cpu) && 2556 (cpus[so].thread_id < 0)) 2557 cpus[so].thread_id = 2558 thread_id++; 2559 } 2560 } 2561 } 2562 } while (!strncmp(&character, ",", 1)); 2563 fclose(filep); 2564 2565 return CPU_COUNT_S(size, thiscpu->put_ids); 2566 } 2567 2568 /* 2569 * run func(thread, core, package) in topology order 2570 * skip non-present cpus 2571 */ 2572 2573 int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *, 2574 struct pkg_data *, struct thread_data *, struct core_data *, 2575 struct pkg_data *), struct thread_data *thread_base, 2576 struct core_data *core_base, struct pkg_data *pkg_base, 2577 struct thread_data *thread_base2, struct core_data *core_base2, 2578 struct pkg_data *pkg_base2) 2579 { 2580 int retval, pkg_no, node_no, core_no, thread_no; 2581 2582 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 2583 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) { 2584 for (core_no = 0; core_no < topo.cores_per_node; 2585 ++core_no) { 2586 for (thread_no = 0; thread_no < 2587 topo.threads_per_core; ++thread_no) { 2588 struct thread_data *t, *t2; 2589 struct core_data *c, *c2; 2590 struct pkg_data *p, *p2; 2591 2592 t = GET_THREAD(thread_base, thread_no, 2593 core_no, node_no, 2594 pkg_no); 2595 2596 if (cpu_is_not_present(t->cpu_id)) 2597 continue; 2598 2599 t2 = GET_THREAD(thread_base2, thread_no, 2600 core_no, node_no, 2601 pkg_no); 2602 2603 c = GET_CORE(core_base, core_no, 2604 node_no, pkg_no); 2605 c2 = GET_CORE(core_base2, core_no, 2606 node_no, 2607 pkg_no); 2608 2609 p = GET_PKG(pkg_base, pkg_no); 2610 p2 = GET_PKG(pkg_base2, pkg_no); 2611 2612 retval = func(t, c, p, t2, c2, p2); 2613 if (retval) 2614 return retval; 2615 } 2616 } 2617 } 2618 } 2619 return 0; 2620 } 2621 2622 /* 2623 * run func(cpu) on every cpu in /proc/stat 2624 * return max_cpu number 2625 */ 2626 int for_all_proc_cpus(int (func)(int)) 2627 { 2628 FILE *fp; 2629 int cpu_num; 2630 int retval; 2631 2632 fp = fopen_or_die(proc_stat, "r"); 2633 2634 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); 2635 if (retval != 0) 2636 err(1, "%s: failed to parse format", proc_stat); 2637 2638 while (1) { 2639 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); 2640 if (retval != 1) 2641 break; 2642 2643 retval = func(cpu_num); 2644 if (retval) { 2645 fclose(fp); 2646 return(retval); 2647 } 2648 } 2649 fclose(fp); 2650 return 0; 2651 } 2652 2653 void re_initialize(void) 2654 { 2655 free_all_buffers(); 2656 setup_all_buffers(); 2657 printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); 2658 } 2659 2660 void set_max_cpu_num(void) 2661 { 2662 FILE *filep; 2663 unsigned long dummy; 2664 2665 topo.max_cpu_num = 0; 2666 filep = fopen_or_die( 2667 "/sys/devices/system/cpu/cpu0/topology/thread_siblings", 2668 "r"); 2669 while (fscanf(filep, "%lx,", &dummy) == 1) 2670 topo.max_cpu_num += BITMASK_SIZE; 2671 fclose(filep); 2672 topo.max_cpu_num--; /* 0 based */ 2673 } 2674 2675 /* 2676 * count_cpus() 2677 * remember the last one seen, it will be the max 2678 */ 2679 int count_cpus(int cpu) 2680 { 2681 topo.num_cpus++; 2682 return 0; 2683 } 2684 int mark_cpu_present(int cpu) 2685 { 2686 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); 2687 return 0; 2688 } 2689 2690 int init_thread_id(int cpu) 2691 { 2692 cpus[cpu].thread_id = -1; 2693 return 0; 2694 } 2695 2696 /* 2697 * snapshot_proc_interrupts() 2698 * 2699 * read and record summary of /proc/interrupts 2700 * 2701 * return 1 if config change requires a restart, else return 0 2702 */ 2703 int snapshot_proc_interrupts(void) 2704 { 2705 static FILE *fp; 2706 int column, retval; 2707 2708 if (fp == NULL) 2709 fp = fopen_or_die("/proc/interrupts", "r"); 2710 else 2711 rewind(fp); 2712 2713 /* read 1st line of /proc/interrupts to get cpu* name for each column */ 2714 for (column = 0; column < topo.num_cpus; ++column) { 2715 int cpu_number; 2716 2717 retval = fscanf(fp, " CPU%d", &cpu_number); 2718 if (retval != 1) 2719 break; 2720 2721 if (cpu_number > topo.max_cpu_num) { 2722 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); 2723 return 1; 2724 } 2725 2726 irq_column_2_cpu[column] = cpu_number; 2727 irqs_per_cpu[cpu_number] = 0; 2728 } 2729 2730 /* read /proc/interrupt count lines and sum up irqs per cpu */ 2731 while (1) { 2732 int column; 2733 char buf[64]; 2734 2735 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ 2736 if (retval != 1) 2737 break; 2738 2739 /* read the count per cpu */ 2740 for (column = 0; column < topo.num_cpus; ++column) { 2741 2742 int cpu_number, irq_count; 2743 2744 retval = fscanf(fp, " %d", &irq_count); 2745 if (retval != 1) 2746 break; 2747 2748 cpu_number = irq_column_2_cpu[column]; 2749 irqs_per_cpu[cpu_number] += irq_count; 2750 2751 } 2752 2753 while (getc(fp) != '\n') 2754 ; /* flush interrupt description */ 2755 2756 } 2757 return 0; 2758 } 2759 /* 2760 * snapshot_gfx_rc6_ms() 2761 * 2762 * record snapshot of 2763 * /sys/class/drm/card0/power/rc6_residency_ms 2764 * 2765 * return 1 if config change requires a restart, else return 0 2766 */ 2767 int snapshot_gfx_rc6_ms(void) 2768 { 2769 FILE *fp; 2770 int retval; 2771 2772 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); 2773 2774 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); 2775 if (retval != 1) 2776 err(1, "GFX rc6"); 2777 2778 fclose(fp); 2779 2780 return 0; 2781 } 2782 /* 2783 * snapshot_gfx_mhz() 2784 * 2785 * record snapshot of 2786 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz 2787 * 2788 * return 1 if config change requires a restart, else return 0 2789 */ 2790 int snapshot_gfx_mhz(void) 2791 { 2792 static FILE *fp; 2793 int retval; 2794 2795 if (fp == NULL) 2796 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); 2797 else { 2798 rewind(fp); 2799 fflush(fp); 2800 } 2801 2802 retval = fscanf(fp, "%d", &gfx_cur_mhz); 2803 if (retval != 1) 2804 err(1, "GFX MHz"); 2805 2806 return 0; 2807 } 2808 2809 /* 2810 * snapshot_cpu_lpi() 2811 * 2812 * record snapshot of 2813 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us 2814 * 2815 * return 1 if config change requires a restart, else return 0 2816 */ 2817 int snapshot_cpu_lpi_us(void) 2818 { 2819 FILE *fp; 2820 int retval; 2821 2822 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r"); 2823 2824 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us); 2825 if (retval != 1) 2826 err(1, "CPU LPI"); 2827 2828 fclose(fp); 2829 2830 return 0; 2831 } 2832 /* 2833 * snapshot_sys_lpi() 2834 * 2835 * record snapshot of 2836 * /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us 2837 * 2838 * return 1 if config change requires a restart, else return 0 2839 */ 2840 int snapshot_sys_lpi_us(void) 2841 { 2842 FILE *fp; 2843 int retval; 2844 2845 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us", "r"); 2846 2847 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us); 2848 if (retval != 1) 2849 err(1, "SYS LPI"); 2850 2851 fclose(fp); 2852 2853 return 0; 2854 } 2855 /* 2856 * snapshot /proc and /sys files 2857 * 2858 * return 1 if configuration restart needed, else return 0 2859 */ 2860 int snapshot_proc_sysfs_files(void) 2861 { 2862 if (DO_BIC(BIC_IRQ)) 2863 if (snapshot_proc_interrupts()) 2864 return 1; 2865 2866 if (DO_BIC(BIC_GFX_rc6)) 2867 snapshot_gfx_rc6_ms(); 2868 2869 if (DO_BIC(BIC_GFXMHz)) 2870 snapshot_gfx_mhz(); 2871 2872 if (DO_BIC(BIC_CPU_LPI)) 2873 snapshot_cpu_lpi_us(); 2874 2875 if (DO_BIC(BIC_SYS_LPI)) 2876 snapshot_sys_lpi_us(); 2877 2878 return 0; 2879 } 2880 2881 int exit_requested; 2882 2883 static void signal_handler (int signal) 2884 { 2885 switch (signal) { 2886 case SIGINT: 2887 exit_requested = 1; 2888 if (debug) 2889 fprintf(stderr, " SIGINT\n"); 2890 break; 2891 case SIGUSR1: 2892 if (debug > 1) 2893 fprintf(stderr, "SIGUSR1\n"); 2894 break; 2895 } 2896 /* make sure this manually-invoked interval is at least 1ms long */ 2897 nanosleep(&one_msec, NULL); 2898 } 2899 2900 void setup_signal_handler(void) 2901 { 2902 struct sigaction sa; 2903 2904 memset(&sa, 0, sizeof(sa)); 2905 2906 sa.sa_handler = &signal_handler; 2907 2908 if (sigaction(SIGINT, &sa, NULL) < 0) 2909 err(1, "sigaction SIGINT"); 2910 if (sigaction(SIGUSR1, &sa, NULL) < 0) 2911 err(1, "sigaction SIGUSR1"); 2912 } 2913 2914 void do_sleep(void) 2915 { 2916 struct timeval select_timeout; 2917 fd_set readfds; 2918 int retval; 2919 2920 FD_ZERO(&readfds); 2921 FD_SET(0, &readfds); 2922 2923 if (!isatty(fileno(stdin))) { 2924 nanosleep(&interval_ts, NULL); 2925 return; 2926 } 2927 2928 select_timeout = interval_tv; 2929 retval = select(1, &readfds, NULL, NULL, &select_timeout); 2930 2931 if (retval == 1) { 2932 switch (getc(stdin)) { 2933 case 'q': 2934 exit_requested = 1; 2935 break; 2936 } 2937 /* make sure this manually-invoked interval is at least 1ms long */ 2938 nanosleep(&one_msec, NULL); 2939 } 2940 } 2941 2942 2943 void turbostat_loop() 2944 { 2945 int retval; 2946 int restarted = 0; 2947 int done_iters = 0; 2948 2949 setup_signal_handler(); 2950 2951 restart: 2952 restarted++; 2953 2954 snapshot_proc_sysfs_files(); 2955 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 2956 first_counter_read = 0; 2957 if (retval < -1) { 2958 exit(retval); 2959 } else if (retval == -1) { 2960 if (restarted > 1) { 2961 exit(retval); 2962 } 2963 re_initialize(); 2964 goto restart; 2965 } 2966 restarted = 0; 2967 done_iters = 0; 2968 gettimeofday(&tv_even, (struct timezone *)NULL); 2969 2970 while (1) { 2971 if (for_all_proc_cpus(cpu_is_not_present)) { 2972 re_initialize(); 2973 goto restart; 2974 } 2975 do_sleep(); 2976 if (snapshot_proc_sysfs_files()) 2977 goto restart; 2978 retval = for_all_cpus(get_counters, ODD_COUNTERS); 2979 if (retval < -1) { 2980 exit(retval); 2981 } else if (retval == -1) { 2982 re_initialize(); 2983 goto restart; 2984 } 2985 gettimeofday(&tv_odd, (struct timezone *)NULL); 2986 timersub(&tv_odd, &tv_even, &tv_delta); 2987 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) { 2988 re_initialize(); 2989 goto restart; 2990 } 2991 compute_average(EVEN_COUNTERS); 2992 format_all_counters(EVEN_COUNTERS); 2993 flush_output_stdout(); 2994 if (exit_requested) 2995 break; 2996 if (num_iterations && ++done_iters >= num_iterations) 2997 break; 2998 do_sleep(); 2999 if (snapshot_proc_sysfs_files()) 3000 goto restart; 3001 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3002 if (retval < -1) { 3003 exit(retval); 3004 } else if (retval == -1) { 3005 re_initialize(); 3006 goto restart; 3007 } 3008 gettimeofday(&tv_even, (struct timezone *)NULL); 3009 timersub(&tv_even, &tv_odd, &tv_delta); 3010 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) { 3011 re_initialize(); 3012 goto restart; 3013 } 3014 compute_average(ODD_COUNTERS); 3015 format_all_counters(ODD_COUNTERS); 3016 flush_output_stdout(); 3017 if (exit_requested) 3018 break; 3019 if (num_iterations && ++done_iters >= num_iterations) 3020 break; 3021 } 3022 } 3023 3024 void check_dev_msr() 3025 { 3026 struct stat sb; 3027 char pathname[32]; 3028 3029 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3030 if (stat(pathname, &sb)) 3031 if (system("/sbin/modprobe msr > /dev/null 2>&1")) 3032 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); 3033 } 3034 3035 void check_permissions() 3036 { 3037 struct __user_cap_header_struct cap_header_data; 3038 cap_user_header_t cap_header = &cap_header_data; 3039 struct __user_cap_data_struct cap_data_data; 3040 cap_user_data_t cap_data = &cap_data_data; 3041 extern int capget(cap_user_header_t hdrp, cap_user_data_t datap); 3042 int do_exit = 0; 3043 char pathname[32]; 3044 3045 /* check for CAP_SYS_RAWIO */ 3046 cap_header->pid = getpid(); 3047 cap_header->version = _LINUX_CAPABILITY_VERSION; 3048 if (capget(cap_header, cap_data) < 0) 3049 err(-6, "capget(2) failed"); 3050 3051 if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) { 3052 do_exit++; 3053 warnx("capget(CAP_SYS_RAWIO) failed," 3054 " try \"# setcap cap_sys_rawio=ep %s\"", progname); 3055 } 3056 3057 /* test file permissions */ 3058 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3059 if (euidaccess(pathname, R_OK)) { 3060 do_exit++; 3061 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); 3062 } 3063 3064 /* if all else fails, thell them to be root */ 3065 if (do_exit) 3066 if (getuid() != 0) 3067 warnx("... or simply run as root"); 3068 3069 if (do_exit) 3070 exit(-6); 3071 } 3072 3073 /* 3074 * NHM adds support for additional MSRs: 3075 * 3076 * MSR_SMI_COUNT 0x00000034 3077 * 3078 * MSR_PLATFORM_INFO 0x000000ce 3079 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 3080 * 3081 * MSR_MISC_PWR_MGMT 0x000001aa 3082 * 3083 * MSR_PKG_C3_RESIDENCY 0x000003f8 3084 * MSR_PKG_C6_RESIDENCY 0x000003f9 3085 * MSR_CORE_C3_RESIDENCY 0x000003fc 3086 * MSR_CORE_C6_RESIDENCY 0x000003fd 3087 * 3088 * Side effect: 3089 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL 3090 * sets has_misc_feature_control 3091 */ 3092 int probe_nhm_msrs(unsigned int family, unsigned int model) 3093 { 3094 unsigned long long msr; 3095 unsigned int base_ratio; 3096 int *pkg_cstate_limits; 3097 3098 if (!genuine_intel) 3099 return 0; 3100 3101 if (family != 6) 3102 return 0; 3103 3104 bclk = discover_bclk(family, model); 3105 3106 switch (model) { 3107 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ 3108 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 3109 case 0x1F: /* Core i7 and i5 Processor - Nehalem */ 3110 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */ 3111 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */ 3112 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3113 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 3114 pkg_cstate_limits = nhm_pkg_cstate_limits; 3115 break; 3116 case INTEL_FAM6_SANDYBRIDGE: /* SNB */ 3117 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */ 3118 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3119 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3120 pkg_cstate_limits = snb_pkg_cstate_limits; 3121 has_misc_feature_control = 1; 3122 break; 3123 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3124 case INTEL_FAM6_HASWELL_X: /* HSX */ 3125 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3126 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3127 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3128 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3129 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3130 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 3131 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3132 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3133 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3134 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3135 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 3136 pkg_cstate_limits = hsw_pkg_cstate_limits; 3137 has_misc_feature_control = 1; 3138 break; 3139 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3140 pkg_cstate_limits = skx_pkg_cstate_limits; 3141 has_misc_feature_control = 1; 3142 break; 3143 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ 3144 no_MSR_MISC_PWR_MGMT = 1; 3145 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ 3146 pkg_cstate_limits = slv_pkg_cstate_limits; 3147 break; 3148 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */ 3149 pkg_cstate_limits = amt_pkg_cstate_limits; 3150 no_MSR_MISC_PWR_MGMT = 1; 3151 break; 3152 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */ 3153 case INTEL_FAM6_XEON_PHI_KNM: 3154 pkg_cstate_limits = phi_pkg_cstate_limits; 3155 break; 3156 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3157 case INTEL_FAM6_ATOM_GEMINI_LAKE: 3158 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 3159 pkg_cstate_limits = bxt_pkg_cstate_limits; 3160 break; 3161 default: 3162 return 0; 3163 } 3164 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 3165 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; 3166 3167 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 3168 base_ratio = (msr >> 8) & 0xFF; 3169 3170 base_hz = base_ratio * bclk * 1000000; 3171 has_base_hz = 1; 3172 return 1; 3173 } 3174 /* 3175 * SLV client has support for unique MSRs: 3176 * 3177 * MSR_CC6_DEMOTION_POLICY_CONFIG 3178 * MSR_MC6_DEMOTION_POLICY_CONFIG 3179 */ 3180 3181 int has_slv_msrs(unsigned int family, unsigned int model) 3182 { 3183 if (!genuine_intel) 3184 return 0; 3185 3186 switch (model) { 3187 case INTEL_FAM6_ATOM_SILVERMONT1: 3188 case INTEL_FAM6_ATOM_MERRIFIELD: 3189 case INTEL_FAM6_ATOM_MOOREFIELD: 3190 return 1; 3191 } 3192 return 0; 3193 } 3194 int is_dnv(unsigned int family, unsigned int model) 3195 { 3196 3197 if (!genuine_intel) 3198 return 0; 3199 3200 switch (model) { 3201 case INTEL_FAM6_ATOM_DENVERTON: 3202 return 1; 3203 } 3204 return 0; 3205 } 3206 int is_bdx(unsigned int family, unsigned int model) 3207 { 3208 3209 if (!genuine_intel) 3210 return 0; 3211 3212 switch (model) { 3213 case INTEL_FAM6_BROADWELL_X: 3214 case INTEL_FAM6_BROADWELL_XEON_D: 3215 return 1; 3216 } 3217 return 0; 3218 } 3219 int is_skx(unsigned int family, unsigned int model) 3220 { 3221 3222 if (!genuine_intel) 3223 return 0; 3224 3225 switch (model) { 3226 case INTEL_FAM6_SKYLAKE_X: 3227 return 1; 3228 } 3229 return 0; 3230 } 3231 3232 int has_turbo_ratio_limit(unsigned int family, unsigned int model) 3233 { 3234 if (has_slv_msrs(family, model)) 3235 return 0; 3236 3237 switch (model) { 3238 /* Nehalem compatible, but do not include turbo-ratio limit support */ 3239 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3240 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 3241 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */ 3242 case INTEL_FAM6_XEON_PHI_KNM: 3243 return 0; 3244 default: 3245 return 1; 3246 } 3247 } 3248 int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model) 3249 { 3250 if (has_slv_msrs(family, model)) 3251 return 1; 3252 3253 return 0; 3254 } 3255 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) 3256 { 3257 if (!genuine_intel) 3258 return 0; 3259 3260 if (family != 6) 3261 return 0; 3262 3263 switch (model) { 3264 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3265 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3266 return 1; 3267 default: 3268 return 0; 3269 } 3270 } 3271 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) 3272 { 3273 if (!genuine_intel) 3274 return 0; 3275 3276 if (family != 6) 3277 return 0; 3278 3279 switch (model) { 3280 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3281 return 1; 3282 default: 3283 return 0; 3284 } 3285 } 3286 3287 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) 3288 { 3289 if (!genuine_intel) 3290 return 0; 3291 3292 if (family != 6) 3293 return 0; 3294 3295 switch (model) { 3296 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 3297 case INTEL_FAM6_XEON_PHI_KNM: 3298 return 1; 3299 default: 3300 return 0; 3301 } 3302 } 3303 int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model) 3304 { 3305 if (!genuine_intel) 3306 return 0; 3307 3308 if (family != 6) 3309 return 0; 3310 3311 switch (model) { 3312 case INTEL_FAM6_ATOM_GOLDMONT: 3313 case INTEL_FAM6_SKYLAKE_X: 3314 return 1; 3315 default: 3316 return 0; 3317 } 3318 } 3319 int has_config_tdp(unsigned int family, unsigned int model) 3320 { 3321 if (!genuine_intel) 3322 return 0; 3323 3324 if (family != 6) 3325 return 0; 3326 3327 switch (model) { 3328 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3329 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3330 case INTEL_FAM6_HASWELL_X: /* HSX */ 3331 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3332 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3333 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3334 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3335 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3336 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 3337 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3338 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3339 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3340 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3341 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 3342 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3343 3344 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 3345 case INTEL_FAM6_XEON_PHI_KNM: 3346 return 1; 3347 default: 3348 return 0; 3349 } 3350 } 3351 3352 static void 3353 dump_cstate_pstate_config_info(unsigned int family, unsigned int model) 3354 { 3355 if (!do_nhm_platform_info) 3356 return; 3357 3358 dump_nhm_platform_info(); 3359 3360 if (has_hsw_turbo_ratio_limit(family, model)) 3361 dump_hsw_turbo_ratio_limits(); 3362 3363 if (has_ivt_turbo_ratio_limit(family, model)) 3364 dump_ivt_turbo_ratio_limits(); 3365 3366 if (has_turbo_ratio_limit(family, model)) 3367 dump_turbo_ratio_limits(family, model); 3368 3369 if (has_atom_turbo_ratio_limit(family, model)) 3370 dump_atom_turbo_ratio_limits(); 3371 3372 if (has_knl_turbo_ratio_limit(family, model)) 3373 dump_knl_turbo_ratio_limits(); 3374 3375 if (has_config_tdp(family, model)) 3376 dump_config_tdp(); 3377 3378 dump_nhm_cst_cfg(); 3379 } 3380 3381 static void 3382 dump_sysfs_cstate_config(void) 3383 { 3384 char path[64]; 3385 char name_buf[16]; 3386 char desc[64]; 3387 FILE *input; 3388 int state; 3389 char *sp; 3390 3391 if (!DO_BIC(BIC_sysfs)) 3392 return; 3393 3394 for (state = 0; state < 10; ++state) { 3395 3396 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 3397 base_cpu, state); 3398 input = fopen(path, "r"); 3399 if (input == NULL) 3400 continue; 3401 fgets(name_buf, sizeof(name_buf), input); 3402 3403 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 3404 sp = strchr(name_buf, '-'); 3405 if (!sp) 3406 sp = strchrnul(name_buf, '\n'); 3407 *sp = '\0'; 3408 3409 fclose(input); 3410 3411 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc", 3412 base_cpu, state); 3413 input = fopen(path, "r"); 3414 if (input == NULL) 3415 continue; 3416 fgets(desc, sizeof(desc), input); 3417 3418 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc); 3419 fclose(input); 3420 } 3421 } 3422 static void 3423 dump_sysfs_pstate_config(void) 3424 { 3425 char path[64]; 3426 char driver_buf[64]; 3427 char governor_buf[64]; 3428 FILE *input; 3429 int turbo; 3430 3431 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver", 3432 base_cpu); 3433 input = fopen(path, "r"); 3434 if (input == NULL) { 3435 fprintf(stderr, "NSFOD %s\n", path); 3436 return; 3437 } 3438 fgets(driver_buf, sizeof(driver_buf), input); 3439 fclose(input); 3440 3441 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor", 3442 base_cpu); 3443 input = fopen(path, "r"); 3444 if (input == NULL) { 3445 fprintf(stderr, "NSFOD %s\n", path); 3446 return; 3447 } 3448 fgets(governor_buf, sizeof(governor_buf), input); 3449 fclose(input); 3450 3451 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf); 3452 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf); 3453 3454 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost"); 3455 input = fopen(path, "r"); 3456 if (input != NULL) { 3457 fscanf(input, "%d", &turbo); 3458 fprintf(outf, "cpufreq boost: %d\n", turbo); 3459 fclose(input); 3460 } 3461 3462 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo"); 3463 input = fopen(path, "r"); 3464 if (input != NULL) { 3465 fscanf(input, "%d", &turbo); 3466 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo); 3467 fclose(input); 3468 } 3469 } 3470 3471 3472 /* 3473 * print_epb() 3474 * Decode the ENERGY_PERF_BIAS MSR 3475 */ 3476 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3477 { 3478 unsigned long long msr; 3479 char *epb_string; 3480 int cpu; 3481 3482 if (!has_epb) 3483 return 0; 3484 3485 cpu = t->cpu_id; 3486 3487 /* EPB is per-package */ 3488 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3489 return 0; 3490 3491 if (cpu_migrate(cpu)) { 3492 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3493 return -1; 3494 } 3495 3496 if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr)) 3497 return 0; 3498 3499 switch (msr & 0xF) { 3500 case ENERGY_PERF_BIAS_PERFORMANCE: 3501 epb_string = "performance"; 3502 break; 3503 case ENERGY_PERF_BIAS_NORMAL: 3504 epb_string = "balanced"; 3505 break; 3506 case ENERGY_PERF_BIAS_POWERSAVE: 3507 epb_string = "powersave"; 3508 break; 3509 default: 3510 epb_string = "custom"; 3511 break; 3512 } 3513 fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string); 3514 3515 return 0; 3516 } 3517 /* 3518 * print_hwp() 3519 * Decode the MSR_HWP_CAPABILITIES 3520 */ 3521 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3522 { 3523 unsigned long long msr; 3524 int cpu; 3525 3526 if (!has_hwp) 3527 return 0; 3528 3529 cpu = t->cpu_id; 3530 3531 /* MSR_HWP_CAPABILITIES is per-package */ 3532 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3533 return 0; 3534 3535 if (cpu_migrate(cpu)) { 3536 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3537 return -1; 3538 } 3539 3540 if (get_msr(cpu, MSR_PM_ENABLE, &msr)) 3541 return 0; 3542 3543 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", 3544 cpu, msr, (msr & (1 << 0)) ? "" : "No-"); 3545 3546 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ 3547 if ((msr & (1 << 0)) == 0) 3548 return 0; 3549 3550 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) 3551 return 0; 3552 3553 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " 3554 "(high %d guar %d eff %d low %d)\n", 3555 cpu, msr, 3556 (unsigned int)HWP_HIGHEST_PERF(msr), 3557 (unsigned int)HWP_GUARANTEED_PERF(msr), 3558 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), 3559 (unsigned int)HWP_LOWEST_PERF(msr)); 3560 3561 if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) 3562 return 0; 3563 3564 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " 3565 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n", 3566 cpu, msr, 3567 (unsigned int)(((msr) >> 0) & 0xff), 3568 (unsigned int)(((msr) >> 8) & 0xff), 3569 (unsigned int)(((msr) >> 16) & 0xff), 3570 (unsigned int)(((msr) >> 24) & 0xff), 3571 (unsigned int)(((msr) >> 32) & 0xff3), 3572 (unsigned int)(((msr) >> 42) & 0x1)); 3573 3574 if (has_hwp_pkg) { 3575 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) 3576 return 0; 3577 3578 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " 3579 "(min %d max %d des %d epp 0x%x window 0x%x)\n", 3580 cpu, msr, 3581 (unsigned int)(((msr) >> 0) & 0xff), 3582 (unsigned int)(((msr) >> 8) & 0xff), 3583 (unsigned int)(((msr) >> 16) & 0xff), 3584 (unsigned int)(((msr) >> 24) & 0xff), 3585 (unsigned int)(((msr) >> 32) & 0xff3)); 3586 } 3587 if (has_hwp_notify) { 3588 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) 3589 return 0; 3590 3591 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " 3592 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", 3593 cpu, msr, 3594 ((msr) & 0x1) ? "EN" : "Dis", 3595 ((msr) & 0x2) ? "EN" : "Dis"); 3596 } 3597 if (get_msr(cpu, MSR_HWP_STATUS, &msr)) 3598 return 0; 3599 3600 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " 3601 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", 3602 cpu, msr, 3603 ((msr) & 0x1) ? "" : "No-", 3604 ((msr) & 0x2) ? "" : "No-"); 3605 3606 return 0; 3607 } 3608 3609 /* 3610 * print_perf_limit() 3611 */ 3612 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3613 { 3614 unsigned long long msr; 3615 int cpu; 3616 3617 cpu = t->cpu_id; 3618 3619 /* per-package */ 3620 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3621 return 0; 3622 3623 if (cpu_migrate(cpu)) { 3624 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3625 return -1; 3626 } 3627 3628 if (do_core_perf_limit_reasons) { 3629 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); 3630 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 3631 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", 3632 (msr & 1 << 15) ? "bit15, " : "", 3633 (msr & 1 << 14) ? "bit14, " : "", 3634 (msr & 1 << 13) ? "Transitions, " : "", 3635 (msr & 1 << 12) ? "MultiCoreTurbo, " : "", 3636 (msr & 1 << 11) ? "PkgPwrL2, " : "", 3637 (msr & 1 << 10) ? "PkgPwrL1, " : "", 3638 (msr & 1 << 9) ? "CorePwr, " : "", 3639 (msr & 1 << 8) ? "Amps, " : "", 3640 (msr & 1 << 6) ? "VR-Therm, " : "", 3641 (msr & 1 << 5) ? "Auto-HWP, " : "", 3642 (msr & 1 << 4) ? "Graphics, " : "", 3643 (msr & 1 << 2) ? "bit2, " : "", 3644 (msr & 1 << 1) ? "ThermStatus, " : "", 3645 (msr & 1 << 0) ? "PROCHOT, " : ""); 3646 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 3647 (msr & 1 << 31) ? "bit31, " : "", 3648 (msr & 1 << 30) ? "bit30, " : "", 3649 (msr & 1 << 29) ? "Transitions, " : "", 3650 (msr & 1 << 28) ? "MultiCoreTurbo, " : "", 3651 (msr & 1 << 27) ? "PkgPwrL2, " : "", 3652 (msr & 1 << 26) ? "PkgPwrL1, " : "", 3653 (msr & 1 << 25) ? "CorePwr, " : "", 3654 (msr & 1 << 24) ? "Amps, " : "", 3655 (msr & 1 << 22) ? "VR-Therm, " : "", 3656 (msr & 1 << 21) ? "Auto-HWP, " : "", 3657 (msr & 1 << 20) ? "Graphics, " : "", 3658 (msr & 1 << 18) ? "bit18, " : "", 3659 (msr & 1 << 17) ? "ThermStatus, " : "", 3660 (msr & 1 << 16) ? "PROCHOT, " : ""); 3661 3662 } 3663 if (do_gfx_perf_limit_reasons) { 3664 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); 3665 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 3666 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", 3667 (msr & 1 << 0) ? "PROCHOT, " : "", 3668 (msr & 1 << 1) ? "ThermStatus, " : "", 3669 (msr & 1 << 4) ? "Graphics, " : "", 3670 (msr & 1 << 6) ? "VR-Therm, " : "", 3671 (msr & 1 << 8) ? "Amps, " : "", 3672 (msr & 1 << 9) ? "GFXPwr, " : "", 3673 (msr & 1 << 10) ? "PkgPwrL1, " : "", 3674 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 3675 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", 3676 (msr & 1 << 16) ? "PROCHOT, " : "", 3677 (msr & 1 << 17) ? "ThermStatus, " : "", 3678 (msr & 1 << 20) ? "Graphics, " : "", 3679 (msr & 1 << 22) ? "VR-Therm, " : "", 3680 (msr & 1 << 24) ? "Amps, " : "", 3681 (msr & 1 << 25) ? "GFXPwr, " : "", 3682 (msr & 1 << 26) ? "PkgPwrL1, " : "", 3683 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 3684 } 3685 if (do_ring_perf_limit_reasons) { 3686 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); 3687 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 3688 fprintf(outf, " (Active: %s%s%s%s%s%s)", 3689 (msr & 1 << 0) ? "PROCHOT, " : "", 3690 (msr & 1 << 1) ? "ThermStatus, " : "", 3691 (msr & 1 << 6) ? "VR-Therm, " : "", 3692 (msr & 1 << 8) ? "Amps, " : "", 3693 (msr & 1 << 10) ? "PkgPwrL1, " : "", 3694 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 3695 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", 3696 (msr & 1 << 16) ? "PROCHOT, " : "", 3697 (msr & 1 << 17) ? "ThermStatus, " : "", 3698 (msr & 1 << 22) ? "VR-Therm, " : "", 3699 (msr & 1 << 24) ? "Amps, " : "", 3700 (msr & 1 << 26) ? "PkgPwrL1, " : "", 3701 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 3702 } 3703 return 0; 3704 } 3705 3706 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ 3707 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ 3708 3709 double get_tdp(unsigned int model) 3710 { 3711 unsigned long long msr; 3712 3713 if (do_rapl & RAPL_PKG_POWER_INFO) 3714 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) 3715 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; 3716 3717 switch (model) { 3718 case INTEL_FAM6_ATOM_SILVERMONT1: 3719 case INTEL_FAM6_ATOM_SILVERMONT2: 3720 return 30.0; 3721 default: 3722 return 135.0; 3723 } 3724 } 3725 3726 /* 3727 * rapl_dram_energy_units_probe() 3728 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR. 3729 */ 3730 static double 3731 rapl_dram_energy_units_probe(int model, double rapl_energy_units) 3732 { 3733 /* only called for genuine_intel, family 6 */ 3734 3735 switch (model) { 3736 case INTEL_FAM6_HASWELL_X: /* HSX */ 3737 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3738 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 3739 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 3740 case INTEL_FAM6_XEON_PHI_KNM: 3741 return (rapl_dram_energy_units = 15.3 / 1000000); 3742 default: 3743 return (rapl_energy_units); 3744 } 3745 } 3746 3747 3748 /* 3749 * rapl_probe() 3750 * 3751 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units 3752 */ 3753 void rapl_probe(unsigned int family, unsigned int model) 3754 { 3755 unsigned long long msr; 3756 unsigned int time_unit; 3757 double tdp; 3758 3759 if (!genuine_intel) 3760 return; 3761 3762 if (family != 6) 3763 return; 3764 3765 switch (model) { 3766 case INTEL_FAM6_SANDYBRIDGE: 3767 case INTEL_FAM6_IVYBRIDGE: 3768 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3769 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3770 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3771 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3772 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3773 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; 3774 if (rapl_joules) { 3775 BIC_PRESENT(BIC_Pkg_J); 3776 BIC_PRESENT(BIC_Cor_J); 3777 BIC_PRESENT(BIC_GFX_J); 3778 } else { 3779 BIC_PRESENT(BIC_PkgWatt); 3780 BIC_PRESENT(BIC_CorWatt); 3781 BIC_PRESENT(BIC_GFXWatt); 3782 } 3783 break; 3784 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3785 case INTEL_FAM6_ATOM_GEMINI_LAKE: 3786 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; 3787 if (rapl_joules) 3788 BIC_PRESENT(BIC_Pkg_J); 3789 else 3790 BIC_PRESENT(BIC_PkgWatt); 3791 break; 3792 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3793 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3794 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3795 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3796 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 3797 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_GFX | RAPL_PKG_POWER_INFO; 3798 BIC_PRESENT(BIC_PKG__); 3799 BIC_PRESENT(BIC_RAM__); 3800 if (rapl_joules) { 3801 BIC_PRESENT(BIC_Pkg_J); 3802 BIC_PRESENT(BIC_Cor_J); 3803 BIC_PRESENT(BIC_RAM_J); 3804 BIC_PRESENT(BIC_GFX_J); 3805 } else { 3806 BIC_PRESENT(BIC_PkgWatt); 3807 BIC_PRESENT(BIC_CorWatt); 3808 BIC_PRESENT(BIC_RAMWatt); 3809 BIC_PRESENT(BIC_GFXWatt); 3810 } 3811 break; 3812 case INTEL_FAM6_HASWELL_X: /* HSX */ 3813 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3814 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 3815 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3816 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 3817 case INTEL_FAM6_XEON_PHI_KNM: 3818 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 3819 BIC_PRESENT(BIC_PKG__); 3820 BIC_PRESENT(BIC_RAM__); 3821 if (rapl_joules) { 3822 BIC_PRESENT(BIC_Pkg_J); 3823 BIC_PRESENT(BIC_RAM_J); 3824 } else { 3825 BIC_PRESENT(BIC_PkgWatt); 3826 BIC_PRESENT(BIC_RAMWatt); 3827 } 3828 break; 3829 case INTEL_FAM6_SANDYBRIDGE_X: 3830 case INTEL_FAM6_IVYBRIDGE_X: 3831 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; 3832 BIC_PRESENT(BIC_PKG__); 3833 BIC_PRESENT(BIC_RAM__); 3834 if (rapl_joules) { 3835 BIC_PRESENT(BIC_Pkg_J); 3836 BIC_PRESENT(BIC_Cor_J); 3837 BIC_PRESENT(BIC_RAM_J); 3838 } else { 3839 BIC_PRESENT(BIC_PkgWatt); 3840 BIC_PRESENT(BIC_CorWatt); 3841 BIC_PRESENT(BIC_RAMWatt); 3842 } 3843 break; 3844 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ 3845 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ 3846 do_rapl = RAPL_PKG | RAPL_CORES; 3847 if (rapl_joules) { 3848 BIC_PRESENT(BIC_Pkg_J); 3849 BIC_PRESENT(BIC_Cor_J); 3850 } else { 3851 BIC_PRESENT(BIC_PkgWatt); 3852 BIC_PRESENT(BIC_CorWatt); 3853 } 3854 break; 3855 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 3856 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS; 3857 BIC_PRESENT(BIC_PKG__); 3858 BIC_PRESENT(BIC_RAM__); 3859 if (rapl_joules) { 3860 BIC_PRESENT(BIC_Pkg_J); 3861 BIC_PRESENT(BIC_Cor_J); 3862 BIC_PRESENT(BIC_RAM_J); 3863 } else { 3864 BIC_PRESENT(BIC_PkgWatt); 3865 BIC_PRESENT(BIC_CorWatt); 3866 BIC_PRESENT(BIC_RAMWatt); 3867 } 3868 break; 3869 default: 3870 return; 3871 } 3872 3873 /* units on package 0, verify later other packages match */ 3874 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) 3875 return; 3876 3877 rapl_power_units = 1.0 / (1 << (msr & 0xF)); 3878 if (model == INTEL_FAM6_ATOM_SILVERMONT1) 3879 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; 3880 else 3881 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 3882 3883 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units); 3884 3885 time_unit = msr >> 16 & 0xF; 3886 if (time_unit == 0) 3887 time_unit = 0xA; 3888 3889 rapl_time_units = 1.0 / (1 << (time_unit)); 3890 3891 tdp = get_tdp(model); 3892 3893 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 3894 if (!quiet) 3895 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 3896 3897 return; 3898 } 3899 3900 void perf_limit_reasons_probe(unsigned int family, unsigned int model) 3901 { 3902 if (!genuine_intel) 3903 return; 3904 3905 if (family != 6) 3906 return; 3907 3908 switch (model) { 3909 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3910 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3911 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3912 do_gfx_perf_limit_reasons = 1; 3913 case INTEL_FAM6_HASWELL_X: /* HSX */ 3914 do_core_perf_limit_reasons = 1; 3915 do_ring_perf_limit_reasons = 1; 3916 default: 3917 return; 3918 } 3919 } 3920 3921 void automatic_cstate_conversion_probe(unsigned int family, unsigned int model) 3922 { 3923 if (is_skx(family, model) || is_bdx(family, model)) 3924 has_automatic_cstate_conversion = 1; 3925 } 3926 3927 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3928 { 3929 unsigned long long msr; 3930 unsigned int dts, dts2; 3931 int cpu; 3932 3933 if (!(do_dts || do_ptm)) 3934 return 0; 3935 3936 cpu = t->cpu_id; 3937 3938 /* DTS is per-core, no need to print for each thread */ 3939 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 3940 return 0; 3941 3942 if (cpu_migrate(cpu)) { 3943 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3944 return -1; 3945 } 3946 3947 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { 3948 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 3949 return 0; 3950 3951 dts = (msr >> 16) & 0x7F; 3952 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", 3953 cpu, msr, tcc_activation_temp - dts); 3954 3955 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) 3956 return 0; 3957 3958 dts = (msr >> 16) & 0x7F; 3959 dts2 = (msr >> 8) & 0x7F; 3960 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 3961 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 3962 } 3963 3964 3965 if (do_dts && debug) { 3966 unsigned int resolution; 3967 3968 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 3969 return 0; 3970 3971 dts = (msr >> 16) & 0x7F; 3972 resolution = (msr >> 27) & 0xF; 3973 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", 3974 cpu, msr, tcc_activation_temp - dts, resolution); 3975 3976 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) 3977 return 0; 3978 3979 dts = (msr >> 16) & 0x7F; 3980 dts2 = (msr >> 8) & 0x7F; 3981 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 3982 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 3983 } 3984 3985 return 0; 3986 } 3987 3988 void print_power_limit_msr(int cpu, unsigned long long msr, char *label) 3989 { 3990 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n", 3991 cpu, label, 3992 ((msr >> 15) & 1) ? "EN" : "DIS", 3993 ((msr >> 0) & 0x7FFF) * rapl_power_units, 3994 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, 3995 (((msr >> 16) & 1) ? "EN" : "DIS")); 3996 3997 return; 3998 } 3999 4000 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4001 { 4002 unsigned long long msr; 4003 int cpu; 4004 4005 if (!do_rapl) 4006 return 0; 4007 4008 /* RAPL counters are per package, so print only for 1st thread/package */ 4009 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4010 return 0; 4011 4012 cpu = t->cpu_id; 4013 if (cpu_migrate(cpu)) { 4014 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 4015 return -1; 4016 } 4017 4018 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) 4019 return -1; 4020 4021 fprintf(outf, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr, 4022 rapl_power_units, rapl_energy_units, rapl_time_units); 4023 4024 if (do_rapl & RAPL_PKG_POWER_INFO) { 4025 4026 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) 4027 return -5; 4028 4029 4030 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4031 cpu, msr, 4032 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4033 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4034 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4035 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4036 4037 } 4038 if (do_rapl & RAPL_PKG) { 4039 4040 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) 4041 return -9; 4042 4043 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", 4044 cpu, msr, (msr >> 63) & 1 ? "" : "UN"); 4045 4046 print_power_limit_msr(cpu, msr, "PKG Limit #1"); 4047 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n", 4048 cpu, 4049 ((msr >> 47) & 1) ? "EN" : "DIS", 4050 ((msr >> 32) & 0x7FFF) * rapl_power_units, 4051 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, 4052 ((msr >> 48) & 1) ? "EN" : "DIS"); 4053 } 4054 4055 if (do_rapl & RAPL_DRAM_POWER_INFO) { 4056 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) 4057 return -6; 4058 4059 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4060 cpu, msr, 4061 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4062 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4063 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4064 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4065 } 4066 if (do_rapl & RAPL_DRAM) { 4067 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) 4068 return -9; 4069 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", 4070 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4071 4072 print_power_limit_msr(cpu, msr, "DRAM Limit"); 4073 } 4074 if (do_rapl & RAPL_CORE_POLICY) { 4075 if (get_msr(cpu, MSR_PP0_POLICY, &msr)) 4076 return -7; 4077 4078 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); 4079 } 4080 if (do_rapl & RAPL_CORES_POWER_LIMIT) { 4081 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) 4082 return -9; 4083 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", 4084 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4085 print_power_limit_msr(cpu, msr, "Cores Limit"); 4086 } 4087 if (do_rapl & RAPL_GFX) { 4088 if (get_msr(cpu, MSR_PP1_POLICY, &msr)) 4089 return -8; 4090 4091 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); 4092 4093 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) 4094 return -9; 4095 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", 4096 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4097 print_power_limit_msr(cpu, msr, "GFX Limit"); 4098 } 4099 return 0; 4100 } 4101 4102 /* 4103 * SNB adds support for additional MSRs: 4104 * 4105 * MSR_PKG_C7_RESIDENCY 0x000003fa 4106 * MSR_CORE_C7_RESIDENCY 0x000003fe 4107 * MSR_PKG_C2_RESIDENCY 0x0000060d 4108 */ 4109 4110 int has_snb_msrs(unsigned int family, unsigned int model) 4111 { 4112 if (!genuine_intel) 4113 return 0; 4114 4115 switch (model) { 4116 case INTEL_FAM6_SANDYBRIDGE: 4117 case INTEL_FAM6_SANDYBRIDGE_X: 4118 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 4119 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 4120 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 4121 case INTEL_FAM6_HASWELL_X: /* HSW */ 4122 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 4123 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 4124 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 4125 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 4126 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4127 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 4128 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4129 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 4130 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 4131 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 4132 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 4133 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4134 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4135 case INTEL_FAM6_ATOM_GEMINI_LAKE: 4136 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 4137 return 1; 4138 } 4139 return 0; 4140 } 4141 4142 /* 4143 * HSW adds support for additional MSRs: 4144 * 4145 * MSR_PKG_C8_RESIDENCY 0x00000630 4146 * MSR_PKG_C9_RESIDENCY 0x00000631 4147 * MSR_PKG_C10_RESIDENCY 0x00000632 4148 * 4149 * MSR_PKGC8_IRTL 0x00000633 4150 * MSR_PKGC9_IRTL 0x00000634 4151 * MSR_PKGC10_IRTL 0x00000635 4152 * 4153 */ 4154 int has_hsw_msrs(unsigned int family, unsigned int model) 4155 { 4156 if (!genuine_intel) 4157 return 0; 4158 4159 switch (model) { 4160 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 4161 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 4162 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4163 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 4164 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 4165 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 4166 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 4167 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4168 case INTEL_FAM6_ATOM_GEMINI_LAKE: 4169 return 1; 4170 } 4171 return 0; 4172 } 4173 4174 /* 4175 * SKL adds support for additional MSRS: 4176 * 4177 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 4178 * MSR_PKG_ANY_CORE_C0_RES 0x00000659 4179 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 4180 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 4181 */ 4182 int has_skl_msrs(unsigned int family, unsigned int model) 4183 { 4184 if (!genuine_intel) 4185 return 0; 4186 4187 switch (model) { 4188 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4189 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 4190 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 4191 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 4192 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 4193 return 1; 4194 } 4195 return 0; 4196 } 4197 4198 int is_slm(unsigned int family, unsigned int model) 4199 { 4200 if (!genuine_intel) 4201 return 0; 4202 switch (model) { 4203 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ 4204 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ 4205 return 1; 4206 } 4207 return 0; 4208 } 4209 4210 int is_knl(unsigned int family, unsigned int model) 4211 { 4212 if (!genuine_intel) 4213 return 0; 4214 switch (model) { 4215 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4216 case INTEL_FAM6_XEON_PHI_KNM: 4217 return 1; 4218 } 4219 return 0; 4220 } 4221 4222 int is_cnl(unsigned int family, unsigned int model) 4223 { 4224 if (!genuine_intel) 4225 return 0; 4226 4227 switch (model) { 4228 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 4229 return 1; 4230 } 4231 4232 return 0; 4233 } 4234 4235 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model) 4236 { 4237 if (is_knl(family, model)) 4238 return 1024; 4239 return 1; 4240 } 4241 4242 #define SLM_BCLK_FREQS 5 4243 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0}; 4244 4245 double slm_bclk(void) 4246 { 4247 unsigned long long msr = 3; 4248 unsigned int i; 4249 double freq; 4250 4251 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) 4252 fprintf(outf, "SLM BCLK: unknown\n"); 4253 4254 i = msr & 0xf; 4255 if (i >= SLM_BCLK_FREQS) { 4256 fprintf(outf, "SLM BCLK[%d] invalid\n", i); 4257 i = 3; 4258 } 4259 freq = slm_freq_table[i]; 4260 4261 if (!quiet) 4262 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); 4263 4264 return freq; 4265 } 4266 4267 double discover_bclk(unsigned int family, unsigned int model) 4268 { 4269 if (has_snb_msrs(family, model) || is_knl(family, model)) 4270 return 100.00; 4271 else if (is_slm(family, model)) 4272 return slm_bclk(); 4273 else 4274 return 133.33; 4275 } 4276 4277 /* 4278 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where 4279 * the Thermal Control Circuit (TCC) activates. 4280 * This is usually equal to tjMax. 4281 * 4282 * Older processors do not have this MSR, so there we guess, 4283 * but also allow cmdline over-ride with -T. 4284 * 4285 * Several MSR temperature values are in units of degrees-C 4286 * below this value, including the Digital Thermal Sensor (DTS), 4287 * Package Thermal Management Sensor (PTM), and thermal event thresholds. 4288 */ 4289 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4290 { 4291 unsigned long long msr; 4292 unsigned int target_c_local; 4293 int cpu; 4294 4295 /* tcc_activation_temp is used only for dts or ptm */ 4296 if (!(do_dts || do_ptm)) 4297 return 0; 4298 4299 /* this is a per-package concept */ 4300 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4301 return 0; 4302 4303 cpu = t->cpu_id; 4304 if (cpu_migrate(cpu)) { 4305 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 4306 return -1; 4307 } 4308 4309 if (tcc_activation_temp_override != 0) { 4310 tcc_activation_temp = tcc_activation_temp_override; 4311 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", 4312 cpu, tcc_activation_temp); 4313 return 0; 4314 } 4315 4316 /* Temperature Target MSR is Nehalem and newer only */ 4317 if (!do_nhm_platform_info) 4318 goto guess; 4319 4320 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) 4321 goto guess; 4322 4323 target_c_local = (msr >> 16) & 0xFF; 4324 4325 if (!quiet) 4326 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", 4327 cpu, msr, target_c_local); 4328 4329 if (!target_c_local) 4330 goto guess; 4331 4332 tcc_activation_temp = target_c_local; 4333 4334 return 0; 4335 4336 guess: 4337 tcc_activation_temp = TJMAX_DEFAULT; 4338 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", 4339 cpu, tcc_activation_temp); 4340 4341 return 0; 4342 } 4343 4344 void decode_feature_control_msr(void) 4345 { 4346 unsigned long long msr; 4347 4348 if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr)) 4349 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", 4350 base_cpu, msr, 4351 msr & FEATURE_CONTROL_LOCKED ? "" : "UN-", 4352 msr & (1 << 18) ? "SGX" : ""); 4353 } 4354 4355 void decode_misc_enable_msr(void) 4356 { 4357 unsigned long long msr; 4358 4359 if (!genuine_intel) 4360 return; 4361 4362 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) 4363 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n", 4364 base_cpu, msr, 4365 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-", 4366 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-", 4367 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-", 4368 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "", 4369 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : ""); 4370 } 4371 4372 void decode_misc_feature_control(void) 4373 { 4374 unsigned long long msr; 4375 4376 if (!has_misc_feature_control) 4377 return; 4378 4379 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr)) 4380 fprintf(outf, "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n", 4381 base_cpu, msr, 4382 msr & (0 << 0) ? "No-" : "", 4383 msr & (1 << 0) ? "No-" : "", 4384 msr & (2 << 0) ? "No-" : "", 4385 msr & (3 << 0) ? "No-" : ""); 4386 } 4387 /* 4388 * Decode MSR_MISC_PWR_MGMT 4389 * 4390 * Decode the bits according to the Nehalem documentation 4391 * bit[0] seems to continue to have same meaning going forward 4392 * bit[1] less so... 4393 */ 4394 void decode_misc_pwr_mgmt_msr(void) 4395 { 4396 unsigned long long msr; 4397 4398 if (!do_nhm_platform_info) 4399 return; 4400 4401 if (no_MSR_MISC_PWR_MGMT) 4402 return; 4403 4404 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) 4405 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n", 4406 base_cpu, msr, 4407 msr & (1 << 0) ? "DIS" : "EN", 4408 msr & (1 << 1) ? "EN" : "DIS", 4409 msr & (1 << 8) ? "EN" : "DIS"); 4410 } 4411 /* 4412 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG 4413 * 4414 * This MSRs are present on Silvermont processors, 4415 * Intel Atom processor E3000 series (Baytrail), and friends. 4416 */ 4417 void decode_c6_demotion_policy_msr(void) 4418 { 4419 unsigned long long msr; 4420 4421 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr)) 4422 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n", 4423 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 4424 4425 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr)) 4426 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n", 4427 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 4428 } 4429 4430 void process_cpuid() 4431 { 4432 unsigned int eax, ebx, ecx, edx, max_level, max_extended_level; 4433 unsigned int fms, family, model, stepping; 4434 unsigned int has_turbo; 4435 4436 eax = ebx = ecx = edx = 0; 4437 4438 __cpuid(0, max_level, ebx, ecx, edx); 4439 4440 if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e) 4441 genuine_intel = 1; 4442 4443 if (!quiet) 4444 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ", 4445 (char *)&ebx, (char *)&edx, (char *)&ecx); 4446 4447 __cpuid(1, fms, ebx, ecx, edx); 4448 family = (fms >> 8) & 0xf; 4449 model = (fms >> 4) & 0xf; 4450 stepping = fms & 0xf; 4451 if (family == 6 || family == 0xf) 4452 model += ((fms >> 16) & 0xf) << 4; 4453 4454 if (!quiet) { 4455 fprintf(outf, "%d CPUID levels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n", 4456 max_level, family, model, stepping, family, model, stepping); 4457 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n", 4458 ecx & (1 << 0) ? "SSE3" : "-", 4459 ecx & (1 << 3) ? "MONITOR" : "-", 4460 ecx & (1 << 6) ? "SMX" : "-", 4461 ecx & (1 << 7) ? "EIST" : "-", 4462 ecx & (1 << 8) ? "TM2" : "-", 4463 edx & (1 << 4) ? "TSC" : "-", 4464 edx & (1 << 5) ? "MSR" : "-", 4465 edx & (1 << 22) ? "ACPI-TM" : "-", 4466 edx & (1 << 28) ? "HT" : "-", 4467 edx & (1 << 29) ? "TM" : "-"); 4468 } 4469 4470 if (!(edx & (1 << 5))) 4471 errx(1, "CPUID: no MSR"); 4472 4473 /* 4474 * check max extended function levels of CPUID. 4475 * This is needed to check for invariant TSC. 4476 * This check is valid for both Intel and AMD. 4477 */ 4478 ebx = ecx = edx = 0; 4479 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); 4480 4481 if (max_extended_level >= 0x80000007) { 4482 4483 /* 4484 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 4485 * this check is valid for both Intel and AMD 4486 */ 4487 __cpuid(0x80000007, eax, ebx, ecx, edx); 4488 has_invariant_tsc = edx & (1 << 8); 4489 } 4490 4491 /* 4492 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 4493 * this check is valid for both Intel and AMD 4494 */ 4495 4496 __cpuid(0x6, eax, ebx, ecx, edx); 4497 has_aperf = ecx & (1 << 0); 4498 if (has_aperf) { 4499 BIC_PRESENT(BIC_Avg_MHz); 4500 BIC_PRESENT(BIC_Busy); 4501 BIC_PRESENT(BIC_Bzy_MHz); 4502 } 4503 do_dts = eax & (1 << 0); 4504 if (do_dts) 4505 BIC_PRESENT(BIC_CoreTmp); 4506 has_turbo = eax & (1 << 1); 4507 do_ptm = eax & (1 << 6); 4508 if (do_ptm) 4509 BIC_PRESENT(BIC_PkgTmp); 4510 has_hwp = eax & (1 << 7); 4511 has_hwp_notify = eax & (1 << 8); 4512 has_hwp_activity_window = eax & (1 << 9); 4513 has_hwp_epp = eax & (1 << 10); 4514 has_hwp_pkg = eax & (1 << 11); 4515 has_epb = ecx & (1 << 3); 4516 4517 if (!quiet) 4518 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, " 4519 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", 4520 has_aperf ? "" : "No-", 4521 has_turbo ? "" : "No-", 4522 do_dts ? "" : "No-", 4523 do_ptm ? "" : "No-", 4524 has_hwp ? "" : "No-", 4525 has_hwp_notify ? "" : "No-", 4526 has_hwp_activity_window ? "" : "No-", 4527 has_hwp_epp ? "" : "No-", 4528 has_hwp_pkg ? "" : "No-", 4529 has_epb ? "" : "No-"); 4530 4531 if (!quiet) 4532 decode_misc_enable_msr(); 4533 4534 4535 if (max_level >= 0x7 && !quiet) { 4536 int has_sgx; 4537 4538 ecx = 0; 4539 4540 __cpuid_count(0x7, 0, eax, ebx, ecx, edx); 4541 4542 has_sgx = ebx & (1 << 2); 4543 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-"); 4544 4545 if (has_sgx) 4546 decode_feature_control_msr(); 4547 } 4548 4549 if (max_level >= 0x15) { 4550 unsigned int eax_crystal; 4551 unsigned int ebx_tsc; 4552 4553 /* 4554 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz 4555 */ 4556 eax_crystal = ebx_tsc = crystal_hz = edx = 0; 4557 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); 4558 4559 if (ebx_tsc != 0) { 4560 4561 if (!quiet && (ebx != 0)) 4562 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", 4563 eax_crystal, ebx_tsc, crystal_hz); 4564 4565 if (crystal_hz == 0) 4566 switch(model) { 4567 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4568 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 4569 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 4570 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 4571 crystal_hz = 24000000; /* 24.0 MHz */ 4572 break; 4573 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 4574 crystal_hz = 25000000; /* 25.0 MHz */ 4575 break; 4576 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4577 case INTEL_FAM6_ATOM_GEMINI_LAKE: 4578 crystal_hz = 19200000; /* 19.2 MHz */ 4579 break; 4580 default: 4581 crystal_hz = 0; 4582 } 4583 4584 if (crystal_hz) { 4585 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal; 4586 if (!quiet) 4587 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", 4588 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); 4589 } 4590 } 4591 } 4592 if (max_level >= 0x16) { 4593 unsigned int base_mhz, max_mhz, bus_mhz, edx; 4594 4595 /* 4596 * CPUID 16H Base MHz, Max MHz, Bus MHz 4597 */ 4598 base_mhz = max_mhz = bus_mhz = edx = 0; 4599 4600 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); 4601 if (!quiet) 4602 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", 4603 base_mhz, max_mhz, bus_mhz); 4604 } 4605 4606 if (has_aperf) 4607 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model); 4608 4609 BIC_PRESENT(BIC_IRQ); 4610 BIC_PRESENT(BIC_TSC_MHz); 4611 4612 if (probe_nhm_msrs(family, model)) { 4613 do_nhm_platform_info = 1; 4614 BIC_PRESENT(BIC_CPU_c1); 4615 BIC_PRESENT(BIC_CPU_c3); 4616 BIC_PRESENT(BIC_CPU_c6); 4617 BIC_PRESENT(BIC_SMI); 4618 } 4619 do_snb_cstates = has_snb_msrs(family, model); 4620 4621 if (do_snb_cstates) 4622 BIC_PRESENT(BIC_CPU_c7); 4623 4624 do_irtl_snb = has_snb_msrs(family, model); 4625 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2)) 4626 BIC_PRESENT(BIC_Pkgpc2); 4627 if (pkg_cstate_limit >= PCL__3) 4628 BIC_PRESENT(BIC_Pkgpc3); 4629 if (pkg_cstate_limit >= PCL__6) 4630 BIC_PRESENT(BIC_Pkgpc6); 4631 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7)) 4632 BIC_PRESENT(BIC_Pkgpc7); 4633 if (has_slv_msrs(family, model)) { 4634 BIC_NOT_PRESENT(BIC_Pkgpc2); 4635 BIC_NOT_PRESENT(BIC_Pkgpc3); 4636 BIC_PRESENT(BIC_Pkgpc6); 4637 BIC_NOT_PRESENT(BIC_Pkgpc7); 4638 BIC_PRESENT(BIC_Mod_c6); 4639 use_c1_residency_msr = 1; 4640 } 4641 if (is_dnv(family, model)) { 4642 BIC_PRESENT(BIC_CPU_c1); 4643 BIC_NOT_PRESENT(BIC_CPU_c3); 4644 BIC_NOT_PRESENT(BIC_Pkgpc3); 4645 BIC_NOT_PRESENT(BIC_CPU_c7); 4646 BIC_NOT_PRESENT(BIC_Pkgpc7); 4647 use_c1_residency_msr = 1; 4648 } 4649 if (is_skx(family, model)) { 4650 BIC_NOT_PRESENT(BIC_CPU_c3); 4651 BIC_NOT_PRESENT(BIC_Pkgpc3); 4652 BIC_NOT_PRESENT(BIC_CPU_c7); 4653 BIC_NOT_PRESENT(BIC_Pkgpc7); 4654 } 4655 if (is_bdx(family, model)) { 4656 BIC_NOT_PRESENT(BIC_CPU_c7); 4657 BIC_NOT_PRESENT(BIC_Pkgpc7); 4658 } 4659 if (has_hsw_msrs(family, model)) { 4660 BIC_PRESENT(BIC_Pkgpc8); 4661 BIC_PRESENT(BIC_Pkgpc9); 4662 BIC_PRESENT(BIC_Pkgpc10); 4663 } 4664 do_irtl_hsw = has_hsw_msrs(family, model); 4665 if (has_skl_msrs(family, model)) { 4666 BIC_PRESENT(BIC_Totl_c0); 4667 BIC_PRESENT(BIC_Any_c0); 4668 BIC_PRESENT(BIC_GFX_c0); 4669 BIC_PRESENT(BIC_CPUGFX); 4670 } 4671 do_slm_cstates = is_slm(family, model); 4672 do_knl_cstates = is_knl(family, model); 4673 do_cnl_cstates = is_cnl(family, model); 4674 4675 if (!quiet) 4676 decode_misc_pwr_mgmt_msr(); 4677 4678 if (!quiet && has_slv_msrs(family, model)) 4679 decode_c6_demotion_policy_msr(); 4680 4681 rapl_probe(family, model); 4682 perf_limit_reasons_probe(family, model); 4683 automatic_cstate_conversion_probe(family, model); 4684 4685 if (!quiet) 4686 dump_cstate_pstate_config_info(family, model); 4687 4688 if (!quiet) 4689 dump_sysfs_cstate_config(); 4690 if (!quiet) 4691 dump_sysfs_pstate_config(); 4692 4693 if (has_skl_msrs(family, model)) 4694 calculate_tsc_tweak(); 4695 4696 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK)) 4697 BIC_PRESENT(BIC_GFX_rc6); 4698 4699 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK)) 4700 BIC_PRESENT(BIC_GFXMHz); 4701 4702 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK)) 4703 BIC_PRESENT(BIC_CPU_LPI); 4704 else 4705 BIC_NOT_PRESENT(BIC_CPU_LPI); 4706 4707 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us", R_OK)) 4708 BIC_PRESENT(BIC_SYS_LPI); 4709 else 4710 BIC_NOT_PRESENT(BIC_SYS_LPI); 4711 4712 if (!quiet) 4713 decode_misc_feature_control(); 4714 4715 return; 4716 } 4717 4718 /* 4719 * in /dev/cpu/ return success for names that are numbers 4720 * ie. filter out ".", "..", "microcode". 4721 */ 4722 int dir_filter(const struct dirent *dirp) 4723 { 4724 if (isdigit(dirp->d_name[0])) 4725 return 1; 4726 else 4727 return 0; 4728 } 4729 4730 int open_dev_cpu_msr(int dummy1) 4731 { 4732 return 0; 4733 } 4734 4735 void topology_probe() 4736 { 4737 int i; 4738 int max_core_id = 0; 4739 int max_package_id = 0; 4740 int max_siblings = 0; 4741 4742 /* Initialize num_cpus, max_cpu_num */ 4743 set_max_cpu_num(); 4744 topo.num_cpus = 0; 4745 for_all_proc_cpus(count_cpus); 4746 if (!summary_only && topo.num_cpus > 1) 4747 BIC_PRESENT(BIC_CPU); 4748 4749 if (debug > 1) 4750 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); 4751 4752 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); 4753 if (cpus == NULL) 4754 err(1, "calloc cpus"); 4755 4756 /* 4757 * Allocate and initialize cpu_present_set 4758 */ 4759 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); 4760 if (cpu_present_set == NULL) 4761 err(3, "CPU_ALLOC"); 4762 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 4763 CPU_ZERO_S(cpu_present_setsize, cpu_present_set); 4764 for_all_proc_cpus(mark_cpu_present); 4765 4766 /* 4767 * Validate that all cpus in cpu_subset are also in cpu_present_set 4768 */ 4769 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) { 4770 if (CPU_ISSET_S(i, cpu_subset_size, cpu_subset)) 4771 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set)) 4772 err(1, "cpu%d not present", i); 4773 } 4774 4775 /* 4776 * Allocate and initialize cpu_affinity_set 4777 */ 4778 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); 4779 if (cpu_affinity_set == NULL) 4780 err(3, "CPU_ALLOC"); 4781 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 4782 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 4783 4784 for_all_proc_cpus(init_thread_id); 4785 4786 /* 4787 * For online cpus 4788 * find max_core_id, max_package_id 4789 */ 4790 for (i = 0; i <= topo.max_cpu_num; ++i) { 4791 int siblings; 4792 4793 if (cpu_is_not_present(i)) { 4794 if (debug > 1) 4795 fprintf(outf, "cpu%d NOT PRESENT\n", i); 4796 continue; 4797 } 4798 4799 cpus[i].logical_cpu_id = i; 4800 4801 /* get package information */ 4802 cpus[i].physical_package_id = get_physical_package_id(i); 4803 if (cpus[i].physical_package_id > max_package_id) 4804 max_package_id = cpus[i].physical_package_id; 4805 4806 /* get numa node information */ 4807 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]); 4808 if (cpus[i].physical_node_id > topo.max_node_num) 4809 topo.max_node_num = cpus[i].physical_node_id; 4810 4811 /* get core information */ 4812 cpus[i].physical_core_id = get_core_id(i); 4813 if (cpus[i].physical_core_id > max_core_id) 4814 max_core_id = cpus[i].physical_core_id; 4815 4816 /* get thread information */ 4817 siblings = get_thread_siblings(&cpus[i]); 4818 if (siblings > max_siblings) 4819 max_siblings = siblings; 4820 if (cpus[i].thread_id != -1) 4821 topo.num_cores++; 4822 4823 if (debug > 1) 4824 fprintf(outf, 4825 "cpu %d pkg %d node %d core %d thread %d\n", 4826 i, cpus[i].physical_package_id, 4827 cpus[i].physical_node_id, 4828 cpus[i].physical_core_id, 4829 cpus[i].thread_id); 4830 } 4831 4832 topo.cores_per_node = max_core_id + 1; 4833 if (debug > 1) 4834 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", 4835 max_core_id, topo.cores_per_node); 4836 if (!summary_only && topo.cores_per_node > 1) 4837 BIC_PRESENT(BIC_Core); 4838 4839 topo.num_packages = max_package_id + 1; 4840 if (debug > 1) 4841 fprintf(outf, "max_package_id %d, sizing for %d packages\n", 4842 max_package_id, topo.num_packages); 4843 if (!summary_only && topo.num_packages > 1) 4844 BIC_PRESENT(BIC_Package); 4845 4846 set_node_data(); 4847 if (debug > 1) 4848 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg); 4849 if (!summary_only && topo.nodes_per_pkg > 1) 4850 BIC_PRESENT(BIC_Node); 4851 4852 topo.threads_per_core = max_siblings; 4853 if (debug > 1) 4854 fprintf(outf, "max_siblings %d\n", max_siblings); 4855 } 4856 4857 void 4858 allocate_counters(struct thread_data **t, struct core_data **c, 4859 struct pkg_data **p) 4860 { 4861 int i; 4862 int num_cores = topo.cores_per_node * topo.nodes_per_pkg * 4863 topo.num_packages; 4864 int num_threads = topo.threads_per_core * num_cores; 4865 4866 *t = calloc(num_threads, sizeof(struct thread_data)); 4867 if (*t == NULL) 4868 goto error; 4869 4870 for (i = 0; i < num_threads; i++) 4871 (*t)[i].cpu_id = -1; 4872 4873 *c = calloc(num_cores, sizeof(struct core_data)); 4874 if (*c == NULL) 4875 goto error; 4876 4877 for (i = 0; i < num_cores; i++) 4878 (*c)[i].core_id = -1; 4879 4880 *p = calloc(topo.num_packages, sizeof(struct pkg_data)); 4881 if (*p == NULL) 4882 goto error; 4883 4884 for (i = 0; i < topo.num_packages; i++) 4885 (*p)[i].package_id = i; 4886 4887 return; 4888 error: 4889 err(1, "calloc counters"); 4890 } 4891 /* 4892 * init_counter() 4893 * 4894 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE 4895 */ 4896 void init_counter(struct thread_data *thread_base, struct core_data *core_base, 4897 struct pkg_data *pkg_base, int cpu_id) 4898 { 4899 int pkg_id = cpus[cpu_id].physical_package_id; 4900 int node_id = cpus[cpu_id].logical_node_id; 4901 int core_id = cpus[cpu_id].physical_core_id; 4902 int thread_id = cpus[cpu_id].thread_id; 4903 struct thread_data *t; 4904 struct core_data *c; 4905 struct pkg_data *p; 4906 4907 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id); 4908 c = GET_CORE(core_base, core_id, node_id, pkg_id); 4909 p = GET_PKG(pkg_base, pkg_id); 4910 4911 t->cpu_id = cpu_id; 4912 if (thread_id == 0) { 4913 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; 4914 if (cpu_is_first_core_in_package(cpu_id)) 4915 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; 4916 } 4917 4918 c->core_id = core_id; 4919 p->package_id = pkg_id; 4920 } 4921 4922 4923 int initialize_counters(int cpu_id) 4924 { 4925 init_counter(EVEN_COUNTERS, cpu_id); 4926 init_counter(ODD_COUNTERS, cpu_id); 4927 return 0; 4928 } 4929 4930 void allocate_output_buffer() 4931 { 4932 output_buffer = calloc(1, (1 + topo.num_cpus) * 1024); 4933 outp = output_buffer; 4934 if (outp == NULL) 4935 err(-1, "calloc output buffer"); 4936 } 4937 void allocate_fd_percpu(void) 4938 { 4939 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 4940 if (fd_percpu == NULL) 4941 err(-1, "calloc fd_percpu"); 4942 } 4943 void allocate_irq_buffers(void) 4944 { 4945 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); 4946 if (irq_column_2_cpu == NULL) 4947 err(-1, "calloc %d", topo.num_cpus); 4948 4949 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 4950 if (irqs_per_cpu == NULL) 4951 err(-1, "calloc %d", topo.max_cpu_num + 1); 4952 } 4953 void setup_all_buffers(void) 4954 { 4955 topology_probe(); 4956 allocate_irq_buffers(); 4957 allocate_fd_percpu(); 4958 allocate_counters(&thread_even, &core_even, &package_even); 4959 allocate_counters(&thread_odd, &core_odd, &package_odd); 4960 allocate_output_buffer(); 4961 for_all_proc_cpus(initialize_counters); 4962 } 4963 4964 void set_base_cpu(void) 4965 { 4966 base_cpu = sched_getcpu(); 4967 if (base_cpu < 0) 4968 err(-ENODEV, "No valid cpus found"); 4969 4970 if (debug > 1) 4971 fprintf(outf, "base_cpu = %d\n", base_cpu); 4972 } 4973 4974 void turbostat_init() 4975 { 4976 setup_all_buffers(); 4977 set_base_cpu(); 4978 check_dev_msr(); 4979 check_permissions(); 4980 process_cpuid(); 4981 4982 4983 if (!quiet) 4984 for_all_cpus(print_hwp, ODD_COUNTERS); 4985 4986 if (!quiet) 4987 for_all_cpus(print_epb, ODD_COUNTERS); 4988 4989 if (!quiet) 4990 for_all_cpus(print_perf_limit, ODD_COUNTERS); 4991 4992 if (!quiet) 4993 for_all_cpus(print_rapl, ODD_COUNTERS); 4994 4995 for_all_cpus(set_temperature_target, ODD_COUNTERS); 4996 4997 if (!quiet) 4998 for_all_cpus(print_thermal, ODD_COUNTERS); 4999 5000 if (!quiet && do_irtl_snb) 5001 print_irtl(); 5002 } 5003 5004 int fork_it(char **argv) 5005 { 5006 pid_t child_pid; 5007 int status; 5008 5009 snapshot_proc_sysfs_files(); 5010 status = for_all_cpus(get_counters, EVEN_COUNTERS); 5011 first_counter_read = 0; 5012 if (status) 5013 exit(status); 5014 /* clear affinity side-effect of get_counters() */ 5015 sched_setaffinity(0, cpu_present_setsize, cpu_present_set); 5016 gettimeofday(&tv_even, (struct timezone *)NULL); 5017 5018 child_pid = fork(); 5019 if (!child_pid) { 5020 /* child */ 5021 execvp(argv[0], argv); 5022 err(errno, "exec %s", argv[0]); 5023 } else { 5024 5025 /* parent */ 5026 if (child_pid == -1) 5027 err(1, "fork"); 5028 5029 signal(SIGINT, SIG_IGN); 5030 signal(SIGQUIT, SIG_IGN); 5031 if (waitpid(child_pid, &status, 0) == -1) 5032 err(status, "waitpid"); 5033 } 5034 /* 5035 * n.b. fork_it() does not check for errors from for_all_cpus() 5036 * because re-starting is problematic when forking 5037 */ 5038 snapshot_proc_sysfs_files(); 5039 for_all_cpus(get_counters, ODD_COUNTERS); 5040 gettimeofday(&tv_odd, (struct timezone *)NULL); 5041 timersub(&tv_odd, &tv_even, &tv_delta); 5042 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) 5043 fprintf(outf, "%s: Counter reset detected\n", progname); 5044 else { 5045 compute_average(EVEN_COUNTERS); 5046 format_all_counters(EVEN_COUNTERS); 5047 } 5048 5049 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0); 5050 5051 flush_output_stderr(); 5052 5053 return status; 5054 } 5055 5056 int get_and_dump_counters(void) 5057 { 5058 int status; 5059 5060 snapshot_proc_sysfs_files(); 5061 status = for_all_cpus(get_counters, ODD_COUNTERS); 5062 if (status) 5063 return status; 5064 5065 status = for_all_cpus(dump_counters, ODD_COUNTERS); 5066 if (status) 5067 return status; 5068 5069 flush_output_stdout(); 5070 5071 return status; 5072 } 5073 5074 void print_version() { 5075 fprintf(outf, "turbostat version 18.06.01" 5076 " - Len Brown <lenb@kernel.org>\n"); 5077 } 5078 5079 int add_counter(unsigned int msr_num, char *path, char *name, 5080 unsigned int width, enum counter_scope scope, 5081 enum counter_type type, enum counter_format format, int flags) 5082 { 5083 struct msr_counter *msrp; 5084 5085 msrp = calloc(1, sizeof(struct msr_counter)); 5086 if (msrp == NULL) { 5087 perror("calloc"); 5088 exit(1); 5089 } 5090 5091 msrp->msr_num = msr_num; 5092 strncpy(msrp->name, name, NAME_BYTES); 5093 if (path) 5094 strncpy(msrp->path, path, PATH_BYTES); 5095 msrp->width = width; 5096 msrp->type = type; 5097 msrp->format = format; 5098 msrp->flags = flags; 5099 5100 switch (scope) { 5101 5102 case SCOPE_CPU: 5103 msrp->next = sys.tp; 5104 sys.tp = msrp; 5105 sys.added_thread_counters++; 5106 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) { 5107 fprintf(stderr, "exceeded max %d added thread counters\n", 5108 MAX_ADDED_COUNTERS); 5109 exit(-1); 5110 } 5111 break; 5112 5113 case SCOPE_CORE: 5114 msrp->next = sys.cp; 5115 sys.cp = msrp; 5116 sys.added_core_counters++; 5117 if (sys.added_core_counters > MAX_ADDED_COUNTERS) { 5118 fprintf(stderr, "exceeded max %d added core counters\n", 5119 MAX_ADDED_COUNTERS); 5120 exit(-1); 5121 } 5122 break; 5123 5124 case SCOPE_PACKAGE: 5125 msrp->next = sys.pp; 5126 sys.pp = msrp; 5127 sys.added_package_counters++; 5128 if (sys.added_package_counters > MAX_ADDED_COUNTERS) { 5129 fprintf(stderr, "exceeded max %d added package counters\n", 5130 MAX_ADDED_COUNTERS); 5131 exit(-1); 5132 } 5133 break; 5134 } 5135 5136 return 0; 5137 } 5138 5139 void parse_add_command(char *add_command) 5140 { 5141 int msr_num = 0; 5142 char *path = NULL; 5143 char name_buffer[NAME_BYTES] = ""; 5144 int width = 64; 5145 int fail = 0; 5146 enum counter_scope scope = SCOPE_CPU; 5147 enum counter_type type = COUNTER_CYCLES; 5148 enum counter_format format = FORMAT_DELTA; 5149 5150 while (add_command) { 5151 5152 if (sscanf(add_command, "msr0x%x", &msr_num) == 1) 5153 goto next; 5154 5155 if (sscanf(add_command, "msr%d", &msr_num) == 1) 5156 goto next; 5157 5158 if (*add_command == '/') { 5159 path = add_command; 5160 goto next; 5161 } 5162 5163 if (sscanf(add_command, "u%d", &width) == 1) { 5164 if ((width == 32) || (width == 64)) 5165 goto next; 5166 width = 64; 5167 } 5168 if (!strncmp(add_command, "cpu", strlen("cpu"))) { 5169 scope = SCOPE_CPU; 5170 goto next; 5171 } 5172 if (!strncmp(add_command, "core", strlen("core"))) { 5173 scope = SCOPE_CORE; 5174 goto next; 5175 } 5176 if (!strncmp(add_command, "package", strlen("package"))) { 5177 scope = SCOPE_PACKAGE; 5178 goto next; 5179 } 5180 if (!strncmp(add_command, "cycles", strlen("cycles"))) { 5181 type = COUNTER_CYCLES; 5182 goto next; 5183 } 5184 if (!strncmp(add_command, "seconds", strlen("seconds"))) { 5185 type = COUNTER_SECONDS; 5186 goto next; 5187 } 5188 if (!strncmp(add_command, "usec", strlen("usec"))) { 5189 type = COUNTER_USEC; 5190 goto next; 5191 } 5192 if (!strncmp(add_command, "raw", strlen("raw"))) { 5193 format = FORMAT_RAW; 5194 goto next; 5195 } 5196 if (!strncmp(add_command, "delta", strlen("delta"))) { 5197 format = FORMAT_DELTA; 5198 goto next; 5199 } 5200 if (!strncmp(add_command, "percent", strlen("percent"))) { 5201 format = FORMAT_PERCENT; 5202 goto next; 5203 } 5204 5205 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */ 5206 char *eos; 5207 5208 eos = strchr(name_buffer, ','); 5209 if (eos) 5210 *eos = '\0'; 5211 goto next; 5212 } 5213 5214 next: 5215 add_command = strchr(add_command, ','); 5216 if (add_command) { 5217 *add_command = '\0'; 5218 add_command++; 5219 } 5220 5221 } 5222 if ((msr_num == 0) && (path == NULL)) { 5223 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n"); 5224 fail++; 5225 } 5226 5227 /* generate default column header */ 5228 if (*name_buffer == '\0') { 5229 if (width == 32) 5230 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 5231 else 5232 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 5233 } 5234 5235 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0)) 5236 fail++; 5237 5238 if (fail) { 5239 help(); 5240 exit(1); 5241 } 5242 } 5243 5244 int is_deferred_skip(char *name) 5245 { 5246 int i; 5247 5248 for (i = 0; i < deferred_skip_index; ++i) 5249 if (!strcmp(name, deferred_skip_names[i])) 5250 return 1; 5251 return 0; 5252 } 5253 5254 void probe_sysfs(void) 5255 { 5256 char path[64]; 5257 char name_buf[16]; 5258 FILE *input; 5259 int state; 5260 char *sp; 5261 5262 if (!DO_BIC(BIC_sysfs)) 5263 return; 5264 5265 for (state = 10; state >= 0; --state) { 5266 5267 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 5268 base_cpu, state); 5269 input = fopen(path, "r"); 5270 if (input == NULL) 5271 continue; 5272 fgets(name_buf, sizeof(name_buf), input); 5273 5274 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 5275 sp = strchr(name_buf, '-'); 5276 if (!sp) 5277 sp = strchrnul(name_buf, '\n'); 5278 *sp = '%'; 5279 *(sp + 1) = '\0'; 5280 5281 fclose(input); 5282 5283 sprintf(path, "cpuidle/state%d/time", state); 5284 5285 if (is_deferred_skip(name_buf)) 5286 continue; 5287 5288 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC, 5289 FORMAT_PERCENT, SYSFS_PERCPU); 5290 } 5291 5292 for (state = 10; state >= 0; --state) { 5293 5294 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 5295 base_cpu, state); 5296 input = fopen(path, "r"); 5297 if (input == NULL) 5298 continue; 5299 fgets(name_buf, sizeof(name_buf), input); 5300 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 5301 sp = strchr(name_buf, '-'); 5302 if (!sp) 5303 sp = strchrnul(name_buf, '\n'); 5304 *sp = '\0'; 5305 fclose(input); 5306 5307 sprintf(path, "cpuidle/state%d/usage", state); 5308 5309 if (is_deferred_skip(name_buf)) 5310 continue; 5311 5312 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS, 5313 FORMAT_DELTA, SYSFS_PERCPU); 5314 } 5315 5316 } 5317 5318 5319 /* 5320 * parse cpuset with following syntax 5321 * 1,2,4..6,8-10 and set bits in cpu_subset 5322 */ 5323 void parse_cpu_command(char *optarg) 5324 { 5325 unsigned int start, end; 5326 char *next; 5327 5328 if (!strcmp(optarg, "core")) { 5329 if (cpu_subset) 5330 goto error; 5331 show_core_only++; 5332 return; 5333 } 5334 if (!strcmp(optarg, "package")) { 5335 if (cpu_subset) 5336 goto error; 5337 show_pkg_only++; 5338 return; 5339 } 5340 if (show_core_only || show_pkg_only) 5341 goto error; 5342 5343 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS); 5344 if (cpu_subset == NULL) 5345 err(3, "CPU_ALLOC"); 5346 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS); 5347 5348 CPU_ZERO_S(cpu_subset_size, cpu_subset); 5349 5350 next = optarg; 5351 5352 while (next && *next) { 5353 5354 if (*next == '-') /* no negative cpu numbers */ 5355 goto error; 5356 5357 start = strtoul(next, &next, 10); 5358 5359 if (start >= CPU_SUBSET_MAXCPUS) 5360 goto error; 5361 CPU_SET_S(start, cpu_subset_size, cpu_subset); 5362 5363 if (*next == '\0') 5364 break; 5365 5366 if (*next == ',') { 5367 next += 1; 5368 continue; 5369 } 5370 5371 if (*next == '-') { 5372 next += 1; /* start range */ 5373 } else if (*next == '.') { 5374 next += 1; 5375 if (*next == '.') 5376 next += 1; /* start range */ 5377 else 5378 goto error; 5379 } 5380 5381 end = strtoul(next, &next, 10); 5382 if (end <= start) 5383 goto error; 5384 5385 while (++start <= end) { 5386 if (start >= CPU_SUBSET_MAXCPUS) 5387 goto error; 5388 CPU_SET_S(start, cpu_subset_size, cpu_subset); 5389 } 5390 5391 if (*next == ',') 5392 next += 1; 5393 else if (*next != '\0') 5394 goto error; 5395 } 5396 5397 return; 5398 5399 error: 5400 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg); 5401 help(); 5402 exit(-1); 5403 } 5404 5405 5406 void cmdline(int argc, char **argv) 5407 { 5408 int opt; 5409 int option_index = 0; 5410 static struct option long_options[] = { 5411 {"add", required_argument, 0, 'a'}, 5412 {"cpu", required_argument, 0, 'c'}, 5413 {"Dump", no_argument, 0, 'D'}, 5414 {"debug", no_argument, 0, 'd'}, /* internal, not documented */ 5415 {"enable", required_argument, 0, 'e'}, 5416 {"interval", required_argument, 0, 'i'}, 5417 {"num_iterations", required_argument, 0, 'n'}, 5418 {"help", no_argument, 0, 'h'}, 5419 {"hide", required_argument, 0, 'H'}, // meh, -h taken by --help 5420 {"Joules", no_argument, 0, 'J'}, 5421 {"list", no_argument, 0, 'l'}, 5422 {"out", required_argument, 0, 'o'}, 5423 {"quiet", no_argument, 0, 'q'}, 5424 {"show", required_argument, 0, 's'}, 5425 {"Summary", no_argument, 0, 'S'}, 5426 {"TCC", required_argument, 0, 'T'}, 5427 {"version", no_argument, 0, 'v' }, 5428 {0, 0, 0, 0 } 5429 }; 5430 5431 progname = argv[0]; 5432 5433 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v", 5434 long_options, &option_index)) != -1) { 5435 switch (opt) { 5436 case 'a': 5437 parse_add_command(optarg); 5438 break; 5439 case 'c': 5440 parse_cpu_command(optarg); 5441 break; 5442 case 'D': 5443 dump_only++; 5444 break; 5445 case 'e': 5446 /* --enable specified counter */ 5447 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST); 5448 break; 5449 case 'd': 5450 debug++; 5451 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 5452 break; 5453 case 'H': 5454 /* 5455 * --hide: do not show those specified 5456 * multiple invocations simply clear more bits in enabled mask 5457 */ 5458 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST); 5459 break; 5460 case 'h': 5461 default: 5462 help(); 5463 exit(1); 5464 case 'i': 5465 { 5466 double interval = strtod(optarg, NULL); 5467 5468 if (interval < 0.001) { 5469 fprintf(outf, "interval %f seconds is too small\n", 5470 interval); 5471 exit(2); 5472 } 5473 5474 interval_tv.tv_sec = interval_ts.tv_sec = interval; 5475 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000; 5476 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; 5477 } 5478 break; 5479 case 'J': 5480 rapl_joules++; 5481 break; 5482 case 'l': 5483 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 5484 list_header_only++; 5485 quiet++; 5486 break; 5487 case 'o': 5488 outf = fopen_or_die(optarg, "w"); 5489 break; 5490 case 'q': 5491 quiet = 1; 5492 break; 5493 case 'n': 5494 num_iterations = strtod(optarg, NULL); 5495 5496 if (num_iterations <= 0) { 5497 fprintf(outf, "iterations %d should be positive number\n", 5498 num_iterations); 5499 exit(2); 5500 } 5501 break; 5502 case 's': 5503 /* 5504 * --show: show only those specified 5505 * The 1st invocation will clear and replace the enabled mask 5506 * subsequent invocations can add to it. 5507 */ 5508 if (shown == 0) 5509 bic_enabled = bic_lookup(optarg, SHOW_LIST); 5510 else 5511 bic_enabled |= bic_lookup(optarg, SHOW_LIST); 5512 shown = 1; 5513 break; 5514 case 'S': 5515 summary_only++; 5516 break; 5517 case 'T': 5518 tcc_activation_temp_override = atoi(optarg); 5519 break; 5520 case 'v': 5521 print_version(); 5522 exit(0); 5523 break; 5524 } 5525 } 5526 } 5527 5528 int main(int argc, char **argv) 5529 { 5530 outf = stderr; 5531 cmdline(argc, argv); 5532 5533 if (!quiet) 5534 print_version(); 5535 5536 probe_sysfs(); 5537 5538 turbostat_init(); 5539 5540 /* dump counters and exit */ 5541 if (dump_only) 5542 return get_and_dump_counters(); 5543 5544 /* list header and exit */ 5545 if (list_header_only) { 5546 print_header(","); 5547 flush_output_stdout(); 5548 return 0; 5549 } 5550 5551 /* 5552 * if any params left, it must be a command to fork 5553 */ 5554 if (argc - optind) 5555 return fork_it(argv + optind); 5556 else 5557 turbostat_loop(); 5558 5559 return 0; 5560 } 5561