1 /* 2 * turbostat -- show CPU frequency and C-state residency 3 * on modern Intel turbo-capable processors. 4 * 5 * Copyright (c) 2013 Intel Corporation. 6 * Len Brown <len.brown@intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 20 */ 21 22 #define _GNU_SOURCE 23 #include MSRHEADER 24 #include INTEL_FAMILY_HEADER 25 #include <stdarg.h> 26 #include <stdio.h> 27 #include <err.h> 28 #include <unistd.h> 29 #include <sys/types.h> 30 #include <sys/wait.h> 31 #include <sys/stat.h> 32 #include <sys/select.h> 33 #include <sys/resource.h> 34 #include <fcntl.h> 35 #include <signal.h> 36 #include <sys/time.h> 37 #include <stdlib.h> 38 #include <getopt.h> 39 #include <dirent.h> 40 #include <string.h> 41 #include <ctype.h> 42 #include <sched.h> 43 #include <time.h> 44 #include <cpuid.h> 45 #include <linux/capability.h> 46 #include <errno.h> 47 48 char *proc_stat = "/proc/stat"; 49 FILE *outf; 50 int *fd_percpu; 51 struct timeval interval_tv = {5, 0}; 52 struct timespec interval_ts = {5, 0}; 53 struct timespec one_msec = {0, 1000000}; 54 unsigned int num_iterations; 55 unsigned int debug; 56 unsigned int quiet; 57 unsigned int shown; 58 unsigned int sums_need_wide_columns; 59 unsigned int rapl_joules; 60 unsigned int summary_only; 61 unsigned int list_header_only; 62 unsigned int dump_only; 63 unsigned int do_snb_cstates; 64 unsigned int do_knl_cstates; 65 unsigned int do_slm_cstates; 66 unsigned int do_cnl_cstates; 67 unsigned int use_c1_residency_msr; 68 unsigned int has_aperf; 69 unsigned int has_epb; 70 unsigned int do_irtl_snb; 71 unsigned int do_irtl_hsw; 72 unsigned int units = 1000000; /* MHz etc */ 73 unsigned int genuine_intel; 74 unsigned int has_invariant_tsc; 75 unsigned int do_nhm_platform_info; 76 unsigned int no_MSR_MISC_PWR_MGMT; 77 unsigned int aperf_mperf_multiplier = 1; 78 double bclk; 79 double base_hz; 80 unsigned int has_base_hz; 81 double tsc_tweak = 1.0; 82 unsigned int show_pkg_only; 83 unsigned int show_core_only; 84 char *output_buffer, *outp; 85 unsigned int do_rapl; 86 unsigned int do_dts; 87 unsigned int do_ptm; 88 unsigned long long gfx_cur_rc6_ms; 89 unsigned long long cpuidle_cur_cpu_lpi_us; 90 unsigned long long cpuidle_cur_sys_lpi_us; 91 unsigned int gfx_cur_mhz; 92 unsigned int tcc_activation_temp; 93 unsigned int tcc_activation_temp_override; 94 double rapl_power_units, rapl_time_units; 95 double rapl_dram_energy_units, rapl_energy_units; 96 double rapl_joule_counter_range; 97 unsigned int do_core_perf_limit_reasons; 98 unsigned int has_automatic_cstate_conversion; 99 unsigned int do_gfx_perf_limit_reasons; 100 unsigned int do_ring_perf_limit_reasons; 101 unsigned int crystal_hz; 102 unsigned long long tsc_hz; 103 int base_cpu; 104 double discover_bclk(unsigned int family, unsigned int model); 105 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ 106 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ 107 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ 108 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ 109 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ 110 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ 111 unsigned int has_misc_feature_control; 112 unsigned int first_counter_read = 1; 113 114 #define RAPL_PKG (1 << 0) 115 /* 0x610 MSR_PKG_POWER_LIMIT */ 116 /* 0x611 MSR_PKG_ENERGY_STATUS */ 117 #define RAPL_PKG_PERF_STATUS (1 << 1) 118 /* 0x613 MSR_PKG_PERF_STATUS */ 119 #define RAPL_PKG_POWER_INFO (1 << 2) 120 /* 0x614 MSR_PKG_POWER_INFO */ 121 122 #define RAPL_DRAM (1 << 3) 123 /* 0x618 MSR_DRAM_POWER_LIMIT */ 124 /* 0x619 MSR_DRAM_ENERGY_STATUS */ 125 #define RAPL_DRAM_PERF_STATUS (1 << 4) 126 /* 0x61b MSR_DRAM_PERF_STATUS */ 127 #define RAPL_DRAM_POWER_INFO (1 << 5) 128 /* 0x61c MSR_DRAM_POWER_INFO */ 129 130 #define RAPL_CORES_POWER_LIMIT (1 << 6) 131 /* 0x638 MSR_PP0_POWER_LIMIT */ 132 #define RAPL_CORE_POLICY (1 << 7) 133 /* 0x63a MSR_PP0_POLICY */ 134 135 #define RAPL_GFX (1 << 8) 136 /* 0x640 MSR_PP1_POWER_LIMIT */ 137 /* 0x641 MSR_PP1_ENERGY_STATUS */ 138 /* 0x642 MSR_PP1_POLICY */ 139 140 #define RAPL_CORES_ENERGY_STATUS (1 << 9) 141 /* 0x639 MSR_PP0_ENERGY_STATUS */ 142 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT) 143 #define TJMAX_DEFAULT 100 144 145 #define MAX(a, b) ((a) > (b) ? (a) : (b)) 146 147 /* 148 * buffer size used by sscanf() for added column names 149 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters 150 */ 151 #define NAME_BYTES 20 152 #define PATH_BYTES 128 153 154 int backwards_count; 155 char *progname; 156 157 #define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */ 158 cpu_set_t *cpu_present_set, *cpu_affinity_set, *cpu_subset; 159 size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size; 160 #define MAX_ADDED_COUNTERS 8 161 #define MAX_ADDED_THREAD_COUNTERS 24 162 #define BITMASK_SIZE 32 163 164 struct thread_data { 165 struct timeval tv_begin; 166 struct timeval tv_end; 167 unsigned long long tsc; 168 unsigned long long aperf; 169 unsigned long long mperf; 170 unsigned long long c1; 171 unsigned long long irq_count; 172 unsigned int smi_count; 173 unsigned int cpu_id; 174 unsigned int apic_id; 175 unsigned int x2apic_id; 176 unsigned int flags; 177 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2 178 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 179 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS]; 180 } *thread_even, *thread_odd; 181 182 struct core_data { 183 unsigned long long c3; 184 unsigned long long c6; 185 unsigned long long c7; 186 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */ 187 unsigned int core_temp_c; 188 unsigned int core_id; 189 unsigned long long counter[MAX_ADDED_COUNTERS]; 190 } *core_even, *core_odd; 191 192 struct pkg_data { 193 unsigned long long pc2; 194 unsigned long long pc3; 195 unsigned long long pc6; 196 unsigned long long pc7; 197 unsigned long long pc8; 198 unsigned long long pc9; 199 unsigned long long pc10; 200 unsigned long long cpu_lpi; 201 unsigned long long sys_lpi; 202 unsigned long long pkg_wtd_core_c0; 203 unsigned long long pkg_any_core_c0; 204 unsigned long long pkg_any_gfxe_c0; 205 unsigned long long pkg_both_core_gfxe_c0; 206 long long gfx_rc6_ms; 207 unsigned int gfx_mhz; 208 unsigned int package_id; 209 unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */ 210 unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */ 211 unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */ 212 unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */ 213 unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ 214 unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ 215 unsigned int pkg_temp_c; 216 unsigned long long counter[MAX_ADDED_COUNTERS]; 217 } *package_even, *package_odd; 218 219 #define ODD_COUNTERS thread_odd, core_odd, package_odd 220 #define EVEN_COUNTERS thread_even, core_even, package_even 221 222 #define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \ 223 ((thread_base) + \ 224 ((pkg_no) * \ 225 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \ 226 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \ 227 ((core_no) * topo.threads_per_core) + \ 228 (thread_no)) 229 230 #define GET_CORE(core_base, core_no, node_no, pkg_no) \ 231 ((core_base) + \ 232 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \ 233 ((node_no) * topo.cores_per_node) + \ 234 (core_no)) 235 236 237 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) 238 239 enum counter_scope {SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE}; 240 enum counter_type {COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC}; 241 enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT}; 242 243 struct msr_counter { 244 unsigned int msr_num; 245 char name[NAME_BYTES]; 246 char path[PATH_BYTES]; 247 unsigned int width; 248 enum counter_type type; 249 enum counter_format format; 250 struct msr_counter *next; 251 unsigned int flags; 252 #define FLAGS_HIDE (1 << 0) 253 #define FLAGS_SHOW (1 << 1) 254 #define SYSFS_PERCPU (1 << 1) 255 }; 256 257 struct sys_counters { 258 unsigned int added_thread_counters; 259 unsigned int added_core_counters; 260 unsigned int added_package_counters; 261 struct msr_counter *tp; 262 struct msr_counter *cp; 263 struct msr_counter *pp; 264 } sys; 265 266 struct system_summary { 267 struct thread_data threads; 268 struct core_data cores; 269 struct pkg_data packages; 270 } average; 271 272 struct cpu_topology { 273 int physical_package_id; 274 int logical_cpu_id; 275 int physical_node_id; 276 int logical_node_id; /* 0-based count within the package */ 277 int physical_core_id; 278 int thread_id; 279 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */ 280 } *cpus; 281 282 struct topo_params { 283 int num_packages; 284 int num_cpus; 285 int num_cores; 286 int max_cpu_num; 287 int max_node_num; 288 int nodes_per_pkg; 289 int cores_per_node; 290 int threads_per_core; 291 } topo; 292 293 struct timeval tv_even, tv_odd, tv_delta; 294 295 int *irq_column_2_cpu; /* /proc/interrupts column numbers */ 296 int *irqs_per_cpu; /* indexed by cpu_num */ 297 298 void setup_all_buffers(void); 299 300 int cpu_is_not_present(int cpu) 301 { 302 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); 303 } 304 /* 305 * run func(thread, core, package) in topology order 306 * skip non-present cpus 307 */ 308 309 int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *), 310 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) 311 { 312 int retval, pkg_no, core_no, thread_no, node_no; 313 314 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 315 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) { 316 for (node_no = 0; node_no < topo.nodes_per_pkg; 317 node_no++) { 318 for (thread_no = 0; thread_no < 319 topo.threads_per_core; ++thread_no) { 320 struct thread_data *t; 321 struct core_data *c; 322 struct pkg_data *p; 323 324 t = GET_THREAD(thread_base, thread_no, 325 core_no, node_no, 326 pkg_no); 327 328 if (cpu_is_not_present(t->cpu_id)) 329 continue; 330 331 c = GET_CORE(core_base, core_no, 332 node_no, pkg_no); 333 p = GET_PKG(pkg_base, pkg_no); 334 335 retval = func(t, c, p); 336 if (retval) 337 return retval; 338 } 339 } 340 } 341 } 342 return 0; 343 } 344 345 int cpu_migrate(int cpu) 346 { 347 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 348 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); 349 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) 350 return -1; 351 else 352 return 0; 353 } 354 int get_msr_fd(int cpu) 355 { 356 char pathname[32]; 357 int fd; 358 359 fd = fd_percpu[cpu]; 360 361 if (fd) 362 return fd; 363 364 sprintf(pathname, "/dev/cpu/%d/msr", cpu); 365 fd = open(pathname, O_RDONLY); 366 if (fd < 0) 367 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); 368 369 fd_percpu[cpu] = fd; 370 371 return fd; 372 } 373 374 int get_msr(int cpu, off_t offset, unsigned long long *msr) 375 { 376 ssize_t retval; 377 378 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); 379 380 if (retval != sizeof *msr) 381 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset); 382 383 return 0; 384 } 385 386 /* 387 * This list matches the column headers, except 388 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time 389 * 2. Core and CPU are moved to the end, we can't have strings that contain them 390 * matching on them for --show and --hide. 391 */ 392 struct msr_counter bic[] = { 393 { 0x0, "usec" }, 394 { 0x0, "Time_Of_Day_Seconds" }, 395 { 0x0, "Package" }, 396 { 0x0, "Node" }, 397 { 0x0, "Avg_MHz" }, 398 { 0x0, "Busy%" }, 399 { 0x0, "Bzy_MHz" }, 400 { 0x0, "TSC_MHz" }, 401 { 0x0, "IRQ" }, 402 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL}, 403 { 0x0, "sysfs" }, 404 { 0x0, "CPU%c1" }, 405 { 0x0, "CPU%c3" }, 406 { 0x0, "CPU%c6" }, 407 { 0x0, "CPU%c7" }, 408 { 0x0, "ThreadC" }, 409 { 0x0, "CoreTmp" }, 410 { 0x0, "CoreCnt" }, 411 { 0x0, "PkgTmp" }, 412 { 0x0, "GFX%rc6" }, 413 { 0x0, "GFXMHz" }, 414 { 0x0, "Pkg%pc2" }, 415 { 0x0, "Pkg%pc3" }, 416 { 0x0, "Pkg%pc6" }, 417 { 0x0, "Pkg%pc7" }, 418 { 0x0, "Pkg%pc8" }, 419 { 0x0, "Pkg%pc9" }, 420 { 0x0, "Pk%pc10" }, 421 { 0x0, "CPU%LPI" }, 422 { 0x0, "SYS%LPI" }, 423 { 0x0, "PkgWatt" }, 424 { 0x0, "CorWatt" }, 425 { 0x0, "GFXWatt" }, 426 { 0x0, "PkgCnt" }, 427 { 0x0, "RAMWatt" }, 428 { 0x0, "PKG_%" }, 429 { 0x0, "RAM_%" }, 430 { 0x0, "Pkg_J" }, 431 { 0x0, "Cor_J" }, 432 { 0x0, "GFX_J" }, 433 { 0x0, "RAM_J" }, 434 { 0x0, "Mod%c6" }, 435 { 0x0, "Totl%C0" }, 436 { 0x0, "Any%C0" }, 437 { 0x0, "GFX%C0" }, 438 { 0x0, "CPUGFX%" }, 439 { 0x0, "Core" }, 440 { 0x0, "CPU" }, 441 { 0x0, "APIC" }, 442 { 0x0, "X2APIC" }, 443 }; 444 445 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter)) 446 #define BIC_USEC (1ULL << 0) 447 #define BIC_TOD (1ULL << 1) 448 #define BIC_Package (1ULL << 2) 449 #define BIC_Node (1ULL << 3) 450 #define BIC_Avg_MHz (1ULL << 4) 451 #define BIC_Busy (1ULL << 5) 452 #define BIC_Bzy_MHz (1ULL << 6) 453 #define BIC_TSC_MHz (1ULL << 7) 454 #define BIC_IRQ (1ULL << 8) 455 #define BIC_SMI (1ULL << 9) 456 #define BIC_sysfs (1ULL << 10) 457 #define BIC_CPU_c1 (1ULL << 11) 458 #define BIC_CPU_c3 (1ULL << 12) 459 #define BIC_CPU_c6 (1ULL << 13) 460 #define BIC_CPU_c7 (1ULL << 14) 461 #define BIC_ThreadC (1ULL << 15) 462 #define BIC_CoreTmp (1ULL << 16) 463 #define BIC_CoreCnt (1ULL << 17) 464 #define BIC_PkgTmp (1ULL << 18) 465 #define BIC_GFX_rc6 (1ULL << 19) 466 #define BIC_GFXMHz (1ULL << 20) 467 #define BIC_Pkgpc2 (1ULL << 21) 468 #define BIC_Pkgpc3 (1ULL << 22) 469 #define BIC_Pkgpc6 (1ULL << 23) 470 #define BIC_Pkgpc7 (1ULL << 24) 471 #define BIC_Pkgpc8 (1ULL << 25) 472 #define BIC_Pkgpc9 (1ULL << 26) 473 #define BIC_Pkgpc10 (1ULL << 27) 474 #define BIC_CPU_LPI (1ULL << 28) 475 #define BIC_SYS_LPI (1ULL << 29) 476 #define BIC_PkgWatt (1ULL << 30) 477 #define BIC_CorWatt (1ULL << 31) 478 #define BIC_GFXWatt (1ULL << 32) 479 #define BIC_PkgCnt (1ULL << 33) 480 #define BIC_RAMWatt (1ULL << 34) 481 #define BIC_PKG__ (1ULL << 35) 482 #define BIC_RAM__ (1ULL << 36) 483 #define BIC_Pkg_J (1ULL << 37) 484 #define BIC_Cor_J (1ULL << 38) 485 #define BIC_GFX_J (1ULL << 39) 486 #define BIC_RAM_J (1ULL << 40) 487 #define BIC_Mod_c6 (1ULL << 41) 488 #define BIC_Totl_c0 (1ULL << 42) 489 #define BIC_Any_c0 (1ULL << 43) 490 #define BIC_GFX_c0 (1ULL << 44) 491 #define BIC_CPUGFX (1ULL << 45) 492 #define BIC_Core (1ULL << 46) 493 #define BIC_CPU (1ULL << 47) 494 #define BIC_APIC (1ULL << 48) 495 #define BIC_X2APIC (1ULL << 49) 496 497 #define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC) 498 499 unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT); 500 unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC; 501 502 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME) 503 #define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME) 504 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT) 505 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT) 506 507 508 #define MAX_DEFERRED 16 509 char *deferred_skip_names[MAX_DEFERRED]; 510 int deferred_skip_index; 511 512 /* 513 * HIDE_LIST - hide this list of counters, show the rest [default] 514 * SHOW_LIST - show this list of counters, hide the rest 515 */ 516 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST; 517 518 void help(void) 519 { 520 fprintf(outf, 521 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" 522 "\n" 523 "Turbostat forks the specified COMMAND and prints statistics\n" 524 "when COMMAND completes.\n" 525 "If no COMMAND is specified, turbostat wakes every 5-seconds\n" 526 "to print statistics, until interrupted.\n" 527 "--add add a counter\n" 528 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n" 529 "--cpu cpu-set limit output to summary plus cpu-set:\n" 530 " {core | package | j,k,l..m,n-p }\n" 531 "--interval sec.subsec Override default 5-second measurement interval\n" 532 "--list list column headers only\n" 533 "--num_iterations num number of the measurement iterations\n" 534 "--out file create or truncate \"file\" for all output\n" 535 "--quiet skip decoding system configuration header\n" 536 "--help print this help message\n" 537 "--version print version information\n" 538 "\n" 539 "For more help, run \"man turbostat\"\n"); 540 } 541 542 /* 543 * bic_lookup 544 * for all the strings in comma separate name_list, 545 * set the approprate bit in return value. 546 */ 547 unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode) 548 { 549 int i; 550 unsigned long long retval = 0; 551 552 while (name_list) { 553 char *comma; 554 555 comma = strchr(name_list, ','); 556 557 if (comma) 558 *comma = '\0'; 559 560 if (!strcmp(name_list, "all")) 561 return ~0; 562 563 for (i = 0; i < MAX_BIC; ++i) { 564 if (!strcmp(name_list, bic[i].name)) { 565 retval |= (1ULL << i); 566 break; 567 } 568 } 569 if (i == MAX_BIC) { 570 if (mode == SHOW_LIST) { 571 fprintf(stderr, "Invalid counter name: %s\n", name_list); 572 exit(-1); 573 } 574 deferred_skip_names[deferred_skip_index++] = name_list; 575 if (debug) 576 fprintf(stderr, "deferred \"%s\"\n", name_list); 577 if (deferred_skip_index >= MAX_DEFERRED) { 578 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n", 579 MAX_DEFERRED, name_list); 580 help(); 581 exit(1); 582 } 583 } 584 585 name_list = comma; 586 if (name_list) 587 name_list++; 588 589 } 590 return retval; 591 } 592 593 594 void print_header(char *delim) 595 { 596 struct msr_counter *mp; 597 int printed = 0; 598 599 if (DO_BIC(BIC_USEC)) 600 outp += sprintf(outp, "%susec", (printed++ ? delim : "")); 601 if (DO_BIC(BIC_TOD)) 602 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : "")); 603 if (DO_BIC(BIC_Package)) 604 outp += sprintf(outp, "%sPackage", (printed++ ? delim : "")); 605 if (DO_BIC(BIC_Node)) 606 outp += sprintf(outp, "%sNode", (printed++ ? delim : "")); 607 if (DO_BIC(BIC_Core)) 608 outp += sprintf(outp, "%sCore", (printed++ ? delim : "")); 609 if (DO_BIC(BIC_CPU)) 610 outp += sprintf(outp, "%sCPU", (printed++ ? delim : "")); 611 if (DO_BIC(BIC_APIC)) 612 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : "")); 613 if (DO_BIC(BIC_X2APIC)) 614 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : "")); 615 if (DO_BIC(BIC_Avg_MHz)) 616 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : "")); 617 if (DO_BIC(BIC_Busy)) 618 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : "")); 619 if (DO_BIC(BIC_Bzy_MHz)) 620 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : "")); 621 if (DO_BIC(BIC_TSC_MHz)) 622 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : "")); 623 624 if (DO_BIC(BIC_IRQ)) { 625 if (sums_need_wide_columns) 626 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : "")); 627 else 628 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : "")); 629 } 630 631 if (DO_BIC(BIC_SMI)) 632 outp += sprintf(outp, "%sSMI", (printed++ ? delim : "")); 633 634 for (mp = sys.tp; mp; mp = mp->next) { 635 636 if (mp->format == FORMAT_RAW) { 637 if (mp->width == 64) 638 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name); 639 else 640 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name); 641 } else { 642 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 643 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name); 644 else 645 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name); 646 } 647 } 648 649 if (DO_BIC(BIC_CPU_c1)) 650 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : "")); 651 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates && !do_cnl_cstates) 652 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : "")); 653 if (DO_BIC(BIC_CPU_c6)) 654 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : "")); 655 if (DO_BIC(BIC_CPU_c7)) 656 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : "")); 657 658 if (DO_BIC(BIC_Mod_c6)) 659 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : "")); 660 661 if (DO_BIC(BIC_CoreTmp)) 662 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : "")); 663 664 for (mp = sys.cp; mp; mp = mp->next) { 665 if (mp->format == FORMAT_RAW) { 666 if (mp->width == 64) 667 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 668 else 669 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 670 } else { 671 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 672 outp += sprintf(outp, "%s%8s", delim, mp->name); 673 else 674 outp += sprintf(outp, "%s%s", delim, mp->name); 675 } 676 } 677 678 if (DO_BIC(BIC_PkgTmp)) 679 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : "")); 680 681 if (DO_BIC(BIC_GFX_rc6)) 682 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : "")); 683 684 if (DO_BIC(BIC_GFXMHz)) 685 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : "")); 686 687 if (DO_BIC(BIC_Totl_c0)) 688 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : "")); 689 if (DO_BIC(BIC_Any_c0)) 690 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : "")); 691 if (DO_BIC(BIC_GFX_c0)) 692 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : "")); 693 if (DO_BIC(BIC_CPUGFX)) 694 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : "")); 695 696 if (DO_BIC(BIC_Pkgpc2)) 697 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : "")); 698 if (DO_BIC(BIC_Pkgpc3)) 699 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : "")); 700 if (DO_BIC(BIC_Pkgpc6)) 701 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : "")); 702 if (DO_BIC(BIC_Pkgpc7)) 703 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : "")); 704 if (DO_BIC(BIC_Pkgpc8)) 705 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : "")); 706 if (DO_BIC(BIC_Pkgpc9)) 707 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : "")); 708 if (DO_BIC(BIC_Pkgpc10)) 709 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : "")); 710 if (DO_BIC(BIC_CPU_LPI)) 711 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : "")); 712 if (DO_BIC(BIC_SYS_LPI)) 713 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : "")); 714 715 if (do_rapl && !rapl_joules) { 716 if (DO_BIC(BIC_PkgWatt)) 717 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : "")); 718 if (DO_BIC(BIC_CorWatt)) 719 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : "")); 720 if (DO_BIC(BIC_GFXWatt)) 721 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : "")); 722 if (DO_BIC(BIC_RAMWatt)) 723 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : "")); 724 if (DO_BIC(BIC_PKG__)) 725 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 726 if (DO_BIC(BIC_RAM__)) 727 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 728 } else if (do_rapl && rapl_joules) { 729 if (DO_BIC(BIC_Pkg_J)) 730 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : "")); 731 if (DO_BIC(BIC_Cor_J)) 732 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : "")); 733 if (DO_BIC(BIC_GFX_J)) 734 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : "")); 735 if (DO_BIC(BIC_RAM_J)) 736 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : "")); 737 if (DO_BIC(BIC_PKG__)) 738 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : "")); 739 if (DO_BIC(BIC_RAM__)) 740 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : "")); 741 } 742 for (mp = sys.pp; mp; mp = mp->next) { 743 if (mp->format == FORMAT_RAW) { 744 if (mp->width == 64) 745 outp += sprintf(outp, "%s%18.18s", delim, mp->name); 746 else 747 outp += sprintf(outp, "%s%10.10s", delim, mp->name); 748 } else { 749 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 750 outp += sprintf(outp, "%s%8s", delim, mp->name); 751 else 752 outp += sprintf(outp, "%s%s", delim, mp->name); 753 } 754 } 755 756 outp += sprintf(outp, "\n"); 757 } 758 759 int dump_counters(struct thread_data *t, struct core_data *c, 760 struct pkg_data *p) 761 { 762 int i; 763 struct msr_counter *mp; 764 765 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); 766 767 if (t) { 768 outp += sprintf(outp, "CPU: %d flags 0x%x\n", 769 t->cpu_id, t->flags); 770 outp += sprintf(outp, "TSC: %016llX\n", t->tsc); 771 outp += sprintf(outp, "aperf: %016llX\n", t->aperf); 772 outp += sprintf(outp, "mperf: %016llX\n", t->mperf); 773 outp += sprintf(outp, "c1: %016llX\n", t->c1); 774 775 if (DO_BIC(BIC_IRQ)) 776 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count); 777 if (DO_BIC(BIC_SMI)) 778 outp += sprintf(outp, "SMI: %d\n", t->smi_count); 779 780 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 781 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", 782 i, mp->msr_num, t->counter[i]); 783 } 784 } 785 786 if (c) { 787 outp += sprintf(outp, "core: %d\n", c->core_id); 788 outp += sprintf(outp, "c3: %016llX\n", c->c3); 789 outp += sprintf(outp, "c6: %016llX\n", c->c6); 790 outp += sprintf(outp, "c7: %016llX\n", c->c7); 791 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); 792 793 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 794 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", 795 i, mp->msr_num, c->counter[i]); 796 } 797 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us); 798 } 799 800 if (p) { 801 outp += sprintf(outp, "package: %d\n", p->package_id); 802 803 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); 804 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); 805 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); 806 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); 807 808 outp += sprintf(outp, "pc2: %016llX\n", p->pc2); 809 if (DO_BIC(BIC_Pkgpc3)) 810 outp += sprintf(outp, "pc3: %016llX\n", p->pc3); 811 if (DO_BIC(BIC_Pkgpc6)) 812 outp += sprintf(outp, "pc6: %016llX\n", p->pc6); 813 if (DO_BIC(BIC_Pkgpc7)) 814 outp += sprintf(outp, "pc7: %016llX\n", p->pc7); 815 outp += sprintf(outp, "pc8: %016llX\n", p->pc8); 816 outp += sprintf(outp, "pc9: %016llX\n", p->pc9); 817 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 818 outp += sprintf(outp, "pc10: %016llX\n", p->pc10); 819 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi); 820 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi); 821 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg); 822 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores); 823 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx); 824 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram); 825 outp += sprintf(outp, "Throttle PKG: %0X\n", 826 p->rapl_pkg_perf_status); 827 outp += sprintf(outp, "Throttle RAM: %0X\n", 828 p->rapl_dram_perf_status); 829 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); 830 831 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 832 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", 833 i, mp->msr_num, p->counter[i]); 834 } 835 } 836 837 outp += sprintf(outp, "\n"); 838 839 return 0; 840 } 841 842 /* 843 * column formatting convention & formats 844 */ 845 int format_counters(struct thread_data *t, struct core_data *c, 846 struct pkg_data *p) 847 { 848 double interval_float, tsc; 849 char *fmt8; 850 int i; 851 struct msr_counter *mp; 852 char *delim = "\t"; 853 int printed = 0; 854 855 /* if showing only 1st thread in core and this isn't one, bail out */ 856 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 857 return 0; 858 859 /* if showing only 1st thread in pkg and this isn't one, bail out */ 860 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 861 return 0; 862 863 /*if not summary line and --cpu is used */ 864 if ((t != &average.threads) && 865 (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset))) 866 return 0; 867 868 if (DO_BIC(BIC_USEC)) { 869 /* on each row, print how many usec each timestamp took to gather */ 870 struct timeval tv; 871 872 timersub(&t->tv_end, &t->tv_begin, &tv); 873 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec); 874 } 875 876 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */ 877 if (DO_BIC(BIC_TOD)) 878 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec); 879 880 interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0; 881 882 tsc = t->tsc * tsc_tweak; 883 884 /* topo columns, print blanks on 1st (average) line */ 885 if (t == &average.threads) { 886 if (DO_BIC(BIC_Package)) 887 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 888 if (DO_BIC(BIC_Node)) 889 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 890 if (DO_BIC(BIC_Core)) 891 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 892 if (DO_BIC(BIC_CPU)) 893 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 894 if (DO_BIC(BIC_APIC)) 895 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 896 if (DO_BIC(BIC_X2APIC)) 897 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 898 } else { 899 if (DO_BIC(BIC_Package)) { 900 if (p) 901 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id); 902 else 903 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 904 } 905 if (DO_BIC(BIC_Node)) { 906 if (t) 907 outp += sprintf(outp, "%s%d", 908 (printed++ ? delim : ""), 909 cpus[t->cpu_id].physical_node_id); 910 else 911 outp += sprintf(outp, "%s-", 912 (printed++ ? delim : "")); 913 } 914 if (DO_BIC(BIC_Core)) { 915 if (c) 916 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id); 917 else 918 outp += sprintf(outp, "%s-", (printed++ ? delim : "")); 919 } 920 if (DO_BIC(BIC_CPU)) 921 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id); 922 if (DO_BIC(BIC_APIC)) 923 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id); 924 if (DO_BIC(BIC_X2APIC)) 925 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id); 926 } 927 928 if (DO_BIC(BIC_Avg_MHz)) 929 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 930 1.0 / units * t->aperf / interval_float); 931 932 if (DO_BIC(BIC_Busy)) 933 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf/tsc); 934 935 if (DO_BIC(BIC_Bzy_MHz)) { 936 if (has_base_hz) 937 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf); 938 else 939 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 940 tsc / units * t->aperf / t->mperf / interval_float); 941 } 942 943 if (DO_BIC(BIC_TSC_MHz)) 944 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc/units/interval_float); 945 946 /* IRQ */ 947 if (DO_BIC(BIC_IRQ)) { 948 if (sums_need_wide_columns) 949 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count); 950 else 951 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count); 952 } 953 954 /* SMI */ 955 if (DO_BIC(BIC_SMI)) 956 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count); 957 958 /* Added counters */ 959 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 960 if (mp->format == FORMAT_RAW) { 961 if (mp->width == 32) 962 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) t->counter[i]); 963 else 964 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]); 965 } else if (mp->format == FORMAT_DELTA) { 966 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 967 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]); 968 else 969 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]); 970 } else if (mp->format == FORMAT_PERCENT) { 971 if (mp->type == COUNTER_USEC) 972 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), t->counter[i]/interval_float/10000); 973 else 974 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i]/tsc); 975 } 976 } 977 978 /* C1 */ 979 if (DO_BIC(BIC_CPU_c1)) 980 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1/tsc); 981 982 983 /* print per-core data only for 1st thread in core */ 984 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 985 goto done; 986 987 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates && !do_cnl_cstates) 988 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3/tsc); 989 if (DO_BIC(BIC_CPU_c6)) 990 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6/tsc); 991 if (DO_BIC(BIC_CPU_c7)) 992 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7/tsc); 993 994 /* Mod%c6 */ 995 if (DO_BIC(BIC_Mod_c6)) 996 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc); 997 998 if (DO_BIC(BIC_CoreTmp)) 999 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c); 1000 1001 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1002 if (mp->format == FORMAT_RAW) { 1003 if (mp->width == 32) 1004 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) c->counter[i]); 1005 else 1006 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]); 1007 } else if (mp->format == FORMAT_DELTA) { 1008 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1009 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]); 1010 else 1011 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]); 1012 } else if (mp->format == FORMAT_PERCENT) { 1013 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i]/tsc); 1014 } 1015 } 1016 1017 /* print per-package data only for 1st core in package */ 1018 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1019 goto done; 1020 1021 /* PkgTmp */ 1022 if (DO_BIC(BIC_PkgTmp)) 1023 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c); 1024 1025 /* GFXrc6 */ 1026 if (DO_BIC(BIC_GFX_rc6)) { 1027 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */ 1028 outp += sprintf(outp, "%s**.**", (printed++ ? delim : "")); 1029 } else { 1030 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1031 p->gfx_rc6_ms / 10.0 / interval_float); 1032 } 1033 } 1034 1035 /* GFXMHz */ 1036 if (DO_BIC(BIC_GFXMHz)) 1037 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz); 1038 1039 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ 1040 if (DO_BIC(BIC_Totl_c0)) 1041 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0/tsc); 1042 if (DO_BIC(BIC_Any_c0)) 1043 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0/tsc); 1044 if (DO_BIC(BIC_GFX_c0)) 1045 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0/tsc); 1046 if (DO_BIC(BIC_CPUGFX)) 1047 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0/tsc); 1048 1049 if (DO_BIC(BIC_Pkgpc2)) 1050 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2/tsc); 1051 if (DO_BIC(BIC_Pkgpc3)) 1052 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3/tsc); 1053 if (DO_BIC(BIC_Pkgpc6)) 1054 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6/tsc); 1055 if (DO_BIC(BIC_Pkgpc7)) 1056 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7/tsc); 1057 if (DO_BIC(BIC_Pkgpc8)) 1058 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8/tsc); 1059 if (DO_BIC(BIC_Pkgpc9)) 1060 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9/tsc); 1061 if (DO_BIC(BIC_Pkgpc10)) 1062 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10/tsc); 1063 1064 if (DO_BIC(BIC_CPU_LPI)) 1065 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float); 1066 if (DO_BIC(BIC_SYS_LPI)) 1067 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float); 1068 1069 /* 1070 * If measurement interval exceeds minimum RAPL Joule Counter range, 1071 * indicate that results are suspect by printing "**" in fraction place. 1072 */ 1073 if (interval_float < rapl_joule_counter_range) 1074 fmt8 = "%s%.2f"; 1075 else 1076 fmt8 = "%6.0f**"; 1077 1078 if (DO_BIC(BIC_PkgWatt)) 1079 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float); 1080 if (DO_BIC(BIC_CorWatt)) 1081 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float); 1082 if (DO_BIC(BIC_GFXWatt)) 1083 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float); 1084 if (DO_BIC(BIC_RAMWatt)) 1085 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units / interval_float); 1086 if (DO_BIC(BIC_Pkg_J)) 1087 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units); 1088 if (DO_BIC(BIC_Cor_J)) 1089 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units); 1090 if (DO_BIC(BIC_GFX_J)) 1091 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units); 1092 if (DO_BIC(BIC_RAM_J)) 1093 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units); 1094 if (DO_BIC(BIC_PKG__)) 1095 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); 1096 if (DO_BIC(BIC_RAM__)) 1097 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); 1098 1099 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1100 if (mp->format == FORMAT_RAW) { 1101 if (mp->width == 32) 1102 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) p->counter[i]); 1103 else 1104 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]); 1105 } else if (mp->format == FORMAT_DELTA) { 1106 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns) 1107 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]); 1108 else 1109 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]); 1110 } else if (mp->format == FORMAT_PERCENT) { 1111 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i]/tsc); 1112 } 1113 } 1114 1115 done: 1116 if (*(outp - 1) != '\n') 1117 outp += sprintf(outp, "\n"); 1118 1119 return 0; 1120 } 1121 1122 void flush_output_stdout(void) 1123 { 1124 FILE *filep; 1125 1126 if (outf == stderr) 1127 filep = stdout; 1128 else 1129 filep = outf; 1130 1131 fputs(output_buffer, filep); 1132 fflush(filep); 1133 1134 outp = output_buffer; 1135 } 1136 void flush_output_stderr(void) 1137 { 1138 fputs(output_buffer, outf); 1139 fflush(outf); 1140 outp = output_buffer; 1141 } 1142 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1143 { 1144 static int printed; 1145 1146 if (!printed || !summary_only) 1147 print_header("\t"); 1148 1149 if (topo.num_cpus > 1) 1150 format_counters(&average.threads, &average.cores, 1151 &average.packages); 1152 1153 printed = 1; 1154 1155 if (summary_only) 1156 return; 1157 1158 for_all_cpus(format_counters, t, c, p); 1159 } 1160 1161 #define DELTA_WRAP32(new, old) \ 1162 if (new > old) { \ 1163 old = new - old; \ 1164 } else { \ 1165 old = 0x100000000 + new - old; \ 1166 } 1167 1168 int 1169 delta_package(struct pkg_data *new, struct pkg_data *old) 1170 { 1171 int i; 1172 struct msr_counter *mp; 1173 1174 1175 if (DO_BIC(BIC_Totl_c0)) 1176 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; 1177 if (DO_BIC(BIC_Any_c0)) 1178 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; 1179 if (DO_BIC(BIC_GFX_c0)) 1180 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; 1181 if (DO_BIC(BIC_CPUGFX)) 1182 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; 1183 1184 old->pc2 = new->pc2 - old->pc2; 1185 if (DO_BIC(BIC_Pkgpc3)) 1186 old->pc3 = new->pc3 - old->pc3; 1187 if (DO_BIC(BIC_Pkgpc6)) 1188 old->pc6 = new->pc6 - old->pc6; 1189 if (DO_BIC(BIC_Pkgpc7)) 1190 old->pc7 = new->pc7 - old->pc7; 1191 old->pc8 = new->pc8 - old->pc8; 1192 old->pc9 = new->pc9 - old->pc9; 1193 old->pc10 = new->pc10 - old->pc10; 1194 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi; 1195 old->sys_lpi = new->sys_lpi - old->sys_lpi; 1196 old->pkg_temp_c = new->pkg_temp_c; 1197 1198 /* flag an error when rc6 counter resets/wraps */ 1199 if (old->gfx_rc6_ms > new->gfx_rc6_ms) 1200 old->gfx_rc6_ms = -1; 1201 else 1202 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; 1203 1204 old->gfx_mhz = new->gfx_mhz; 1205 1206 DELTA_WRAP32(new->energy_pkg, old->energy_pkg); 1207 DELTA_WRAP32(new->energy_cores, old->energy_cores); 1208 DELTA_WRAP32(new->energy_gfx, old->energy_gfx); 1209 DELTA_WRAP32(new->energy_dram, old->energy_dram); 1210 DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status); 1211 DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status); 1212 1213 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1214 if (mp->format == FORMAT_RAW) 1215 old->counter[i] = new->counter[i]; 1216 else 1217 old->counter[i] = new->counter[i] - old->counter[i]; 1218 } 1219 1220 return 0; 1221 } 1222 1223 void 1224 delta_core(struct core_data *new, struct core_data *old) 1225 { 1226 int i; 1227 struct msr_counter *mp; 1228 1229 old->c3 = new->c3 - old->c3; 1230 old->c6 = new->c6 - old->c6; 1231 old->c7 = new->c7 - old->c7; 1232 old->core_temp_c = new->core_temp_c; 1233 old->mc6_us = new->mc6_us - old->mc6_us; 1234 1235 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1236 if (mp->format == FORMAT_RAW) 1237 old->counter[i] = new->counter[i]; 1238 else 1239 old->counter[i] = new->counter[i] - old->counter[i]; 1240 } 1241 } 1242 1243 /* 1244 * old = new - old 1245 */ 1246 int 1247 delta_thread(struct thread_data *new, struct thread_data *old, 1248 struct core_data *core_delta) 1249 { 1250 int i; 1251 struct msr_counter *mp; 1252 1253 /* we run cpuid just the 1st time, copy the results */ 1254 if (DO_BIC(BIC_APIC)) 1255 new->apic_id = old->apic_id; 1256 if (DO_BIC(BIC_X2APIC)) 1257 new->x2apic_id = old->x2apic_id; 1258 1259 /* 1260 * the timestamps from start of measurement interval are in "old" 1261 * the timestamp from end of measurement interval are in "new" 1262 * over-write old w/ new so we can print end of interval values 1263 */ 1264 1265 old->tv_begin = new->tv_begin; 1266 old->tv_end = new->tv_end; 1267 1268 old->tsc = new->tsc - old->tsc; 1269 1270 /* check for TSC < 1 Mcycles over interval */ 1271 if (old->tsc < (1000 * 1000)) 1272 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" 1273 "You can disable all c-states by booting with \"idle=poll\"\n" 1274 "or just the deep ones with \"processor.max_cstate=1\""); 1275 1276 old->c1 = new->c1 - old->c1; 1277 1278 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) { 1279 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { 1280 old->aperf = new->aperf - old->aperf; 1281 old->mperf = new->mperf - old->mperf; 1282 } else { 1283 return -1; 1284 } 1285 } 1286 1287 1288 if (use_c1_residency_msr) { 1289 /* 1290 * Some models have a dedicated C1 residency MSR, 1291 * which should be more accurate than the derivation below. 1292 */ 1293 } else { 1294 /* 1295 * As counter collection is not atomic, 1296 * it is possible for mperf's non-halted cycles + idle states 1297 * to exceed TSC's all cycles: show c1 = 0% in that case. 1298 */ 1299 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak)) 1300 old->c1 = 0; 1301 else { 1302 /* normal case, derive c1 */ 1303 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3 1304 - core_delta->c6 - core_delta->c7; 1305 } 1306 } 1307 1308 if (old->mperf == 0) { 1309 if (debug > 1) 1310 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); 1311 old->mperf = 1; /* divide by 0 protection */ 1312 } 1313 1314 if (DO_BIC(BIC_IRQ)) 1315 old->irq_count = new->irq_count - old->irq_count; 1316 1317 if (DO_BIC(BIC_SMI)) 1318 old->smi_count = new->smi_count - old->smi_count; 1319 1320 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1321 if (mp->format == FORMAT_RAW) 1322 old->counter[i] = new->counter[i]; 1323 else 1324 old->counter[i] = new->counter[i] - old->counter[i]; 1325 } 1326 return 0; 1327 } 1328 1329 int delta_cpu(struct thread_data *t, struct core_data *c, 1330 struct pkg_data *p, struct thread_data *t2, 1331 struct core_data *c2, struct pkg_data *p2) 1332 { 1333 int retval = 0; 1334 1335 /* calculate core delta only for 1st thread in core */ 1336 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) 1337 delta_core(c, c2); 1338 1339 /* always calculate thread delta */ 1340 retval = delta_thread(t, t2, c2); /* c2 is core delta */ 1341 if (retval) 1342 return retval; 1343 1344 /* calculate package delta only for 1st core in package */ 1345 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) 1346 retval = delta_package(p, p2); 1347 1348 return retval; 1349 } 1350 1351 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1352 { 1353 int i; 1354 struct msr_counter *mp; 1355 1356 t->tv_begin.tv_sec = 0; 1357 t->tv_begin.tv_usec = 0; 1358 t->tv_end.tv_sec = 0; 1359 t->tv_end.tv_usec = 0; 1360 1361 t->tsc = 0; 1362 t->aperf = 0; 1363 t->mperf = 0; 1364 t->c1 = 0; 1365 1366 t->irq_count = 0; 1367 t->smi_count = 0; 1368 1369 /* tells format_counters to dump all fields from this set */ 1370 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; 1371 1372 c->c3 = 0; 1373 c->c6 = 0; 1374 c->c7 = 0; 1375 c->mc6_us = 0; 1376 c->core_temp_c = 0; 1377 1378 p->pkg_wtd_core_c0 = 0; 1379 p->pkg_any_core_c0 = 0; 1380 p->pkg_any_gfxe_c0 = 0; 1381 p->pkg_both_core_gfxe_c0 = 0; 1382 1383 p->pc2 = 0; 1384 if (DO_BIC(BIC_Pkgpc3)) 1385 p->pc3 = 0; 1386 if (DO_BIC(BIC_Pkgpc6)) 1387 p->pc6 = 0; 1388 if (DO_BIC(BIC_Pkgpc7)) 1389 p->pc7 = 0; 1390 p->pc8 = 0; 1391 p->pc9 = 0; 1392 p->pc10 = 0; 1393 p->cpu_lpi = 0; 1394 p->sys_lpi = 0; 1395 1396 p->energy_pkg = 0; 1397 p->energy_dram = 0; 1398 p->energy_cores = 0; 1399 p->energy_gfx = 0; 1400 p->rapl_pkg_perf_status = 0; 1401 p->rapl_dram_perf_status = 0; 1402 p->pkg_temp_c = 0; 1403 1404 p->gfx_rc6_ms = 0; 1405 p->gfx_mhz = 0; 1406 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) 1407 t->counter[i] = 0; 1408 1409 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) 1410 c->counter[i] = 0; 1411 1412 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) 1413 p->counter[i] = 0; 1414 } 1415 int sum_counters(struct thread_data *t, struct core_data *c, 1416 struct pkg_data *p) 1417 { 1418 int i; 1419 struct msr_counter *mp; 1420 1421 /* copy un-changing apic_id's */ 1422 if (DO_BIC(BIC_APIC)) 1423 average.threads.apic_id = t->apic_id; 1424 if (DO_BIC(BIC_X2APIC)) 1425 average.threads.x2apic_id = t->x2apic_id; 1426 1427 /* remember first tv_begin */ 1428 if (average.threads.tv_begin.tv_sec == 0) 1429 average.threads.tv_begin = t->tv_begin; 1430 1431 /* remember last tv_end */ 1432 average.threads.tv_end = t->tv_end; 1433 1434 average.threads.tsc += t->tsc; 1435 average.threads.aperf += t->aperf; 1436 average.threads.mperf += t->mperf; 1437 average.threads.c1 += t->c1; 1438 1439 average.threads.irq_count += t->irq_count; 1440 average.threads.smi_count += t->smi_count; 1441 1442 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1443 if (mp->format == FORMAT_RAW) 1444 continue; 1445 average.threads.counter[i] += t->counter[i]; 1446 } 1447 1448 /* sum per-core values only for 1st thread in core */ 1449 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1450 return 0; 1451 1452 average.cores.c3 += c->c3; 1453 average.cores.c6 += c->c6; 1454 average.cores.c7 += c->c7; 1455 average.cores.mc6_us += c->mc6_us; 1456 1457 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); 1458 1459 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1460 if (mp->format == FORMAT_RAW) 1461 continue; 1462 average.cores.counter[i] += c->counter[i]; 1463 } 1464 1465 /* sum per-pkg values only for 1st core in pkg */ 1466 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1467 return 0; 1468 1469 if (DO_BIC(BIC_Totl_c0)) 1470 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; 1471 if (DO_BIC(BIC_Any_c0)) 1472 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; 1473 if (DO_BIC(BIC_GFX_c0)) 1474 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; 1475 if (DO_BIC(BIC_CPUGFX)) 1476 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; 1477 1478 average.packages.pc2 += p->pc2; 1479 if (DO_BIC(BIC_Pkgpc3)) 1480 average.packages.pc3 += p->pc3; 1481 if (DO_BIC(BIC_Pkgpc6)) 1482 average.packages.pc6 += p->pc6; 1483 if (DO_BIC(BIC_Pkgpc7)) 1484 average.packages.pc7 += p->pc7; 1485 average.packages.pc8 += p->pc8; 1486 average.packages.pc9 += p->pc9; 1487 average.packages.pc10 += p->pc10; 1488 1489 average.packages.cpu_lpi = p->cpu_lpi; 1490 average.packages.sys_lpi = p->sys_lpi; 1491 1492 average.packages.energy_pkg += p->energy_pkg; 1493 average.packages.energy_dram += p->energy_dram; 1494 average.packages.energy_cores += p->energy_cores; 1495 average.packages.energy_gfx += p->energy_gfx; 1496 1497 average.packages.gfx_rc6_ms = p->gfx_rc6_ms; 1498 average.packages.gfx_mhz = p->gfx_mhz; 1499 1500 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); 1501 1502 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; 1503 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; 1504 1505 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1506 if (mp->format == FORMAT_RAW) 1507 continue; 1508 average.packages.counter[i] += p->counter[i]; 1509 } 1510 return 0; 1511 } 1512 /* 1513 * sum the counters for all cpus in the system 1514 * compute the weighted average 1515 */ 1516 void compute_average(struct thread_data *t, struct core_data *c, 1517 struct pkg_data *p) 1518 { 1519 int i; 1520 struct msr_counter *mp; 1521 1522 clear_counters(&average.threads, &average.cores, &average.packages); 1523 1524 for_all_cpus(sum_counters, t, c, p); 1525 1526 average.threads.tsc /= topo.num_cpus; 1527 average.threads.aperf /= topo.num_cpus; 1528 average.threads.mperf /= topo.num_cpus; 1529 average.threads.c1 /= topo.num_cpus; 1530 1531 if (average.threads.irq_count > 9999999) 1532 sums_need_wide_columns = 1; 1533 1534 average.cores.c3 /= topo.num_cores; 1535 average.cores.c6 /= topo.num_cores; 1536 average.cores.c7 /= topo.num_cores; 1537 average.cores.mc6_us /= topo.num_cores; 1538 1539 if (DO_BIC(BIC_Totl_c0)) 1540 average.packages.pkg_wtd_core_c0 /= topo.num_packages; 1541 if (DO_BIC(BIC_Any_c0)) 1542 average.packages.pkg_any_core_c0 /= topo.num_packages; 1543 if (DO_BIC(BIC_GFX_c0)) 1544 average.packages.pkg_any_gfxe_c0 /= topo.num_packages; 1545 if (DO_BIC(BIC_CPUGFX)) 1546 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages; 1547 1548 average.packages.pc2 /= topo.num_packages; 1549 if (DO_BIC(BIC_Pkgpc3)) 1550 average.packages.pc3 /= topo.num_packages; 1551 if (DO_BIC(BIC_Pkgpc6)) 1552 average.packages.pc6 /= topo.num_packages; 1553 if (DO_BIC(BIC_Pkgpc7)) 1554 average.packages.pc7 /= topo.num_packages; 1555 1556 average.packages.pc8 /= topo.num_packages; 1557 average.packages.pc9 /= topo.num_packages; 1558 average.packages.pc10 /= topo.num_packages; 1559 1560 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1561 if (mp->format == FORMAT_RAW) 1562 continue; 1563 if (mp->type == COUNTER_ITEMS) { 1564 if (average.threads.counter[i] > 9999999) 1565 sums_need_wide_columns = 1; 1566 continue; 1567 } 1568 average.threads.counter[i] /= topo.num_cpus; 1569 } 1570 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1571 if (mp->format == FORMAT_RAW) 1572 continue; 1573 if (mp->type == COUNTER_ITEMS) { 1574 if (average.cores.counter[i] > 9999999) 1575 sums_need_wide_columns = 1; 1576 } 1577 average.cores.counter[i] /= topo.num_cores; 1578 } 1579 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1580 if (mp->format == FORMAT_RAW) 1581 continue; 1582 if (mp->type == COUNTER_ITEMS) { 1583 if (average.packages.counter[i] > 9999999) 1584 sums_need_wide_columns = 1; 1585 } 1586 average.packages.counter[i] /= topo.num_packages; 1587 } 1588 } 1589 1590 static unsigned long long rdtsc(void) 1591 { 1592 unsigned int low, high; 1593 1594 asm volatile("rdtsc" : "=a" (low), "=d" (high)); 1595 1596 return low | ((unsigned long long)high) << 32; 1597 } 1598 1599 /* 1600 * Open a file, and exit on failure 1601 */ 1602 FILE *fopen_or_die(const char *path, const char *mode) 1603 { 1604 FILE *filep = fopen(path, mode); 1605 1606 if (!filep) 1607 err(1, "%s: open failed", path); 1608 return filep; 1609 } 1610 /* 1611 * snapshot_sysfs_counter() 1612 * 1613 * return snapshot of given counter 1614 */ 1615 unsigned long long snapshot_sysfs_counter(char *path) 1616 { 1617 FILE *fp; 1618 int retval; 1619 unsigned long long counter; 1620 1621 fp = fopen_or_die(path, "r"); 1622 1623 retval = fscanf(fp, "%lld", &counter); 1624 if (retval != 1) 1625 err(1, "snapshot_sysfs_counter(%s)", path); 1626 1627 fclose(fp); 1628 1629 return counter; 1630 } 1631 1632 int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp) 1633 { 1634 if (mp->msr_num != 0) { 1635 if (get_msr(cpu, mp->msr_num, counterp)) 1636 return -1; 1637 } else { 1638 char path[128 + PATH_BYTES]; 1639 1640 if (mp->flags & SYSFS_PERCPU) { 1641 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s", 1642 cpu, mp->path); 1643 1644 *counterp = snapshot_sysfs_counter(path); 1645 } else { 1646 *counterp = snapshot_sysfs_counter(mp->path); 1647 } 1648 } 1649 1650 return 0; 1651 } 1652 1653 void get_apic_id(struct thread_data *t) 1654 { 1655 unsigned int eax, ebx, ecx, edx, max_level; 1656 1657 eax = ebx = ecx = edx = 0; 1658 1659 if (!genuine_intel) 1660 return; 1661 1662 __cpuid(0, max_level, ebx, ecx, edx); 1663 1664 __cpuid(1, eax, ebx, ecx, edx); 1665 t->apic_id = (ebx >> 24) & 0xf; 1666 1667 if (max_level < 0xb) 1668 return; 1669 1670 if (!DO_BIC(BIC_X2APIC)) 1671 return; 1672 1673 ecx = 0; 1674 __cpuid(0xb, eax, ebx, ecx, edx); 1675 t->x2apic_id = edx; 1676 1677 if (debug && (t->apic_id != t->x2apic_id)) 1678 fprintf(stderr, "cpu%d: apic 0x%x x2apic 0x%x\n", t->cpu_id, t->apic_id, t->x2apic_id); 1679 } 1680 1681 /* 1682 * get_counters(...) 1683 * migrate to cpu 1684 * acquire and record local counters for that cpu 1685 */ 1686 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) 1687 { 1688 int cpu = t->cpu_id; 1689 unsigned long long msr; 1690 int aperf_mperf_retry_count = 0; 1691 struct msr_counter *mp; 1692 int i; 1693 1694 gettimeofday(&t->tv_begin, (struct timezone *)NULL); 1695 1696 if (cpu_migrate(cpu)) { 1697 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 1698 return -1; 1699 } 1700 1701 if (first_counter_read) 1702 get_apic_id(t); 1703 retry: 1704 t->tsc = rdtsc(); /* we are running on local CPU of interest */ 1705 1706 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) { 1707 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; 1708 1709 /* 1710 * The TSC, APERF and MPERF must be read together for 1711 * APERF/MPERF and MPERF/TSC to give accurate results. 1712 * 1713 * Unfortunately, APERF and MPERF are read by 1714 * individual system call, so delays may occur 1715 * between them. If the time to read them 1716 * varies by a large amount, we re-read them. 1717 */ 1718 1719 /* 1720 * This initial dummy APERF read has been seen to 1721 * reduce jitter in the subsequent reads. 1722 */ 1723 1724 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1725 return -3; 1726 1727 t->tsc = rdtsc(); /* re-read close to APERF */ 1728 1729 tsc_before = t->tsc; 1730 1731 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) 1732 return -3; 1733 1734 tsc_between = rdtsc(); 1735 1736 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) 1737 return -4; 1738 1739 tsc_after = rdtsc(); 1740 1741 aperf_time = tsc_between - tsc_before; 1742 mperf_time = tsc_after - tsc_between; 1743 1744 /* 1745 * If the system call latency to read APERF and MPERF 1746 * differ by more than 2x, then try again. 1747 */ 1748 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { 1749 aperf_mperf_retry_count++; 1750 if (aperf_mperf_retry_count < 5) 1751 goto retry; 1752 else 1753 warnx("cpu%d jitter %lld %lld", 1754 cpu, aperf_time, mperf_time); 1755 } 1756 aperf_mperf_retry_count = 0; 1757 1758 t->aperf = t->aperf * aperf_mperf_multiplier; 1759 t->mperf = t->mperf * aperf_mperf_multiplier; 1760 } 1761 1762 if (DO_BIC(BIC_IRQ)) 1763 t->irq_count = irqs_per_cpu[cpu]; 1764 if (DO_BIC(BIC_SMI)) { 1765 if (get_msr(cpu, MSR_SMI_COUNT, &msr)) 1766 return -5; 1767 t->smi_count = msr & 0xFFFFFFFF; 1768 } 1769 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) { 1770 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) 1771 return -6; 1772 } 1773 1774 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) { 1775 if (get_mp(cpu, mp, &t->counter[i])) 1776 return -10; 1777 } 1778 1779 /* collect core counters only for 1st thread in core */ 1780 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 1781 goto done; 1782 1783 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates && !do_cnl_cstates) { 1784 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) 1785 return -6; 1786 } 1787 1788 if (DO_BIC(BIC_CPU_c6) && !do_knl_cstates) { 1789 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) 1790 return -7; 1791 } else if (do_knl_cstates) { 1792 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) 1793 return -7; 1794 } 1795 1796 if (DO_BIC(BIC_CPU_c7)) 1797 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) 1798 return -8; 1799 1800 if (DO_BIC(BIC_Mod_c6)) 1801 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us)) 1802 return -8; 1803 1804 if (DO_BIC(BIC_CoreTmp)) { 1805 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 1806 return -9; 1807 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1808 } 1809 1810 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) { 1811 if (get_mp(cpu, mp, &c->counter[i])) 1812 return -10; 1813 } 1814 1815 /* collect package counters only for 1st core in package */ 1816 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 1817 goto done; 1818 1819 if (DO_BIC(BIC_Totl_c0)) { 1820 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) 1821 return -10; 1822 } 1823 if (DO_BIC(BIC_Any_c0)) { 1824 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) 1825 return -11; 1826 } 1827 if (DO_BIC(BIC_GFX_c0)) { 1828 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) 1829 return -12; 1830 } 1831 if (DO_BIC(BIC_CPUGFX)) { 1832 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) 1833 return -13; 1834 } 1835 if (DO_BIC(BIC_Pkgpc3)) 1836 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) 1837 return -9; 1838 if (DO_BIC(BIC_Pkgpc6)) { 1839 if (do_slm_cstates) { 1840 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6)) 1841 return -10; 1842 } else { 1843 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) 1844 return -10; 1845 } 1846 } 1847 1848 if (DO_BIC(BIC_Pkgpc2)) 1849 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) 1850 return -11; 1851 if (DO_BIC(BIC_Pkgpc7)) 1852 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) 1853 return -12; 1854 if (DO_BIC(BIC_Pkgpc8)) 1855 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) 1856 return -13; 1857 if (DO_BIC(BIC_Pkgpc9)) 1858 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) 1859 return -13; 1860 if (DO_BIC(BIC_Pkgpc10)) 1861 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) 1862 return -13; 1863 1864 if (DO_BIC(BIC_CPU_LPI)) 1865 p->cpu_lpi = cpuidle_cur_cpu_lpi_us; 1866 if (DO_BIC(BIC_SYS_LPI)) 1867 p->sys_lpi = cpuidle_cur_sys_lpi_us; 1868 1869 if (do_rapl & RAPL_PKG) { 1870 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr)) 1871 return -13; 1872 p->energy_pkg = msr & 0xFFFFFFFF; 1873 } 1874 if (do_rapl & RAPL_CORES_ENERGY_STATUS) { 1875 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr)) 1876 return -14; 1877 p->energy_cores = msr & 0xFFFFFFFF; 1878 } 1879 if (do_rapl & RAPL_DRAM) { 1880 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) 1881 return -15; 1882 p->energy_dram = msr & 0xFFFFFFFF; 1883 } 1884 if (do_rapl & RAPL_GFX) { 1885 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr)) 1886 return -16; 1887 p->energy_gfx = msr & 0xFFFFFFFF; 1888 } 1889 if (do_rapl & RAPL_PKG_PERF_STATUS) { 1890 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr)) 1891 return -16; 1892 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF; 1893 } 1894 if (do_rapl & RAPL_DRAM_PERF_STATUS) { 1895 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr)) 1896 return -16; 1897 p->rapl_dram_perf_status = msr & 0xFFFFFFFF; 1898 } 1899 if (DO_BIC(BIC_PkgTmp)) { 1900 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 1901 return -17; 1902 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); 1903 } 1904 1905 if (DO_BIC(BIC_GFX_rc6)) 1906 p->gfx_rc6_ms = gfx_cur_rc6_ms; 1907 1908 if (DO_BIC(BIC_GFXMHz)) 1909 p->gfx_mhz = gfx_cur_mhz; 1910 1911 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) { 1912 if (get_mp(cpu, mp, &p->counter[i])) 1913 return -10; 1914 } 1915 done: 1916 gettimeofday(&t->tv_end, (struct timezone *)NULL); 1917 1918 return 0; 1919 } 1920 1921 /* 1922 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: 1923 * If you change the values, note they are used both in comparisons 1924 * (>= PCL__7) and to index pkg_cstate_limit_strings[]. 1925 */ 1926 1927 #define PCLUKN 0 /* Unknown */ 1928 #define PCLRSV 1 /* Reserved */ 1929 #define PCL__0 2 /* PC0 */ 1930 #define PCL__1 3 /* PC1 */ 1931 #define PCL__2 4 /* PC2 */ 1932 #define PCL__3 5 /* PC3 */ 1933 #define PCL__4 6 /* PC4 */ 1934 #define PCL__6 7 /* PC6 */ 1935 #define PCL_6N 8 /* PC6 No Retention */ 1936 #define PCL_6R 9 /* PC6 Retention */ 1937 #define PCL__7 10 /* PC7 */ 1938 #define PCL_7S 11 /* PC7 Shrink */ 1939 #define PCL__8 12 /* PC8 */ 1940 #define PCL__9 13 /* PC9 */ 1941 #define PCLUNL 14 /* Unlimited */ 1942 1943 int pkg_cstate_limit = PCLUKN; 1944 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", 1945 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"}; 1946 1947 int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1948 int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1949 int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1950 int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7}; 1951 int amt_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1952 int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1953 int bxt_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1954 int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; 1955 1956 1957 static void 1958 calculate_tsc_tweak() 1959 { 1960 tsc_tweak = base_hz / tsc_hz; 1961 } 1962 1963 static void 1964 dump_nhm_platform_info(void) 1965 { 1966 unsigned long long msr; 1967 unsigned int ratio; 1968 1969 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 1970 1971 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); 1972 1973 ratio = (msr >> 40) & 0xFF; 1974 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", 1975 ratio, bclk, ratio * bclk); 1976 1977 ratio = (msr >> 8) & 0xFF; 1978 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", 1979 ratio, bclk, ratio * bclk); 1980 1981 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); 1982 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", 1983 base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); 1984 1985 return; 1986 } 1987 1988 static void 1989 dump_hsw_turbo_ratio_limits(void) 1990 { 1991 unsigned long long msr; 1992 unsigned int ratio; 1993 1994 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); 1995 1996 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); 1997 1998 ratio = (msr >> 8) & 0xFF; 1999 if (ratio) 2000 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", 2001 ratio, bclk, ratio * bclk); 2002 2003 ratio = (msr >> 0) & 0xFF; 2004 if (ratio) 2005 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", 2006 ratio, bclk, ratio * bclk); 2007 return; 2008 } 2009 2010 static void 2011 dump_ivt_turbo_ratio_limits(void) 2012 { 2013 unsigned long long msr; 2014 unsigned int ratio; 2015 2016 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); 2017 2018 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); 2019 2020 ratio = (msr >> 56) & 0xFF; 2021 if (ratio) 2022 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", 2023 ratio, bclk, ratio * bclk); 2024 2025 ratio = (msr >> 48) & 0xFF; 2026 if (ratio) 2027 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", 2028 ratio, bclk, ratio * bclk); 2029 2030 ratio = (msr >> 40) & 0xFF; 2031 if (ratio) 2032 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", 2033 ratio, bclk, ratio * bclk); 2034 2035 ratio = (msr >> 32) & 0xFF; 2036 if (ratio) 2037 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", 2038 ratio, bclk, ratio * bclk); 2039 2040 ratio = (msr >> 24) & 0xFF; 2041 if (ratio) 2042 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", 2043 ratio, bclk, ratio * bclk); 2044 2045 ratio = (msr >> 16) & 0xFF; 2046 if (ratio) 2047 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", 2048 ratio, bclk, ratio * bclk); 2049 2050 ratio = (msr >> 8) & 0xFF; 2051 if (ratio) 2052 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", 2053 ratio, bclk, ratio * bclk); 2054 2055 ratio = (msr >> 0) & 0xFF; 2056 if (ratio) 2057 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", 2058 ratio, bclk, ratio * bclk); 2059 return; 2060 } 2061 int has_turbo_ratio_group_limits(int family, int model) 2062 { 2063 2064 if (!genuine_intel) 2065 return 0; 2066 2067 switch (model) { 2068 case INTEL_FAM6_ATOM_GOLDMONT: 2069 case INTEL_FAM6_SKYLAKE_X: 2070 case INTEL_FAM6_ATOM_DENVERTON: 2071 return 1; 2072 } 2073 return 0; 2074 } 2075 2076 static void 2077 dump_turbo_ratio_limits(int family, int model) 2078 { 2079 unsigned long long msr, core_counts; 2080 unsigned int ratio, group_size; 2081 2082 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2083 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); 2084 2085 if (has_turbo_ratio_group_limits(family, model)) { 2086 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts); 2087 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts); 2088 } else { 2089 core_counts = 0x0807060504030201; 2090 } 2091 2092 ratio = (msr >> 56) & 0xFF; 2093 group_size = (core_counts >> 56) & 0xFF; 2094 if (ratio) 2095 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2096 ratio, bclk, ratio * bclk, group_size); 2097 2098 ratio = (msr >> 48) & 0xFF; 2099 group_size = (core_counts >> 48) & 0xFF; 2100 if (ratio) 2101 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2102 ratio, bclk, ratio * bclk, group_size); 2103 2104 ratio = (msr >> 40) & 0xFF; 2105 group_size = (core_counts >> 40) & 0xFF; 2106 if (ratio) 2107 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2108 ratio, bclk, ratio * bclk, group_size); 2109 2110 ratio = (msr >> 32) & 0xFF; 2111 group_size = (core_counts >> 32) & 0xFF; 2112 if (ratio) 2113 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2114 ratio, bclk, ratio * bclk, group_size); 2115 2116 ratio = (msr >> 24) & 0xFF; 2117 group_size = (core_counts >> 24) & 0xFF; 2118 if (ratio) 2119 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2120 ratio, bclk, ratio * bclk, group_size); 2121 2122 ratio = (msr >> 16) & 0xFF; 2123 group_size = (core_counts >> 16) & 0xFF; 2124 if (ratio) 2125 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2126 ratio, bclk, ratio * bclk, group_size); 2127 2128 ratio = (msr >> 8) & 0xFF; 2129 group_size = (core_counts >> 8) & 0xFF; 2130 if (ratio) 2131 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2132 ratio, bclk, ratio * bclk, group_size); 2133 2134 ratio = (msr >> 0) & 0xFF; 2135 group_size = (core_counts >> 0) & 0xFF; 2136 if (ratio) 2137 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2138 ratio, bclk, ratio * bclk, group_size); 2139 return; 2140 } 2141 2142 static void 2143 dump_atom_turbo_ratio_limits(void) 2144 { 2145 unsigned long long msr; 2146 unsigned int ratio; 2147 2148 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr); 2149 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2150 2151 ratio = (msr >> 0) & 0x3F; 2152 if (ratio) 2153 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", 2154 ratio, bclk, ratio * bclk); 2155 2156 ratio = (msr >> 8) & 0x3F; 2157 if (ratio) 2158 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", 2159 ratio, bclk, ratio * bclk); 2160 2161 ratio = (msr >> 16) & 0x3F; 2162 if (ratio) 2163 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", 2164 ratio, bclk, ratio * bclk); 2165 2166 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr); 2167 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF); 2168 2169 ratio = (msr >> 24) & 0x3F; 2170 if (ratio) 2171 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", 2172 ratio, bclk, ratio * bclk); 2173 2174 ratio = (msr >> 16) & 0x3F; 2175 if (ratio) 2176 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", 2177 ratio, bclk, ratio * bclk); 2178 2179 ratio = (msr >> 8) & 0x3F; 2180 if (ratio) 2181 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", 2182 ratio, bclk, ratio * bclk); 2183 2184 ratio = (msr >> 0) & 0x3F; 2185 if (ratio) 2186 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", 2187 ratio, bclk, ratio * bclk); 2188 } 2189 2190 static void 2191 dump_knl_turbo_ratio_limits(void) 2192 { 2193 const unsigned int buckets_no = 7; 2194 2195 unsigned long long msr; 2196 int delta_cores, delta_ratio; 2197 int i, b_nr; 2198 unsigned int cores[buckets_no]; 2199 unsigned int ratio[buckets_no]; 2200 2201 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); 2202 2203 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", 2204 base_cpu, msr); 2205 2206 /** 2207 * Turbo encoding in KNL is as follows: 2208 * [0] -- Reserved 2209 * [7:1] -- Base value of number of active cores of bucket 1. 2210 * [15:8] -- Base value of freq ratio of bucket 1. 2211 * [20:16] -- +ve delta of number of active cores of bucket 2. 2212 * i.e. active cores of bucket 2 = 2213 * active cores of bucket 1 + delta 2214 * [23:21] -- Negative delta of freq ratio of bucket 2. 2215 * i.e. freq ratio of bucket 2 = 2216 * freq ratio of bucket 1 - delta 2217 * [28:24]-- +ve delta of number of active cores of bucket 3. 2218 * [31:29]-- -ve delta of freq ratio of bucket 3. 2219 * [36:32]-- +ve delta of number of active cores of bucket 4. 2220 * [39:37]-- -ve delta of freq ratio of bucket 4. 2221 * [44:40]-- +ve delta of number of active cores of bucket 5. 2222 * [47:45]-- -ve delta of freq ratio of bucket 5. 2223 * [52:48]-- +ve delta of number of active cores of bucket 6. 2224 * [55:53]-- -ve delta of freq ratio of bucket 6. 2225 * [60:56]-- +ve delta of number of active cores of bucket 7. 2226 * [63:61]-- -ve delta of freq ratio of bucket 7. 2227 */ 2228 2229 b_nr = 0; 2230 cores[b_nr] = (msr & 0xFF) >> 1; 2231 ratio[b_nr] = (msr >> 8) & 0xFF; 2232 2233 for (i = 16; i < 64; i += 8) { 2234 delta_cores = (msr >> i) & 0x1F; 2235 delta_ratio = (msr >> (i + 5)) & 0x7; 2236 2237 cores[b_nr + 1] = cores[b_nr] + delta_cores; 2238 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; 2239 b_nr++; 2240 } 2241 2242 for (i = buckets_no - 1; i >= 0; i--) 2243 if (i > 0 ? ratio[i] != ratio[i - 1] : 1) 2244 fprintf(outf, 2245 "%d * %.1f = %.1f MHz max turbo %d active cores\n", 2246 ratio[i], bclk, ratio[i] * bclk, cores[i]); 2247 } 2248 2249 static void 2250 dump_nhm_cst_cfg(void) 2251 { 2252 unsigned long long msr; 2253 2254 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 2255 2256 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr); 2257 2258 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)", 2259 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", 2260 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", 2261 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", 2262 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", 2263 (msr & (1 << 15)) ? "" : "UN", 2264 (unsigned int)msr & 0xF, 2265 pkg_cstate_limit_strings[pkg_cstate_limit]); 2266 2267 #define AUTOMATIC_CSTATE_CONVERSION (1UL << 16) 2268 if (has_automatic_cstate_conversion) { 2269 fprintf(outf, ", automatic c-state conversion=%s", 2270 (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off"); 2271 } 2272 2273 fprintf(outf, ")\n"); 2274 2275 return; 2276 } 2277 2278 static void 2279 dump_config_tdp(void) 2280 { 2281 unsigned long long msr; 2282 2283 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); 2284 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); 2285 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); 2286 2287 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); 2288 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); 2289 if (msr) { 2290 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2291 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2292 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2293 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); 2294 } 2295 fprintf(outf, ")\n"); 2296 2297 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); 2298 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); 2299 if (msr) { 2300 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); 2301 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); 2302 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); 2303 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); 2304 } 2305 fprintf(outf, ")\n"); 2306 2307 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); 2308 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); 2309 if ((msr) & 0x3) 2310 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); 2311 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2312 fprintf(outf, ")\n"); 2313 2314 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); 2315 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); 2316 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); 2317 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); 2318 fprintf(outf, ")\n"); 2319 } 2320 2321 unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 }; 2322 2323 void print_irtl(void) 2324 { 2325 unsigned long long msr; 2326 2327 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr); 2328 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr); 2329 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2330 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2331 2332 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr); 2333 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr); 2334 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2335 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2336 2337 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr); 2338 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr); 2339 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2340 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2341 2342 if (!do_irtl_hsw) 2343 return; 2344 2345 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr); 2346 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr); 2347 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2348 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2349 2350 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr); 2351 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr); 2352 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2353 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2354 2355 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr); 2356 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr); 2357 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT", 2358 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]); 2359 2360 } 2361 void free_fd_percpu(void) 2362 { 2363 int i; 2364 2365 for (i = 0; i < topo.max_cpu_num + 1; ++i) { 2366 if (fd_percpu[i] != 0) 2367 close(fd_percpu[i]); 2368 } 2369 2370 free(fd_percpu); 2371 } 2372 2373 void free_all_buffers(void) 2374 { 2375 int i; 2376 2377 CPU_FREE(cpu_present_set); 2378 cpu_present_set = NULL; 2379 cpu_present_setsize = 0; 2380 2381 CPU_FREE(cpu_affinity_set); 2382 cpu_affinity_set = NULL; 2383 cpu_affinity_setsize = 0; 2384 2385 free(thread_even); 2386 free(core_even); 2387 free(package_even); 2388 2389 thread_even = NULL; 2390 core_even = NULL; 2391 package_even = NULL; 2392 2393 free(thread_odd); 2394 free(core_odd); 2395 free(package_odd); 2396 2397 thread_odd = NULL; 2398 core_odd = NULL; 2399 package_odd = NULL; 2400 2401 free(output_buffer); 2402 output_buffer = NULL; 2403 outp = NULL; 2404 2405 free_fd_percpu(); 2406 2407 free(irq_column_2_cpu); 2408 free(irqs_per_cpu); 2409 2410 for (i = 0; i <= topo.max_cpu_num; ++i) { 2411 if (cpus[i].put_ids) 2412 CPU_FREE(cpus[i].put_ids); 2413 } 2414 free(cpus); 2415 } 2416 2417 2418 /* 2419 * Parse a file containing a single int. 2420 */ 2421 int parse_int_file(const char *fmt, ...) 2422 { 2423 va_list args; 2424 char path[PATH_MAX]; 2425 FILE *filep; 2426 int value; 2427 2428 va_start(args, fmt); 2429 vsnprintf(path, sizeof(path), fmt, args); 2430 va_end(args); 2431 filep = fopen_or_die(path, "r"); 2432 if (fscanf(filep, "%d", &value) != 1) 2433 err(1, "%s: failed to parse number from file", path); 2434 fclose(filep); 2435 return value; 2436 } 2437 2438 /* 2439 * cpu_is_first_core_in_package(cpu) 2440 * return 1 if given CPU is 1st core in package 2441 */ 2442 int cpu_is_first_core_in_package(int cpu) 2443 { 2444 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); 2445 } 2446 2447 int get_physical_package_id(int cpu) 2448 { 2449 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); 2450 } 2451 2452 int get_core_id(int cpu) 2453 { 2454 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); 2455 } 2456 2457 void set_node_data(void) 2458 { 2459 char path[80]; 2460 FILE *filep; 2461 int pkg, node, cpu; 2462 2463 struct pkg_node_info { 2464 int count; 2465 int min; 2466 } *pni; 2467 2468 pni = calloc(topo.num_packages, sizeof(struct pkg_node_info)); 2469 if (!pni) 2470 err(1, "calloc pkg_node_count"); 2471 2472 for (pkg = 0; pkg < topo.num_packages; pkg++) 2473 pni[pkg].min = topo.num_cpus; 2474 2475 for (node = 0; node <= topo.max_node_num; node++) { 2476 /* find the "first" cpu in the node */ 2477 sprintf(path, "/sys/bus/node/devices/node%d/cpulist", node); 2478 filep = fopen(path, "r"); 2479 if (!filep) 2480 continue; 2481 fscanf(filep, "%d", &cpu); 2482 fclose(filep); 2483 2484 pkg = cpus[cpu].physical_package_id; 2485 pni[pkg].count++; 2486 2487 if (node < pni[pkg].min) 2488 pni[pkg].min = node; 2489 } 2490 2491 for (pkg = 0; pkg < topo.num_packages; pkg++) 2492 if (pni[pkg].count > topo.nodes_per_pkg) 2493 topo.nodes_per_pkg = pni[0].count; 2494 2495 /* Fake 1 node per pkg for machines that don't 2496 * expose nodes and thus avoid -nan results 2497 */ 2498 if (topo.nodes_per_pkg == 0) 2499 topo.nodes_per_pkg = 1; 2500 2501 for (cpu = 0; cpu < topo.num_cpus; cpu++) { 2502 pkg = cpus[cpu].physical_package_id; 2503 node = cpus[cpu].physical_node_id; 2504 cpus[cpu].logical_node_id = node - pni[pkg].min; 2505 } 2506 free(pni); 2507 2508 } 2509 2510 int get_physical_node_id(struct cpu_topology *thiscpu) 2511 { 2512 char path[80]; 2513 FILE *filep; 2514 int i; 2515 int cpu = thiscpu->logical_cpu_id; 2516 2517 for (i = 0; i <= topo.max_cpu_num; i++) { 2518 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist", 2519 cpu, i); 2520 filep = fopen(path, "r"); 2521 if (!filep) 2522 continue; 2523 fclose(filep); 2524 return i; 2525 } 2526 return -1; 2527 } 2528 2529 int get_thread_siblings(struct cpu_topology *thiscpu) 2530 { 2531 char path[80], character; 2532 FILE *filep; 2533 unsigned long map; 2534 int so, shift, sib_core; 2535 int cpu = thiscpu->logical_cpu_id; 2536 int offset = topo.max_cpu_num + 1; 2537 size_t size; 2538 int thread_id = 0; 2539 2540 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1)); 2541 if (thiscpu->thread_id < 0) 2542 thiscpu->thread_id = thread_id++; 2543 if (!thiscpu->put_ids) 2544 return -1; 2545 2546 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 2547 CPU_ZERO_S(size, thiscpu->put_ids); 2548 2549 sprintf(path, 2550 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu); 2551 filep = fopen_or_die(path, "r"); 2552 do { 2553 offset -= BITMASK_SIZE; 2554 fscanf(filep, "%lx%c", &map, &character); 2555 for (shift = 0; shift < BITMASK_SIZE; shift++) { 2556 if ((map >> shift) & 0x1) { 2557 so = shift + offset; 2558 sib_core = get_core_id(so); 2559 if (sib_core == thiscpu->physical_core_id) { 2560 CPU_SET_S(so, size, thiscpu->put_ids); 2561 if ((so != cpu) && 2562 (cpus[so].thread_id < 0)) 2563 cpus[so].thread_id = 2564 thread_id++; 2565 } 2566 } 2567 } 2568 } while (!strncmp(&character, ",", 1)); 2569 fclose(filep); 2570 2571 return CPU_COUNT_S(size, thiscpu->put_ids); 2572 } 2573 2574 /* 2575 * run func(thread, core, package) in topology order 2576 * skip non-present cpus 2577 */ 2578 2579 int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *, 2580 struct pkg_data *, struct thread_data *, struct core_data *, 2581 struct pkg_data *), struct thread_data *thread_base, 2582 struct core_data *core_base, struct pkg_data *pkg_base, 2583 struct thread_data *thread_base2, struct core_data *core_base2, 2584 struct pkg_data *pkg_base2) 2585 { 2586 int retval, pkg_no, node_no, core_no, thread_no; 2587 2588 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { 2589 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) { 2590 for (core_no = 0; core_no < topo.cores_per_node; 2591 ++core_no) { 2592 for (thread_no = 0; thread_no < 2593 topo.threads_per_core; ++thread_no) { 2594 struct thread_data *t, *t2; 2595 struct core_data *c, *c2; 2596 struct pkg_data *p, *p2; 2597 2598 t = GET_THREAD(thread_base, thread_no, 2599 core_no, node_no, 2600 pkg_no); 2601 2602 if (cpu_is_not_present(t->cpu_id)) 2603 continue; 2604 2605 t2 = GET_THREAD(thread_base2, thread_no, 2606 core_no, node_no, 2607 pkg_no); 2608 2609 c = GET_CORE(core_base, core_no, 2610 node_no, pkg_no); 2611 c2 = GET_CORE(core_base2, core_no, 2612 node_no, 2613 pkg_no); 2614 2615 p = GET_PKG(pkg_base, pkg_no); 2616 p2 = GET_PKG(pkg_base2, pkg_no); 2617 2618 retval = func(t, c, p, t2, c2, p2); 2619 if (retval) 2620 return retval; 2621 } 2622 } 2623 } 2624 } 2625 return 0; 2626 } 2627 2628 /* 2629 * run func(cpu) on every cpu in /proc/stat 2630 * return max_cpu number 2631 */ 2632 int for_all_proc_cpus(int (func)(int)) 2633 { 2634 FILE *fp; 2635 int cpu_num; 2636 int retval; 2637 2638 fp = fopen_or_die(proc_stat, "r"); 2639 2640 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); 2641 if (retval != 0) 2642 err(1, "%s: failed to parse format", proc_stat); 2643 2644 while (1) { 2645 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); 2646 if (retval != 1) 2647 break; 2648 2649 retval = func(cpu_num); 2650 if (retval) { 2651 fclose(fp); 2652 return(retval); 2653 } 2654 } 2655 fclose(fp); 2656 return 0; 2657 } 2658 2659 void re_initialize(void) 2660 { 2661 free_all_buffers(); 2662 setup_all_buffers(); 2663 printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); 2664 } 2665 2666 void set_max_cpu_num(void) 2667 { 2668 FILE *filep; 2669 unsigned long dummy; 2670 2671 topo.max_cpu_num = 0; 2672 filep = fopen_or_die( 2673 "/sys/devices/system/cpu/cpu0/topology/thread_siblings", 2674 "r"); 2675 while (fscanf(filep, "%lx,", &dummy) == 1) 2676 topo.max_cpu_num += BITMASK_SIZE; 2677 fclose(filep); 2678 topo.max_cpu_num--; /* 0 based */ 2679 } 2680 2681 /* 2682 * count_cpus() 2683 * remember the last one seen, it will be the max 2684 */ 2685 int count_cpus(int cpu) 2686 { 2687 topo.num_cpus++; 2688 return 0; 2689 } 2690 int mark_cpu_present(int cpu) 2691 { 2692 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); 2693 return 0; 2694 } 2695 2696 int init_thread_id(int cpu) 2697 { 2698 cpus[cpu].thread_id = -1; 2699 return 0; 2700 } 2701 2702 /* 2703 * snapshot_proc_interrupts() 2704 * 2705 * read and record summary of /proc/interrupts 2706 * 2707 * return 1 if config change requires a restart, else return 0 2708 */ 2709 int snapshot_proc_interrupts(void) 2710 { 2711 static FILE *fp; 2712 int column, retval; 2713 2714 if (fp == NULL) 2715 fp = fopen_or_die("/proc/interrupts", "r"); 2716 else 2717 rewind(fp); 2718 2719 /* read 1st line of /proc/interrupts to get cpu* name for each column */ 2720 for (column = 0; column < topo.num_cpus; ++column) { 2721 int cpu_number; 2722 2723 retval = fscanf(fp, " CPU%d", &cpu_number); 2724 if (retval != 1) 2725 break; 2726 2727 if (cpu_number > topo.max_cpu_num) { 2728 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); 2729 return 1; 2730 } 2731 2732 irq_column_2_cpu[column] = cpu_number; 2733 irqs_per_cpu[cpu_number] = 0; 2734 } 2735 2736 /* read /proc/interrupt count lines and sum up irqs per cpu */ 2737 while (1) { 2738 int column; 2739 char buf[64]; 2740 2741 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ 2742 if (retval != 1) 2743 break; 2744 2745 /* read the count per cpu */ 2746 for (column = 0; column < topo.num_cpus; ++column) { 2747 2748 int cpu_number, irq_count; 2749 2750 retval = fscanf(fp, " %d", &irq_count); 2751 if (retval != 1) 2752 break; 2753 2754 cpu_number = irq_column_2_cpu[column]; 2755 irqs_per_cpu[cpu_number] += irq_count; 2756 2757 } 2758 2759 while (getc(fp) != '\n') 2760 ; /* flush interrupt description */ 2761 2762 } 2763 return 0; 2764 } 2765 /* 2766 * snapshot_gfx_rc6_ms() 2767 * 2768 * record snapshot of 2769 * /sys/class/drm/card0/power/rc6_residency_ms 2770 * 2771 * return 1 if config change requires a restart, else return 0 2772 */ 2773 int snapshot_gfx_rc6_ms(void) 2774 { 2775 FILE *fp; 2776 int retval; 2777 2778 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); 2779 2780 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); 2781 if (retval != 1) 2782 err(1, "GFX rc6"); 2783 2784 fclose(fp); 2785 2786 return 0; 2787 } 2788 /* 2789 * snapshot_gfx_mhz() 2790 * 2791 * record snapshot of 2792 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz 2793 * 2794 * return 1 if config change requires a restart, else return 0 2795 */ 2796 int snapshot_gfx_mhz(void) 2797 { 2798 static FILE *fp; 2799 int retval; 2800 2801 if (fp == NULL) 2802 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); 2803 else { 2804 rewind(fp); 2805 fflush(fp); 2806 } 2807 2808 retval = fscanf(fp, "%d", &gfx_cur_mhz); 2809 if (retval != 1) 2810 err(1, "GFX MHz"); 2811 2812 return 0; 2813 } 2814 2815 /* 2816 * snapshot_cpu_lpi() 2817 * 2818 * record snapshot of 2819 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us 2820 * 2821 * return 1 if config change requires a restart, else return 0 2822 */ 2823 int snapshot_cpu_lpi_us(void) 2824 { 2825 FILE *fp; 2826 int retval; 2827 2828 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r"); 2829 2830 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us); 2831 if (retval != 1) 2832 err(1, "CPU LPI"); 2833 2834 fclose(fp); 2835 2836 return 0; 2837 } 2838 /* 2839 * snapshot_sys_lpi() 2840 * 2841 * record snapshot of 2842 * /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us 2843 * 2844 * return 1 if config change requires a restart, else return 0 2845 */ 2846 int snapshot_sys_lpi_us(void) 2847 { 2848 FILE *fp; 2849 int retval; 2850 2851 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us", "r"); 2852 2853 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us); 2854 if (retval != 1) 2855 err(1, "SYS LPI"); 2856 2857 fclose(fp); 2858 2859 return 0; 2860 } 2861 /* 2862 * snapshot /proc and /sys files 2863 * 2864 * return 1 if configuration restart needed, else return 0 2865 */ 2866 int snapshot_proc_sysfs_files(void) 2867 { 2868 if (DO_BIC(BIC_IRQ)) 2869 if (snapshot_proc_interrupts()) 2870 return 1; 2871 2872 if (DO_BIC(BIC_GFX_rc6)) 2873 snapshot_gfx_rc6_ms(); 2874 2875 if (DO_BIC(BIC_GFXMHz)) 2876 snapshot_gfx_mhz(); 2877 2878 if (DO_BIC(BIC_CPU_LPI)) 2879 snapshot_cpu_lpi_us(); 2880 2881 if (DO_BIC(BIC_SYS_LPI)) 2882 snapshot_sys_lpi_us(); 2883 2884 return 0; 2885 } 2886 2887 int exit_requested; 2888 2889 static void signal_handler (int signal) 2890 { 2891 switch (signal) { 2892 case SIGINT: 2893 exit_requested = 1; 2894 if (debug) 2895 fprintf(stderr, " SIGINT\n"); 2896 break; 2897 case SIGUSR1: 2898 if (debug > 1) 2899 fprintf(stderr, "SIGUSR1\n"); 2900 break; 2901 } 2902 /* make sure this manually-invoked interval is at least 1ms long */ 2903 nanosleep(&one_msec, NULL); 2904 } 2905 2906 void setup_signal_handler(void) 2907 { 2908 struct sigaction sa; 2909 2910 memset(&sa, 0, sizeof(sa)); 2911 2912 sa.sa_handler = &signal_handler; 2913 2914 if (sigaction(SIGINT, &sa, NULL) < 0) 2915 err(1, "sigaction SIGINT"); 2916 if (sigaction(SIGUSR1, &sa, NULL) < 0) 2917 err(1, "sigaction SIGUSR1"); 2918 } 2919 2920 void do_sleep(void) 2921 { 2922 struct timeval select_timeout; 2923 fd_set readfds; 2924 int retval; 2925 2926 FD_ZERO(&readfds); 2927 FD_SET(0, &readfds); 2928 2929 if (!isatty(fileno(stdin))) { 2930 nanosleep(&interval_ts, NULL); 2931 return; 2932 } 2933 2934 select_timeout = interval_tv; 2935 retval = select(1, &readfds, NULL, NULL, &select_timeout); 2936 2937 if (retval == 1) { 2938 switch (getc(stdin)) { 2939 case 'q': 2940 exit_requested = 1; 2941 break; 2942 } 2943 /* make sure this manually-invoked interval is at least 1ms long */ 2944 nanosleep(&one_msec, NULL); 2945 } 2946 } 2947 2948 2949 void turbostat_loop() 2950 { 2951 int retval; 2952 int restarted = 0; 2953 int done_iters = 0; 2954 2955 setup_signal_handler(); 2956 2957 restart: 2958 restarted++; 2959 2960 snapshot_proc_sysfs_files(); 2961 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 2962 first_counter_read = 0; 2963 if (retval < -1) { 2964 exit(retval); 2965 } else if (retval == -1) { 2966 if (restarted > 1) { 2967 exit(retval); 2968 } 2969 re_initialize(); 2970 goto restart; 2971 } 2972 restarted = 0; 2973 done_iters = 0; 2974 gettimeofday(&tv_even, (struct timezone *)NULL); 2975 2976 while (1) { 2977 if (for_all_proc_cpus(cpu_is_not_present)) { 2978 re_initialize(); 2979 goto restart; 2980 } 2981 do_sleep(); 2982 if (snapshot_proc_sysfs_files()) 2983 goto restart; 2984 retval = for_all_cpus(get_counters, ODD_COUNTERS); 2985 if (retval < -1) { 2986 exit(retval); 2987 } else if (retval == -1) { 2988 re_initialize(); 2989 goto restart; 2990 } 2991 gettimeofday(&tv_odd, (struct timezone *)NULL); 2992 timersub(&tv_odd, &tv_even, &tv_delta); 2993 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) { 2994 re_initialize(); 2995 goto restart; 2996 } 2997 compute_average(EVEN_COUNTERS); 2998 format_all_counters(EVEN_COUNTERS); 2999 flush_output_stdout(); 3000 if (exit_requested) 3001 break; 3002 if (num_iterations && ++done_iters >= num_iterations) 3003 break; 3004 do_sleep(); 3005 if (snapshot_proc_sysfs_files()) 3006 goto restart; 3007 retval = for_all_cpus(get_counters, EVEN_COUNTERS); 3008 if (retval < -1) { 3009 exit(retval); 3010 } else if (retval == -1) { 3011 re_initialize(); 3012 goto restart; 3013 } 3014 gettimeofday(&tv_even, (struct timezone *)NULL); 3015 timersub(&tv_even, &tv_odd, &tv_delta); 3016 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) { 3017 re_initialize(); 3018 goto restart; 3019 } 3020 compute_average(ODD_COUNTERS); 3021 format_all_counters(ODD_COUNTERS); 3022 flush_output_stdout(); 3023 if (exit_requested) 3024 break; 3025 if (num_iterations && ++done_iters >= num_iterations) 3026 break; 3027 } 3028 } 3029 3030 void check_dev_msr() 3031 { 3032 struct stat sb; 3033 char pathname[32]; 3034 3035 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3036 if (stat(pathname, &sb)) 3037 if (system("/sbin/modprobe msr > /dev/null 2>&1")) 3038 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); 3039 } 3040 3041 void check_permissions() 3042 { 3043 struct __user_cap_header_struct cap_header_data; 3044 cap_user_header_t cap_header = &cap_header_data; 3045 struct __user_cap_data_struct cap_data_data; 3046 cap_user_data_t cap_data = &cap_data_data; 3047 extern int capget(cap_user_header_t hdrp, cap_user_data_t datap); 3048 int do_exit = 0; 3049 char pathname[32]; 3050 3051 /* check for CAP_SYS_RAWIO */ 3052 cap_header->pid = getpid(); 3053 cap_header->version = _LINUX_CAPABILITY_VERSION; 3054 if (capget(cap_header, cap_data) < 0) 3055 err(-6, "capget(2) failed"); 3056 3057 if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) { 3058 do_exit++; 3059 warnx("capget(CAP_SYS_RAWIO) failed," 3060 " try \"# setcap cap_sys_rawio=ep %s\"", progname); 3061 } 3062 3063 /* test file permissions */ 3064 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); 3065 if (euidaccess(pathname, R_OK)) { 3066 do_exit++; 3067 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); 3068 } 3069 3070 /* if all else fails, thell them to be root */ 3071 if (do_exit) 3072 if (getuid() != 0) 3073 warnx("... or simply run as root"); 3074 3075 if (do_exit) 3076 exit(-6); 3077 } 3078 3079 /* 3080 * NHM adds support for additional MSRs: 3081 * 3082 * MSR_SMI_COUNT 0x00000034 3083 * 3084 * MSR_PLATFORM_INFO 0x000000ce 3085 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 3086 * 3087 * MSR_MISC_PWR_MGMT 0x000001aa 3088 * 3089 * MSR_PKG_C3_RESIDENCY 0x000003f8 3090 * MSR_PKG_C6_RESIDENCY 0x000003f9 3091 * MSR_CORE_C3_RESIDENCY 0x000003fc 3092 * MSR_CORE_C6_RESIDENCY 0x000003fd 3093 * 3094 * Side effect: 3095 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL 3096 * sets has_misc_feature_control 3097 */ 3098 int probe_nhm_msrs(unsigned int family, unsigned int model) 3099 { 3100 unsigned long long msr; 3101 unsigned int base_ratio; 3102 int *pkg_cstate_limits; 3103 3104 if (!genuine_intel) 3105 return 0; 3106 3107 if (family != 6) 3108 return 0; 3109 3110 bclk = discover_bclk(family, model); 3111 3112 switch (model) { 3113 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ 3114 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ 3115 case 0x1F: /* Core i7 and i5 Processor - Nehalem */ 3116 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */ 3117 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */ 3118 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3119 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 3120 pkg_cstate_limits = nhm_pkg_cstate_limits; 3121 break; 3122 case INTEL_FAM6_SANDYBRIDGE: /* SNB */ 3123 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */ 3124 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3125 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3126 pkg_cstate_limits = snb_pkg_cstate_limits; 3127 has_misc_feature_control = 1; 3128 break; 3129 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3130 case INTEL_FAM6_HASWELL_X: /* HSX */ 3131 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3132 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3133 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3134 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3135 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3136 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 3137 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3138 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3139 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3140 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3141 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 3142 pkg_cstate_limits = hsw_pkg_cstate_limits; 3143 has_misc_feature_control = 1; 3144 break; 3145 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3146 pkg_cstate_limits = skx_pkg_cstate_limits; 3147 has_misc_feature_control = 1; 3148 break; 3149 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ 3150 no_MSR_MISC_PWR_MGMT = 1; 3151 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ 3152 pkg_cstate_limits = slv_pkg_cstate_limits; 3153 break; 3154 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */ 3155 pkg_cstate_limits = amt_pkg_cstate_limits; 3156 no_MSR_MISC_PWR_MGMT = 1; 3157 break; 3158 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */ 3159 case INTEL_FAM6_XEON_PHI_KNM: 3160 pkg_cstate_limits = phi_pkg_cstate_limits; 3161 break; 3162 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3163 case INTEL_FAM6_ATOM_GEMINI_LAKE: 3164 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 3165 pkg_cstate_limits = bxt_pkg_cstate_limits; 3166 break; 3167 default: 3168 return 0; 3169 } 3170 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr); 3171 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; 3172 3173 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); 3174 base_ratio = (msr >> 8) & 0xFF; 3175 3176 base_hz = base_ratio * bclk * 1000000; 3177 has_base_hz = 1; 3178 return 1; 3179 } 3180 /* 3181 * SLV client has support for unique MSRs: 3182 * 3183 * MSR_CC6_DEMOTION_POLICY_CONFIG 3184 * MSR_MC6_DEMOTION_POLICY_CONFIG 3185 */ 3186 3187 int has_slv_msrs(unsigned int family, unsigned int model) 3188 { 3189 if (!genuine_intel) 3190 return 0; 3191 3192 switch (model) { 3193 case INTEL_FAM6_ATOM_SILVERMONT1: 3194 case INTEL_FAM6_ATOM_MERRIFIELD: 3195 case INTEL_FAM6_ATOM_MOOREFIELD: 3196 return 1; 3197 } 3198 return 0; 3199 } 3200 int is_dnv(unsigned int family, unsigned int model) 3201 { 3202 3203 if (!genuine_intel) 3204 return 0; 3205 3206 switch (model) { 3207 case INTEL_FAM6_ATOM_DENVERTON: 3208 return 1; 3209 } 3210 return 0; 3211 } 3212 int is_bdx(unsigned int family, unsigned int model) 3213 { 3214 3215 if (!genuine_intel) 3216 return 0; 3217 3218 switch (model) { 3219 case INTEL_FAM6_BROADWELL_X: 3220 case INTEL_FAM6_BROADWELL_XEON_D: 3221 return 1; 3222 } 3223 return 0; 3224 } 3225 int is_skx(unsigned int family, unsigned int model) 3226 { 3227 3228 if (!genuine_intel) 3229 return 0; 3230 3231 switch (model) { 3232 case INTEL_FAM6_SKYLAKE_X: 3233 return 1; 3234 } 3235 return 0; 3236 } 3237 3238 int has_turbo_ratio_limit(unsigned int family, unsigned int model) 3239 { 3240 if (has_slv_msrs(family, model)) 3241 return 0; 3242 3243 switch (model) { 3244 /* Nehalem compatible, but do not include turbo-ratio limit support */ 3245 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ 3246 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ 3247 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */ 3248 case INTEL_FAM6_XEON_PHI_KNM: 3249 return 0; 3250 default: 3251 return 1; 3252 } 3253 } 3254 int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model) 3255 { 3256 if (has_slv_msrs(family, model)) 3257 return 1; 3258 3259 return 0; 3260 } 3261 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) 3262 { 3263 if (!genuine_intel) 3264 return 0; 3265 3266 if (family != 6) 3267 return 0; 3268 3269 switch (model) { 3270 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 3271 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3272 return 1; 3273 default: 3274 return 0; 3275 } 3276 } 3277 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) 3278 { 3279 if (!genuine_intel) 3280 return 0; 3281 3282 if (family != 6) 3283 return 0; 3284 3285 switch (model) { 3286 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ 3287 return 1; 3288 default: 3289 return 0; 3290 } 3291 } 3292 3293 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) 3294 { 3295 if (!genuine_intel) 3296 return 0; 3297 3298 if (family != 6) 3299 return 0; 3300 3301 switch (model) { 3302 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 3303 case INTEL_FAM6_XEON_PHI_KNM: 3304 return 1; 3305 default: 3306 return 0; 3307 } 3308 } 3309 int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model) 3310 { 3311 if (!genuine_intel) 3312 return 0; 3313 3314 if (family != 6) 3315 return 0; 3316 3317 switch (model) { 3318 case INTEL_FAM6_ATOM_GOLDMONT: 3319 case INTEL_FAM6_SKYLAKE_X: 3320 return 1; 3321 default: 3322 return 0; 3323 } 3324 } 3325 int has_config_tdp(unsigned int family, unsigned int model) 3326 { 3327 if (!genuine_intel) 3328 return 0; 3329 3330 if (family != 6) 3331 return 0; 3332 3333 switch (model) { 3334 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 3335 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3336 case INTEL_FAM6_HASWELL_X: /* HSX */ 3337 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3338 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3339 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3340 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3341 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3342 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 3343 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3344 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3345 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3346 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3347 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 3348 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3349 3350 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ 3351 case INTEL_FAM6_XEON_PHI_KNM: 3352 return 1; 3353 default: 3354 return 0; 3355 } 3356 } 3357 3358 static void 3359 dump_cstate_pstate_config_info(unsigned int family, unsigned int model) 3360 { 3361 if (!do_nhm_platform_info) 3362 return; 3363 3364 dump_nhm_platform_info(); 3365 3366 if (has_hsw_turbo_ratio_limit(family, model)) 3367 dump_hsw_turbo_ratio_limits(); 3368 3369 if (has_ivt_turbo_ratio_limit(family, model)) 3370 dump_ivt_turbo_ratio_limits(); 3371 3372 if (has_turbo_ratio_limit(family, model)) 3373 dump_turbo_ratio_limits(family, model); 3374 3375 if (has_atom_turbo_ratio_limit(family, model)) 3376 dump_atom_turbo_ratio_limits(); 3377 3378 if (has_knl_turbo_ratio_limit(family, model)) 3379 dump_knl_turbo_ratio_limits(); 3380 3381 if (has_config_tdp(family, model)) 3382 dump_config_tdp(); 3383 3384 dump_nhm_cst_cfg(); 3385 } 3386 3387 static void 3388 dump_sysfs_cstate_config(void) 3389 { 3390 char path[64]; 3391 char name_buf[16]; 3392 char desc[64]; 3393 FILE *input; 3394 int state; 3395 char *sp; 3396 3397 if (!DO_BIC(BIC_sysfs)) 3398 return; 3399 3400 for (state = 0; state < 10; ++state) { 3401 3402 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 3403 base_cpu, state); 3404 input = fopen(path, "r"); 3405 if (input == NULL) 3406 continue; 3407 fgets(name_buf, sizeof(name_buf), input); 3408 3409 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 3410 sp = strchr(name_buf, '-'); 3411 if (!sp) 3412 sp = strchrnul(name_buf, '\n'); 3413 *sp = '\0'; 3414 3415 fclose(input); 3416 3417 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc", 3418 base_cpu, state); 3419 input = fopen(path, "r"); 3420 if (input == NULL) 3421 continue; 3422 fgets(desc, sizeof(desc), input); 3423 3424 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc); 3425 fclose(input); 3426 } 3427 } 3428 static void 3429 dump_sysfs_pstate_config(void) 3430 { 3431 char path[64]; 3432 char driver_buf[64]; 3433 char governor_buf[64]; 3434 FILE *input; 3435 int turbo; 3436 3437 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver", 3438 base_cpu); 3439 input = fopen(path, "r"); 3440 if (input == NULL) { 3441 fprintf(stderr, "NSFOD %s\n", path); 3442 return; 3443 } 3444 fgets(driver_buf, sizeof(driver_buf), input); 3445 fclose(input); 3446 3447 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor", 3448 base_cpu); 3449 input = fopen(path, "r"); 3450 if (input == NULL) { 3451 fprintf(stderr, "NSFOD %s\n", path); 3452 return; 3453 } 3454 fgets(governor_buf, sizeof(governor_buf), input); 3455 fclose(input); 3456 3457 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf); 3458 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf); 3459 3460 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost"); 3461 input = fopen(path, "r"); 3462 if (input != NULL) { 3463 fscanf(input, "%d", &turbo); 3464 fprintf(outf, "cpufreq boost: %d\n", turbo); 3465 fclose(input); 3466 } 3467 3468 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo"); 3469 input = fopen(path, "r"); 3470 if (input != NULL) { 3471 fscanf(input, "%d", &turbo); 3472 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo); 3473 fclose(input); 3474 } 3475 } 3476 3477 3478 /* 3479 * print_epb() 3480 * Decode the ENERGY_PERF_BIAS MSR 3481 */ 3482 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3483 { 3484 unsigned long long msr; 3485 char *epb_string; 3486 int cpu; 3487 3488 if (!has_epb) 3489 return 0; 3490 3491 cpu = t->cpu_id; 3492 3493 /* EPB is per-package */ 3494 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3495 return 0; 3496 3497 if (cpu_migrate(cpu)) { 3498 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3499 return -1; 3500 } 3501 3502 if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr)) 3503 return 0; 3504 3505 switch (msr & 0xF) { 3506 case ENERGY_PERF_BIAS_PERFORMANCE: 3507 epb_string = "performance"; 3508 break; 3509 case ENERGY_PERF_BIAS_NORMAL: 3510 epb_string = "balanced"; 3511 break; 3512 case ENERGY_PERF_BIAS_POWERSAVE: 3513 epb_string = "powersave"; 3514 break; 3515 default: 3516 epb_string = "custom"; 3517 break; 3518 } 3519 fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string); 3520 3521 return 0; 3522 } 3523 /* 3524 * print_hwp() 3525 * Decode the MSR_HWP_CAPABILITIES 3526 */ 3527 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3528 { 3529 unsigned long long msr; 3530 int cpu; 3531 3532 if (!has_hwp) 3533 return 0; 3534 3535 cpu = t->cpu_id; 3536 3537 /* MSR_HWP_CAPABILITIES is per-package */ 3538 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3539 return 0; 3540 3541 if (cpu_migrate(cpu)) { 3542 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3543 return -1; 3544 } 3545 3546 if (get_msr(cpu, MSR_PM_ENABLE, &msr)) 3547 return 0; 3548 3549 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", 3550 cpu, msr, (msr & (1 << 0)) ? "" : "No-"); 3551 3552 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ 3553 if ((msr & (1 << 0)) == 0) 3554 return 0; 3555 3556 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) 3557 return 0; 3558 3559 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " 3560 "(high %d guar %d eff %d low %d)\n", 3561 cpu, msr, 3562 (unsigned int)HWP_HIGHEST_PERF(msr), 3563 (unsigned int)HWP_GUARANTEED_PERF(msr), 3564 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), 3565 (unsigned int)HWP_LOWEST_PERF(msr)); 3566 3567 if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) 3568 return 0; 3569 3570 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " 3571 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n", 3572 cpu, msr, 3573 (unsigned int)(((msr) >> 0) & 0xff), 3574 (unsigned int)(((msr) >> 8) & 0xff), 3575 (unsigned int)(((msr) >> 16) & 0xff), 3576 (unsigned int)(((msr) >> 24) & 0xff), 3577 (unsigned int)(((msr) >> 32) & 0xff3), 3578 (unsigned int)(((msr) >> 42) & 0x1)); 3579 3580 if (has_hwp_pkg) { 3581 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) 3582 return 0; 3583 3584 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " 3585 "(min %d max %d des %d epp 0x%x window 0x%x)\n", 3586 cpu, msr, 3587 (unsigned int)(((msr) >> 0) & 0xff), 3588 (unsigned int)(((msr) >> 8) & 0xff), 3589 (unsigned int)(((msr) >> 16) & 0xff), 3590 (unsigned int)(((msr) >> 24) & 0xff), 3591 (unsigned int)(((msr) >> 32) & 0xff3)); 3592 } 3593 if (has_hwp_notify) { 3594 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) 3595 return 0; 3596 3597 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " 3598 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", 3599 cpu, msr, 3600 ((msr) & 0x1) ? "EN" : "Dis", 3601 ((msr) & 0x2) ? "EN" : "Dis"); 3602 } 3603 if (get_msr(cpu, MSR_HWP_STATUS, &msr)) 3604 return 0; 3605 3606 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " 3607 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", 3608 cpu, msr, 3609 ((msr) & 0x1) ? "" : "No-", 3610 ((msr) & 0x2) ? "" : "No-"); 3611 3612 return 0; 3613 } 3614 3615 /* 3616 * print_perf_limit() 3617 */ 3618 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3619 { 3620 unsigned long long msr; 3621 int cpu; 3622 3623 cpu = t->cpu_id; 3624 3625 /* per-package */ 3626 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 3627 return 0; 3628 3629 if (cpu_migrate(cpu)) { 3630 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3631 return -1; 3632 } 3633 3634 if (do_core_perf_limit_reasons) { 3635 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); 3636 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 3637 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", 3638 (msr & 1 << 15) ? "bit15, " : "", 3639 (msr & 1 << 14) ? "bit14, " : "", 3640 (msr & 1 << 13) ? "Transitions, " : "", 3641 (msr & 1 << 12) ? "MultiCoreTurbo, " : "", 3642 (msr & 1 << 11) ? "PkgPwrL2, " : "", 3643 (msr & 1 << 10) ? "PkgPwrL1, " : "", 3644 (msr & 1 << 9) ? "CorePwr, " : "", 3645 (msr & 1 << 8) ? "Amps, " : "", 3646 (msr & 1 << 6) ? "VR-Therm, " : "", 3647 (msr & 1 << 5) ? "Auto-HWP, " : "", 3648 (msr & 1 << 4) ? "Graphics, " : "", 3649 (msr & 1 << 2) ? "bit2, " : "", 3650 (msr & 1 << 1) ? "ThermStatus, " : "", 3651 (msr & 1 << 0) ? "PROCHOT, " : ""); 3652 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 3653 (msr & 1 << 31) ? "bit31, " : "", 3654 (msr & 1 << 30) ? "bit30, " : "", 3655 (msr & 1 << 29) ? "Transitions, " : "", 3656 (msr & 1 << 28) ? "MultiCoreTurbo, " : "", 3657 (msr & 1 << 27) ? "PkgPwrL2, " : "", 3658 (msr & 1 << 26) ? "PkgPwrL1, " : "", 3659 (msr & 1 << 25) ? "CorePwr, " : "", 3660 (msr & 1 << 24) ? "Amps, " : "", 3661 (msr & 1 << 22) ? "VR-Therm, " : "", 3662 (msr & 1 << 21) ? "Auto-HWP, " : "", 3663 (msr & 1 << 20) ? "Graphics, " : "", 3664 (msr & 1 << 18) ? "bit18, " : "", 3665 (msr & 1 << 17) ? "ThermStatus, " : "", 3666 (msr & 1 << 16) ? "PROCHOT, " : ""); 3667 3668 } 3669 if (do_gfx_perf_limit_reasons) { 3670 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); 3671 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 3672 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", 3673 (msr & 1 << 0) ? "PROCHOT, " : "", 3674 (msr & 1 << 1) ? "ThermStatus, " : "", 3675 (msr & 1 << 4) ? "Graphics, " : "", 3676 (msr & 1 << 6) ? "VR-Therm, " : "", 3677 (msr & 1 << 8) ? "Amps, " : "", 3678 (msr & 1 << 9) ? "GFXPwr, " : "", 3679 (msr & 1 << 10) ? "PkgPwrL1, " : "", 3680 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 3681 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", 3682 (msr & 1 << 16) ? "PROCHOT, " : "", 3683 (msr & 1 << 17) ? "ThermStatus, " : "", 3684 (msr & 1 << 20) ? "Graphics, " : "", 3685 (msr & 1 << 22) ? "VR-Therm, " : "", 3686 (msr & 1 << 24) ? "Amps, " : "", 3687 (msr & 1 << 25) ? "GFXPwr, " : "", 3688 (msr & 1 << 26) ? "PkgPwrL1, " : "", 3689 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 3690 } 3691 if (do_ring_perf_limit_reasons) { 3692 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); 3693 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); 3694 fprintf(outf, " (Active: %s%s%s%s%s%s)", 3695 (msr & 1 << 0) ? "PROCHOT, " : "", 3696 (msr & 1 << 1) ? "ThermStatus, " : "", 3697 (msr & 1 << 6) ? "VR-Therm, " : "", 3698 (msr & 1 << 8) ? "Amps, " : "", 3699 (msr & 1 << 10) ? "PkgPwrL1, " : "", 3700 (msr & 1 << 11) ? "PkgPwrL2, " : ""); 3701 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", 3702 (msr & 1 << 16) ? "PROCHOT, " : "", 3703 (msr & 1 << 17) ? "ThermStatus, " : "", 3704 (msr & 1 << 22) ? "VR-Therm, " : "", 3705 (msr & 1 << 24) ? "Amps, " : "", 3706 (msr & 1 << 26) ? "PkgPwrL1, " : "", 3707 (msr & 1 << 27) ? "PkgPwrL2, " : ""); 3708 } 3709 return 0; 3710 } 3711 3712 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ 3713 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ 3714 3715 double get_tdp(unsigned int model) 3716 { 3717 unsigned long long msr; 3718 3719 if (do_rapl & RAPL_PKG_POWER_INFO) 3720 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) 3721 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; 3722 3723 switch (model) { 3724 case INTEL_FAM6_ATOM_SILVERMONT1: 3725 case INTEL_FAM6_ATOM_SILVERMONT2: 3726 return 30.0; 3727 default: 3728 return 135.0; 3729 } 3730 } 3731 3732 /* 3733 * rapl_dram_energy_units_probe() 3734 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR. 3735 */ 3736 static double 3737 rapl_dram_energy_units_probe(int model, double rapl_energy_units) 3738 { 3739 /* only called for genuine_intel, family 6 */ 3740 3741 switch (model) { 3742 case INTEL_FAM6_HASWELL_X: /* HSX */ 3743 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3744 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 3745 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 3746 case INTEL_FAM6_XEON_PHI_KNM: 3747 return (rapl_dram_energy_units = 15.3 / 1000000); 3748 default: 3749 return (rapl_energy_units); 3750 } 3751 } 3752 3753 3754 /* 3755 * rapl_probe() 3756 * 3757 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units 3758 */ 3759 void rapl_probe(unsigned int family, unsigned int model) 3760 { 3761 unsigned long long msr; 3762 unsigned int time_unit; 3763 double tdp; 3764 3765 if (!genuine_intel) 3766 return; 3767 3768 if (family != 6) 3769 return; 3770 3771 switch (model) { 3772 case INTEL_FAM6_SANDYBRIDGE: 3773 case INTEL_FAM6_IVYBRIDGE: 3774 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3775 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3776 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3777 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 3778 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 3779 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; 3780 if (rapl_joules) { 3781 BIC_PRESENT(BIC_Pkg_J); 3782 BIC_PRESENT(BIC_Cor_J); 3783 BIC_PRESENT(BIC_GFX_J); 3784 } else { 3785 BIC_PRESENT(BIC_PkgWatt); 3786 BIC_PRESENT(BIC_CorWatt); 3787 BIC_PRESENT(BIC_GFXWatt); 3788 } 3789 break; 3790 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 3791 case INTEL_FAM6_ATOM_GEMINI_LAKE: 3792 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; 3793 if (rapl_joules) 3794 BIC_PRESENT(BIC_Pkg_J); 3795 else 3796 BIC_PRESENT(BIC_PkgWatt); 3797 break; 3798 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 3799 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 3800 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 3801 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 3802 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 3803 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_GFX | RAPL_PKG_POWER_INFO; 3804 BIC_PRESENT(BIC_PKG__); 3805 BIC_PRESENT(BIC_RAM__); 3806 if (rapl_joules) { 3807 BIC_PRESENT(BIC_Pkg_J); 3808 BIC_PRESENT(BIC_Cor_J); 3809 BIC_PRESENT(BIC_RAM_J); 3810 BIC_PRESENT(BIC_GFX_J); 3811 } else { 3812 BIC_PRESENT(BIC_PkgWatt); 3813 BIC_PRESENT(BIC_CorWatt); 3814 BIC_PRESENT(BIC_RAMWatt); 3815 BIC_PRESENT(BIC_GFXWatt); 3816 } 3817 break; 3818 case INTEL_FAM6_HASWELL_X: /* HSX */ 3819 case INTEL_FAM6_BROADWELL_X: /* BDX */ 3820 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 3821 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 3822 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 3823 case INTEL_FAM6_XEON_PHI_KNM: 3824 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; 3825 BIC_PRESENT(BIC_PKG__); 3826 BIC_PRESENT(BIC_RAM__); 3827 if (rapl_joules) { 3828 BIC_PRESENT(BIC_Pkg_J); 3829 BIC_PRESENT(BIC_RAM_J); 3830 } else { 3831 BIC_PRESENT(BIC_PkgWatt); 3832 BIC_PRESENT(BIC_RAMWatt); 3833 } 3834 break; 3835 case INTEL_FAM6_SANDYBRIDGE_X: 3836 case INTEL_FAM6_IVYBRIDGE_X: 3837 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; 3838 BIC_PRESENT(BIC_PKG__); 3839 BIC_PRESENT(BIC_RAM__); 3840 if (rapl_joules) { 3841 BIC_PRESENT(BIC_Pkg_J); 3842 BIC_PRESENT(BIC_Cor_J); 3843 BIC_PRESENT(BIC_RAM_J); 3844 } else { 3845 BIC_PRESENT(BIC_PkgWatt); 3846 BIC_PRESENT(BIC_CorWatt); 3847 BIC_PRESENT(BIC_RAMWatt); 3848 } 3849 break; 3850 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ 3851 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ 3852 do_rapl = RAPL_PKG | RAPL_CORES; 3853 if (rapl_joules) { 3854 BIC_PRESENT(BIC_Pkg_J); 3855 BIC_PRESENT(BIC_Cor_J); 3856 } else { 3857 BIC_PRESENT(BIC_PkgWatt); 3858 BIC_PRESENT(BIC_CorWatt); 3859 } 3860 break; 3861 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 3862 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS; 3863 BIC_PRESENT(BIC_PKG__); 3864 BIC_PRESENT(BIC_RAM__); 3865 if (rapl_joules) { 3866 BIC_PRESENT(BIC_Pkg_J); 3867 BIC_PRESENT(BIC_Cor_J); 3868 BIC_PRESENT(BIC_RAM_J); 3869 } else { 3870 BIC_PRESENT(BIC_PkgWatt); 3871 BIC_PRESENT(BIC_CorWatt); 3872 BIC_PRESENT(BIC_RAMWatt); 3873 } 3874 break; 3875 default: 3876 return; 3877 } 3878 3879 /* units on package 0, verify later other packages match */ 3880 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) 3881 return; 3882 3883 rapl_power_units = 1.0 / (1 << (msr & 0xF)); 3884 if (model == INTEL_FAM6_ATOM_SILVERMONT1) 3885 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; 3886 else 3887 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); 3888 3889 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units); 3890 3891 time_unit = msr >> 16 & 0xF; 3892 if (time_unit == 0) 3893 time_unit = 0xA; 3894 3895 rapl_time_units = 1.0 / (1 << (time_unit)); 3896 3897 tdp = get_tdp(model); 3898 3899 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; 3900 if (!quiet) 3901 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); 3902 3903 return; 3904 } 3905 3906 void perf_limit_reasons_probe(unsigned int family, unsigned int model) 3907 { 3908 if (!genuine_intel) 3909 return; 3910 3911 if (family != 6) 3912 return; 3913 3914 switch (model) { 3915 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 3916 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 3917 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 3918 do_gfx_perf_limit_reasons = 1; 3919 case INTEL_FAM6_HASWELL_X: /* HSX */ 3920 do_core_perf_limit_reasons = 1; 3921 do_ring_perf_limit_reasons = 1; 3922 default: 3923 return; 3924 } 3925 } 3926 3927 void automatic_cstate_conversion_probe(unsigned int family, unsigned int model) 3928 { 3929 if (is_skx(family, model) || is_bdx(family, model)) 3930 has_automatic_cstate_conversion = 1; 3931 } 3932 3933 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) 3934 { 3935 unsigned long long msr; 3936 unsigned int dts, dts2; 3937 int cpu; 3938 3939 if (!(do_dts || do_ptm)) 3940 return 0; 3941 3942 cpu = t->cpu_id; 3943 3944 /* DTS is per-core, no need to print for each thread */ 3945 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) 3946 return 0; 3947 3948 if (cpu_migrate(cpu)) { 3949 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 3950 return -1; 3951 } 3952 3953 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { 3954 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) 3955 return 0; 3956 3957 dts = (msr >> 16) & 0x7F; 3958 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", 3959 cpu, msr, tcc_activation_temp - dts); 3960 3961 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) 3962 return 0; 3963 3964 dts = (msr >> 16) & 0x7F; 3965 dts2 = (msr >> 8) & 0x7F; 3966 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 3967 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 3968 } 3969 3970 3971 if (do_dts && debug) { 3972 unsigned int resolution; 3973 3974 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) 3975 return 0; 3976 3977 dts = (msr >> 16) & 0x7F; 3978 resolution = (msr >> 27) & 0xF; 3979 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", 3980 cpu, msr, tcc_activation_temp - dts, resolution); 3981 3982 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) 3983 return 0; 3984 3985 dts = (msr >> 16) & 0x7F; 3986 dts2 = (msr >> 8) & 0x7F; 3987 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", 3988 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); 3989 } 3990 3991 return 0; 3992 } 3993 3994 void print_power_limit_msr(int cpu, unsigned long long msr, char *label) 3995 { 3996 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n", 3997 cpu, label, 3998 ((msr >> 15) & 1) ? "EN" : "DIS", 3999 ((msr >> 0) & 0x7FFF) * rapl_power_units, 4000 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, 4001 (((msr >> 16) & 1) ? "EN" : "DIS")); 4002 4003 return; 4004 } 4005 4006 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4007 { 4008 unsigned long long msr; 4009 int cpu; 4010 4011 if (!do_rapl) 4012 return 0; 4013 4014 /* RAPL counters are per package, so print only for 1st thread/package */ 4015 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4016 return 0; 4017 4018 cpu = t->cpu_id; 4019 if (cpu_migrate(cpu)) { 4020 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 4021 return -1; 4022 } 4023 4024 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) 4025 return -1; 4026 4027 fprintf(outf, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr, 4028 rapl_power_units, rapl_energy_units, rapl_time_units); 4029 4030 if (do_rapl & RAPL_PKG_POWER_INFO) { 4031 4032 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) 4033 return -5; 4034 4035 4036 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4037 cpu, msr, 4038 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4039 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4040 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4041 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4042 4043 } 4044 if (do_rapl & RAPL_PKG) { 4045 4046 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) 4047 return -9; 4048 4049 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", 4050 cpu, msr, (msr >> 63) & 1 ? "" : "UN"); 4051 4052 print_power_limit_msr(cpu, msr, "PKG Limit #1"); 4053 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n", 4054 cpu, 4055 ((msr >> 47) & 1) ? "EN" : "DIS", 4056 ((msr >> 32) & 0x7FFF) * rapl_power_units, 4057 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, 4058 ((msr >> 48) & 1) ? "EN" : "DIS"); 4059 } 4060 4061 if (do_rapl & RAPL_DRAM_POWER_INFO) { 4062 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) 4063 return -6; 4064 4065 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", 4066 cpu, msr, 4067 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4068 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4069 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, 4070 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); 4071 } 4072 if (do_rapl & RAPL_DRAM) { 4073 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) 4074 return -9; 4075 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", 4076 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4077 4078 print_power_limit_msr(cpu, msr, "DRAM Limit"); 4079 } 4080 if (do_rapl & RAPL_CORE_POLICY) { 4081 if (get_msr(cpu, MSR_PP0_POLICY, &msr)) 4082 return -7; 4083 4084 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); 4085 } 4086 if (do_rapl & RAPL_CORES_POWER_LIMIT) { 4087 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) 4088 return -9; 4089 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", 4090 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4091 print_power_limit_msr(cpu, msr, "Cores Limit"); 4092 } 4093 if (do_rapl & RAPL_GFX) { 4094 if (get_msr(cpu, MSR_PP1_POLICY, &msr)) 4095 return -8; 4096 4097 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); 4098 4099 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) 4100 return -9; 4101 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", 4102 cpu, msr, (msr >> 31) & 1 ? "" : "UN"); 4103 print_power_limit_msr(cpu, msr, "GFX Limit"); 4104 } 4105 return 0; 4106 } 4107 4108 /* 4109 * SNB adds support for additional MSRs: 4110 * 4111 * MSR_PKG_C7_RESIDENCY 0x000003fa 4112 * MSR_CORE_C7_RESIDENCY 0x000003fe 4113 * MSR_PKG_C2_RESIDENCY 0x0000060d 4114 */ 4115 4116 int has_snb_msrs(unsigned int family, unsigned int model) 4117 { 4118 if (!genuine_intel) 4119 return 0; 4120 4121 switch (model) { 4122 case INTEL_FAM6_SANDYBRIDGE: 4123 case INTEL_FAM6_SANDYBRIDGE_X: 4124 case INTEL_FAM6_IVYBRIDGE: /* IVB */ 4125 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ 4126 case INTEL_FAM6_HASWELL_CORE: /* HSW */ 4127 case INTEL_FAM6_HASWELL_X: /* HSW */ 4128 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 4129 case INTEL_FAM6_HASWELL_GT3E: /* HSW */ 4130 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 4131 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ 4132 case INTEL_FAM6_BROADWELL_X: /* BDX */ 4133 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ 4134 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4135 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 4136 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 4137 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 4138 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 4139 case INTEL_FAM6_SKYLAKE_X: /* SKX */ 4140 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4141 case INTEL_FAM6_ATOM_GEMINI_LAKE: 4142 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 4143 return 1; 4144 } 4145 return 0; 4146 } 4147 4148 /* 4149 * HSW adds support for additional MSRs: 4150 * 4151 * MSR_PKG_C8_RESIDENCY 0x00000630 4152 * MSR_PKG_C9_RESIDENCY 0x00000631 4153 * MSR_PKG_C10_RESIDENCY 0x00000632 4154 * 4155 * MSR_PKGC8_IRTL 0x00000633 4156 * MSR_PKGC9_IRTL 0x00000634 4157 * MSR_PKGC10_IRTL 0x00000635 4158 * 4159 */ 4160 int has_hsw_msrs(unsigned int family, unsigned int model) 4161 { 4162 if (!genuine_intel) 4163 return 0; 4164 4165 switch (model) { 4166 case INTEL_FAM6_HASWELL_ULT: /* HSW */ 4167 case INTEL_FAM6_BROADWELL_CORE: /* BDW */ 4168 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4169 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 4170 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 4171 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 4172 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 4173 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4174 case INTEL_FAM6_ATOM_GEMINI_LAKE: 4175 return 1; 4176 } 4177 return 0; 4178 } 4179 4180 /* 4181 * SKL adds support for additional MSRS: 4182 * 4183 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 4184 * MSR_PKG_ANY_CORE_C0_RES 0x00000659 4185 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 4186 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 4187 */ 4188 int has_skl_msrs(unsigned int family, unsigned int model) 4189 { 4190 if (!genuine_intel) 4191 return 0; 4192 4193 switch (model) { 4194 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4195 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 4196 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 4197 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 4198 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 4199 return 1; 4200 } 4201 return 0; 4202 } 4203 4204 int is_slm(unsigned int family, unsigned int model) 4205 { 4206 if (!genuine_intel) 4207 return 0; 4208 switch (model) { 4209 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ 4210 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ 4211 return 1; 4212 } 4213 return 0; 4214 } 4215 4216 int is_knl(unsigned int family, unsigned int model) 4217 { 4218 if (!genuine_intel) 4219 return 0; 4220 switch (model) { 4221 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ 4222 case INTEL_FAM6_XEON_PHI_KNM: 4223 return 1; 4224 } 4225 return 0; 4226 } 4227 4228 int is_cnl(unsigned int family, unsigned int model) 4229 { 4230 if (!genuine_intel) 4231 return 0; 4232 4233 switch (model) { 4234 case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ 4235 return 1; 4236 } 4237 4238 return 0; 4239 } 4240 4241 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model) 4242 { 4243 if (is_knl(family, model)) 4244 return 1024; 4245 return 1; 4246 } 4247 4248 #define SLM_BCLK_FREQS 5 4249 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0}; 4250 4251 double slm_bclk(void) 4252 { 4253 unsigned long long msr = 3; 4254 unsigned int i; 4255 double freq; 4256 4257 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) 4258 fprintf(outf, "SLM BCLK: unknown\n"); 4259 4260 i = msr & 0xf; 4261 if (i >= SLM_BCLK_FREQS) { 4262 fprintf(outf, "SLM BCLK[%d] invalid\n", i); 4263 i = 3; 4264 } 4265 freq = slm_freq_table[i]; 4266 4267 if (!quiet) 4268 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); 4269 4270 return freq; 4271 } 4272 4273 double discover_bclk(unsigned int family, unsigned int model) 4274 { 4275 if (has_snb_msrs(family, model) || is_knl(family, model)) 4276 return 100.00; 4277 else if (is_slm(family, model)) 4278 return slm_bclk(); 4279 else 4280 return 133.33; 4281 } 4282 4283 /* 4284 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where 4285 * the Thermal Control Circuit (TCC) activates. 4286 * This is usually equal to tjMax. 4287 * 4288 * Older processors do not have this MSR, so there we guess, 4289 * but also allow cmdline over-ride with -T. 4290 * 4291 * Several MSR temperature values are in units of degrees-C 4292 * below this value, including the Digital Thermal Sensor (DTS), 4293 * Package Thermal Management Sensor (PTM), and thermal event thresholds. 4294 */ 4295 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) 4296 { 4297 unsigned long long msr; 4298 unsigned int target_c_local; 4299 int cpu; 4300 4301 /* tcc_activation_temp is used only for dts or ptm */ 4302 if (!(do_dts || do_ptm)) 4303 return 0; 4304 4305 /* this is a per-package concept */ 4306 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) 4307 return 0; 4308 4309 cpu = t->cpu_id; 4310 if (cpu_migrate(cpu)) { 4311 fprintf(outf, "Could not migrate to CPU %d\n", cpu); 4312 return -1; 4313 } 4314 4315 if (tcc_activation_temp_override != 0) { 4316 tcc_activation_temp = tcc_activation_temp_override; 4317 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", 4318 cpu, tcc_activation_temp); 4319 return 0; 4320 } 4321 4322 /* Temperature Target MSR is Nehalem and newer only */ 4323 if (!do_nhm_platform_info) 4324 goto guess; 4325 4326 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) 4327 goto guess; 4328 4329 target_c_local = (msr >> 16) & 0xFF; 4330 4331 if (!quiet) 4332 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", 4333 cpu, msr, target_c_local); 4334 4335 if (!target_c_local) 4336 goto guess; 4337 4338 tcc_activation_temp = target_c_local; 4339 4340 return 0; 4341 4342 guess: 4343 tcc_activation_temp = TJMAX_DEFAULT; 4344 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", 4345 cpu, tcc_activation_temp); 4346 4347 return 0; 4348 } 4349 4350 void decode_feature_control_msr(void) 4351 { 4352 unsigned long long msr; 4353 4354 if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr)) 4355 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", 4356 base_cpu, msr, 4357 msr & FEATURE_CONTROL_LOCKED ? "" : "UN-", 4358 msr & (1 << 18) ? "SGX" : ""); 4359 } 4360 4361 void decode_misc_enable_msr(void) 4362 { 4363 unsigned long long msr; 4364 4365 if (!genuine_intel) 4366 return; 4367 4368 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) 4369 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n", 4370 base_cpu, msr, 4371 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-", 4372 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-", 4373 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-", 4374 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "", 4375 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : ""); 4376 } 4377 4378 void decode_misc_feature_control(void) 4379 { 4380 unsigned long long msr; 4381 4382 if (!has_misc_feature_control) 4383 return; 4384 4385 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr)) 4386 fprintf(outf, "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n", 4387 base_cpu, msr, 4388 msr & (0 << 0) ? "No-" : "", 4389 msr & (1 << 0) ? "No-" : "", 4390 msr & (2 << 0) ? "No-" : "", 4391 msr & (3 << 0) ? "No-" : ""); 4392 } 4393 /* 4394 * Decode MSR_MISC_PWR_MGMT 4395 * 4396 * Decode the bits according to the Nehalem documentation 4397 * bit[0] seems to continue to have same meaning going forward 4398 * bit[1] less so... 4399 */ 4400 void decode_misc_pwr_mgmt_msr(void) 4401 { 4402 unsigned long long msr; 4403 4404 if (!do_nhm_platform_info) 4405 return; 4406 4407 if (no_MSR_MISC_PWR_MGMT) 4408 return; 4409 4410 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) 4411 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n", 4412 base_cpu, msr, 4413 msr & (1 << 0) ? "DIS" : "EN", 4414 msr & (1 << 1) ? "EN" : "DIS", 4415 msr & (1 << 8) ? "EN" : "DIS"); 4416 } 4417 /* 4418 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG 4419 * 4420 * This MSRs are present on Silvermont processors, 4421 * Intel Atom processor E3000 series (Baytrail), and friends. 4422 */ 4423 void decode_c6_demotion_policy_msr(void) 4424 { 4425 unsigned long long msr; 4426 4427 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr)) 4428 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n", 4429 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 4430 4431 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr)) 4432 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n", 4433 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS"); 4434 } 4435 4436 void process_cpuid() 4437 { 4438 unsigned int eax, ebx, ecx, edx, max_level, max_extended_level; 4439 unsigned int fms, family, model, stepping; 4440 unsigned int has_turbo; 4441 4442 eax = ebx = ecx = edx = 0; 4443 4444 __cpuid(0, max_level, ebx, ecx, edx); 4445 4446 if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e) 4447 genuine_intel = 1; 4448 4449 if (!quiet) 4450 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ", 4451 (char *)&ebx, (char *)&edx, (char *)&ecx); 4452 4453 __cpuid(1, fms, ebx, ecx, edx); 4454 family = (fms >> 8) & 0xf; 4455 model = (fms >> 4) & 0xf; 4456 stepping = fms & 0xf; 4457 if (family == 6 || family == 0xf) 4458 model += ((fms >> 16) & 0xf) << 4; 4459 4460 if (!quiet) { 4461 fprintf(outf, "%d CPUID levels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n", 4462 max_level, family, model, stepping, family, model, stepping); 4463 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n", 4464 ecx & (1 << 0) ? "SSE3" : "-", 4465 ecx & (1 << 3) ? "MONITOR" : "-", 4466 ecx & (1 << 6) ? "SMX" : "-", 4467 ecx & (1 << 7) ? "EIST" : "-", 4468 ecx & (1 << 8) ? "TM2" : "-", 4469 edx & (1 << 4) ? "TSC" : "-", 4470 edx & (1 << 5) ? "MSR" : "-", 4471 edx & (1 << 22) ? "ACPI-TM" : "-", 4472 edx & (1 << 28) ? "HT" : "-", 4473 edx & (1 << 29) ? "TM" : "-"); 4474 } 4475 4476 if (!(edx & (1 << 5))) 4477 errx(1, "CPUID: no MSR"); 4478 4479 /* 4480 * check max extended function levels of CPUID. 4481 * This is needed to check for invariant TSC. 4482 * This check is valid for both Intel and AMD. 4483 */ 4484 ebx = ecx = edx = 0; 4485 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); 4486 4487 if (max_extended_level >= 0x80000007) { 4488 4489 /* 4490 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 4491 * this check is valid for both Intel and AMD 4492 */ 4493 __cpuid(0x80000007, eax, ebx, ecx, edx); 4494 has_invariant_tsc = edx & (1 << 8); 4495 } 4496 4497 /* 4498 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 4499 * this check is valid for both Intel and AMD 4500 */ 4501 4502 __cpuid(0x6, eax, ebx, ecx, edx); 4503 has_aperf = ecx & (1 << 0); 4504 if (has_aperf) { 4505 BIC_PRESENT(BIC_Avg_MHz); 4506 BIC_PRESENT(BIC_Busy); 4507 BIC_PRESENT(BIC_Bzy_MHz); 4508 } 4509 do_dts = eax & (1 << 0); 4510 if (do_dts) 4511 BIC_PRESENT(BIC_CoreTmp); 4512 has_turbo = eax & (1 << 1); 4513 do_ptm = eax & (1 << 6); 4514 if (do_ptm) 4515 BIC_PRESENT(BIC_PkgTmp); 4516 has_hwp = eax & (1 << 7); 4517 has_hwp_notify = eax & (1 << 8); 4518 has_hwp_activity_window = eax & (1 << 9); 4519 has_hwp_epp = eax & (1 << 10); 4520 has_hwp_pkg = eax & (1 << 11); 4521 has_epb = ecx & (1 << 3); 4522 4523 if (!quiet) 4524 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, " 4525 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", 4526 has_aperf ? "" : "No-", 4527 has_turbo ? "" : "No-", 4528 do_dts ? "" : "No-", 4529 do_ptm ? "" : "No-", 4530 has_hwp ? "" : "No-", 4531 has_hwp_notify ? "" : "No-", 4532 has_hwp_activity_window ? "" : "No-", 4533 has_hwp_epp ? "" : "No-", 4534 has_hwp_pkg ? "" : "No-", 4535 has_epb ? "" : "No-"); 4536 4537 if (!quiet) 4538 decode_misc_enable_msr(); 4539 4540 4541 if (max_level >= 0x7 && !quiet) { 4542 int has_sgx; 4543 4544 ecx = 0; 4545 4546 __cpuid_count(0x7, 0, eax, ebx, ecx, edx); 4547 4548 has_sgx = ebx & (1 << 2); 4549 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-"); 4550 4551 if (has_sgx) 4552 decode_feature_control_msr(); 4553 } 4554 4555 if (max_level >= 0x15) { 4556 unsigned int eax_crystal; 4557 unsigned int ebx_tsc; 4558 4559 /* 4560 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz 4561 */ 4562 eax_crystal = ebx_tsc = crystal_hz = edx = 0; 4563 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); 4564 4565 if (ebx_tsc != 0) { 4566 4567 if (!quiet && (ebx != 0)) 4568 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", 4569 eax_crystal, ebx_tsc, crystal_hz); 4570 4571 if (crystal_hz == 0) 4572 switch(model) { 4573 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ 4574 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ 4575 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ 4576 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ 4577 crystal_hz = 24000000; /* 24.0 MHz */ 4578 break; 4579 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */ 4580 crystal_hz = 25000000; /* 25.0 MHz */ 4581 break; 4582 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ 4583 case INTEL_FAM6_ATOM_GEMINI_LAKE: 4584 crystal_hz = 19200000; /* 19.2 MHz */ 4585 break; 4586 default: 4587 crystal_hz = 0; 4588 } 4589 4590 if (crystal_hz) { 4591 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal; 4592 if (!quiet) 4593 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", 4594 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); 4595 } 4596 } 4597 } 4598 if (max_level >= 0x16) { 4599 unsigned int base_mhz, max_mhz, bus_mhz, edx; 4600 4601 /* 4602 * CPUID 16H Base MHz, Max MHz, Bus MHz 4603 */ 4604 base_mhz = max_mhz = bus_mhz = edx = 0; 4605 4606 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); 4607 if (!quiet) 4608 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", 4609 base_mhz, max_mhz, bus_mhz); 4610 } 4611 4612 if (has_aperf) 4613 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model); 4614 4615 BIC_PRESENT(BIC_IRQ); 4616 BIC_PRESENT(BIC_TSC_MHz); 4617 4618 if (probe_nhm_msrs(family, model)) { 4619 do_nhm_platform_info = 1; 4620 BIC_PRESENT(BIC_CPU_c1); 4621 BIC_PRESENT(BIC_CPU_c3); 4622 BIC_PRESENT(BIC_CPU_c6); 4623 BIC_PRESENT(BIC_SMI); 4624 } 4625 do_snb_cstates = has_snb_msrs(family, model); 4626 4627 if (do_snb_cstates) 4628 BIC_PRESENT(BIC_CPU_c7); 4629 4630 do_irtl_snb = has_snb_msrs(family, model); 4631 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2)) 4632 BIC_PRESENT(BIC_Pkgpc2); 4633 if (pkg_cstate_limit >= PCL__3) 4634 BIC_PRESENT(BIC_Pkgpc3); 4635 if (pkg_cstate_limit >= PCL__6) 4636 BIC_PRESENT(BIC_Pkgpc6); 4637 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7)) 4638 BIC_PRESENT(BIC_Pkgpc7); 4639 if (has_slv_msrs(family, model)) { 4640 BIC_NOT_PRESENT(BIC_Pkgpc2); 4641 BIC_NOT_PRESENT(BIC_Pkgpc3); 4642 BIC_PRESENT(BIC_Pkgpc6); 4643 BIC_NOT_PRESENT(BIC_Pkgpc7); 4644 BIC_PRESENT(BIC_Mod_c6); 4645 use_c1_residency_msr = 1; 4646 } 4647 if (is_dnv(family, model)) { 4648 BIC_PRESENT(BIC_CPU_c1); 4649 BIC_NOT_PRESENT(BIC_CPU_c3); 4650 BIC_NOT_PRESENT(BIC_Pkgpc3); 4651 BIC_NOT_PRESENT(BIC_CPU_c7); 4652 BIC_NOT_PRESENT(BIC_Pkgpc7); 4653 use_c1_residency_msr = 1; 4654 } 4655 if (is_skx(family, model)) { 4656 BIC_NOT_PRESENT(BIC_CPU_c3); 4657 BIC_NOT_PRESENT(BIC_Pkgpc3); 4658 BIC_NOT_PRESENT(BIC_CPU_c7); 4659 BIC_NOT_PRESENT(BIC_Pkgpc7); 4660 } 4661 if (is_bdx(family, model)) { 4662 BIC_NOT_PRESENT(BIC_CPU_c7); 4663 BIC_NOT_PRESENT(BIC_Pkgpc7); 4664 } 4665 if (has_hsw_msrs(family, model)) { 4666 BIC_PRESENT(BIC_Pkgpc8); 4667 BIC_PRESENT(BIC_Pkgpc9); 4668 BIC_PRESENT(BIC_Pkgpc10); 4669 } 4670 do_irtl_hsw = has_hsw_msrs(family, model); 4671 if (has_skl_msrs(family, model)) { 4672 BIC_PRESENT(BIC_Totl_c0); 4673 BIC_PRESENT(BIC_Any_c0); 4674 BIC_PRESENT(BIC_GFX_c0); 4675 BIC_PRESENT(BIC_CPUGFX); 4676 } 4677 do_slm_cstates = is_slm(family, model); 4678 do_knl_cstates = is_knl(family, model); 4679 do_cnl_cstates = is_cnl(family, model); 4680 4681 if (!quiet) 4682 decode_misc_pwr_mgmt_msr(); 4683 4684 if (!quiet && has_slv_msrs(family, model)) 4685 decode_c6_demotion_policy_msr(); 4686 4687 rapl_probe(family, model); 4688 perf_limit_reasons_probe(family, model); 4689 automatic_cstate_conversion_probe(family, model); 4690 4691 if (!quiet) 4692 dump_cstate_pstate_config_info(family, model); 4693 4694 if (!quiet) 4695 dump_sysfs_cstate_config(); 4696 if (!quiet) 4697 dump_sysfs_pstate_config(); 4698 4699 if (has_skl_msrs(family, model)) 4700 calculate_tsc_tweak(); 4701 4702 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK)) 4703 BIC_PRESENT(BIC_GFX_rc6); 4704 4705 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK)) 4706 BIC_PRESENT(BIC_GFXMHz); 4707 4708 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK)) 4709 BIC_PRESENT(BIC_CPU_LPI); 4710 else 4711 BIC_NOT_PRESENT(BIC_CPU_LPI); 4712 4713 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us", R_OK)) 4714 BIC_PRESENT(BIC_SYS_LPI); 4715 else 4716 BIC_NOT_PRESENT(BIC_SYS_LPI); 4717 4718 if (!quiet) 4719 decode_misc_feature_control(); 4720 4721 return; 4722 } 4723 4724 /* 4725 * in /dev/cpu/ return success for names that are numbers 4726 * ie. filter out ".", "..", "microcode". 4727 */ 4728 int dir_filter(const struct dirent *dirp) 4729 { 4730 if (isdigit(dirp->d_name[0])) 4731 return 1; 4732 else 4733 return 0; 4734 } 4735 4736 int open_dev_cpu_msr(int dummy1) 4737 { 4738 return 0; 4739 } 4740 4741 void topology_probe() 4742 { 4743 int i; 4744 int max_core_id = 0; 4745 int max_package_id = 0; 4746 int max_siblings = 0; 4747 4748 /* Initialize num_cpus, max_cpu_num */ 4749 set_max_cpu_num(); 4750 topo.num_cpus = 0; 4751 for_all_proc_cpus(count_cpus); 4752 if (!summary_only && topo.num_cpus > 1) 4753 BIC_PRESENT(BIC_CPU); 4754 4755 if (debug > 1) 4756 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); 4757 4758 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); 4759 if (cpus == NULL) 4760 err(1, "calloc cpus"); 4761 4762 /* 4763 * Allocate and initialize cpu_present_set 4764 */ 4765 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); 4766 if (cpu_present_set == NULL) 4767 err(3, "CPU_ALLOC"); 4768 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 4769 CPU_ZERO_S(cpu_present_setsize, cpu_present_set); 4770 for_all_proc_cpus(mark_cpu_present); 4771 4772 /* 4773 * Validate that all cpus in cpu_subset are also in cpu_present_set 4774 */ 4775 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) { 4776 if (CPU_ISSET_S(i, cpu_subset_size, cpu_subset)) 4777 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set)) 4778 err(1, "cpu%d not present", i); 4779 } 4780 4781 /* 4782 * Allocate and initialize cpu_affinity_set 4783 */ 4784 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); 4785 if (cpu_affinity_set == NULL) 4786 err(3, "CPU_ALLOC"); 4787 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); 4788 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); 4789 4790 for_all_proc_cpus(init_thread_id); 4791 4792 /* 4793 * For online cpus 4794 * find max_core_id, max_package_id 4795 */ 4796 for (i = 0; i <= topo.max_cpu_num; ++i) { 4797 int siblings; 4798 4799 if (cpu_is_not_present(i)) { 4800 if (debug > 1) 4801 fprintf(outf, "cpu%d NOT PRESENT\n", i); 4802 continue; 4803 } 4804 4805 cpus[i].logical_cpu_id = i; 4806 4807 /* get package information */ 4808 cpus[i].physical_package_id = get_physical_package_id(i); 4809 if (cpus[i].physical_package_id > max_package_id) 4810 max_package_id = cpus[i].physical_package_id; 4811 4812 /* get numa node information */ 4813 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]); 4814 if (cpus[i].physical_node_id > topo.max_node_num) 4815 topo.max_node_num = cpus[i].physical_node_id; 4816 4817 /* get core information */ 4818 cpus[i].physical_core_id = get_core_id(i); 4819 if (cpus[i].physical_core_id > max_core_id) 4820 max_core_id = cpus[i].physical_core_id; 4821 4822 /* get thread information */ 4823 siblings = get_thread_siblings(&cpus[i]); 4824 if (siblings > max_siblings) 4825 max_siblings = siblings; 4826 if (cpus[i].thread_id != -1) 4827 topo.num_cores++; 4828 4829 if (debug > 1) 4830 fprintf(outf, 4831 "cpu %d pkg %d node %d core %d thread %d\n", 4832 i, cpus[i].physical_package_id, 4833 cpus[i].physical_node_id, 4834 cpus[i].physical_core_id, 4835 cpus[i].thread_id); 4836 } 4837 4838 topo.cores_per_node = max_core_id + 1; 4839 if (debug > 1) 4840 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", 4841 max_core_id, topo.cores_per_node); 4842 if (!summary_only && topo.cores_per_node > 1) 4843 BIC_PRESENT(BIC_Core); 4844 4845 topo.num_packages = max_package_id + 1; 4846 if (debug > 1) 4847 fprintf(outf, "max_package_id %d, sizing for %d packages\n", 4848 max_package_id, topo.num_packages); 4849 if (!summary_only && topo.num_packages > 1) 4850 BIC_PRESENT(BIC_Package); 4851 4852 set_node_data(); 4853 if (debug > 1) 4854 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg); 4855 if (!summary_only && topo.nodes_per_pkg > 1) 4856 BIC_PRESENT(BIC_Node); 4857 4858 topo.threads_per_core = max_siblings; 4859 if (debug > 1) 4860 fprintf(outf, "max_siblings %d\n", max_siblings); 4861 } 4862 4863 void 4864 allocate_counters(struct thread_data **t, struct core_data **c, 4865 struct pkg_data **p) 4866 { 4867 int i; 4868 int num_cores = topo.cores_per_node * topo.nodes_per_pkg * 4869 topo.num_packages; 4870 int num_threads = topo.threads_per_core * num_cores; 4871 4872 *t = calloc(num_threads, sizeof(struct thread_data)); 4873 if (*t == NULL) 4874 goto error; 4875 4876 for (i = 0; i < num_threads; i++) 4877 (*t)[i].cpu_id = -1; 4878 4879 *c = calloc(num_cores, sizeof(struct core_data)); 4880 if (*c == NULL) 4881 goto error; 4882 4883 for (i = 0; i < num_cores; i++) 4884 (*c)[i].core_id = -1; 4885 4886 *p = calloc(topo.num_packages, sizeof(struct pkg_data)); 4887 if (*p == NULL) 4888 goto error; 4889 4890 for (i = 0; i < topo.num_packages; i++) 4891 (*p)[i].package_id = i; 4892 4893 return; 4894 error: 4895 err(1, "calloc counters"); 4896 } 4897 /* 4898 * init_counter() 4899 * 4900 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE 4901 */ 4902 void init_counter(struct thread_data *thread_base, struct core_data *core_base, 4903 struct pkg_data *pkg_base, int cpu_id) 4904 { 4905 int pkg_id = cpus[cpu_id].physical_package_id; 4906 int node_id = cpus[cpu_id].logical_node_id; 4907 int core_id = cpus[cpu_id].physical_core_id; 4908 int thread_id = cpus[cpu_id].thread_id; 4909 struct thread_data *t; 4910 struct core_data *c; 4911 struct pkg_data *p; 4912 4913 4914 /* Workaround for systems where physical_node_id==-1 4915 * and logical_node_id==(-1 - topo.num_cpus) 4916 */ 4917 if (node_id < 0) 4918 node_id = 0; 4919 4920 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id); 4921 c = GET_CORE(core_base, core_id, node_id, pkg_id); 4922 p = GET_PKG(pkg_base, pkg_id); 4923 4924 t->cpu_id = cpu_id; 4925 if (thread_id == 0) { 4926 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; 4927 if (cpu_is_first_core_in_package(cpu_id)) 4928 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; 4929 } 4930 4931 c->core_id = core_id; 4932 p->package_id = pkg_id; 4933 } 4934 4935 4936 int initialize_counters(int cpu_id) 4937 { 4938 init_counter(EVEN_COUNTERS, cpu_id); 4939 init_counter(ODD_COUNTERS, cpu_id); 4940 return 0; 4941 } 4942 4943 void allocate_output_buffer() 4944 { 4945 output_buffer = calloc(1, (1 + topo.num_cpus) * 1024); 4946 outp = output_buffer; 4947 if (outp == NULL) 4948 err(-1, "calloc output buffer"); 4949 } 4950 void allocate_fd_percpu(void) 4951 { 4952 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 4953 if (fd_percpu == NULL) 4954 err(-1, "calloc fd_percpu"); 4955 } 4956 void allocate_irq_buffers(void) 4957 { 4958 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); 4959 if (irq_column_2_cpu == NULL) 4960 err(-1, "calloc %d", topo.num_cpus); 4961 4962 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int)); 4963 if (irqs_per_cpu == NULL) 4964 err(-1, "calloc %d", topo.max_cpu_num + 1); 4965 } 4966 void setup_all_buffers(void) 4967 { 4968 topology_probe(); 4969 allocate_irq_buffers(); 4970 allocate_fd_percpu(); 4971 allocate_counters(&thread_even, &core_even, &package_even); 4972 allocate_counters(&thread_odd, &core_odd, &package_odd); 4973 allocate_output_buffer(); 4974 for_all_proc_cpus(initialize_counters); 4975 } 4976 4977 void set_base_cpu(void) 4978 { 4979 base_cpu = sched_getcpu(); 4980 if (base_cpu < 0) 4981 err(-ENODEV, "No valid cpus found"); 4982 4983 if (debug > 1) 4984 fprintf(outf, "base_cpu = %d\n", base_cpu); 4985 } 4986 4987 void turbostat_init() 4988 { 4989 setup_all_buffers(); 4990 set_base_cpu(); 4991 check_dev_msr(); 4992 check_permissions(); 4993 process_cpuid(); 4994 4995 4996 if (!quiet) 4997 for_all_cpus(print_hwp, ODD_COUNTERS); 4998 4999 if (!quiet) 5000 for_all_cpus(print_epb, ODD_COUNTERS); 5001 5002 if (!quiet) 5003 for_all_cpus(print_perf_limit, ODD_COUNTERS); 5004 5005 if (!quiet) 5006 for_all_cpus(print_rapl, ODD_COUNTERS); 5007 5008 for_all_cpus(set_temperature_target, ODD_COUNTERS); 5009 5010 if (!quiet) 5011 for_all_cpus(print_thermal, ODD_COUNTERS); 5012 5013 if (!quiet && do_irtl_snb) 5014 print_irtl(); 5015 } 5016 5017 int fork_it(char **argv) 5018 { 5019 pid_t child_pid; 5020 int status; 5021 5022 snapshot_proc_sysfs_files(); 5023 status = for_all_cpus(get_counters, EVEN_COUNTERS); 5024 first_counter_read = 0; 5025 if (status) 5026 exit(status); 5027 /* clear affinity side-effect of get_counters() */ 5028 sched_setaffinity(0, cpu_present_setsize, cpu_present_set); 5029 gettimeofday(&tv_even, (struct timezone *)NULL); 5030 5031 child_pid = fork(); 5032 if (!child_pid) { 5033 /* child */ 5034 execvp(argv[0], argv); 5035 err(errno, "exec %s", argv[0]); 5036 } else { 5037 5038 /* parent */ 5039 if (child_pid == -1) 5040 err(1, "fork"); 5041 5042 signal(SIGINT, SIG_IGN); 5043 signal(SIGQUIT, SIG_IGN); 5044 if (waitpid(child_pid, &status, 0) == -1) 5045 err(status, "waitpid"); 5046 } 5047 /* 5048 * n.b. fork_it() does not check for errors from for_all_cpus() 5049 * because re-starting is problematic when forking 5050 */ 5051 snapshot_proc_sysfs_files(); 5052 for_all_cpus(get_counters, ODD_COUNTERS); 5053 gettimeofday(&tv_odd, (struct timezone *)NULL); 5054 timersub(&tv_odd, &tv_even, &tv_delta); 5055 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) 5056 fprintf(outf, "%s: Counter reset detected\n", progname); 5057 else { 5058 compute_average(EVEN_COUNTERS); 5059 format_all_counters(EVEN_COUNTERS); 5060 } 5061 5062 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0); 5063 5064 flush_output_stderr(); 5065 5066 return status; 5067 } 5068 5069 int get_and_dump_counters(void) 5070 { 5071 int status; 5072 5073 snapshot_proc_sysfs_files(); 5074 status = for_all_cpus(get_counters, ODD_COUNTERS); 5075 if (status) 5076 return status; 5077 5078 status = for_all_cpus(dump_counters, ODD_COUNTERS); 5079 if (status) 5080 return status; 5081 5082 flush_output_stdout(); 5083 5084 return status; 5085 } 5086 5087 void print_version() { 5088 fprintf(outf, "turbostat version 18.06.01" 5089 " - Len Brown <lenb@kernel.org>\n"); 5090 } 5091 5092 int add_counter(unsigned int msr_num, char *path, char *name, 5093 unsigned int width, enum counter_scope scope, 5094 enum counter_type type, enum counter_format format, int flags) 5095 { 5096 struct msr_counter *msrp; 5097 5098 msrp = calloc(1, sizeof(struct msr_counter)); 5099 if (msrp == NULL) { 5100 perror("calloc"); 5101 exit(1); 5102 } 5103 5104 msrp->msr_num = msr_num; 5105 strncpy(msrp->name, name, NAME_BYTES); 5106 if (path) 5107 strncpy(msrp->path, path, PATH_BYTES); 5108 msrp->width = width; 5109 msrp->type = type; 5110 msrp->format = format; 5111 msrp->flags = flags; 5112 5113 switch (scope) { 5114 5115 case SCOPE_CPU: 5116 msrp->next = sys.tp; 5117 sys.tp = msrp; 5118 sys.added_thread_counters++; 5119 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) { 5120 fprintf(stderr, "exceeded max %d added thread counters\n", 5121 MAX_ADDED_COUNTERS); 5122 exit(-1); 5123 } 5124 break; 5125 5126 case SCOPE_CORE: 5127 msrp->next = sys.cp; 5128 sys.cp = msrp; 5129 sys.added_core_counters++; 5130 if (sys.added_core_counters > MAX_ADDED_COUNTERS) { 5131 fprintf(stderr, "exceeded max %d added core counters\n", 5132 MAX_ADDED_COUNTERS); 5133 exit(-1); 5134 } 5135 break; 5136 5137 case SCOPE_PACKAGE: 5138 msrp->next = sys.pp; 5139 sys.pp = msrp; 5140 sys.added_package_counters++; 5141 if (sys.added_package_counters > MAX_ADDED_COUNTERS) { 5142 fprintf(stderr, "exceeded max %d added package counters\n", 5143 MAX_ADDED_COUNTERS); 5144 exit(-1); 5145 } 5146 break; 5147 } 5148 5149 return 0; 5150 } 5151 5152 void parse_add_command(char *add_command) 5153 { 5154 int msr_num = 0; 5155 char *path = NULL; 5156 char name_buffer[NAME_BYTES] = ""; 5157 int width = 64; 5158 int fail = 0; 5159 enum counter_scope scope = SCOPE_CPU; 5160 enum counter_type type = COUNTER_CYCLES; 5161 enum counter_format format = FORMAT_DELTA; 5162 5163 while (add_command) { 5164 5165 if (sscanf(add_command, "msr0x%x", &msr_num) == 1) 5166 goto next; 5167 5168 if (sscanf(add_command, "msr%d", &msr_num) == 1) 5169 goto next; 5170 5171 if (*add_command == '/') { 5172 path = add_command; 5173 goto next; 5174 } 5175 5176 if (sscanf(add_command, "u%d", &width) == 1) { 5177 if ((width == 32) || (width == 64)) 5178 goto next; 5179 width = 64; 5180 } 5181 if (!strncmp(add_command, "cpu", strlen("cpu"))) { 5182 scope = SCOPE_CPU; 5183 goto next; 5184 } 5185 if (!strncmp(add_command, "core", strlen("core"))) { 5186 scope = SCOPE_CORE; 5187 goto next; 5188 } 5189 if (!strncmp(add_command, "package", strlen("package"))) { 5190 scope = SCOPE_PACKAGE; 5191 goto next; 5192 } 5193 if (!strncmp(add_command, "cycles", strlen("cycles"))) { 5194 type = COUNTER_CYCLES; 5195 goto next; 5196 } 5197 if (!strncmp(add_command, "seconds", strlen("seconds"))) { 5198 type = COUNTER_SECONDS; 5199 goto next; 5200 } 5201 if (!strncmp(add_command, "usec", strlen("usec"))) { 5202 type = COUNTER_USEC; 5203 goto next; 5204 } 5205 if (!strncmp(add_command, "raw", strlen("raw"))) { 5206 format = FORMAT_RAW; 5207 goto next; 5208 } 5209 if (!strncmp(add_command, "delta", strlen("delta"))) { 5210 format = FORMAT_DELTA; 5211 goto next; 5212 } 5213 if (!strncmp(add_command, "percent", strlen("percent"))) { 5214 format = FORMAT_PERCENT; 5215 goto next; 5216 } 5217 5218 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */ 5219 char *eos; 5220 5221 eos = strchr(name_buffer, ','); 5222 if (eos) 5223 *eos = '\0'; 5224 goto next; 5225 } 5226 5227 next: 5228 add_command = strchr(add_command, ','); 5229 if (add_command) { 5230 *add_command = '\0'; 5231 add_command++; 5232 } 5233 5234 } 5235 if ((msr_num == 0) && (path == NULL)) { 5236 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n"); 5237 fail++; 5238 } 5239 5240 /* generate default column header */ 5241 if (*name_buffer == '\0') { 5242 if (width == 32) 5243 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 5244 else 5245 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : ""); 5246 } 5247 5248 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0)) 5249 fail++; 5250 5251 if (fail) { 5252 help(); 5253 exit(1); 5254 } 5255 } 5256 5257 int is_deferred_skip(char *name) 5258 { 5259 int i; 5260 5261 for (i = 0; i < deferred_skip_index; ++i) 5262 if (!strcmp(name, deferred_skip_names[i])) 5263 return 1; 5264 return 0; 5265 } 5266 5267 void probe_sysfs(void) 5268 { 5269 char path[64]; 5270 char name_buf[16]; 5271 FILE *input; 5272 int state; 5273 char *sp; 5274 5275 if (!DO_BIC(BIC_sysfs)) 5276 return; 5277 5278 for (state = 10; state >= 0; --state) { 5279 5280 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 5281 base_cpu, state); 5282 input = fopen(path, "r"); 5283 if (input == NULL) 5284 continue; 5285 fgets(name_buf, sizeof(name_buf), input); 5286 5287 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 5288 sp = strchr(name_buf, '-'); 5289 if (!sp) 5290 sp = strchrnul(name_buf, '\n'); 5291 *sp = '%'; 5292 *(sp + 1) = '\0'; 5293 5294 fclose(input); 5295 5296 sprintf(path, "cpuidle/state%d/time", state); 5297 5298 if (is_deferred_skip(name_buf)) 5299 continue; 5300 5301 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC, 5302 FORMAT_PERCENT, SYSFS_PERCPU); 5303 } 5304 5305 for (state = 10; state >= 0; --state) { 5306 5307 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", 5308 base_cpu, state); 5309 input = fopen(path, "r"); 5310 if (input == NULL) 5311 continue; 5312 fgets(name_buf, sizeof(name_buf), input); 5313 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */ 5314 sp = strchr(name_buf, '-'); 5315 if (!sp) 5316 sp = strchrnul(name_buf, '\n'); 5317 *sp = '\0'; 5318 fclose(input); 5319 5320 sprintf(path, "cpuidle/state%d/usage", state); 5321 5322 if (is_deferred_skip(name_buf)) 5323 continue; 5324 5325 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS, 5326 FORMAT_DELTA, SYSFS_PERCPU); 5327 } 5328 5329 } 5330 5331 5332 /* 5333 * parse cpuset with following syntax 5334 * 1,2,4..6,8-10 and set bits in cpu_subset 5335 */ 5336 void parse_cpu_command(char *optarg) 5337 { 5338 unsigned int start, end; 5339 char *next; 5340 5341 if (!strcmp(optarg, "core")) { 5342 if (cpu_subset) 5343 goto error; 5344 show_core_only++; 5345 return; 5346 } 5347 if (!strcmp(optarg, "package")) { 5348 if (cpu_subset) 5349 goto error; 5350 show_pkg_only++; 5351 return; 5352 } 5353 if (show_core_only || show_pkg_only) 5354 goto error; 5355 5356 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS); 5357 if (cpu_subset == NULL) 5358 err(3, "CPU_ALLOC"); 5359 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS); 5360 5361 CPU_ZERO_S(cpu_subset_size, cpu_subset); 5362 5363 next = optarg; 5364 5365 while (next && *next) { 5366 5367 if (*next == '-') /* no negative cpu numbers */ 5368 goto error; 5369 5370 start = strtoul(next, &next, 10); 5371 5372 if (start >= CPU_SUBSET_MAXCPUS) 5373 goto error; 5374 CPU_SET_S(start, cpu_subset_size, cpu_subset); 5375 5376 if (*next == '\0') 5377 break; 5378 5379 if (*next == ',') { 5380 next += 1; 5381 continue; 5382 } 5383 5384 if (*next == '-') { 5385 next += 1; /* start range */ 5386 } else if (*next == '.') { 5387 next += 1; 5388 if (*next == '.') 5389 next += 1; /* start range */ 5390 else 5391 goto error; 5392 } 5393 5394 end = strtoul(next, &next, 10); 5395 if (end <= start) 5396 goto error; 5397 5398 while (++start <= end) { 5399 if (start >= CPU_SUBSET_MAXCPUS) 5400 goto error; 5401 CPU_SET_S(start, cpu_subset_size, cpu_subset); 5402 } 5403 5404 if (*next == ',') 5405 next += 1; 5406 else if (*next != '\0') 5407 goto error; 5408 } 5409 5410 return; 5411 5412 error: 5413 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg); 5414 help(); 5415 exit(-1); 5416 } 5417 5418 5419 void cmdline(int argc, char **argv) 5420 { 5421 int opt; 5422 int option_index = 0; 5423 static struct option long_options[] = { 5424 {"add", required_argument, 0, 'a'}, 5425 {"cpu", required_argument, 0, 'c'}, 5426 {"Dump", no_argument, 0, 'D'}, 5427 {"debug", no_argument, 0, 'd'}, /* internal, not documented */ 5428 {"enable", required_argument, 0, 'e'}, 5429 {"interval", required_argument, 0, 'i'}, 5430 {"num_iterations", required_argument, 0, 'n'}, 5431 {"help", no_argument, 0, 'h'}, 5432 {"hide", required_argument, 0, 'H'}, // meh, -h taken by --help 5433 {"Joules", no_argument, 0, 'J'}, 5434 {"list", no_argument, 0, 'l'}, 5435 {"out", required_argument, 0, 'o'}, 5436 {"quiet", no_argument, 0, 'q'}, 5437 {"show", required_argument, 0, 's'}, 5438 {"Summary", no_argument, 0, 'S'}, 5439 {"TCC", required_argument, 0, 'T'}, 5440 {"version", no_argument, 0, 'v' }, 5441 {0, 0, 0, 0 } 5442 }; 5443 5444 progname = argv[0]; 5445 5446 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v", 5447 long_options, &option_index)) != -1) { 5448 switch (opt) { 5449 case 'a': 5450 parse_add_command(optarg); 5451 break; 5452 case 'c': 5453 parse_cpu_command(optarg); 5454 break; 5455 case 'D': 5456 dump_only++; 5457 break; 5458 case 'e': 5459 /* --enable specified counter */ 5460 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST); 5461 break; 5462 case 'd': 5463 debug++; 5464 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 5465 break; 5466 case 'H': 5467 /* 5468 * --hide: do not show those specified 5469 * multiple invocations simply clear more bits in enabled mask 5470 */ 5471 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST); 5472 break; 5473 case 'h': 5474 default: 5475 help(); 5476 exit(1); 5477 case 'i': 5478 { 5479 double interval = strtod(optarg, NULL); 5480 5481 if (interval < 0.001) { 5482 fprintf(outf, "interval %f seconds is too small\n", 5483 interval); 5484 exit(2); 5485 } 5486 5487 interval_tv.tv_sec = interval_ts.tv_sec = interval; 5488 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000; 5489 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; 5490 } 5491 break; 5492 case 'J': 5493 rapl_joules++; 5494 break; 5495 case 'l': 5496 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT); 5497 list_header_only++; 5498 quiet++; 5499 break; 5500 case 'o': 5501 outf = fopen_or_die(optarg, "w"); 5502 break; 5503 case 'q': 5504 quiet = 1; 5505 break; 5506 case 'n': 5507 num_iterations = strtod(optarg, NULL); 5508 5509 if (num_iterations <= 0) { 5510 fprintf(outf, "iterations %d should be positive number\n", 5511 num_iterations); 5512 exit(2); 5513 } 5514 break; 5515 case 's': 5516 /* 5517 * --show: show only those specified 5518 * The 1st invocation will clear and replace the enabled mask 5519 * subsequent invocations can add to it. 5520 */ 5521 if (shown == 0) 5522 bic_enabled = bic_lookup(optarg, SHOW_LIST); 5523 else 5524 bic_enabled |= bic_lookup(optarg, SHOW_LIST); 5525 shown = 1; 5526 break; 5527 case 'S': 5528 summary_only++; 5529 break; 5530 case 'T': 5531 tcc_activation_temp_override = atoi(optarg); 5532 break; 5533 case 'v': 5534 print_version(); 5535 exit(0); 5536 break; 5537 } 5538 } 5539 } 5540 5541 int main(int argc, char **argv) 5542 { 5543 outf = stderr; 5544 cmdline(argc, argv); 5545 5546 if (!quiet) 5547 print_version(); 5548 5549 probe_sysfs(); 5550 5551 turbostat_init(); 5552 5553 /* dump counters and exit */ 5554 if (dump_only) 5555 return get_and_dump_counters(); 5556 5557 /* list header and exit */ 5558 if (list_header_only) { 5559 print_header(","); 5560 flush_output_stdout(); 5561 return 0; 5562 } 5563 5564 /* 5565 * if any params left, it must be a command to fork 5566 */ 5567 if (argc - optind) 5568 return fork_it(argv + optind); 5569 else 5570 turbostat_loop(); 5571 5572 return 0; 5573 } 5574