1d910f0baSAndi Kleen[ 2d910f0baSAndi Kleen { 3d910f0baSAndi Kleen "BriefDescription": "Divide operations executed", 4d910f0baSAndi Kleen "CounterMask": "1", 5194b6fa4SAndi Kleen "EdgeDetect": "1", 670d90a6aSIan Rogers "EventCode": "0x14", 770d90a6aSIan Rogers "EventName": "ARITH.FPU_DIV", 870d90a6aSIan Rogers "PublicDescription": "Divide operations executed.", 970d90a6aSIan Rogers "SampleAfterValue": "100003", 1070d90a6aSIan Rogers "UMask": "0x4" 11194b6fa4SAndi Kleen }, 12194b6fa4SAndi Kleen { 1370d90a6aSIan Rogers "BriefDescription": "Cycles when divider is busy executing divide operations", 1470d90a6aSIan Rogers "EventCode": "0x14", 1570d90a6aSIan Rogers "EventName": "ARITH.FPU_DIV_ACTIVE", 1670d90a6aSIan Rogers "PublicDescription": "Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides.", 17d910f0baSAndi Kleen "SampleAfterValue": "2000003", 1870d90a6aSIan Rogers "UMask": "0x1" 19d910f0baSAndi Kleen }, 20d910f0baSAndi Kleen { 2170d90a6aSIan Rogers "BriefDescription": "Speculative and retired branches", 22d910f0baSAndi Kleen "EventCode": "0x88", 2370d90a6aSIan Rogers "EventName": "BR_INST_EXEC.ALL_BRANCHES", 2470d90a6aSIan Rogers "PublicDescription": "Counts all near executed branches (not necessarily retired).", 25d910f0baSAndi Kleen "SampleAfterValue": "200003", 2670d90a6aSIan Rogers "UMask": "0xff" 27d910f0baSAndi Kleen }, 28d910f0baSAndi Kleen { 29d910f0baSAndi Kleen "BriefDescription": "Speculative and retired macro-conditional branches", 3070d90a6aSIan Rogers "EventCode": "0x88", 3170d90a6aSIan Rogers "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", 3270d90a6aSIan Rogers "PublicDescription": "Speculative and retired macro-conditional branches.", 3370d90a6aSIan Rogers "SampleAfterValue": "200003", 3470d90a6aSIan Rogers "UMask": "0xc1" 35d910f0baSAndi Kleen }, 36d910f0baSAndi Kleen { 37d910f0baSAndi Kleen "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects", 3870d90a6aSIan Rogers "EventCode": "0x88", 3970d90a6aSIan Rogers "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", 4070d90a6aSIan Rogers "PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", 41d910f0baSAndi Kleen "SampleAfterValue": "200003", 4270d90a6aSIan Rogers "UMask": "0xc2" 43d910f0baSAndi Kleen }, 44d910f0baSAndi Kleen { 4570d90a6aSIan Rogers "BriefDescription": "Speculative and retired direct near calls", 4670d90a6aSIan Rogers "EventCode": "0x88", 4770d90a6aSIan Rogers "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", 4870d90a6aSIan Rogers "PublicDescription": "Speculative and retired direct near calls.", 4970d90a6aSIan Rogers "SampleAfterValue": "200003", 5070d90a6aSIan Rogers "UMask": "0xd0" 5170d90a6aSIan Rogers }, 5270d90a6aSIan Rogers { 5370d90a6aSIan Rogers "BriefDescription": "Speculative and retired indirect branches excluding calls and returns", 5470d90a6aSIan Rogers "EventCode": "0x88", 5570d90a6aSIan Rogers "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", 5670d90a6aSIan Rogers "PublicDescription": "Speculative and retired indirect branches excluding calls and returns.", 5770d90a6aSIan Rogers "SampleAfterValue": "200003", 5870d90a6aSIan Rogers "UMask": "0xc4" 5970d90a6aSIan Rogers }, 6070d90a6aSIan Rogers { 6170d90a6aSIan Rogers "BriefDescription": "Speculative and retired indirect return branches.", 6270d90a6aSIan Rogers "EventCode": "0x88", 63d910f0baSAndi Kleen "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", 64d910f0baSAndi Kleen "SampleAfterValue": "200003", 6570d90a6aSIan Rogers "UMask": "0xc8" 66d910f0baSAndi Kleen }, 67d910f0baSAndi Kleen { 6870d90a6aSIan Rogers "BriefDescription": "Not taken macro-conditional branches", 69d910f0baSAndi Kleen "EventCode": "0x88", 7070d90a6aSIan Rogers "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", 7170d90a6aSIan Rogers "PublicDescription": "Not taken macro-conditional branches.", 72d910f0baSAndi Kleen "SampleAfterValue": "200003", 7370d90a6aSIan Rogers "UMask": "0x41" 74d910f0baSAndi Kleen }, 75d910f0baSAndi Kleen { 7670d90a6aSIan Rogers "BriefDescription": "Taken speculative and retired macro-conditional branches", 77d910f0baSAndi Kleen "EventCode": "0x88", 7870d90a6aSIan Rogers "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", 7970d90a6aSIan Rogers "PublicDescription": "Taken speculative and retired macro-conditional branches.", 80d910f0baSAndi Kleen "SampleAfterValue": "200003", 8170d90a6aSIan Rogers "UMask": "0x81" 82d910f0baSAndi Kleen }, 83d910f0baSAndi Kleen { 8470d90a6aSIan Rogers "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", 8570d90a6aSIan Rogers "EventCode": "0x88", 8670d90a6aSIan Rogers "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", 8770d90a6aSIan Rogers "PublicDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", 88d910f0baSAndi Kleen "SampleAfterValue": "200003", 8970d90a6aSIan Rogers "UMask": "0x82" 90d910f0baSAndi Kleen }, 91d910f0baSAndi Kleen { 9270d90a6aSIan Rogers "BriefDescription": "Taken speculative and retired direct near calls", 9370d90a6aSIan Rogers "EventCode": "0x88", 9470d90a6aSIan Rogers "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", 9570d90a6aSIan Rogers "PublicDescription": "Taken speculative and retired direct near calls.", 96d910f0baSAndi Kleen "SampleAfterValue": "200003", 9770d90a6aSIan Rogers "UMask": "0x90" 98d910f0baSAndi Kleen }, 99d910f0baSAndi Kleen { 10070d90a6aSIan Rogers "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", 10170d90a6aSIan Rogers "EventCode": "0x88", 10270d90a6aSIan Rogers "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", 10370d90a6aSIan Rogers "PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns.", 104d910f0baSAndi Kleen "SampleAfterValue": "200003", 10570d90a6aSIan Rogers "UMask": "0x84" 106d910f0baSAndi Kleen }, 107d910f0baSAndi Kleen { 10870d90a6aSIan Rogers "BriefDescription": "Taken speculative and retired indirect calls", 10970d90a6aSIan Rogers "EventCode": "0x88", 11070d90a6aSIan Rogers "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", 11170d90a6aSIan Rogers "PublicDescription": "Taken speculative and retired indirect calls.", 112d910f0baSAndi Kleen "SampleAfterValue": "200003", 11370d90a6aSIan Rogers "UMask": "0xa0" 114d910f0baSAndi Kleen }, 115d910f0baSAndi Kleen { 11670d90a6aSIan Rogers "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", 11770d90a6aSIan Rogers "EventCode": "0x88", 11870d90a6aSIan Rogers "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", 11970d90a6aSIan Rogers "PublicDescription": "Taken speculative and retired indirect branches with return mnemonic.", 120d910f0baSAndi Kleen "SampleAfterValue": "200003", 12170d90a6aSIan Rogers "UMask": "0x88" 122d910f0baSAndi Kleen }, 123d910f0baSAndi Kleen { 12470d90a6aSIan Rogers "BriefDescription": "All (macro) branch instructions retired.", 12570d90a6aSIan Rogers "EventCode": "0xC4", 12670d90a6aSIan Rogers "EventName": "BR_INST_RETIRED.ALL_BRANCHES", 12770d90a6aSIan Rogers "PublicDescription": "Branch instructions at retirement.", 12870d90a6aSIan Rogers "SampleAfterValue": "400009" 12970d90a6aSIan Rogers }, 13070d90a6aSIan Rogers { 13170d90a6aSIan Rogers "BriefDescription": "All (macro) branch instructions retired.", 13270d90a6aSIan Rogers "EventCode": "0xC4", 13370d90a6aSIan Rogers "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", 13470d90a6aSIan Rogers "PEBS": "2", 13570d90a6aSIan Rogers "SampleAfterValue": "400009", 13670d90a6aSIan Rogers "UMask": "0x4" 13770d90a6aSIan Rogers }, 13870d90a6aSIan Rogers { 13970d90a6aSIan Rogers "BriefDescription": "Conditional branch instructions retired.", 14070d90a6aSIan Rogers "EventCode": "0xC4", 14170d90a6aSIan Rogers "EventName": "BR_INST_RETIRED.CONDITIONAL", 14270d90a6aSIan Rogers "PEBS": "1", 14370d90a6aSIan Rogers "SampleAfterValue": "400009", 14470d90a6aSIan Rogers "UMask": "0x1" 14570d90a6aSIan Rogers }, 14670d90a6aSIan Rogers { 14770d90a6aSIan Rogers "BriefDescription": "Far branch instructions retired.", 14870d90a6aSIan Rogers "EventCode": "0xC4", 14970d90a6aSIan Rogers "EventName": "BR_INST_RETIRED.FAR_BRANCH", 15070d90a6aSIan Rogers "PublicDescription": "Number of far branches retired.", 15170d90a6aSIan Rogers "SampleAfterValue": "100007", 15270d90a6aSIan Rogers "UMask": "0x40" 15370d90a6aSIan Rogers }, 15470d90a6aSIan Rogers { 15570d90a6aSIan Rogers "BriefDescription": "Direct and indirect near call instructions retired.", 15670d90a6aSIan Rogers "EventCode": "0xC4", 15770d90a6aSIan Rogers "EventName": "BR_INST_RETIRED.NEAR_CALL", 15870d90a6aSIan Rogers "PEBS": "1", 15970d90a6aSIan Rogers "SampleAfterValue": "100007", 16070d90a6aSIan Rogers "UMask": "0x2" 16170d90a6aSIan Rogers }, 16270d90a6aSIan Rogers { 16370d90a6aSIan Rogers "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", 16470d90a6aSIan Rogers "EventCode": "0xC4", 16570d90a6aSIan Rogers "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", 16670d90a6aSIan Rogers "PEBS": "1", 16770d90a6aSIan Rogers "SampleAfterValue": "100007", 16870d90a6aSIan Rogers "UMask": "0x2" 16970d90a6aSIan Rogers }, 17070d90a6aSIan Rogers { 17170d90a6aSIan Rogers "BriefDescription": "Return instructions retired.", 17270d90a6aSIan Rogers "EventCode": "0xC4", 17370d90a6aSIan Rogers "EventName": "BR_INST_RETIRED.NEAR_RETURN", 17470d90a6aSIan Rogers "PEBS": "1", 17570d90a6aSIan Rogers "SampleAfterValue": "100007", 17670d90a6aSIan Rogers "UMask": "0x8" 17770d90a6aSIan Rogers }, 17870d90a6aSIan Rogers { 17970d90a6aSIan Rogers "BriefDescription": "Taken branch instructions retired.", 18070d90a6aSIan Rogers "EventCode": "0xC4", 18170d90a6aSIan Rogers "EventName": "BR_INST_RETIRED.NEAR_TAKEN", 18270d90a6aSIan Rogers "PEBS": "1", 18370d90a6aSIan Rogers "SampleAfterValue": "400009", 18470d90a6aSIan Rogers "UMask": "0x20" 18570d90a6aSIan Rogers }, 18670d90a6aSIan Rogers { 18770d90a6aSIan Rogers "BriefDescription": "Not taken branch instructions retired.", 18870d90a6aSIan Rogers "EventCode": "0xC4", 18970d90a6aSIan Rogers "EventName": "BR_INST_RETIRED.NOT_TAKEN", 19070d90a6aSIan Rogers "PublicDescription": "Counts the number of not taken branch instructions retired.", 19170d90a6aSIan Rogers "SampleAfterValue": "400009", 19270d90a6aSIan Rogers "UMask": "0x10" 19370d90a6aSIan Rogers }, 19470d90a6aSIan Rogers { 195d910f0baSAndi Kleen "BriefDescription": "Speculative and retired mispredicted macro conditional branches", 196d910f0baSAndi Kleen "EventCode": "0x89", 197d910f0baSAndi Kleen "EventName": "BR_MISP_EXEC.ALL_BRANCHES", 19870d90a6aSIan Rogers "PublicDescription": "Counts all near executed branches (not necessarily retired).", 199d910f0baSAndi Kleen "SampleAfterValue": "200003", 20070d90a6aSIan Rogers "UMask": "0xff" 20170d90a6aSIan Rogers }, 20270d90a6aSIan Rogers { 203d910f0baSAndi Kleen "BriefDescription": "Speculative and retired mispredicted macro conditional branches", 20470d90a6aSIan Rogers "EventCode": "0x89", 20570d90a6aSIan Rogers "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", 20670d90a6aSIan Rogers "PublicDescription": "Speculative and retired mispredicted macro conditional branches.", 20770d90a6aSIan Rogers "SampleAfterValue": "200003", 20870d90a6aSIan Rogers "UMask": "0xc1" 209d910f0baSAndi Kleen }, 210d910f0baSAndi Kleen { 21170d90a6aSIan Rogers "BriefDescription": "Mispredicted indirect branches excluding calls and returns", 21270d90a6aSIan Rogers "EventCode": "0x89", 21370d90a6aSIan Rogers "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", 21470d90a6aSIan Rogers "PublicDescription": "Mispredicted indirect branches excluding calls and returns.", 21570d90a6aSIan Rogers "SampleAfterValue": "200003", 21670d90a6aSIan Rogers "UMask": "0xc4" 21770d90a6aSIan Rogers }, 21870d90a6aSIan Rogers { 219*31959321SIan Rogers "BriefDescription": "Speculative mispredicted indirect branches", 220*31959321SIan Rogers "EventCode": "0x89", 221*31959321SIan Rogers "EventName": "BR_MISP_EXEC.INDIRECT", 222*31959321SIan Rogers "PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).", 223*31959321SIan Rogers "SampleAfterValue": "200003", 224*31959321SIan Rogers "UMask": "0xe4" 225*31959321SIan Rogers }, 226*31959321SIan Rogers { 22770d90a6aSIan Rogers "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", 22870d90a6aSIan Rogers "EventCode": "0x89", 22970d90a6aSIan Rogers "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", 23070d90a6aSIan Rogers "PublicDescription": "Not taken speculative and retired mispredicted macro conditional branches.", 23170d90a6aSIan Rogers "SampleAfterValue": "200003", 23270d90a6aSIan Rogers "UMask": "0x41" 23370d90a6aSIan Rogers }, 23470d90a6aSIan Rogers { 23570d90a6aSIan Rogers "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", 23670d90a6aSIan Rogers "EventCode": "0x89", 23770d90a6aSIan Rogers "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", 23870d90a6aSIan Rogers "PublicDescription": "Taken speculative and retired mispredicted macro conditional branches.", 23970d90a6aSIan Rogers "SampleAfterValue": "200003", 24070d90a6aSIan Rogers "UMask": "0x81" 24170d90a6aSIan Rogers }, 24270d90a6aSIan Rogers { 24370d90a6aSIan Rogers "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", 24470d90a6aSIan Rogers "EventCode": "0x89", 24570d90a6aSIan Rogers "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", 24670d90a6aSIan Rogers "PublicDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", 24770d90a6aSIan Rogers "SampleAfterValue": "200003", 24870d90a6aSIan Rogers "UMask": "0x84" 24970d90a6aSIan Rogers }, 25070d90a6aSIan Rogers { 25170d90a6aSIan Rogers "BriefDescription": "Taken speculative and retired mispredicted indirect calls", 25270d90a6aSIan Rogers "EventCode": "0x89", 25370d90a6aSIan Rogers "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", 25470d90a6aSIan Rogers "PublicDescription": "Taken speculative and retired mispredicted indirect calls.", 25570d90a6aSIan Rogers "SampleAfterValue": "200003", 25670d90a6aSIan Rogers "UMask": "0xa0" 25770d90a6aSIan Rogers }, 25870d90a6aSIan Rogers { 25970d90a6aSIan Rogers "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", 26070d90a6aSIan Rogers "EventCode": "0x89", 26170d90a6aSIan Rogers "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", 26270d90a6aSIan Rogers "PublicDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", 26370d90a6aSIan Rogers "SampleAfterValue": "200003", 26470d90a6aSIan Rogers "UMask": "0x88" 26570d90a6aSIan Rogers }, 26670d90a6aSIan Rogers { 26770d90a6aSIan Rogers "BriefDescription": "All mispredicted macro branch instructions retired.", 26870d90a6aSIan Rogers "EventCode": "0xC5", 26970d90a6aSIan Rogers "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", 27070d90a6aSIan Rogers "PublicDescription": "Mispredicted branch instructions at retirement.", 27170d90a6aSIan Rogers "SampleAfterValue": "400009" 27270d90a6aSIan Rogers }, 27370d90a6aSIan Rogers { 27470d90a6aSIan Rogers "BriefDescription": "Mispredicted macro branch instructions retired.", 27570d90a6aSIan Rogers "EventCode": "0xC5", 27670d90a6aSIan Rogers "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", 27770d90a6aSIan Rogers "PEBS": "2", 27870d90a6aSIan Rogers "SampleAfterValue": "400009", 27970d90a6aSIan Rogers "UMask": "0x4" 28070d90a6aSIan Rogers }, 28170d90a6aSIan Rogers { 28270d90a6aSIan Rogers "BriefDescription": "Mispredicted conditional branch instructions retired.", 28370d90a6aSIan Rogers "EventCode": "0xC5", 28470d90a6aSIan Rogers "EventName": "BR_MISP_RETIRED.CONDITIONAL", 28570d90a6aSIan Rogers "PEBS": "1", 28670d90a6aSIan Rogers "SampleAfterValue": "400009", 28770d90a6aSIan Rogers "UMask": "0x1" 28870d90a6aSIan Rogers }, 28970d90a6aSIan Rogers { 29070d90a6aSIan Rogers "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", 29170d90a6aSIan Rogers "EventCode": "0xC5", 29270d90a6aSIan Rogers "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", 29370d90a6aSIan Rogers "PEBS": "1", 29470d90a6aSIan Rogers "SampleAfterValue": "400009", 29570d90a6aSIan Rogers "UMask": "0x20" 29670d90a6aSIan Rogers }, 29770d90a6aSIan Rogers { 29870d90a6aSIan Rogers "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.", 29970d90a6aSIan Rogers "EventCode": "0x3C", 30070d90a6aSIan Rogers "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", 301d910f0baSAndi Kleen "SampleAfterValue": "2000003", 30270d90a6aSIan Rogers "UMask": "0x2" 303d910f0baSAndi Kleen }, 304d910f0baSAndi Kleen { 30570d90a6aSIan Rogers "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 30670d90a6aSIan Rogers "EventCode": "0x3C", 30770d90a6aSIan Rogers "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", 30870d90a6aSIan Rogers "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.", 30970d90a6aSIan Rogers "SampleAfterValue": "2000003", 31070d90a6aSIan Rogers "UMask": "0x1" 31170d90a6aSIan Rogers }, 31270d90a6aSIan Rogers { 313d910f0baSAndi Kleen "AnyThread": "1", 31470d90a6aSIan Rogers "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)", 31570d90a6aSIan Rogers "EventCode": "0x3C", 31670d90a6aSIan Rogers "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", 317d910f0baSAndi Kleen "SampleAfterValue": "2000003", 31870d90a6aSIan Rogers "UMask": "0x1" 319d910f0baSAndi Kleen }, 320d910f0baSAndi Kleen { 32170d90a6aSIan Rogers "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", 32270d90a6aSIan Rogers "EventCode": "0x3C", 32370d90a6aSIan Rogers "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", 324194b6fa4SAndi Kleen "SampleAfterValue": "2000003", 32570d90a6aSIan Rogers "UMask": "0x2" 326194b6fa4SAndi Kleen }, 327194b6fa4SAndi Kleen { 32870d90a6aSIan Rogers "BriefDescription": "Reference cycles when the core is not in halt state.", 32970d90a6aSIan Rogers "EventName": "CPU_CLK_UNHALTED.REF_TSC", 33070d90a6aSIan Rogers "SampleAfterValue": "2000003", 33170d90a6aSIan Rogers "UMask": "0x3" 33270d90a6aSIan Rogers }, 33370d90a6aSIan Rogers { 33470d90a6aSIan Rogers "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", 33570d90a6aSIan Rogers "EventCode": "0x3C", 33670d90a6aSIan Rogers "EventName": "CPU_CLK_UNHALTED.REF_XCLK", 33770d90a6aSIan Rogers "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", 33870d90a6aSIan Rogers "SampleAfterValue": "2000003", 33970d90a6aSIan Rogers "UMask": "0x1" 34070d90a6aSIan Rogers }, 34170d90a6aSIan Rogers { 342d910f0baSAndi Kleen "AnyThread": "1", 34370d90a6aSIan Rogers "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)", 34470d90a6aSIan Rogers "EventCode": "0x3C", 34570d90a6aSIan Rogers "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", 346d910f0baSAndi Kleen "SampleAfterValue": "2000003", 34770d90a6aSIan Rogers "UMask": "0x1" 348d910f0baSAndi Kleen }, 349d910f0baSAndi Kleen { 35070d90a6aSIan Rogers "BriefDescription": "Core cycles when the thread is not in halt state.", 35170d90a6aSIan Rogers "EventName": "CPU_CLK_UNHALTED.THREAD", 352d910f0baSAndi Kleen "SampleAfterValue": "2000003", 35370d90a6aSIan Rogers "UMask": "0x2" 354d910f0baSAndi Kleen }, 355d910f0baSAndi Kleen { 356d910f0baSAndi Kleen "AnyThread": "1", 35770d90a6aSIan Rogers "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state", 35870d90a6aSIan Rogers "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", 35970d90a6aSIan Rogers "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.", 360d910f0baSAndi Kleen "SampleAfterValue": "2000003", 36170d90a6aSIan Rogers "UMask": "0x2" 362d910f0baSAndi Kleen }, 363d910f0baSAndi Kleen { 36470d90a6aSIan Rogers "BriefDescription": "Thread cycles when thread is not in halt state", 36570d90a6aSIan Rogers "EventCode": "0x3C", 36670d90a6aSIan Rogers "EventName": "CPU_CLK_UNHALTED.THREAD_P", 36770d90a6aSIan Rogers "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", 36870d90a6aSIan Rogers "SampleAfterValue": "2000003" 369194b6fa4SAndi Kleen }, 370194b6fa4SAndi Kleen { 371d910f0baSAndi Kleen "AnyThread": "1", 37270d90a6aSIan Rogers "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state", 37370d90a6aSIan Rogers "EventCode": "0x3C", 37470d90a6aSIan Rogers "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", 37570d90a6aSIan Rogers "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.", 37670d90a6aSIan Rogers "SampleAfterValue": "2000003" 377194b6fa4SAndi Kleen }, 378194b6fa4SAndi Kleen { 37970d90a6aSIan Rogers "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", 380194b6fa4SAndi Kleen "CounterMask": "8", 381194b6fa4SAndi Kleen "EventCode": "0xA3", 382194b6fa4SAndi Kleen "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", 383194b6fa4SAndi Kleen "SampleAfterValue": "2000003", 38470d90a6aSIan Rogers "UMask": "0x8" 38570d90a6aSIan Rogers }, 38670d90a6aSIan Rogers { 38770d90a6aSIan Rogers "BriefDescription": "Cycles with pending L1 cache miss loads.", 388194b6fa4SAndi Kleen "CounterMask": "8", 389d910f0baSAndi Kleen "EventCode": "0xA3", 39070d90a6aSIan Rogers "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", 39170d90a6aSIan Rogers "PublicDescription": "Cycles with pending L1 cache miss loads. Set AnyThread to count per core.", 392d910f0baSAndi Kleen "SampleAfterValue": "2000003", 39370d90a6aSIan Rogers "UMask": "0x8" 394d910f0baSAndi Kleen }, 395d910f0baSAndi Kleen { 39670d90a6aSIan Rogers "BriefDescription": "Cycles while L2 cache miss load* is outstanding.", 39770d90a6aSIan Rogers "CounterMask": "1", 398194b6fa4SAndi Kleen "EventCode": "0xA3", 39970d90a6aSIan Rogers "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", 40070d90a6aSIan Rogers "SampleAfterValue": "2000003", 40170d90a6aSIan Rogers "UMask": "0x1" 40270d90a6aSIan Rogers }, 40370d90a6aSIan Rogers { 40470d90a6aSIan Rogers "BriefDescription": "Cycles with pending L2 cache miss loads.", 40570d90a6aSIan Rogers "CounterMask": "1", 40670d90a6aSIan Rogers "EventCode": "0xA3", 40770d90a6aSIan Rogers "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", 40870d90a6aSIan Rogers "PublicDescription": "Cycles with pending L2 miss loads. Set AnyThread to count per core.", 40970d90a6aSIan Rogers "SampleAfterValue": "2000003", 41070d90a6aSIan Rogers "UMask": "0x1" 41170d90a6aSIan Rogers }, 41270d90a6aSIan Rogers { 41370d90a6aSIan Rogers "BriefDescription": "Cycles with pending memory loads.", 41470d90a6aSIan Rogers "CounterMask": "2", 41570d90a6aSIan Rogers "EventCode": "0xA3", 41670d90a6aSIan Rogers "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", 41770d90a6aSIan Rogers "PublicDescription": "Cycles with pending memory loads. Set AnyThread to count per core.", 41870d90a6aSIan Rogers "SampleAfterValue": "2000003", 41970d90a6aSIan Rogers "UMask": "0x2" 42070d90a6aSIan Rogers }, 42170d90a6aSIan Rogers { 42270d90a6aSIan Rogers "BriefDescription": "Cycles while memory subsystem has an outstanding load.", 42370d90a6aSIan Rogers "CounterMask": "2", 42470d90a6aSIan Rogers "EventCode": "0xA3", 42570d90a6aSIan Rogers "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", 42670d90a6aSIan Rogers "SampleAfterValue": "2000003", 42770d90a6aSIan Rogers "UMask": "0x2" 42870d90a6aSIan Rogers }, 42970d90a6aSIan Rogers { 43070d90a6aSIan Rogers "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", 43170d90a6aSIan Rogers "CounterMask": "4", 43270d90a6aSIan Rogers "EventCode": "0xA3", 43370d90a6aSIan Rogers "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", 43470d90a6aSIan Rogers "PublicDescription": "Total execution stalls.", 43570d90a6aSIan Rogers "SampleAfterValue": "2000003", 43670d90a6aSIan Rogers "UMask": "0x4" 43770d90a6aSIan Rogers }, 43870d90a6aSIan Rogers { 43970d90a6aSIan Rogers "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", 44070d90a6aSIan Rogers "CounterMask": "12", 44170d90a6aSIan Rogers "EventCode": "0xA3", 442194b6fa4SAndi Kleen "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", 443194b6fa4SAndi Kleen "SampleAfterValue": "2000003", 44470d90a6aSIan Rogers "UMask": "0xc" 44570d90a6aSIan Rogers }, 44670d90a6aSIan Rogers { 44770d90a6aSIan Rogers "BriefDescription": "Execution stalls due to L1 data cache misses", 448194b6fa4SAndi Kleen "CounterMask": "12", 44970d90a6aSIan Rogers "EventCode": "0xA3", 45070d90a6aSIan Rogers "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", 45170d90a6aSIan Rogers "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.", 45270d90a6aSIan Rogers "SampleAfterValue": "2000003", 45370d90a6aSIan Rogers "UMask": "0xc" 454194b6fa4SAndi Kleen }, 455194b6fa4SAndi Kleen { 45670d90a6aSIan Rogers "BriefDescription": "Execution stalls while L2 cache miss load* is outstanding.", 45770d90a6aSIan Rogers "CounterMask": "5", 45870d90a6aSIan Rogers "EventCode": "0xA3", 45970d90a6aSIan Rogers "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", 460d910f0baSAndi Kleen "SampleAfterValue": "2000003", 46170d90a6aSIan Rogers "UMask": "0x5" 462d910f0baSAndi Kleen }, 463d910f0baSAndi Kleen { 46470d90a6aSIan Rogers "BriefDescription": "Execution stalls due to L2 cache misses.", 46570d90a6aSIan Rogers "CounterMask": "5", 46670d90a6aSIan Rogers "EventCode": "0xA3", 46770d90a6aSIan Rogers "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", 46870d90a6aSIan Rogers "PublicDescription": "Number of loads missed L2.", 469d910f0baSAndi Kleen "SampleAfterValue": "2000003", 47070d90a6aSIan Rogers "UMask": "0x5" 471d910f0baSAndi Kleen }, 472d910f0baSAndi Kleen { 47370d90a6aSIan Rogers "BriefDescription": "Execution stalls due to memory subsystem.", 47470d90a6aSIan Rogers "CounterMask": "6", 47570d90a6aSIan Rogers "EventCode": "0xA3", 47670d90a6aSIan Rogers "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", 477194b6fa4SAndi Kleen "SampleAfterValue": "2000003", 47870d90a6aSIan Rogers "UMask": "0x6" 47970d90a6aSIan Rogers }, 48070d90a6aSIan Rogers { 48170d90a6aSIan Rogers "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", 48270d90a6aSIan Rogers "CounterMask": "6", 48370d90a6aSIan Rogers "EventCode": "0xA3", 48470d90a6aSIan Rogers "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", 48570d90a6aSIan Rogers "SampleAfterValue": "2000003", 48670d90a6aSIan Rogers "UMask": "0x6" 48770d90a6aSIan Rogers }, 48870d90a6aSIan Rogers { 48970d90a6aSIan Rogers "BriefDescription": "Total execution stalls.", 490194b6fa4SAndi Kleen "CounterMask": "4", 49170d90a6aSIan Rogers "EventCode": "0xA3", 49270d90a6aSIan Rogers "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", 49370d90a6aSIan Rogers "SampleAfterValue": "2000003", 49470d90a6aSIan Rogers "UMask": "0x4" 495194b6fa4SAndi Kleen }, 496194b6fa4SAndi Kleen { 49770d90a6aSIan Rogers "BriefDescription": "Stall cycles because IQ is full", 49870d90a6aSIan Rogers "EventCode": "0x87", 49970d90a6aSIan Rogers "EventName": "ILD_STALL.IQ_FULL", 50070d90a6aSIan Rogers "PublicDescription": "Stall cycles due to IQ is full.", 501d910f0baSAndi Kleen "SampleAfterValue": "2000003", 50270d90a6aSIan Rogers "UMask": "0x4" 503d910f0baSAndi Kleen }, 504d910f0baSAndi Kleen { 50570d90a6aSIan Rogers "BriefDescription": "Stalls caused by changing prefix length of the instruction.", 50670d90a6aSIan Rogers "EventCode": "0x87", 50770d90a6aSIan Rogers "EventName": "ILD_STALL.LCP", 508d910f0baSAndi Kleen "SampleAfterValue": "2000003", 50970d90a6aSIan Rogers "UMask": "0x1" 510d910f0baSAndi Kleen }, 511d910f0baSAndi Kleen { 51270d90a6aSIan Rogers "BriefDescription": "Instructions retired from execution.", 51370d90a6aSIan Rogers "EventName": "INST_RETIRED.ANY", 514d910f0baSAndi Kleen "SampleAfterValue": "2000003", 51570d90a6aSIan Rogers "UMask": "0x1" 516d910f0baSAndi Kleen }, 517d910f0baSAndi Kleen { 518194b6fa4SAndi Kleen "BriefDescription": "Number of instructions retired. General Counter - architectural event", 51970d90a6aSIan Rogers "EventCode": "0xC0", 52070d90a6aSIan Rogers "EventName": "INST_RETIRED.ANY_P", 52170d90a6aSIan Rogers "PublicDescription": "Number of instructions at retirement.", 52270d90a6aSIan Rogers "SampleAfterValue": "2000003" 523d910f0baSAndi Kleen }, 524d910f0baSAndi Kleen { 52570d90a6aSIan Rogers "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", 52670d90a6aSIan Rogers "EventCode": "0xC0", 52770d90a6aSIan Rogers "EventName": "INST_RETIRED.PREC_DIST", 528194b6fa4SAndi Kleen "PEBS": "2", 529194b6fa4SAndi Kleen "PublicDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution.", 530194b6fa4SAndi Kleen "SampleAfterValue": "2000003", 53170d90a6aSIan Rogers "UMask": "0x1" 532194b6fa4SAndi Kleen }, 533194b6fa4SAndi Kleen { 53470d90a6aSIan Rogers "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)", 535194b6fa4SAndi Kleen "CounterMask": "1", 53670d90a6aSIan Rogers "EventCode": "0x0D", 53770d90a6aSIan Rogers "EventName": "INT_MISC.RECOVERY_CYCLES", 538194b6fa4SAndi Kleen "SampleAfterValue": "2000003", 53970d90a6aSIan Rogers "UMask": "0x3" 540194b6fa4SAndi Kleen }, 541194b6fa4SAndi Kleen { 542d910f0baSAndi Kleen "AnyThread": "1", 54370d90a6aSIan Rogers "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", 544194b6fa4SAndi Kleen "CounterMask": "1", 54570d90a6aSIan Rogers "EventCode": "0x0D", 54670d90a6aSIan Rogers "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", 547194b6fa4SAndi Kleen "SampleAfterValue": "2000003", 54870d90a6aSIan Rogers "UMask": "0x3" 549d910f0baSAndi Kleen }, 550d910f0baSAndi Kleen { 5518ce185d4SIan Rogers "BriefDescription": "Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)", 55270d90a6aSIan Rogers "CounterMask": "1", 553194b6fa4SAndi Kleen "EdgeDetect": "1", 55470d90a6aSIan Rogers "EventCode": "0x0D", 55570d90a6aSIan Rogers "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", 55670d90a6aSIan Rogers "SampleAfterValue": "2000003", 55770d90a6aSIan Rogers "UMask": "0x3" 55870d90a6aSIan Rogers }, 55970d90a6aSIan Rogers { 56070d90a6aSIan Rogers "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", 56170d90a6aSIan Rogers "EventCode": "0x03", 56270d90a6aSIan Rogers "EventName": "LD_BLOCKS.NO_SR", 56370d90a6aSIan Rogers "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", 56470d90a6aSIan Rogers "SampleAfterValue": "100003", 56570d90a6aSIan Rogers "UMask": "0x8" 56670d90a6aSIan Rogers }, 56770d90a6aSIan Rogers { 56870d90a6aSIan Rogers "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", 56970d90a6aSIan Rogers "EventCode": "0x03", 57070d90a6aSIan Rogers "EventName": "LD_BLOCKS.STORE_FORWARD", 57170d90a6aSIan Rogers "PublicDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded.", 57270d90a6aSIan Rogers "SampleAfterValue": "100003", 57370d90a6aSIan Rogers "UMask": "0x2" 57470d90a6aSIan Rogers }, 57570d90a6aSIan Rogers { 57670d90a6aSIan Rogers "BriefDescription": "False dependencies in MOB due to partial compare on address", 57770d90a6aSIan Rogers "EventCode": "0x07", 57870d90a6aSIan Rogers "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", 57970d90a6aSIan Rogers "PublicDescription": "False dependencies in MOB due to partial compare on address.", 58070d90a6aSIan Rogers "SampleAfterValue": "100003", 58170d90a6aSIan Rogers "UMask": "0x1" 58270d90a6aSIan Rogers }, 58370d90a6aSIan Rogers { 58470d90a6aSIan Rogers "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", 58570d90a6aSIan Rogers "EventCode": "0x4C", 58670d90a6aSIan Rogers "EventName": "LOAD_HIT_PRE.HW_PF", 58770d90a6aSIan Rogers "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.", 58870d90a6aSIan Rogers "SampleAfterValue": "100003", 58970d90a6aSIan Rogers "UMask": "0x2" 59070d90a6aSIan Rogers }, 59170d90a6aSIan Rogers { 59270d90a6aSIan Rogers "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", 59370d90a6aSIan Rogers "EventCode": "0x4C", 59470d90a6aSIan Rogers "EventName": "LOAD_HIT_PRE.SW_PF", 59570d90a6aSIan Rogers "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.", 59670d90a6aSIan Rogers "SampleAfterValue": "100003", 59770d90a6aSIan Rogers "UMask": "0x1" 59870d90a6aSIan Rogers }, 59970d90a6aSIan Rogers { 60070d90a6aSIan Rogers "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder", 60170d90a6aSIan Rogers "CounterMask": "4", 60270d90a6aSIan Rogers "EventCode": "0xA8", 60370d90a6aSIan Rogers "EventName": "LSD.CYCLES_4_UOPS", 60470d90a6aSIan Rogers "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", 60570d90a6aSIan Rogers "SampleAfterValue": "2000003", 60670d90a6aSIan Rogers "UMask": "0x1" 60770d90a6aSIan Rogers }, 60870d90a6aSIan Rogers { 60970d90a6aSIan Rogers "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder", 61070d90a6aSIan Rogers "CounterMask": "1", 61170d90a6aSIan Rogers "EventCode": "0xA8", 61270d90a6aSIan Rogers "EventName": "LSD.CYCLES_ACTIVE", 61370d90a6aSIan Rogers "PublicDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", 61470d90a6aSIan Rogers "SampleAfterValue": "2000003", 61570d90a6aSIan Rogers "UMask": "0x1" 61670d90a6aSIan Rogers }, 61770d90a6aSIan Rogers { 61870d90a6aSIan Rogers "BriefDescription": "Number of Uops delivered by the LSD.", 61970d90a6aSIan Rogers "EventCode": "0xA8", 62070d90a6aSIan Rogers "EventName": "LSD.UOPS", 62170d90a6aSIan Rogers "SampleAfterValue": "2000003", 62270d90a6aSIan Rogers "UMask": "0x1" 62370d90a6aSIan Rogers }, 62470d90a6aSIan Rogers { 62570d90a6aSIan Rogers "BriefDescription": "Number of machine clears (nukes) of any type.", 62670d90a6aSIan Rogers "CounterMask": "1", 62770d90a6aSIan Rogers "EdgeDetect": "1", 62870d90a6aSIan Rogers "EventCode": "0xC3", 629194b6fa4SAndi Kleen "EventName": "MACHINE_CLEARS.COUNT", 630194b6fa4SAndi Kleen "SampleAfterValue": "100003", 63170d90a6aSIan Rogers "UMask": "0x1" 632194b6fa4SAndi Kleen }, 633194b6fa4SAndi Kleen { 634194b6fa4SAndi Kleen "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", 63570d90a6aSIan Rogers "EventCode": "0xC3", 63670d90a6aSIan Rogers "EventName": "MACHINE_CLEARS.MASKMOV", 63770d90a6aSIan Rogers "PublicDescription": "Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", 638194b6fa4SAndi Kleen "SampleAfterValue": "100003", 63970d90a6aSIan Rogers "UMask": "0x20" 64070d90a6aSIan Rogers }, 64170d90a6aSIan Rogers { 64270d90a6aSIan Rogers "BriefDescription": "Self-modifying code (SMC) detected.", 64370d90a6aSIan Rogers "EventCode": "0xC3", 64470d90a6aSIan Rogers "EventName": "MACHINE_CLEARS.SMC", 64570d90a6aSIan Rogers "PublicDescription": "Number of self-modifying-code machine clears detected.", 64670d90a6aSIan Rogers "SampleAfterValue": "100003", 64770d90a6aSIan Rogers "UMask": "0x4" 64870d90a6aSIan Rogers }, 64970d90a6aSIan Rogers { 65070d90a6aSIan Rogers "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", 65170d90a6aSIan Rogers "EventCode": "0x58", 65270d90a6aSIan Rogers "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", 65370d90a6aSIan Rogers "SampleAfterValue": "1000003", 65470d90a6aSIan Rogers "UMask": "0x1" 65570d90a6aSIan Rogers }, 65670d90a6aSIan Rogers { 65770d90a6aSIan Rogers "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", 65870d90a6aSIan Rogers "EventCode": "0x58", 65970d90a6aSIan Rogers "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", 66070d90a6aSIan Rogers "SampleAfterValue": "1000003", 66170d90a6aSIan Rogers "UMask": "0x4" 66270d90a6aSIan Rogers }, 66370d90a6aSIan Rogers { 66470d90a6aSIan Rogers "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", 66570d90a6aSIan Rogers "EventCode": "0xC1", 66670d90a6aSIan Rogers "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", 66770d90a6aSIan Rogers "SampleAfterValue": "100003", 66870d90a6aSIan Rogers "UMask": "0x80" 66970d90a6aSIan Rogers }, 67070d90a6aSIan Rogers { 67170d90a6aSIan Rogers "BriefDescription": "Resource-related stall cycles", 67270d90a6aSIan Rogers "EventCode": "0xA2", 67370d90a6aSIan Rogers "EventName": "RESOURCE_STALLS.ANY", 67470d90a6aSIan Rogers "PublicDescription": "Cycles Allocation is stalled due to Resource Related reason.", 67570d90a6aSIan Rogers "SampleAfterValue": "2000003", 67670d90a6aSIan Rogers "UMask": "0x1" 67770d90a6aSIan Rogers }, 67870d90a6aSIan Rogers { 67970d90a6aSIan Rogers "BriefDescription": "Cycles stalled due to re-order buffer full.", 68070d90a6aSIan Rogers "EventCode": "0xA2", 68170d90a6aSIan Rogers "EventName": "RESOURCE_STALLS.ROB", 68270d90a6aSIan Rogers "SampleAfterValue": "2000003", 68370d90a6aSIan Rogers "UMask": "0x10" 68470d90a6aSIan Rogers }, 68570d90a6aSIan Rogers { 68670d90a6aSIan Rogers "BriefDescription": "Cycles stalled due to no eligible RS entry available.", 68770d90a6aSIan Rogers "EventCode": "0xA2", 68870d90a6aSIan Rogers "EventName": "RESOURCE_STALLS.RS", 68970d90a6aSIan Rogers "SampleAfterValue": "2000003", 69070d90a6aSIan Rogers "UMask": "0x4" 69170d90a6aSIan Rogers }, 69270d90a6aSIan Rogers { 69370d90a6aSIan Rogers "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", 69470d90a6aSIan Rogers "EventCode": "0xA2", 69570d90a6aSIan Rogers "EventName": "RESOURCE_STALLS.SB", 69670d90a6aSIan Rogers "PublicDescription": "Cycles stalled due to no store buffers available (not including draining form sync).", 69770d90a6aSIan Rogers "SampleAfterValue": "2000003", 69870d90a6aSIan Rogers "UMask": "0x8" 69970d90a6aSIan Rogers }, 70070d90a6aSIan Rogers { 70170d90a6aSIan Rogers "BriefDescription": "Count cases of saving new LBR", 70270d90a6aSIan Rogers "EventCode": "0xCC", 70370d90a6aSIan Rogers "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", 70470d90a6aSIan Rogers "PublicDescription": "Count cases of saving new LBR records by hardware.", 70570d90a6aSIan Rogers "SampleAfterValue": "2000003", 70670d90a6aSIan Rogers "UMask": "0x20" 70770d90a6aSIan Rogers }, 70870d90a6aSIan Rogers { 70970d90a6aSIan Rogers "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", 71070d90a6aSIan Rogers "EventCode": "0x5E", 71170d90a6aSIan Rogers "EventName": "RS_EVENTS.EMPTY_CYCLES", 71270d90a6aSIan Rogers "PublicDescription": "Cycles the RS is empty for the thread.", 71370d90a6aSIan Rogers "SampleAfterValue": "2000003", 71470d90a6aSIan Rogers "UMask": "0x1" 71570d90a6aSIan Rogers }, 71670d90a6aSIan Rogers { 71770d90a6aSIan Rogers "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", 71870d90a6aSIan Rogers "CounterMask": "1", 71970d90a6aSIan Rogers "EdgeDetect": "1", 72070d90a6aSIan Rogers "EventCode": "0x5E", 72170d90a6aSIan Rogers "EventName": "RS_EVENTS.EMPTY_END", 72270d90a6aSIan Rogers "Invert": "1", 72370d90a6aSIan Rogers "SampleAfterValue": "200003", 72470d90a6aSIan Rogers "UMask": "0x1" 72570d90a6aSIan Rogers }, 72670d90a6aSIan Rogers { 72770d90a6aSIan Rogers "BriefDescription": "Cycles per thread when uops are dispatched to port 0", 72870d90a6aSIan Rogers "EventCode": "0xA1", 72970d90a6aSIan Rogers "EventName": "UOPS_DISPATCHED_PORT.PORT_0", 73070d90a6aSIan Rogers "PublicDescription": "Cycles which a Uop is dispatched on port 0.", 73170d90a6aSIan Rogers "SampleAfterValue": "2000003", 73270d90a6aSIan Rogers "UMask": "0x1" 73370d90a6aSIan Rogers }, 73470d90a6aSIan Rogers { 73570d90a6aSIan Rogers "AnyThread": "1", 73670d90a6aSIan Rogers "BriefDescription": "Cycles per core when uops are dispatched to port 0", 73770d90a6aSIan Rogers "EventCode": "0xA1", 73870d90a6aSIan Rogers "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", 73970d90a6aSIan Rogers "PublicDescription": "Cycles per core when uops are dispatched to port 0.", 74070d90a6aSIan Rogers "SampleAfterValue": "2000003", 74170d90a6aSIan Rogers "UMask": "0x1" 74270d90a6aSIan Rogers }, 74370d90a6aSIan Rogers { 74470d90a6aSIan Rogers "BriefDescription": "Cycles per thread when uops are dispatched to port 1", 74570d90a6aSIan Rogers "EventCode": "0xA1", 74670d90a6aSIan Rogers "EventName": "UOPS_DISPATCHED_PORT.PORT_1", 74770d90a6aSIan Rogers "PublicDescription": "Cycles which a Uop is dispatched on port 1.", 74870d90a6aSIan Rogers "SampleAfterValue": "2000003", 74970d90a6aSIan Rogers "UMask": "0x2" 75070d90a6aSIan Rogers }, 75170d90a6aSIan Rogers { 75270d90a6aSIan Rogers "AnyThread": "1", 75370d90a6aSIan Rogers "BriefDescription": "Cycles per core when uops are dispatched to port 1", 75470d90a6aSIan Rogers "EventCode": "0xA1", 75570d90a6aSIan Rogers "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", 75670d90a6aSIan Rogers "PublicDescription": "Cycles per core when uops are dispatched to port 1.", 75770d90a6aSIan Rogers "SampleAfterValue": "2000003", 75870d90a6aSIan Rogers "UMask": "0x2" 75970d90a6aSIan Rogers }, 76070d90a6aSIan Rogers { 76170d90a6aSIan Rogers "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2", 76270d90a6aSIan Rogers "EventCode": "0xA1", 76370d90a6aSIan Rogers "EventName": "UOPS_DISPATCHED_PORT.PORT_2", 76470d90a6aSIan Rogers "PublicDescription": "Cycles which a Uop is dispatched on port 2.", 76570d90a6aSIan Rogers "SampleAfterValue": "2000003", 76670d90a6aSIan Rogers "UMask": "0xc" 76770d90a6aSIan Rogers }, 76870d90a6aSIan Rogers { 76970d90a6aSIan Rogers "AnyThread": "1", 77070d90a6aSIan Rogers "BriefDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired).", 77170d90a6aSIan Rogers "EventCode": "0xA1", 77270d90a6aSIan Rogers "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", 77370d90a6aSIan Rogers "SampleAfterValue": "2000003", 77470d90a6aSIan Rogers "UMask": "0xc" 77570d90a6aSIan Rogers }, 77670d90a6aSIan Rogers { 77770d90a6aSIan Rogers "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3", 77870d90a6aSIan Rogers "EventCode": "0xA1", 77970d90a6aSIan Rogers "EventName": "UOPS_DISPATCHED_PORT.PORT_3", 78070d90a6aSIan Rogers "PublicDescription": "Cycles which a Uop is dispatched on port 3.", 78170d90a6aSIan Rogers "SampleAfterValue": "2000003", 78270d90a6aSIan Rogers "UMask": "0x30" 78370d90a6aSIan Rogers }, 78470d90a6aSIan Rogers { 78570d90a6aSIan Rogers "AnyThread": "1", 78670d90a6aSIan Rogers "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3", 78770d90a6aSIan Rogers "EventCode": "0xA1", 78870d90a6aSIan Rogers "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", 78970d90a6aSIan Rogers "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.", 79070d90a6aSIan Rogers "SampleAfterValue": "2000003", 79170d90a6aSIan Rogers "UMask": "0x30" 79270d90a6aSIan Rogers }, 79370d90a6aSIan Rogers { 79470d90a6aSIan Rogers "BriefDescription": "Cycles per thread when uops are dispatched to port 4", 79570d90a6aSIan Rogers "EventCode": "0xA1", 79670d90a6aSIan Rogers "EventName": "UOPS_DISPATCHED_PORT.PORT_4", 79770d90a6aSIan Rogers "PublicDescription": "Cycles which a Uop is dispatched on port 4.", 79870d90a6aSIan Rogers "SampleAfterValue": "2000003", 79970d90a6aSIan Rogers "UMask": "0x40" 80070d90a6aSIan Rogers }, 80170d90a6aSIan Rogers { 80270d90a6aSIan Rogers "AnyThread": "1", 80370d90a6aSIan Rogers "BriefDescription": "Cycles per core when uops are dispatched to port 4", 80470d90a6aSIan Rogers "EventCode": "0xA1", 80570d90a6aSIan Rogers "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", 80670d90a6aSIan Rogers "PublicDescription": "Cycles per core when uops are dispatched to port 4.", 80770d90a6aSIan Rogers "SampleAfterValue": "2000003", 80870d90a6aSIan Rogers "UMask": "0x40" 80970d90a6aSIan Rogers }, 81070d90a6aSIan Rogers { 81170d90a6aSIan Rogers "BriefDescription": "Cycles per thread when uops are dispatched to port 5", 81270d90a6aSIan Rogers "EventCode": "0xA1", 81370d90a6aSIan Rogers "EventName": "UOPS_DISPATCHED_PORT.PORT_5", 81470d90a6aSIan Rogers "PublicDescription": "Cycles which a Uop is dispatched on port 5.", 81570d90a6aSIan Rogers "SampleAfterValue": "2000003", 81670d90a6aSIan Rogers "UMask": "0x80" 81770d90a6aSIan Rogers }, 81870d90a6aSIan Rogers { 81970d90a6aSIan Rogers "AnyThread": "1", 82070d90a6aSIan Rogers "BriefDescription": "Cycles per core when uops are dispatched to port 5", 82170d90a6aSIan Rogers "EventCode": "0xA1", 82270d90a6aSIan Rogers "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", 82370d90a6aSIan Rogers "PublicDescription": "Cycles per core when uops are dispatched to port 5.", 82470d90a6aSIan Rogers "SampleAfterValue": "2000003", 82570d90a6aSIan Rogers "UMask": "0x80" 82670d90a6aSIan Rogers }, 82770d90a6aSIan Rogers { 82870d90a6aSIan Rogers "BriefDescription": "Number of uops executed on the core.", 82970d90a6aSIan Rogers "EventCode": "0xB1", 83070d90a6aSIan Rogers "EventName": "UOPS_EXECUTED.CORE", 83170d90a6aSIan Rogers "PublicDescription": "Counts total number of uops to be executed per-core each cycle.", 83270d90a6aSIan Rogers "SampleAfterValue": "2000003", 83370d90a6aSIan Rogers "UMask": "0x2" 83470d90a6aSIan Rogers }, 83570d90a6aSIan Rogers { 83670d90a6aSIan Rogers "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core", 83770d90a6aSIan Rogers "CounterMask": "1", 83870d90a6aSIan Rogers "EventCode": "0xB1", 83970d90a6aSIan Rogers "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", 84070d90a6aSIan Rogers "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", 84170d90a6aSIan Rogers "SampleAfterValue": "2000003", 84270d90a6aSIan Rogers "UMask": "0x2" 84370d90a6aSIan Rogers }, 84470d90a6aSIan Rogers { 84570d90a6aSIan Rogers "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core", 84670d90a6aSIan Rogers "CounterMask": "2", 84770d90a6aSIan Rogers "EventCode": "0xB1", 84870d90a6aSIan Rogers "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", 84970d90a6aSIan Rogers "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", 85070d90a6aSIan Rogers "SampleAfterValue": "2000003", 85170d90a6aSIan Rogers "UMask": "0x2" 85270d90a6aSIan Rogers }, 85370d90a6aSIan Rogers { 85470d90a6aSIan Rogers "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core", 85570d90a6aSIan Rogers "CounterMask": "3", 85670d90a6aSIan Rogers "EventCode": "0xB1", 85770d90a6aSIan Rogers "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", 85870d90a6aSIan Rogers "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", 85970d90a6aSIan Rogers "SampleAfterValue": "2000003", 86070d90a6aSIan Rogers "UMask": "0x2" 86170d90a6aSIan Rogers }, 86270d90a6aSIan Rogers { 86370d90a6aSIan Rogers "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core", 86470d90a6aSIan Rogers "CounterMask": "4", 86570d90a6aSIan Rogers "EventCode": "0xB1", 86670d90a6aSIan Rogers "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", 86770d90a6aSIan Rogers "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", 86870d90a6aSIan Rogers "SampleAfterValue": "2000003", 86970d90a6aSIan Rogers "UMask": "0x2" 87070d90a6aSIan Rogers }, 87170d90a6aSIan Rogers { 87270d90a6aSIan Rogers "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core", 87370d90a6aSIan Rogers "EventCode": "0xB1", 87470d90a6aSIan Rogers "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", 87570d90a6aSIan Rogers "Invert": "1", 87670d90a6aSIan Rogers "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core.", 87770d90a6aSIan Rogers "SampleAfterValue": "2000003", 87870d90a6aSIan Rogers "UMask": "0x2" 87970d90a6aSIan Rogers }, 88070d90a6aSIan Rogers { 88170d90a6aSIan Rogers "BriefDescription": "Cycles where at least 1 uop was executed per-thread", 88270d90a6aSIan Rogers "CounterMask": "1", 88370d90a6aSIan Rogers "EventCode": "0xB1", 88470d90a6aSIan Rogers "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", 88570d90a6aSIan Rogers "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", 88670d90a6aSIan Rogers "SampleAfterValue": "2000003", 88770d90a6aSIan Rogers "UMask": "0x1" 88870d90a6aSIan Rogers }, 88970d90a6aSIan Rogers { 89070d90a6aSIan Rogers "BriefDescription": "Cycles where at least 2 uops were executed per-thread", 89170d90a6aSIan Rogers "CounterMask": "2", 89270d90a6aSIan Rogers "EventCode": "0xB1", 89370d90a6aSIan Rogers "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", 89470d90a6aSIan Rogers "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", 89570d90a6aSIan Rogers "SampleAfterValue": "2000003", 89670d90a6aSIan Rogers "UMask": "0x1" 89770d90a6aSIan Rogers }, 89870d90a6aSIan Rogers { 89970d90a6aSIan Rogers "BriefDescription": "Cycles where at least 3 uops were executed per-thread", 90070d90a6aSIan Rogers "CounterMask": "3", 90170d90a6aSIan Rogers "EventCode": "0xB1", 90270d90a6aSIan Rogers "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", 90370d90a6aSIan Rogers "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", 90470d90a6aSIan Rogers "SampleAfterValue": "2000003", 90570d90a6aSIan Rogers "UMask": "0x1" 90670d90a6aSIan Rogers }, 90770d90a6aSIan Rogers { 90870d90a6aSIan Rogers "BriefDescription": "Cycles where at least 4 uops were executed per-thread", 90970d90a6aSIan Rogers "CounterMask": "4", 91070d90a6aSIan Rogers "EventCode": "0xB1", 91170d90a6aSIan Rogers "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", 91270d90a6aSIan Rogers "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", 91370d90a6aSIan Rogers "SampleAfterValue": "2000003", 91470d90a6aSIan Rogers "UMask": "0x1" 91570d90a6aSIan Rogers }, 91670d90a6aSIan Rogers { 91770d90a6aSIan Rogers "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", 91870d90a6aSIan Rogers "CounterMask": "1", 91970d90a6aSIan Rogers "EventCode": "0xB1", 92070d90a6aSIan Rogers "EventName": "UOPS_EXECUTED.STALL_CYCLES", 92170d90a6aSIan Rogers "Invert": "1", 92270d90a6aSIan Rogers "SampleAfterValue": "2000003", 92370d90a6aSIan Rogers "UMask": "0x1" 92470d90a6aSIan Rogers }, 92570d90a6aSIan Rogers { 92670d90a6aSIan Rogers "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", 92770d90a6aSIan Rogers "EventCode": "0xB1", 92870d90a6aSIan Rogers "EventName": "UOPS_EXECUTED.THREAD", 92970d90a6aSIan Rogers "PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.", 93070d90a6aSIan Rogers "SampleAfterValue": "2000003", 93170d90a6aSIan Rogers "UMask": "0x1" 93270d90a6aSIan Rogers }, 93370d90a6aSIan Rogers { 93470d90a6aSIan Rogers "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", 93570d90a6aSIan Rogers "EventCode": "0x0E", 93670d90a6aSIan Rogers "EventName": "UOPS_ISSUED.ANY", 93770d90a6aSIan Rogers "PublicDescription": "Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.", 93870d90a6aSIan Rogers "SampleAfterValue": "2000003", 93970d90a6aSIan Rogers "UMask": "0x1" 94070d90a6aSIan Rogers }, 94170d90a6aSIan Rogers { 94270d90a6aSIan Rogers "AnyThread": "1", 94370d90a6aSIan Rogers "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads", 94470d90a6aSIan Rogers "CounterMask": "1", 94570d90a6aSIan Rogers "EventCode": "0x0E", 94670d90a6aSIan Rogers "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", 94770d90a6aSIan Rogers "Invert": "1", 94870d90a6aSIan Rogers "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", 94970d90a6aSIan Rogers "SampleAfterValue": "2000003", 95070d90a6aSIan Rogers "UMask": "0x1" 95170d90a6aSIan Rogers }, 95270d90a6aSIan Rogers { 95370d90a6aSIan Rogers "BriefDescription": "Number of flags-merge uops being allocated.", 95470d90a6aSIan Rogers "EventCode": "0x0E", 95570d90a6aSIan Rogers "EventName": "UOPS_ISSUED.FLAGS_MERGE", 95670d90a6aSIan Rogers "PublicDescription": "Number of flags-merge uops allocated. Such uops adds delay.", 95770d90a6aSIan Rogers "SampleAfterValue": "2000003", 95870d90a6aSIan Rogers "UMask": "0x10" 95970d90a6aSIan Rogers }, 96070d90a6aSIan Rogers { 96170d90a6aSIan Rogers "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated", 96270d90a6aSIan Rogers "EventCode": "0x0E", 96370d90a6aSIan Rogers "EventName": "UOPS_ISSUED.SINGLE_MUL", 96470d90a6aSIan Rogers "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.", 96570d90a6aSIan Rogers "SampleAfterValue": "2000003", 96670d90a6aSIan Rogers "UMask": "0x40" 96770d90a6aSIan Rogers }, 96870d90a6aSIan Rogers { 96970d90a6aSIan Rogers "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", 97070d90a6aSIan Rogers "EventCode": "0x0E", 97170d90a6aSIan Rogers "EventName": "UOPS_ISSUED.SLOW_LEA", 97270d90a6aSIan Rogers "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", 97370d90a6aSIan Rogers "SampleAfterValue": "2000003", 97470d90a6aSIan Rogers "UMask": "0x20" 97570d90a6aSIan Rogers }, 97670d90a6aSIan Rogers { 97770d90a6aSIan Rogers "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", 97870d90a6aSIan Rogers "CounterMask": "1", 97970d90a6aSIan Rogers "EventCode": "0x0E", 98070d90a6aSIan Rogers "EventName": "UOPS_ISSUED.STALL_CYCLES", 98170d90a6aSIan Rogers "Invert": "1", 98270d90a6aSIan Rogers "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", 98370d90a6aSIan Rogers "SampleAfterValue": "2000003", 98470d90a6aSIan Rogers "UMask": "0x1" 98570d90a6aSIan Rogers }, 98670d90a6aSIan Rogers { 98770d90a6aSIan Rogers "BriefDescription": "Retired uops.", 98870d90a6aSIan Rogers "EventCode": "0xC2", 98970d90a6aSIan Rogers "EventName": "UOPS_RETIRED.ALL", 99070d90a6aSIan Rogers "PEBS": "1", 99170d90a6aSIan Rogers "SampleAfterValue": "2000003", 99270d90a6aSIan Rogers "UMask": "0x1" 99370d90a6aSIan Rogers }, 99470d90a6aSIan Rogers { 99570d90a6aSIan Rogers "AnyThread": "1", 99670d90a6aSIan Rogers "BriefDescription": "Cycles without actually retired uops.", 99770d90a6aSIan Rogers "CounterMask": "1", 99870d90a6aSIan Rogers "EventCode": "0xC2", 99970d90a6aSIan Rogers "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", 100070d90a6aSIan Rogers "Invert": "1", 100170d90a6aSIan Rogers "SampleAfterValue": "2000003", 100270d90a6aSIan Rogers "UMask": "0x1" 100370d90a6aSIan Rogers }, 100470d90a6aSIan Rogers { 100570d90a6aSIan Rogers "BriefDescription": "Retirement slots used.", 100670d90a6aSIan Rogers "EventCode": "0xC2", 100770d90a6aSIan Rogers "EventName": "UOPS_RETIRED.RETIRE_SLOTS", 100870d90a6aSIan Rogers "PEBS": "1", 100970d90a6aSIan Rogers "SampleAfterValue": "2000003", 101070d90a6aSIan Rogers "UMask": "0x2" 101170d90a6aSIan Rogers }, 101270d90a6aSIan Rogers { 101370d90a6aSIan Rogers "BriefDescription": "Cycles without actually retired uops.", 101470d90a6aSIan Rogers "CounterMask": "1", 101570d90a6aSIan Rogers "EventCode": "0xC2", 101670d90a6aSIan Rogers "EventName": "UOPS_RETIRED.STALL_CYCLES", 101770d90a6aSIan Rogers "Invert": "1", 101870d90a6aSIan Rogers "SampleAfterValue": "2000003", 101970d90a6aSIan Rogers "UMask": "0x1" 102070d90a6aSIan Rogers }, 102170d90a6aSIan Rogers { 102270d90a6aSIan Rogers "BriefDescription": "Cycles with less than 10 actually retired uops.", 102370d90a6aSIan Rogers "CounterMask": "10", 102470d90a6aSIan Rogers "EventCode": "0xC2", 102570d90a6aSIan Rogers "EventName": "UOPS_RETIRED.TOTAL_CYCLES", 102670d90a6aSIan Rogers "Invert": "1", 102770d90a6aSIan Rogers "SampleAfterValue": "2000003", 102870d90a6aSIan Rogers "UMask": "0x1" 1029d910f0baSAndi Kleen } 1030d910f0baSAndi Kleen] 1031