1ede00740SAndi Kleen[ 2ede00740SAndi Kleen { 3ede00740SAndi Kleen "BriefDescription": "Unhalted core cycles when the thread is in ring 0", 4*f16c3236SIan Rogers "EventCode": "0x5C", 5ede00740SAndi Kleen "EventName": "CPL_CYCLES.RING0", 6ede00740SAndi Kleen "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", 7ede00740SAndi Kleen "SampleAfterValue": "2000003", 8*f16c3236SIan Rogers "UMask": "0x1" 9ede00740SAndi Kleen }, 10ede00740SAndi Kleen { 11ede00740SAndi Kleen "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", 12ede00740SAndi Kleen "CounterMask": "1", 13*f16c3236SIan Rogers "EdgeDetect": "1", 14*f16c3236SIan Rogers "EventCode": "0x5C", 15*f16c3236SIan Rogers "EventName": "CPL_CYCLES.RING0_TRANS", 16ede00740SAndi Kleen "SampleAfterValue": "100003", 17*f16c3236SIan Rogers "UMask": "0x1" 18ede00740SAndi Kleen }, 19ede00740SAndi Kleen { 20032c16b2SAndi Kleen "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", 21*f16c3236SIan Rogers "EventCode": "0x5C", 22032c16b2SAndi Kleen "EventName": "CPL_CYCLES.RING123", 23032c16b2SAndi Kleen "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", 24032c16b2SAndi Kleen "SampleAfterValue": "2000003", 25*f16c3236SIan Rogers "UMask": "0x2" 26032c16b2SAndi Kleen }, 27032c16b2SAndi Kleen { 28ede00740SAndi Kleen "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", 29*f16c3236SIan Rogers "EventCode": "0x63", 30ede00740SAndi Kleen "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 31ede00740SAndi Kleen "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", 32ede00740SAndi Kleen "SampleAfterValue": "2000003", 33*f16c3236SIan Rogers "UMask": "0x1" 34ede00740SAndi Kleen } 35ede00740SAndi Kleen] 36