1dcfbad10SAndi Kleen[ 2dcfbad10SAndi Kleen { 3dcfbad10SAndi Kleen "BriefDescription": "Unhalted core cycles when the thread is in ring 0", 4*4dd25272SIan Rogers "EventCode": "0x5C", 5*4dd25272SIan Rogers "EventName": "CPL_CYCLES.RING0", 6*4dd25272SIan Rogers "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", 7*4dd25272SIan Rogers "SampleAfterValue": "2000003", 8*4dd25272SIan Rogers "UMask": "0x1" 9dcfbad10SAndi Kleen }, 10dcfbad10SAndi Kleen { 11*4dd25272SIan Rogers "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", 12*4dd25272SIan Rogers "CounterMask": "1", 13dcfbad10SAndi Kleen "EdgeDetect": "1", 14*4dd25272SIan Rogers "EventCode": "0x5C", 15dcfbad10SAndi Kleen "EventName": "CPL_CYCLES.RING0_TRANS", 16dcfbad10SAndi Kleen "SampleAfterValue": "100003", 17*4dd25272SIan Rogers "UMask": "0x1" 18dcfbad10SAndi Kleen }, 19dcfbad10SAndi Kleen { 20ca3a2d05SAndi Kleen "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", 21*4dd25272SIan Rogers "EventCode": "0x5C", 22*4dd25272SIan Rogers "EventName": "CPL_CYCLES.RING123", 23*4dd25272SIan Rogers "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", 24*4dd25272SIan Rogers "SampleAfterValue": "2000003", 25*4dd25272SIan Rogers "UMask": "0x2" 26ca3a2d05SAndi Kleen }, 27ca3a2d05SAndi Kleen { 28dcfbad10SAndi Kleen "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", 29*4dd25272SIan Rogers "EventCode": "0x63", 30*4dd25272SIan Rogers "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 31*4dd25272SIan Rogers "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", 32*4dd25272SIan Rogers "SampleAfterValue": "2000003", 33*4dd25272SIan Rogers "UMask": "0x1" 34dcfbad10SAndi Kleen } 35dcfbad10SAndi Kleen] 36