119c0389bSAndi Kleen[ 219c0389bSAndi Kleen { 319c0389bSAndi Kleen "BriefDescription": "Unhalted core cycles when the thread is in ring 0", 4*56f57cffSIan Rogers "EventCode": "0x5C", 519c0389bSAndi Kleen "EventName": "CPL_CYCLES.RING0", 619c0389bSAndi Kleen "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", 719c0389bSAndi Kleen "SampleAfterValue": "2000003", 8*56f57cffSIan Rogers "UMask": "0x1" 919c0389bSAndi Kleen }, 1019c0389bSAndi Kleen { 1119c0389bSAndi Kleen "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", 1219c0389bSAndi Kleen "CounterMask": "1", 13*56f57cffSIan Rogers "EdgeDetect": "1", 14*56f57cffSIan Rogers "EventCode": "0x5C", 15*56f57cffSIan Rogers "EventName": "CPL_CYCLES.RING0_TRANS", 1619c0389bSAndi Kleen "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", 1719c0389bSAndi Kleen "SampleAfterValue": "100007", 18*56f57cffSIan Rogers "UMask": "0x1" 1919c0389bSAndi Kleen }, 2019c0389bSAndi Kleen { 2197d00f2dSAndi Kleen "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", 22*56f57cffSIan Rogers "EventCode": "0x5C", 2397d00f2dSAndi Kleen "EventName": "CPL_CYCLES.RING123", 2497d00f2dSAndi Kleen "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", 2597d00f2dSAndi Kleen "SampleAfterValue": "2000003", 26*56f57cffSIan Rogers "UMask": "0x2" 2797d00f2dSAndi Kleen }, 2897d00f2dSAndi Kleen { 2919c0389bSAndi Kleen "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", 30*56f57cffSIan Rogers "EventCode": "0x63", 3119c0389bSAndi Kleen "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 3219c0389bSAndi Kleen "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", 3319c0389bSAndi Kleen "SampleAfterValue": "2000003", 34*56f57cffSIan Rogers "UMask": "0x1" 3519c0389bSAndi Kleen } 3619c0389bSAndi Kleen] 37