127b565b1SAndi Kleen[ 227b565b1SAndi Kleen { 327b565b1SAndi Kleen "BriefDescription": "Unhalted core cycles when the thread is in ring 0", 4*34cb72efSIan Rogers "EventCode": "0x5C", 527b565b1SAndi Kleen "EventName": "CPL_CYCLES.RING0", 627b565b1SAndi Kleen "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", 727b565b1SAndi Kleen "SampleAfterValue": "2000003", 8*34cb72efSIan Rogers "UMask": "0x1" 927b565b1SAndi Kleen }, 1027b565b1SAndi Kleen { 1127b565b1SAndi Kleen "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", 1227b565b1SAndi Kleen "CounterMask": "1", 13*34cb72efSIan Rogers "EdgeDetect": "1", 14*34cb72efSIan Rogers "EventCode": "0x5C", 15*34cb72efSIan Rogers "EventName": "CPL_CYCLES.RING0_TRANS", 1627b565b1SAndi Kleen "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", 1727b565b1SAndi Kleen "SampleAfterValue": "100007", 18*34cb72efSIan Rogers "UMask": "0x1" 1927b565b1SAndi Kleen }, 2027b565b1SAndi Kleen { 21fae0a4dfSAndi Kleen "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", 22*34cb72efSIan Rogers "EventCode": "0x5C", 23fae0a4dfSAndi Kleen "EventName": "CPL_CYCLES.RING123", 24fae0a4dfSAndi Kleen "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", 25fae0a4dfSAndi Kleen "SampleAfterValue": "2000003", 26*34cb72efSIan Rogers "UMask": "0x2" 27fae0a4dfSAndi Kleen }, 28fae0a4dfSAndi Kleen { 2927b565b1SAndi Kleen "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", 30*34cb72efSIan Rogers "EventCode": "0x63", 3127b565b1SAndi Kleen "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 3227b565b1SAndi Kleen "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", 3327b565b1SAndi Kleen "SampleAfterValue": "2000003", 34*34cb72efSIan Rogers "UMask": "0x1" 3527b565b1SAndi Kleen } 3627b565b1SAndi Kleen] 37