1b74d1315SAndi Kleen[ 2b74d1315SAndi Kleen { 3b74d1315SAndi Kleen "BriefDescription": "Unhalted core cycles when the thread is in ring 0", 4*10e8d85fSIan Rogers "EventCode": "0x5C", 5*10e8d85fSIan Rogers "EventName": "CPL_CYCLES.RING0", 6*10e8d85fSIan Rogers "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", 7*10e8d85fSIan Rogers "SampleAfterValue": "2000003", 8*10e8d85fSIan Rogers "UMask": "0x1" 9b74d1315SAndi Kleen }, 10b74d1315SAndi Kleen { 11b74d1315SAndi Kleen "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", 12b74d1315SAndi Kleen "CounterMask": "1", 13*10e8d85fSIan Rogers "EdgeDetect": "1", 14b3ab8adcSAndi Kleen "EventCode": "0x5C", 15*10e8d85fSIan Rogers "EventName": "CPL_CYCLES.RING0_TRANS", 16*10e8d85fSIan Rogers "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", 17*10e8d85fSIan Rogers "SampleAfterValue": "100007", 18*10e8d85fSIan Rogers "UMask": "0x1" 19b3ab8adcSAndi Kleen }, 20b3ab8adcSAndi Kleen { 21*10e8d85fSIan Rogers "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", 22*10e8d85fSIan Rogers "EventCode": "0x5C", 23*10e8d85fSIan Rogers "EventName": "CPL_CYCLES.RING123", 24*10e8d85fSIan Rogers "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", 25b74d1315SAndi Kleen "SampleAfterValue": "2000003", 26*10e8d85fSIan Rogers "UMask": "0x2" 27*10e8d85fSIan Rogers }, 28*10e8d85fSIan Rogers { 29b74d1315SAndi Kleen "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", 30*10e8d85fSIan Rogers "EventCode": "0x63", 31*10e8d85fSIan Rogers "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 32*10e8d85fSIan Rogers "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", 33*10e8d85fSIan Rogers "SampleAfterValue": "2000003", 34*10e8d85fSIan Rogers "UMask": "0x1" 35b74d1315SAndi Kleen } 36b74d1315SAndi Kleen] 37